Semiconductor test structure for failure analysis

Abstract

The invention discloses a semiconductor test structure, which comprises a semiconductor substrate, a first conductive connection structure, a second conductive connection structure and a plurality of test units, the first conductive connecting lines of the first conductive connecting structure and the second conductive connecting lines of the second conductive connecting structure are arranged in a staggered and spaced manner, so that staggered spaces are formed between the staggered first conductive connecting lines and second conductive connecting lines; the first pole and the second pole of the test unit are respectively connected with the first conductive connecting line and the second conductive connecting line which form the corresponding staggered space; the first plugs and the second plugs are arranged on the outer side of the test unit array, each first plug is electrically connected with the corresponding first conductive connecting line, and each second plug is electrically connected with the corresponding second conductive connecting line; the tops of the first plug and the second plug are higher than the tops of the first conductive connecting line and the second conductive connecting line. And the failed test unit can be quickly locked.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and more particularly to a semiconductor test structure for performing failure analysis. Background Art

[0002] During the semiconductor design and manufacturing process, various test structures are set up on the wafer to perform reliability tests on the test array unit structure to evaluate and verify the stability and reliability of the product process under different conditions.

[0003] Currently, test patterns (testkeys) used to measure the breakdown voltage (Vbd), time-dependent dielectric breakdown (TDDB), or dielectric layer leakage of array cell structures use a design where multiple test cells share a common metal wire connection. When a breakdown actually occurs and the broken cell needs to be quickly found for failure analysis, it is difficult to quickly and accurately locate the failed test cell, resulting in a significant loss of time, manpower, and analysis costs. Summary of the Invention

[0004] The present application is proposed to solve the above-mentioned problems. According to one aspect of the present application, a semiconductor test structure for performing failure analysis is provided. The semiconductor test structure includes: semiconductor substrates; A first conductive connection structure and a second conductive connection structure located on the semiconductor substrate, the first conductive connection structure comprising a plurality of first conductive connection lines arranged parallel to each other and horizontally, the second conductive connection structure comprising a plurality of second conductive connection lines arranged parallel to each other and horizontally, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure being arranged in an interlaced and spaced manner to form interlaced spaces between the interlaced first conductive connection lines and the second conductive connection lines; A plurality of test cells are located on a semiconductor substrate, the plurality of test cells are arranged in a horizontal array to form a test cell array, the test cells are arranged corresponding to the staggered spaces, the test cells include a first electrode and a second electrode, the first electrode and the second electrode are respectively connected to a first conductive connection line and a second conductive connection line forming the corresponding staggered space; At least two first plugs are disposed outside the test unit array and spaced apart from each other, each first plug being disposed corresponding to a first conductive connection line, and each first plug being electrically connected to the corresponding first conductive connection line; At least two second plugs are disposed outside the test unit array and spaced apart from each other, each second plug being disposed corresponding to a second conductive connection line, and each second plug being electrically connected to the corresponding second conductive connection line; The tops of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate are higher than the tops of the at least two first conductive connecting lines and the at least two second conductive connecting lines.

[0005] In some embodiments of the present application, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged in an interlaced and spaced manner to form an interlaced space between the interlaced first conductive connection lines and the second conductive connection lines, including: The extension directions of the first conductive connection line and the second conductive connection line intersect, the first conductive connection line and the second conductive connection line are located in different layers, the staggered space is located at the intersection of the first conductive connection line and the second conductive connection line, and multiple staggered spaces are arranged in an array.

[0006] In some embodiments of the present application, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged in an interlaced and spaced manner to form an interlaced space between the interlaced first conductive connection lines and the second conductive connection lines, including: The extension directions of the first conductive connection lines are parallel to those of the second conductive connection lines. The first conductive connection lines and the second conductive connection lines are located in the same or different layers. The first conductive connection lines and the second conductive connection lines are adjacent to each other in a one-to-one correspondence so as to be staggered. One or more staggered spaces are formed between adjacent first conductive connection lines and second conductive connection lines.

[0007] In some embodiments of the present application, the semiconductor test structure further includes: A first common conductive line is located on top of the first plugs, and the first common conductive line electrically connects at least two first plugs.

[0008] In some embodiments of the present application, the semiconductor test structure further includes: A second common conductive line is located on top of the second plugs, and the second common conductive line electrically connects at least two second plugs.

[0009] In some embodiments of the present application, the first common conductive line and the second common conductive line have the same height in a direction perpendicular to the surface of the semiconductor substrate.

[0010] In some embodiments of the present application, the semiconductor test structure further includes: A first test pad is electrically connected to the first common conductive line, and a second test pad is electrically connected to the second common conductive line. The first test pad and the second test pad have the same height in a direction perpendicular to the surface of the semiconductor substrate.

[0011] In some embodiments of the present application, the first common conductive line and the second common conductive line are both located in a top metal layer of the semiconductor test structure.

[0012] In some embodiments of the present application, the semiconductor test structure further includes: The third common conductive line is located on a side of the first plug away from the test unit array and is electrically connected to at least two first conductive connection lines. The third common conductive line and the at least two first conductive connection lines form a first comb structure.

[0013] In some embodiments of the present application, the semiconductor test structure further includes: The fourth common conductive line is located on a side of the second plug away from the test unit array and is electrically connected to at least two second conductive connection lines. The fourth common conductive line and the at least two second conductive connection lines form a second comb-tooth structure.

[0014] In some embodiments of the present application, each first plug is electrically connected to a corresponding first conductive connection line through a first transfer structure; The first adapter structure includes at least one first adapter plug and at least one first adapter wire. The first adapter plug and the first adapter wire are connected in series on a conductive path between the first plug and the first conductive connection wire.

[0015] In some embodiments of the present application, a bottom of the first plug is higher or lower than a top of the first conductive connection line in a direction perpendicular to the surface of the semiconductor substrate.

[0016] In some embodiments of the present application, each second plug is electrically connected to the corresponding second conductive connection line through a second adapter structure, and the second adapter structure includes at least one second adapter plug and at least one second adapter line, and the second adapter plug and the second adapter line are connected in series on the conductive path between the second plug and the second conductive connection line.

[0017] In some embodiments of the present application, a bottom of the second plug is higher or lower than a top of the second conductive connection line in a direction perpendicular to the surface of the semiconductor substrate.

[0018] In some embodiments of the present application, in a direction perpendicular to the surface of the semiconductor substrate, a bottom height of the first plug is the same as a bottom height of the second plug.

[0019] In some embodiments of the present application, top heights of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate are higher than a top of the test unit.

[0020] In some embodiments of the present application, the test unit includes a transistor, the transistor includes a source, a gate, a drain and a channel region, and the first electrode and the second electrode respectively include one of the source, the gate and the drain; or, The test unit includes a capacitor structure including a first capacitor plate and a second capacitor plate. The first electrode includes the first capacitor plate, and the second electrode includes the second capacitor plate.

[0021] According to a second aspect of the present application, a testing method based on some of the above-mentioned semiconductor test structures is provided, the testing method comprising: After confirming that a failed test cell exists in the test cell array, performing a planarization process on the semiconductor test structure to expose tops of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate; A first test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two first plugs, and a second test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two second plugs, and several test units are tested in sequence to find failed test units.

[0022] According to the third aspect of the present application, a testing method based on some of the above-mentioned semiconductor test structures is provided, and the testing method includes: After confirming that a failed test cell exists in the test cell array, cutting the semiconductor test structure along a region between the first plug and the third common conductive line, and a region between the second plug and the fourth common conductive line, to disconnect the electrical connection between the third common conductive line and the first plug, and disconnect the electrical connection between the fourth common conductive line and the second plug; exposing tops of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate; A first test probe of the test device is sequentially electrically contacted with the top of one of the at least two first plugs, and a second test probe of the test device is sequentially electrically contacted with the top of one of the at least two second plugs, and several test units are tested in sequence to find a failed test unit among the several test units.

[0023] According to the semiconductor test structure provided by the embodiments of the present application, at least two first plugs and at least two second plugs are provided outside the test cell array, spaced apart from each other. Each first plug corresponds to and is electrically connected to a first conductive connection line, and each second plug corresponds to and is electrically connected to a second conductive connection line. Furthermore, the top heights of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate are both greater than the tops of the at least two first conductive connection lines and the at least two second conductive connection lines. During the testing process of the semiconductor test structure, the semiconductor test structure can be planarized to expose the tops of the first plugs and the second plugs in a direction perpendicular to the surface of the semiconductor substrate, thereby providing an electrically independent independent test circuit for each test cell. When locating a failure, an electron beam can be used to scan the independent test circuit of each test cell, which facilitates rapid identification of the failed test cell and reduces time, manpower, and analysis costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1A A schematic diagram of a three-dimensional structure of a semiconductor test structure according to an embodiment of the present application; Figure 1B for Figure 1A A schematic top view of a semiconductor test structure is shown; Figure 2A A schematic diagram of a three-dimensional structure of a semiconductor test structure according to another embodiment of the present application; Figure 2B for Figure 2A A schematic top view of a semiconductor test structure is shown; Figures 3 to 7A Schematic diagrams of the three-dimensional structures of semiconductor test structures shown in different embodiments of the present application; Figure 7B for Figure 7A A schematic top view of a semiconductor test structure is shown; Figure 7C For Figure 7A The three-dimensional structure diagram of the semiconductor test structure after the common conductive lines and test pads are cut away is shown; Figure 7D for Figure 7C A schematic top view of a semiconductor test structure is shown; Figure 8 A schematic diagram of a three-dimensional structure of a semiconductor test structure according to another embodiment of the present application; Figure 9 A schematic top view of a semiconductor test structure according to another embodiment of the present application; Figure 10 FIG1 is a schematic top view of a semiconductor test structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present application more apparent, the following is a detailed description of example embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in this application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of this application.

[0027] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0028] It should be understood that the present application can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and will fully convey the scope of the present application to those skilled in the art.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, confirm the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] In order to fully understand the present application, a detailed structure will be provided in the following description to illustrate the technical solution proposed by the present application. The optional embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0031] In related technologies, in order to evaluate and verify the reliability of product processes under different conditions and monitor the stability of online processes, various test unit structures are designed on the wafer, and these structures can be distributed on the cutting paths between each die in the wafer. Reliability testing of these structures is a very important step in semiconductor process technology and product manufacturing.

[0032] Currently, to measure the breakdown voltage (Vbd), dielectric breakdown (TDDB), or dielectric leakage of array structures such as MOS transistors or capacitors, test structures are designed with upper and lower layers of wiring, either perpendicular or parallel to each other. For example, a test structure comprising a MOS transistor test cell array and performing a dielectric breakdown test is used: for a test cell array, the source, drain, and gate terminals of all test cells (i.e., MOS transistors) are connected to the same source test pad, drain test pad, and gate test pad via source wiring, drain wiring, and gate wiring, respectively. By applying a voltage (V), the current flowing through the source, drain, and gate test pads is measured to determine whether dielectric breakdown has occurred in the MOS transistor test cell array.

[0033] If electrical breakdown occurs in a MOS transistor test array (i.e., a test cell array), failure analysis techniques are needed to infer the cause of the failure. Generally, this analysis begins with electrical failure analysis (EFA), followed by physical failure analysis (PFA) to observe morphology and other phenomena. A key step is to locate the failed test cell within the test cell array. However, due to the limited magnification and clarity of current OBIRCH (Optical Beam Induced Resistance Change) technology, and its low accuracy in locating the failure point in test structures arranged in arrays such as transistors or capacitors, EBIRCH (Electron Beam Induced Resistance Change) technology is labor-intensive.

[0034] Existing breakdown voltage (Vbd) test structures consist of an array of numerous transistor cells. When electrical breakdown occurs, the first step is to locate the failed test cell before conducting topographic observation and failure analysis. However, because the test pads in the current structure connect the corresponding electrodes of all test cells via a shared conductive wire (for example, the gate test pad connects all gates in the test cell array via gate wiring), conducting electrical failure analysis by introducing the laser beam only through the test pad will result in the bright spot area displayed by OBIRCH covering multiple test cells, making it impossible to quickly and accurately locate a failed test cell.

[0035] The current method for locating failures through analysis is as follows: First, a sample is prepared for the test structure area to be analyzed, but some test unit structures may be damaged during the sample preparation process. OBIRCH is then used to scan the structure, but this has limited magnification and low accuracy, and can only locate a large area containing the failed test unit. EBIRCH and EBAC (Electron Beam Absorbed Current) are then used for fine positioning, using an electron beam to sequentially scan each point in the bright spot area (in units of resolution) to locate the failed test unit, and then perform subsequent failure analysis. This requires a lot of sample preparation manpower and analysis costs.

[0036] To solve at least some of the technical problems in the above-mentioned related technologies, the present application proposes the following embodiments.

[0037] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0038] First, the application scenario of the semiconductor test structure shown in the example of this application is introduced. The semiconductor test structure can be applied to, for example, but not limited to, between dies of a wafer. Example 1

[0039] refer to Figure 1A and Figure 1B , an embodiment of the present application provides a semiconductor test structure, which mainly includes: a semiconductor substrate (not shown); A first conductive connection structure and a second conductive connection structure are located on the semiconductor substrate, wherein the first conductive connection structure includes a plurality of first conductive connection lines 21 arranged parallel to each other and horizontally, and the second conductive connection structure includes a plurality of second conductive connection lines 31 arranged parallel to each other and horizontally, wherein the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure are arranged in an interlaced and spaced manner to form interlaced spaces between the interlaced first conductive connection lines 21 and the second conductive connection lines 31; A plurality of test units 10 are disposed on a semiconductor substrate, the plurality of test units 10 being arranged in a horizontal array to form a test unit array. The test units 10 are disposed corresponding to the interleaved spaces. The test units 10 include a first electrode and a second electrode, the first electrode and the second electrode being respectively connected to a first conductive connection line 21 and a second conductive connection line 31 forming the corresponding interleaved spaces. At least two first plugs 22 are disposed outside the test unit array and spaced apart from each other, each first plug 22 being disposed corresponding to a first conductive connection line 21 and each first plug 22 being electrically connected to a corresponding first conductive connection line 21; At least two second plugs 32 are disposed outside the test unit array and spaced apart from each other, each second plug 32 being disposed corresponding to a second conductive connection line 31 and each second plug 32 being electrically connected to a corresponding second conductive connection line 31; The tops of the at least two first plugs 22 and the at least two second plugs 32 in a direction perpendicular to the surface of the semiconductor substrate are higher than the tops of the at least two first conductive connection lines 21 and the at least two second conductive connection lines 31 .

[0040] The above embodiment has the following advantageous effects: by disposing at least two first plugs 22 and at least two second plugs 32 spaced apart from each other outside the test cell array, each first plug 22 is disposed corresponding to and electrically connected to a first conductive connection line 21, and each second plug 32 is disposed corresponding to and electrically connected to a second conductive connection line 31; and the top heights of the at least two first plugs 22 and the at least two second plugs 32 in a direction perpendicular to the surface of the semiconductor substrate are both greater than the top heights of the at least two first conductive connection lines 21 and the at least two second conductive connection lines 31. During testing of the semiconductor test structure, the semiconductor test structure can be planarized to expose the tops of the first plugs 22 and the second plugs 32 in a direction perpendicular to the surface of the semiconductor substrate, thereby providing an electrically independent test circuit for each test cell 10.

[0041] When locating a failure, electron beam scanning can be performed using the independent test circuit of each test cell 10 to quickly identify the failure site (the failed test cell 10), reducing time, labor, and analysis costs. This ensures the original test functionality while enabling faster and more accurate failure location and quickly identifying the failed test cell 10. Furthermore, this semiconductor test structure can be fabricated simultaneously with structures within the die (e.g., non-test structures) by simply modifying the pattern of the corresponding metal layer in the photomask. This achieves rapid and accurate failure location without affecting the internal structure of the test cell array. In other words, the semiconductor test structure illustrated in the embodiments of this application can be fabricated without requiring additional photomasks. Specifically, by introducing independent first and second plugs 22 and 32 based on the existing test structure, the semiconductor test structure provides each test cell 10 in the test cell array with an electrically independent test circuit without changing the test functionality or adding additional photomasks, eliminating the need for interconnecting the test circuits of the entire array. When locating a failure, electrical failure analysis can directly apply a nanoprobe to the two ends of an independent test circuit electrically connected to the same test unit 10 (the tops of the first plug 22 and the second plug 32), scanning with an electron beam. This facilitates rapid identification of the failure site. Therefore, for example, when testing MOS transistor arrays, there is no need to grind down to the top of the gate, destroying the test unit 10 structure, and then conduct detailed scanning and observation over a large area. This avoids excessive sample preparation and analysis costs, thereby reducing sample preparation and analysis costs during the failure analysis process.

[0042] The semiconductor test structure is described in detail below with reference to the accompanying drawings.

[0043] Regarding the material of the semiconductor substrate, any substrate material can be selected. Exemplarily, the semiconductor substrate can be a substrate of an insulating material, silicon, or silicon on insulator (SOI). For example, the semiconductor substrate can be a Si-containing semiconductor substrate. The term "Si-containing semiconductor substrate" refers to any semiconductor material containing at least silicon. Illustrative examples of Si-containing semiconductor materials that can be used as substrates include: Si, SiGe, SiC, SiGeC, silicon on insulator (SOI) or SiGe on insulator (SGOI), but are not limited thereto. Depending on the device being manufactured, the substrate can be undoped or doped. Exemplarily, the semiconductor substrate can be made of single crystal silicon material.

[0044] Regarding the type of test unit 10, any electrical device can be used. For example, the test unit 10 can include any one or more of a transistor structure and a capacitor structure. Depending on the type of test unit 10, electrodes in the test unit 10, such as but not limited to a source, a drain, a gate, an emitter, a collector, a positive electrode, and a negative electrode, are connected to the first conductive connection line 21 and the second conductive connection line 31, so that the test unit 10 can be tested through the first conductive connection line 21 or the second conductive connection line 31.

[0045] Exemplarily, the test unit 10 may include a transistor, and the transistor may include a source, a gate, a drain, and a channel region. In this case, the first electrode and the second electrode may each include one of the source, the gate, and the drain. Specifically, the first electrode and the second electrode may each include a source and a drain, a source and a gate, or a drain and a gate.

[0046] It should be noted that the transistors included in the test unit 10 can be any type of transistor structure. For example, the above-mentioned transistors can be any type of transistors such as but not limited to Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Insulated-Gate Bipolar Transistor (IGBT), bipolar transistor, diode, etc., and the first pole and the second pole can be any electrodes of the above-mentioned transistors respectively.

[0047] Exemplarily, the test unit 10 may include a capacitor structure including a first capacitor plate and a second capacitor plate, wherein the first electrode includes the first capacitor plate and the second electrode includes the second capacitor plate.

[0048] The above-mentioned capacitor structure can be any type of capacitor structure. For example, the capacitor structure can be any type of capacitor structure such as, but not limited to, a cylindrical capacitor, a plate capacitor, or the like.

[0049] The above-mentioned capacitor structure and / or transistor can individually or collectively constitute a memory cell or part of a memory cell having a storage function. For example, the above-mentioned memory cell can be any cell structure capable of storing a binary information bit, such as, but not limited to, a DRAM memory cell, an MRAM memory cell, or an FeRAM memory cell.

[0050] Of course, it should be noted that the above-mentioned test unit 10 is not limited to the above-mentioned enumerated structures. Other test units 10 that can form an array structure are also applicable and are within the protection scope of this application.

[0051] Regarding the staggered and spaced arrangement of the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure, various methods can be used. As long as a staggered space for arranging part or all of the structure of the test unit 10 can be formed between the staggered first conductive connection lines 21 and the second conductive connection lines 31, the staggered arrangement is within the scope of protection of the embodiments of the present application. The following exemplifies some examples of staggered and spaced arrangements.

[0052] In some embodiments, reference Figure 1A and Figure 1B The first conductive connection line 21 of the first conductive connection structure and the second conductive connection line 31 of the second conductive connection structure are arranged in an interlaced and spaced manner to form an interlaced space between the interlaced first conductive connection line 21 and the second conductive connection line 31, including: the extension directions of the first conductive connection line 21 and the second conductive connection line 31 intersect, the first conductive connection line 21 and the second conductive connection line 31 are located in different layers, the interlaced space is located at the intersection of the first conductive connection line 21 and the second conductive connection line 31, and multiple interlaced spaces are arranged in an array.

[0053] That is, in this embodiment, reference Figure 1A and Figure 1B The first conductive connection line 21 and the second conductive connection line 31 are located in different layers. Specifically, the first conductive connection line 21 can be located above the second conductive connection line 31 and spaced apart by an interlayer dielectric layer to insulate, or the second conductive connection line 31 can be located above the first conductive connection line 21 and spaced apart by an interlayer dielectric layer to insulate. The extension direction of the first conductive connection line 21 and the extension direction of the second conductive connection line 31 are at a non-zero angle such as, but not limited to, 90°, 75°, or 105°, so that the extension directions of the first conductive connection line 21 and the second conductive connection line 31 are arranged to intersect with each other. In this case, there is an intersection between each first conductive connection line 21 and each second conductive connection line 31, so that multiple intersections are formed between all the first conductive connection lines 21 and all the second conductive connection lines 31, and the interlaced space for setting the test unit 10 is located at the intersection of the first conductive connection line 21 and the second conductive connection line 31, so that multiple interlaced spaces can be formed. Due to the horizontal arrangement of the plurality of first conductive connection lines 21 and the horizontal arrangement of the plurality of second conductive connection lines 31, the plurality of interlaced spaces can be arranged in an array along the extension direction of the first conductive connection lines 21 and the extension direction of the second conductive connection lines 31, so that the plurality of test units are arranged in an array to form a test unit array.

[0054] Exemplary, reference Figure 1A and Figure 1B, a first conductive connection structure and a second conductive connection structure are provided on the semiconductor substrate. The first conductive connection structure includes a plurality of first conductive connection lines 21, each of which extends along the first direction, and the plurality of first conductive connection lines 21 are arranged at intervals along the second direction, and adjacent first conductive connection lines 21 are insulated and separated by dielectric material. The first direction and the second direction are arranged crosswise, and the first direction and the second direction are both parallel to the surface of the semiconductor substrate. Exemplarily, the first direction and the second direction can be arranged vertically. Of course, the first direction and the second direction are not limited to a vertical arrangement. As long as the first direction and the second direction have an angle to form a cross arrangement, they are within the protection scope of the embodiments of the present application.

[0055] refer to Figure 1A and Figure 1B The second conductive connection structure includes at least two second conductive connection lines 31, each extending along the second direction. At least two second conductive connection lines 31 are spaced apart along the first direction, and adjacent second conductive connection lines 31 are insulated and separated by a dielectric material. For example, each second conductive connection line 31 can be parallel to the surface of the semiconductor substrate.

[0056] refer to Figure 1A and Figure 1B The first conductive connection line 21 and the second conductive connection line 31 are located on two different planes in a direction perpendicular to the surface of the semiconductor substrate, that is, the first conductive connection line 21 and the second conductive connection line 31 are located in different layers. Exemplarily, the first conductive connection line 21 and the second conductive connection line 31 are located in different metal layers of the semiconductor test structure.

[0057] refer to Figure 1A and Figure 1B Several test units 10 are also provided on the semiconductor substrate. The test units 10 are located at the intersections of at least two first conductive connection lines 21 and at least two second conductive connection lines 31, so that the test units 10 constitute a test unit array.

[0058] refer to Figure 1A and Figure 1BAt least two first plugs 22 are also provided on the semiconductor substrate, spaced apart from each other. These first plugs 22 are located outside the test cell array. Each first plug 22 corresponds to a first conductive connection line 21, and each first plug 22 is electrically connected to a corresponding first conductive connection line 21, thereby forming an electrically independent test circuit. Specifically, different first plugs 22 are insulated and separated by a dielectric material, such as, but not limited to, oxide, and different first conductive connection lines 21 are also insulated and separated by a dielectric material, such as, but not limited to, oxide. As a result, each first plug 22 is electrically connected only to its corresponding first conductive connection line 21, and is insulated and separated from other first conductive connection lines 21 by a dielectric material, thereby being electrically independent of each other.

[0059] Furthermore, the top height of each first plug 22 in a direction perpendicular to the surface of the semiconductor substrate is greater than the top heights of at least two first conductive connection lines 21 and at least two second conductive connection lines 31. That is, the top height of the first plug 22 in a direction perpendicular to the surface of the semiconductor substrate is not only greater than the top heights of all first conductive connection lines 21, but also greater than the top heights of all second conductive connection lines 31. During the grinding process of the semiconductor substrate downward to the top surface, the top of the first plug 22 is exposed before the first conductive connection lines 21 and the second conductive connection lines 31.

[0060] It should be noted that the first plug 22 and the first conductive connection line 21 can be electrically connected in a variety of ways, some of which are exemplarily described below.

[0061] Exemplary, reference Figure 1A 、 2A as well as Figure 3 The bottom of the first plug 22 can be in direct contact and electrically connected to a corresponding first conductive connection line 21 , thereby achieving electrical connection between the first plug 22 and the first conductive connection line 21 .

[0062] However, sometimes, considering the spatial arrangement and process sequence in the manufacturing process, the bottom of the first plug 22 is not directly electrically connected to the corresponding first conductive connection line 21 .

[0063] In other embodiments, each first plug 22 is electrically connected to a corresponding first conductive connection line 21 via a first transfer structure. The first transfer structure includes at least one first transfer plug 26 and at least one first transfer line 25, with the first transfer plug 26 and the first transfer line 25 connected in series in the conductive path between the first plug 22 and the first conductive connection line 21. Specifically, the bottom of the first plug 22 can also be indirectly electrically connected to a corresponding first conductive connection line 21 via a first transfer structure disposed on the semiconductor substrate and comprising the first transfer line 25 and the first transfer plug 26. It is essential to ensure that the first transfer structures corresponding to different first plugs 22 are electrically independent and insulated from each other, thereby preserving the electrically independent functionality of the independent test circuits.

[0064] When the first plug 22 is electrically connected to the corresponding first conductive connection line 21 through the first transfer structure, the bottom of the first plug 22 can be made higher or lower than the top of the first conductive connection line 21 in a direction perpendicular to the surface of the semiconductor substrate. Specifically, whether the bottom height of the first plug 22 is higher or lower than the top of the first conductive connection line 21 can be determined based on the specific positions of the first plug 22 and the first conductive connection line 21 and the preparation process.

[0065] In some embodiments, the bottom height of the first plug 22 is higher than the top of the first conductive connection line 21. At this time, in the vertical direction perpendicular to the semiconductor substrate, the first transfer plug 26 and the first transfer line 25 can be located between the bottom of the first plug 22 and the first conductive connection line 21, that is, the first transfer plug 26 can be connected to the upper surface of the first conductive connection line 21 and then extend upward to connect to the first transfer line 25, and the upper surface of the first transfer line 25 is connected to the bottom of the first plug 22.

[0066] For example, sometimes the first adapter plug 26 connected to the first conductive connection line 21 is not directly connected upward, but is first connected to the first adapter line 25 located at the lower layer of the first conductive connection line 21, and then connected to the upper layer through the first plug 22, that is, the bottom of the first plug 22 is lower than the first conductive connection line 21.

[0067] The present application is not limited thereto. In some embodiments, the first transfer structure includes a plurality of first transfer wires 25 and a plurality of first transfer plugs 26 . The first transfer wires 25 and the first transfer plugs 26 are alternately connected in series between the first plugs 22 and the first conductive connection line 21 .

[0068] Exemplary, reference Figure 4 and Figure 5The semiconductor test structure also includes at least two first transfer lines 25, each extending along the first direction and spaced apart along the second direction. Each first transfer line 25 corresponds to a first conductive connection line 21 and is located below the corresponding first conductive connection line 21. Two adjacent first transfer lines 25 are insulated and separated by dielectric material, thereby maintaining electrical independence from each other. Each first transfer line 25 is electrically connected to a corresponding first conductive connection line 21 through a first transfer plug 26, and is not connected to other first conductive connection lines 21, and is electrically independent from each other. Each first transfer line 25 corresponds to a first plug 22, and is directly in contact and electrically connected to the bottom of the corresponding first plug 22, and is not connected to other first plugs 22, and is electrically independent from each other. In this way, the bottom of the first plug 22 is electrically connected to the corresponding first conductive connection line 21 through the corresponding first transfer line 25 and the first transfer plug 26 in sequence, forming an electrically independent independent test circuit.

[0069] Exemplary, reference Figure 4 and Figure 5 The first transfer line 25 can be located in an adjacent metal layer below the first conductive connection line 21. Of course, the adjacent metal layers are insulated and separated by a dielectric layer. For example, there can also be at least one metal layer between the first transfer line 25 and the first conductive connection line 21, that is, the first transfer line 25 is not adjacent to the metal layer where the first conductive connection line 21 is located.

[0070] refer to Figure 1A and Figure 1B At least two second plugs 32 are also provided on the semiconductor substrate, spaced apart from each other. These second plugs 32 are located outside the test cell array. Each second plug 32 corresponds to a second conductive connection line 31, and each second plug 32 is electrically connected to a corresponding second conductive connection line 31, thereby forming an electrically independent test circuit. Specifically, different second plugs 32 are insulated and separated by a dielectric material, such as, but not limited to, oxide, and different second conductive connection lines 31 are also insulated and separated by a dielectric material, such as, but not limited to, oxide. As a result, each second plug 32 is electrically connected only to its corresponding second conductive connection line 31, and is insulated and separated from other second conductive connection lines 31 by a dielectric material, thereby being electrically independent of each other.

[0071] Furthermore, the top height of each second plug 32 in a direction perpendicular to the surface of the semiconductor substrate is greater than the top heights of at least two first conductive connection lines 21 and at least two second conductive connection lines 31. That is, the top height of the second plug 32 in a direction perpendicular to the surface of the semiconductor substrate is not only greater than the top heights of all first conductive connection lines 21, but also greater than the top heights of all second conductive connection lines 31. During the grinding process from the semiconductor substrate down to the top surface, the tops of the second plugs 32 are exposed before the first conductive connection lines 21 and the second conductive connection lines 31.

[0072] It should be noted that the second plug 32 and the second conductive connection line 31 can be electrically connected in a variety of ways, some of which are exemplified below.

[0073] Exemplary, reference Figure 1A and Figure 1B The bottom of the second plug 32 can be in direct contact and electrically connected to a corresponding second conductive connection line 31 , thereby achieving electrical connection between the second plug 32 and the second conductive connection line 31 .

[0074] However, sometimes, considering the spatial arrangement and process sequence in the manufacturing process, the bottom of the second plug 32 is not directly electrically connected to the corresponding second conductive connection line 31 .

[0075] In other embodiments, each second plug 32 is electrically connected to a corresponding second conductive connection line 31 via a second transfer structure. The second transfer structure includes at least one second transfer plug 36 and at least one second transfer line 35. The second transfer plug 36 and the second transfer line 35 are connected in series on the conductive path between the second plug 32 and the second conductive connection line 31. Specifically, the bottom of the second plug 32 can also be indirectly electrically connected to a corresponding second conductive connection line 31 via a second transfer structure disposed on the semiconductor substrate and composed of the second transfer line 35 and the second transfer plug 36. It is only necessary to ensure that the second transfer structures corresponding to different second plugs 32 are electrically independent and insulated from each other, thereby ensuring that the electrically independent function of the independent test circuits is not lost.

[0076] When the second plug 32 is electrically connected to the corresponding second conductive connection line 31 through the second transfer structure, the bottom of the second plug 32 can be made higher or lower than the top of the second conductive connection line 31 in a direction perpendicular to the surface of the semiconductor substrate. Specifically, whether the bottom height of the second plug 32 is higher or lower than the top of the second conductive connection line 31 can be determined based on the specific positions of the second plug 32 and the second conductive connection line 31 and the preparation process.

[0077] In some embodiments, the bottom height of the second plug 32 is higher than the top of the second conductive connection line 31. At this time, in the vertical direction perpendicular to the semiconductor substrate, the second transfer plug 36 and the second transfer line 35 can be located between the bottom of the second plug 32 and the second conductive connection line 31, that is, the second transfer plug 36 can be connected to the upper surface of the second conductive connection line 31 and then extend upward to connect to the second transfer line 35, and the upper surface of the second transfer line 35 is connected to the bottom of the second plug 32.

[0078] For example, sometimes the second adapter plug 36 connected to the second conductive connection line 31 is not directly connected upward, but is first connected to the second adapter line 35 located at the lower layer of the second conductive connection line 31, and then connected to the upper layer through the second plug 32, that is, the bottom of the second plug 32 is lower than the second conductive connection line 31.

[0079] The present application is not limited thereto. In some embodiments, the second transfer structure includes a plurality of second transfer wires 35 and a plurality of second transfer plugs 36 . The second transfer wires 35 and the second transfer plugs 36 are alternately connected in series between the second plugs 32 and the second conductive connection line 31 .

[0080] Exemplary, reference Figure 4 and Figure 5 The semiconductor test structure also includes at least two second transfer lines 35, each extending along the second direction and spaced apart along the first direction. Each second transfer line 35 corresponds to a second conductive connection line 31 and is located below the corresponding second conductive connection line 31. The two adjacent second transfer lines 35 are insulated and separated by a dielectric material, thereby maintaining electrical independence from each other. Each second transfer line 35 is electrically connected to a corresponding second conductive connection line 31 through a second transfer plug 36, and is not connected to other second conductive connection lines 31, and is electrically independent from each other. Each second transfer line 35 corresponds to a second plug 32, and is directly in contact and electrically connected to the bottom of the corresponding second plug 32, and is not connected to other second plugs 32, and is electrically independent from each other. In this way, the bottom of the second plug 32 is electrically connected to the corresponding second conductive connection line 31 through the corresponding second transfer line 35 and the second transfer plug 36 in sequence, forming an electrically independent independent test circuit.

[0081] Exemplary, reference Figure 4 and Figure 5 The second transfer line 35 can be located in an adjacent metal layer below the second conductive connection line 31. Of course, the adjacent metal layers are insulated and separated by a dielectric layer. Exemplarily, there can also be at least one metal layer between the second transfer line 35 and the second conductive connection line 31, that is, the second transfer line 35 is not adjacent to the metal layer where the second conductive connection line 31 is located.

[0082] For example, in a direction perpendicular to the surface of the semiconductor substrate, the bottom height of the first plug 22 is the same as the bottom height of the second plug 32. It should be noted that this is applicable to a situation where the first plug 22 is directly connected to the first conductive connection line 21, and the second plug 32 is directly connected to the second conductive connection line 31. In this case, the first conductive connection line 21 and the second conductive connection line 31 are located on the same layer.

[0083] The above embodiment can also be applied to situations where the first plug 22 is connected to the first conductive connection line 21 via the first adapter structure, and / or the second plug 32 is connected to the second conductive connection line 31 via the second adapter structure. For example, in situations where both the first adapter structure and the second adapter structure are present, the first adapter line 25 and the second adapter line 35 can be located on the same layer, thereby ensuring that the bottom height of the first plug 22 and the bottom height of the second plug 32 are the same and are electrically connected to the top surface of the corresponding adapter line. For example, in situations where only the first adapter structure is present but not the second adapter structure, the first adapter line 25 and the second conductive connection line 31 can be located on the same layer, such that when the bottom heights of the first plug 22 and the second plug 32 are the same, the bottom of the first plug 22 contacts the top surface of the first adapter line 25, and the bottom of the second plug 32 contacts the top surface of the second conductive connection line 31. In the case where only the second transfer structure is provided but not the first transfer structure, the second transfer line 35 and the first conductive connection line 21 can be located on the same layer, so that when the bottom height of the first plug 22 is the same as the bottom height of the second plug 32, the bottom of the first plug 22 contacts the upper surface of the first conductive connection line 21, and the bottom of the second plug 32 contacts the upper surface of the second transfer line 35.

[0084] Thus, the first plug 22 and the second plug 32 can be prepared at the same time, and the wire connected to the first plug 22 (the first conductive connection wire 21 or the first adapter wire 25) and the wire connected to the second plug 32 (the second conductive connection wire 31 or the second adapter wire 35) can be prepared on the same layer, avoiding the preparation of deep holes of different depths, reducing the process difficulty, and thus reducing production costs.

[0085] In some embodiments, the tops of the at least two first plugs 22 and the at least two second plugs 32 in a direction perpendicular to the surface of the semiconductor substrate are higher than the tops of the test cells 10. Therefore, when the semiconductor test structure is ground from top to bottom, the tops of the first plugs 22 and the second plugs 32 can be exposed without grinding down to the test cells 10, thereby facilitating accurate location of failed test cells 10 in the test cell array.

[0086] For example, reference Figure 1A and Figure 1BThe top height of the test unit 10 in a direction perpendicular to the surface of the semiconductor substrate can be greater than the top height of the first conductive connection line 21 and the second conductive connection line 31 in a direction perpendicular to the surface of the semiconductor substrate. In this case, the top height of each first plug 22 in a direction perpendicular to the surface of the semiconductor substrate can be greater than the top height of the test unit 10. Consequently, when polishing the semiconductor test structure from top to bottom, the tops of the first plugs 22 can be exposed without polishing down to the test units 10, thus preventing damage to the test units 10 and facilitating accurate location of failed test units 10 in the test unit array.

[0087] For example, reference Figure 1A and Figure 1B When the top height of the test unit 10 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the first conductive connection line 21 and the second conductive connection line 31 in the direction perpendicular to the surface of the semiconductor substrate, the top height of each second plug 32 in the direction perpendicular to the surface of the semiconductor substrate can be greater than the top height of the test unit 10. Therefore, when the semiconductor test structure is polished from top to bottom, the top of the second plug 32 can be exposed without polishing to the test unit 10, without damaging the test unit 10, thereby facilitating accurate location of failed test units 10 in the test unit array.

[0088] Exemplary, reference Figure 2A and Figure 2B The semiconductor test structure may further include: a first common conductive line 23 located on top of the first plugs 22, the first common conductive line 23 electrically connecting at least two first plugs 22. For example, the extension direction of the first common conductive line 23 may be the same as the arrangement direction of the plurality of first plugs 22 and perpendicular to the extension direction of the first conductive connection line 21, thereby connecting all the first plugs 22. For example, referring to Figure 2A and Figure 2B The first common conductive line 23 extends along the second direction to electrically connect at least two first plugs 22 spaced apart along the second direction.

[0089] The above embodiment has the following beneficial effects: by forming a first common conductive line 23 electrically connecting at least two first plugs 22 on top of the first plugs 22, it is convenient to apply a voltage such as but not limited to a voltage V through the first common conductive line 23 to test the current flowing through the test unit array, thereby determining whether dielectric layer breakdown occurs.

[0090] It should be noted that the first common conductive line 23 and the at least two first plugs 22 may be electrically connected in a variety of ways, some of which are exemplified below.

[0091] Exemplary, reference Figure 2A and Figure 2B The first common conductive line 23 can be in direct contact and electrically connected with the top of the first plug 22 , thereby achieving direct electrical connection between the first common conductive line 23 and the first plug 22 .

[0092] In other embodiments, the first common conductive line 23 may be electrically connected to the first plug 22 via an interconnect structure composed of a conductive connection line and a metal plug disposed on the semiconductor substrate, thereby achieving indirect electrical connection between the first common conductive line 23 and the first plug 22 .

[0093] Exemplary, reference Figure 2A and Figure 2B The semiconductor test structure further includes: a second common conductive line 33 located on top of the second plugs 32, the second common conductive line 33 electrically connecting at least two second plugs 32. For example, the extension direction of the second common conductive line 33 can be the same as the arrangement direction of the plurality of second plugs 32 and perpendicular to the extension direction of the second conductive connection line 31, thereby connecting all the second plugs 32. For example, referring to Figure 2A and Figure 2B The second common conductive line 33 extends along the first direction to electrically connect at least two second plugs 32 spaced apart along the first direction.

[0094] The above embodiment has the following beneficial effects: by forming a second common conductive line 33 electrically connecting at least two second plugs 32 on top of the second plugs 32, it is convenient to apply a voltage such as but not limited to a voltage V through the second common conductive line 33 to test the current flowing through the test unit array, thereby determining whether dielectric layer breakdown occurs.

[0095] It should be noted that the second common conductive line 33 can be electrically connected to the at least two second plugs 32 in a variety of ways, some of which are exemplified below.

[0096] Exemplary, reference Figure 2A and Figure 2B The second common conductive line 33 can be in direct contact and electrically connected with the top of the second plug 32 , thereby achieving direct electrical connection between the second common conductive line 33 and the second plug 32 .

[0097] In other embodiments, the second common conductive line 33 may be electrically connected to the second plug 32 via an interconnect structure composed of a conductive connection line and a metal plug disposed on the semiconductor substrate, thereby achieving indirect electrical connection between the second common conductive line 33 and the second plug 32 .

[0098] Exemplarily, the first common conductive line 23 and the second common conductive line 33 are at the same height in a direction perpendicular to the surface of the semiconductor substrate. Specifically, the top height of the first plug 22 can be made the same as the top height of the second plug 32, and the first common conductive line 23 and the second common conductive line 33 are located on the same layer, so that the first common conductive line 23 and the second common conductive line 33 are directly electrically connected to the tops of the first plug 22 and the second plug 32, respectively. By arranging the first common conductive line 23 and the second common conductive line 33 at the same height, during the top-down polishing process of the semiconductor substrate, the tops of the first plug 22 and the second plug 32 can be exposed at a certain level.

[0099] Of course, in other embodiments, the first common conductive line 23 and the second common conductive line 33 may be located at different heights in the direction perpendicular to the surface of the semiconductor substrate, that is, the first common conductive line 23 and the second common conductive line 33 are located in different layers.

[0100] Exemplary, reference Figure 2A and Figure 2B The semiconductor test structure may further include: a first test pad 24 electrically connected to the first common conductive line 23, and a second test pad 34 electrically connected to the second common conductive line 33, the first test pad 24 and the second test pad 34 having the same height in a direction perpendicular to the surface of the semiconductor substrate.

[0101] The above embodiment has the following advantageous effects: by providing a first test pad 24 electrically connected to the first common conductive line 23 and a second test pad 34 electrically connected to the second common conductive line 33, when applying a voltage such as, but not limited to, a voltage V to the first common conductive line 23, the first test pad 24 can be used, thereby reducing the difficulty of applying the voltage such as, but not limited to, a voltage V to the first common conductive line 23. When applying a voltage such as, but not limited to, a voltage V to the second common conductive line 33, the second test pad 34 can be used, thereby reducing the difficulty of applying the voltage such as, but not limited to, a voltage V to the second common conductive line 33. Furthermore, by arranging the first test pad 24 and the second test pad 34 on the same layer of the semiconductor test structure, it is convenient to simultaneously apply a voltage such as, but not limited to, a voltage V to the first test pad 24 and the second test pad 34. For example, the current flowing through the test cell array can be tested to determine whether a dielectric layer breakdown has occurred.

[0102] It should be noted that the electrical connection between the first common conductive line 23 and the first test pad 24 can be achieved in a variety of ways.

[0103] In some embodiments, reference Figure 3The first common conductive line 23 and the first test pad 24 can be electrically connected in a direct contact manner. For example, the first common conductive line 23 and the first test pad 24 can be disposed on the same metal layer of the semiconductor substrate.

[0104] In some other embodiments, the first common conductive line 23 may also be electrically connected to the first test pad 24 through an interconnection structure formed by a conductive connection line and a metal plug disposed on the semiconductor substrate.

[0105] Similarly, the second common conductive line 33 and the second test pad 34 can be electrically connected in a variety of ways.

[0106] In some embodiments, reference Figure 3 The second common conductive line 33 and the second test pad 34 can be electrically connected in a direct contact manner. For example, the second common conductive line 33 and the second test pad 34 can be provided on the same metal layer of the semiconductor substrate.

[0107] In some other embodiments, the second common conductive line 33 may also be electrically connected to the second test pad 34 through an interconnection structure formed by a conductive connection line and a metal plug disposed on the semiconductor substrate.

[0108] Exemplarily, the first test pad 24 and the second test pad 34 can both be located at the top metal layer of the semiconductor test structure, so that the first test pad 24 and the second test pad 34 can be exposed to the semiconductor test structure and can be tested without grinding or damaging the interconnect structure. Optionally, the first test pad 24, the second test pad 34, the first common conductive line 23 and the second common conductive line 33 are all located at the top metal layer of the semiconductor test structure, and the first common conductive line 23 and the second common conductive line 33 are directly connected to the first plug 22 and the second plug 32, respectively. Optionally, the first common conductive line 23 and the second common conductive line 33 are both located at the top metal layer of the semiconductor test structure. Thus, the tops of the first plug 22 and the second plug 32 can be exposed without grinding or damaging the interconnect structure, and an independent test circuit can be formed for testing.

[0109] Exemplarily, one or N metal layers can be stacked above the first conductive connection line 21, but it is necessary to ensure that the first conductive connection line 21 and the corresponding first plug 22 are independently designed and electrically connected, and are insulated and isolated from other first conductive connection lines 21 and first plugs 22, are electrically independent, and do not interfere with each other. The first common conductive line 23 electrically connected to each of the first conductive connection lines 21 is electrically connected at the top metal layer of the stacked structure, and then connected to the first test pad 24. One or N metal layers can be stacked above the second conductive connection line 31, but it is necessary to ensure that the second conductive connection line 31 and the corresponding second plug 32 are independently designed and electrically connected, and are insulated and isolated from other second conductive connection lines 31 and second plugs 32, are electrically independent, and do not interfere with each other. The second common conductive line 33 electrically connected to each of the second conductive connection lines 31 is electrically connected at the top metal layer of the stacked structure, and then connected to the second test pad 34. The first test pad 24 and the second test pad 34 are located on the same layer.

[0110] For example, the test cell array may be a memory cell array composed of transistors and capacitor structures. Figure 1A and Figure 1B One of the first conductive connection line 21 and the second conductive connection line 31 may be a word line (WL), and the other conductive connection line may be a bit line (BL).

[0111] Exemplary, reference Figure 2A and Figure 2B A semiconductor test structure is shown, in which a first conductive connection line 21 is a bit line (BL) and a second conductive connection line 31 is a word line (WL). The second conductive connection line 31 and the first conductive connection line 21 are located on different layers. The second conductive connection line 31 on the upper layer is designed perpendicular to the first conductive connection line 21 on the lower layer. An array of test cells, such as but not limited to transistors and / or capacitor structures, is arranged at the cross-over position.

[0112] Multiple first conductive connection lines 21 are electrically independently designed. Each first conductive connection line 21 is electrically connected by a corresponding first plug 22 and connected to the metal layer above it. A first common conductive line 23 is provided in the metal layer above it. The first common conductive line 23 electrically connects the tops of all the first plugs 22, so that all the first conductive connection lines 21 are electrically connected through the first common conductive line 23 and then led out through the first test pad 24 on the same layer.

[0113] Multiple second conductive connection lines 31 are electrically independently designed. Each second conductive connection line 31 is electrically connected by a corresponding second plug 32 and connected to the metal layer above it. A second common conductive line 33 is provided in the metal layer above it. The second common conductive line 33 electrically connects the tops of all the second plugs 32, so that all the second conductive connection lines 31 are electrically connected through the second common conductive line 33 and then led out through the second test pad 34 on the same layer.

[0114] Figure 2A and Figure 2B The semiconductor test structure shown differs from existing test structures in that an independent first plug 22 is designed to electrically connect each first conductive connection line 21 to the first common conductive line 23, and an independent second plug 32 is designed to electrically connect each second conductive connection line 31 to the second common conductive line 33. This structure is characterized by providing independent circuitry for each test cell 10 in the test cell array.

[0115] against Figure 2A and Figure 2B The advantage of the semiconductor test structure shown is that a failed test unit 10 can be located more quickly and accurately. A failure analysis method for the semiconductor test structure is exemplarily introduced below.

[0116] After confirming that there is a failed unit in the test unit array, an electrical failure analysis is performed to locate the failed test unit 10: first, the first test pad 24, the second test pad 34, the first common conductive line 23 and the second common conductive line 33 are removed by planarization. The planarization process can be chemical mechanical polishing to obtain the following Figure 1A and Figure 1B The results shown expose the tops of the first plugs 22 and the second plugs 32. At this point, each test cell 10 in the test cell array is connected via an independent test circuit formed by the first plugs 22, the first conductive connection line 21, the second conductive connection line 31, and the second plugs 32. Subsequently, a first test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two first plugs 22, and a second test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two second plugs 32. Several test cells 10 are then tested sequentially to identify failed test cells 10. For example, after OBIRCH can be used to locate a large area using a bright spot, the EBIRCH probe can then be sequentially inserted into each first plug 22 corresponding to a first conductive connection line 21 and each second plug 32 corresponding to a second conductive connection line 31 for scanning measurement, allowing the failed test cell 10 to be quickly and accurately located.

[0117] Exemplary, reference Figure 7A and Figure 7B The semiconductor test structure further includes a third common conductive line 27 located on a side of the first plug 22 away from the test unit array and electrically connected to at least two first conductive connection lines 21. The third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb-tooth structure. Specifically, the third common conductive line 27 and the first conductive connection lines 21 are located in the same layer and electrically connected to the same end of the at least two first conductive connection lines 21, thereby forming the first comb-tooth structure together with the at least two first conductive connection lines 21. In this case, the connection point between the bottom of the first plug 22 and the first conductive connection line 21 is located between the third common conductive line 27 and the test unit array.

[0118] For example, reference Figure 7A and Figure 7B The third common conductive line 27 extends along the second direction. The third common conductive line 27 is located on the side of the first plug 22 away from the test unit array and is electrically connected to the first ends of at least two first conductive connection lines 21. The third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb tooth structure.

[0119] Specifically, refer to Figure 7A and Figure 7B A third common conductive line 27 is also provided on the semiconductor substrate. The third common conductive line 27 extends along the second direction and is located on a side of the first plug 22 away from the test cell array. Specifically, the first plug 22 is located between the test cell array and the third common conductive line 27. The electrical connection point between the first plug 22 and a corresponding first conductive connection line 21 is located between the third common conductive line 27 and the test cell array. Furthermore, the third common conductive line 27 electrically connects the first ends of at least two first conductive connection lines 21, thereby forming a first comb-tooth structure with the at least two first conductive connection lines 21. Specifically, the third common conductive line 27 and the at least two first conductive connection lines 21 are located on the same metal layer and are directly electrically connected to each other.

[0120] The above embodiment has the following beneficial effects: by providing a third common conductive line 27 on the basis of the first plug 22, the third common conductive line 27 is located on the side of the first plug 22 away from the test unit array and is electrically connected to the first ends of at least two first conductive connection lines 21, and the third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb tooth structure, so that the first plug 22 can be used as a redundant plug to facilitate locating failed test units 10 when performing electrical failure analysis on the semiconductor test structure.

[0121] The above embodiment is similar to the existing test structure in that each regularly arranged first conductive connection line 21 is electrically connected to the third common conductive line 27 on the same layer. The above embodiment differs from the existing test structure in that redundant, electrically independent first plugs 22 are provided on each regularly arranged first conductive connection line 21 between the test cell array and the third common conductive line 27. This structure is characterized by providing an electrically independent, independent test circuit for each test cell 10 in the test cell array after the third common conductive line 27 is removed by cutting or other means, thereby facilitating the rapid location of failed test cells 10.

[0122] Regarding the lead-out method of the first plug 22, it can be extended upward by at least one metal layer. Preferably, the top height of the first plug 22 is higher than the top height of the test unit 10. Preferably, the first plug 22 can be directly extended to the top metal layer of the semiconductor test structure to provide an electrically independent independent test circuit for each first conductive connection line 21, thereby cooperating with the second conductive connection line 31 to provide an electrically independent independent test circuit for each test unit 10.

[0123] Exemplary, reference Figure 7A and Figure 7B The semiconductor test structure may further include: a third test pad 28 electrically connected to the third common conductive line 27 .

[0124] The above embodiment has the following beneficial effects: by providing a third test pad 28 electrically connected to the third common conductive line 27, when applying a voltage such as but not limited to a voltage V to the third common conductive line 27, the difficulty of applying a voltage such as but not limited to a voltage V to the third common conductive line 27 can be reduced with the help of the third test pad 28.

[0125] It should be noted that the third common conductive line 27 and the third test pad 28 may be electrically connected in a variety of ways.

[0126] In some embodiments, reference Figure 7A and Figure 7B A direct contact electrical connection may be adopted between the third common conductive line 27 and the third test pad 28. For example, the third common conductive line 27 and the third test pad 28 may be provided on the same metal layer of the semiconductor substrate.

[0127] In other embodiments, the third common conductive line 27 can also be electrically connected to the third test pad 28 through an interconnection structure formed by a conductive connecting line and a metal plug arranged on the semiconductor substrate, thereby allowing the third test pad 28 to be arranged in any metal layer, for example, allowing the third test pad 28 to be arranged in the top metal layer, which can reduce the difficulty of applying voltages such as but not limited to voltage V to the third test pad 28.

[0128] Exemplary, reference Figure 7A and Figure 7B The semiconductor test structure further includes a fourth common conductive line 37 located on a side of the second plug 32 away from the test unit array and electrically connected to at least two second conductive connection lines 31. The fourth common conductive line 37 and the at least two second conductive connection lines 31 form a second comb-tooth structure. Specifically, the fourth common conductive line 37 and the second conductive connection lines 31 are located in the same layer and electrically connected to the same end of the at least two second conductive connection lines 31, thereby forming the second comb-tooth structure together with the at least two second conductive connection lines 31. In this case, the connection point between the bottom of the second plug 32 and the second conductive connection line 31 is located between the fourth common conductive line 37 and the test unit array.

[0129] For example, reference Figure 7A and Figure 7B The fourth common conductive line 37 extends along the first direction. The fourth common conductive line 37 is located on the side of the second plug 32 away from the test unit array and is electrically connected to the first ends of at least two second conductive connection lines 31. The fourth common conductive line 37 and the at least two second conductive connection lines 31 form a second comb tooth structure.

[0130] Specifically, refer to Figure 7A and Figure 7B A fourth common conductive line 37 is also disposed on the semiconductor substrate. The fourth common conductive line 37 extends along the first direction and is located on a side of the second plug 32 away from the test cell array. Specifically, the second plug 32 is located between the test cell array and the fourth common conductive line 37. The electrical connection point between the second plug 32 and a corresponding second conductive connection line 31 is located between the fourth common conductive line 37 and the test cell array. Furthermore, the fourth common conductive line 37 electrically connects the first ends of at least two second conductive connection lines 31, thereby forming a second comb-tooth structure with the at least two second conductive connection lines 31. Specifically, the fourth common conductive line 37 and the at least two second conductive connection lines 31 are located on the same metal layer, and are directly electrically connected to each other.

[0131] The above embodiment has the following beneficial effects: by providing a fourth common conductive line 37 on the basis of the second plug 32, the fourth common conductive line 37 is located on the side of the second plug 32 away from the test unit array and is electrically connected to the first ends of at least two second conductive connection lines 31, and the fourth common conductive line 37 and the at least two second conductive connection lines 31 form a second comb-tooth structure, so that the second plug 32 can be used as a redundant plug to facilitate locating failed test units 10 when performing electrical failure analysis on the semiconductor test structure.

[0132] The above embodiment differs from existing test structures in that redundant, electrically independent second plugs 32 are designed on each of the regularly arranged second conductive connection lines 31 between the test cell array and the fourth common conductive line 37. This structure is characterized by providing an electrically independent, independent test circuit for each test cell 10 in the test cell array after the fourth common conductive line 37 is removed by cutting or other means, thereby facilitating rapid location of failed test cells 10.

[0133] The second plug 32 may be extended upward by at least one metal layer. Preferably, the top height of the second plug 32 is higher than the top height of the test unit 10. Preferably, the second plug 32 may be extended directly to the top metal layer of the semiconductor test structure to provide an electrically independent test circuit for each second conductive connection line 31, thereby cooperating with the first conductive connection line 21 to provide an electrically independent test circuit for each test unit 10.

[0134] Exemplary, reference Figure 7A and Figure 7B The semiconductor test structure may further include: a fourth test pad 38 electrically connected to the fourth common conductive line 37 .

[0135] The above embodiment has the following beneficial effects: by providing a fourth test pad 38 electrically connected to the fourth common conductive line 37, when applying a voltage such as but not limited to a voltage V to the fourth common conductive line 37, the fourth test pad 38 can be used to reduce the difficulty of applying a voltage such as but not limited to a voltage V to the fourth common conductive line 37.

[0136] It should be noted that the fourth common conductive line 37 and the fourth test pad 38 may be electrically connected in a variety of ways.

[0137] In some embodiments, reference Figure 7A and Figure 7B A direct contact electrical connection may be adopted between the fourth common conductive line 37 and the fourth test pad 38. For example, the fourth common conductive line 37 and the fourth test pad 38 may be provided on the same metal layer of the semiconductor substrate.

[0138] In other embodiments, the fourth common conductive line 37 can also be electrically connected to the fourth test pad 38 through an interconnection structure formed by a conductive connecting line and a metal plug arranged on the semiconductor substrate, thereby allowing the fourth test pad 38 to be arranged in any metal layer, for example, allowing the fourth test pad 38 to be arranged in the top metal layer, which can reduce the difficulty of applying voltages such as but not limited to voltage V to the fourth test pad 38.

[0139] With respect to the above-mentioned solution including the third comb-tooth structure, the first plug 22 , the fourth comb-tooth structure, and the second plug 32 , a failure analysis method is exemplarily introduced as follows.

[0140] refer to Figure 7A and Figure 7B After an electrical breakdown occurs, when an electrical failure analysis is performed to locate the failed test unit 10, since the third test pad 28, the third common conductive line 27, the fourth test pad 38, and the fourth common conductive line 37 are all located outside the first plug 22 and the second plug 32, the third test pad 28, the third common conductive line 27, the fourth test pad 38, and the fourth common conductive line 37 can be removed by cutting, such as by sawing or laser cutting, as shown in FIG. Figure 7C and Figure 7D The first and second plugs 22, 32 involved in the retained structure are then removed. The upper layer of the semiconductor test structure is then milled away until the tops of the first and second plugs 22, 32 are exposed. This indicates that each of the closely spaced test cells 10 in the underlying test cell array structure is electrically independent. Using a probe to sequentially penetrate each first and second plugs 22, 32 allows for quick and accurate location of the failed test cell 10.

[0141] In some other embodiments, the semiconductor test structure may further include: a first common conductive line 23 located on top of the first plugs 22 , the first common conductive line 23 electrically connecting at least two first plugs 22 ; and The fourth common conductive line 37 is located on a side of the second plug 32 away from the test unit array and electrically connects at least two second conductive connection lines 31 . The fourth common conductive line 37 and the at least two second conductive connection lines 31 form a second comb-tooth structure.

[0142] Specifically, in this embodiment, the combination of the first common conductive line 23 and the second comb-tooth structure in the above embodiment is adopted. Therefore, when performing failure analysis on the semiconductor test structure, the semiconductor test structure can be ground from top to bottom to expose the tops of the first plug 22 and the second plug 32, and the fourth common conductive line 37 can be cut off to obtain the first plug 22 and the second plug 32 that are electrically independently arranged. Thereafter, the above-mentioned failure analysis method can be used for testing.

[0143] For example, after confirming that a failed test cell 10 exists in the test cell array, the semiconductor test structure is cut along the area between the second plug 32 and the fourth common conductive line 37 to disconnect the electrical connection between the fourth common conductive line 37 and the second conductive connection line 31. The second conductive connection line 31 can provide an independent test circuit for the test cell 10 in the test cell array. refer to Figure 7C and Figure 7D , thinning the semiconductor test structure to expose tops of the first plugs 22 and the second plugs 32 in a direction perpendicular to the surface of the semiconductor substrate. The thinning process, such as a planarization process, removes the first common conductive line 23 through the thinning process, so that the first conductive connection line 21 can provide an independent test circuit for the test unit 10 in the test unit array; The first test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two first plugs 22 , and the second test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two second plugs 32 , and several test units 10 are tested in sequence to find failed test units 10 .

[0144] It should be understood that the staggered and spaced arrangement of the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure is not limited to the above-mentioned staggered and spaced arrangement of the two in different layers. In addition, other methods can also be used.

[0145] For example, in other embodiments, the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure are arranged in an interlaced and spaced manner to form interlaced spaces between the interlaced first conductive connection lines 21 and second conductive connection lines 31. This may include: the extension directions of the first conductive connection lines 21 and the second conductive connection lines 31 are parallel, the first conductive connection lines 21 and the second conductive connection lines 31 are located in the same or different layers, the first conductive connection lines 21 and the second conductive connection lines 31 are adjacent to each other in a one-to-one correspondence to interlace, and one or more interlaced spaces are formed between adjacent first conductive connection lines 21 and second conductive connection lines 31. That is, in this embodiment, the extension directions of the first conductive connection lines 21 and the extension directions of the second conductive connection lines 31 are arranged in parallel, the first conductive connection lines 21 and the second conductive connection lines 31 are adjacent to each other in a one-to-one correspondence to interlace, thereby forming interlaced spaces between adjacent first conductive connection lines 21 and second conductive connection lines 31. In this case, different arrangement methods can be adopted depending on whether the first conductive connection lines 21 and the second conductive connection lines 31 are located in the same layer or different layers. They are described below.

[0146] First, in some embodiments, the first conductive connection lines 21 and the second conductive connection lines 31 are located in different layers. Specifically, the first conductive connection lines 21 can be located above the second conductive connection lines 31 and insulated and spaced apart by an interlayer dielectric layer, or the second conductive connection lines 31 can be located above the first conductive connection lines 21 and insulated and spaced apart by an interlayer dielectric layer. In this case, the plurality of first conductive connection lines 21 and the plurality of second conductive connection lines 31 are respectively arranged horizontally in different layers along the same direction, parallel to each other and spaced apart. Specifically, the plurality of first conductive connection lines 21 are arranged horizontally and spaced apart in a direction perpendicular to the extension direction of the first conductive connection lines 21 in the layer in which they are located, and the plurality of second conductive connection lines 31 are arranged horizontally and spaced apart in a direction perpendicular to the extension direction of the second conductive connection lines 31 in the layer in which they are located. Since the extension directions of the first conductive connection lines 21 and the second conductive connection lines 31 are parallel, the arrangement directions of the plurality of first conductive connection lines 21 and the plurality of second conductive connection lines 31 are also parallel.

[0147] In this case, each first conductive connection line 21 corresponds to a second conductive connection line 31 and is interlaced with the corresponding second conductive connection line 31 at least in the vertical direction (a direction perpendicular to the surface of the semiconductor substrate), with the spacing between adjacent first conductive connection lines 21 and second conductive connection lines 31 serving as the interlaced space. Furthermore, each first conductive connection line 21 and the corresponding second conductive connection line 31 can be arranged to overlap or stagger in the vertical direction. Specifically, when the first conductive connection line 21 and the corresponding second conductive connection line 31 are arranged directly opposite each other in the vertical direction, the two are arranged to overlap in the vertical direction; when the first conductive connection line 21 and the corresponding second conductive connection line 31 are not arranged directly opposite each other in the vertical direction, that is, the first conductive connection line 21 and the corresponding second conductive connection line 31 are partially staggered in the vertical direction, the two are staggered in the vertical direction.

[0148] The number of interleaved spaces formed in the spaces between adjacent first conductive connection lines 21 and second conductive connection lines 31 is determined according to the number of test units 10 provided. Specifically, if one test unit 10 is provided in the spaces between adjacent first conductive connection lines 21 and second conductive connection lines 31, the spaces between the adjacent first conductive connection lines 21 and second conductive connection lines 31 are considered as an interleaved space to provide one test unit 10. If multiple test units 10 are provided in the spaces between adjacent first conductive connection lines 21 and second conductive connection lines 31, for example, multiple test units 10 are arranged along the extension direction of the first conductive connection lines 21, the spaces between the adjacent first conductive connection lines 21 and second conductive connection lines 31 are further divided into multiple subspaces, each of which is considered as an interleaved space to provide one test unit 10.

[0149] For ease of distinction, the following embodiment is briefly described by taking the third conductive connection line replacing the above-mentioned second conductive connection line 31 and the third plug replacing the above-mentioned second plug as an example, and the parts not described below can refer to the aforementioned connection and lead-out methods of the second conductive connection line 31 and the second plug.

[0150] refer to Figure 3 and Figure 6The semiconductor test structure may include: at least two third conductive connection lines 41 located on the semiconductor substrate and extending along a first direction, the at least two third conductive connection lines 41 being spaced apart along a second direction intersecting the first direction, that is, two adjacent third conductive connection lines 41 are insulated and separated by a dielectric material, thereby being electrically independent of each other. The third conductive connection line 41 and the first conductive connection line 21 are located on different planes in a direction perpendicular to the surface of the semiconductor substrate, that is, the first conductive connection line 21 and the third conductive connection line 41 are located on different metal layers of the semiconductor test structure. Specifically, the third conductive connection line 41 is parallel to the extension direction of the first conductive connection line 21 and is located directly above the first conductive connection line 21. The multiple third conductive connection lines 41 are spaced apart along the second direction. Each first conductive connection line 21 and the third conductive connection line 41 are spaced apart in a vertical direction perpendicular to the surface of the semiconductor substrate so that there is a spacing space between the two. The spacing space serves as one or more interlaced spaces between the two, so that part or all of the structure of the test unit 10 can be set in the spacing space between the first conductive connection line 21 and the third conductive connection line 41 in the vertical direction.

[0151] Exemplary, reference Figure 3 and Figure 6 The semiconductor test structure may further include: at least two third plugs 42 disposed outside the test cell array and spaced apart from each other, each third plug 42 corresponding to a third conductive connection line 41, and each third plug 42 electrically connected to a corresponding third conductive connection line 41 to form an electrically independent test circuit. Specifically, different third plugs 42 are insulated and separated by a dielectric material such as, but not limited to, oxide, and different third conductive connection lines 41 are also insulated and separated by a dielectric material such as, but not limited to, oxide. Thus, each third plug 42 is electrically connected only to its corresponding third conductive connection line 41, and is insulated and separated from other third conductive connection lines 41 by a dielectric material, thereby being electrically independent of each other.

[0152] Furthermore, the top heights of at least two first plugs 22 and at least two third plugs 42, in a direction perpendicular to the surface of the semiconductor substrate, are greater than the top heights of at least two first conductive connection lines 21 and at least two third conductive connection lines 41. Specifically, the top heights of all first plugs 22 are greater than the top heights of all first conductive connection lines 21 and third conductive connection lines 41. Furthermore, the top heights of all third plugs 42 are greater than the top heights of all first conductive connection lines 21 and third conductive connection lines 41. That is, the top height of each third plug 42, in a direction perpendicular to the surface of the semiconductor substrate, is greater than the top heights of at least two first conductive connection lines 21 and at least two third conductive connection lines 41. This provides an independent lead-out circuit for each third conductive connection line 41. Consequently, during top-down polishing of the semiconductor test structure, the tops of the first plugs 22 and third plugs 42 are exposed before the tops of the first conductive connection lines 21 and third conductive connection lines 41.

[0153] The lead-out method of the third plug 42 can also be applied to the arrangement method of the aforementioned second common conductive line 33, second test pad 34, fourth common conductive line 37, fourth test pad 38, second transfer line 35 and second transfer plug 36. It is only necessary to replace the aforementioned second plug 32 with the third plug 42, and adaptively adjust the arrangement position and extension direction of the second common conductive line 33, second test pad 34, fourth common conductive line 37, fourth test pad 38, second transfer line 35 and second transfer plug 36.

[0154] It should be noted that in some other embodiments, in addition to the first and second conductive connection lines 21 and 31 located on different layers and intersecting with each other, the semiconductor test structure may further include a third conductive connection line located on a different layer from at least one of the first and second conductive connection lines 21 and 31. This is described in detail below.

[0155] Exemplary, reference Figure 3 and Figure 6 The semiconductor test structure may further include: a third conductive connection structure located on the semiconductor substrate. The third conductive connection structure includes at least two third conductive connection lines 41 extending along a third direction, and the at least two third conductive connection lines 41 are spaced apart along a fourth direction intersecting the third direction, that is, two adjacent third conductive connection lines 41 are insulated and separated by a dielectric material, so that they are electrically independent of each other. The third conductive connection line 41 and the first conductive connection line 21 and the second conductive connection line 31 are located on three different planes in a direction perpendicular to the surface of the semiconductor substrate, that is, the first conductive connection line 21, the second conductive connection line 31 and the third conductive connection line 41 are located on different metal layers of the semiconductor test structure.

[0156] The third direction is arranged to intersect at least one of the first and second directions, so that the test unit 10 can also be located at the intersection of the third conductive connection line 41 and at least one of the first and second conductive connection lines 21 and 31, so that the test unit 10 can be electrically connected to the third conductive connection line 41. Similarly, the above-mentioned intersecting arrangement is arranged in such a way that there is an angle such as but not limited to 90° between the two directions, so that the two directions can intersect. For example, the third direction can be arranged to intersect with the first direction and be parallel to the second direction; the third direction can also be arranged to intersect with the second direction and be parallel to the first direction; or the third direction can be arranged to intersect with both the first and second directions. The fourth direction only needs to be arranged to intersect with the third direction, and there is no need to limit whether the fourth direction is arranged to intersect with the first and second directions. In some embodiments, the fourth direction can be arranged parallel to one of the first and second directions.

[0157] Exemplary, reference Figure 3 , the third conductive connection line 41 is parallel to the extension direction of the first conductive connection line 21 and is located directly above the first conductive connection line 21. Multiple third conductive connection lines 41 are arranged at intervals along the second direction. That is, in this embodiment, the third direction is arranged parallel to the first direction, and the fourth direction is arranged parallel to the second direction. The third conductive connection line 41 can also be electrically connected to the test unit 10. For example, when the test unit 10 is a vertical MOS transistor structure, the third conductive connection line 41 can be electrically connected to the drain of the vertical transistor structure, the first conductive connection line 21 is connected to the source of the vertical transistor structure, and the second conductive connection line 31 is connected to the gate of the vertical transistor structure. The first conductive connection line 21, the second conductive connection line 31 and the third conductive connection line 41 are arranged in a cross shape, and the test unit 10 is electrically connected at the intersection to form a test unit array.

[0158] Exemplary, reference Figure 3 The semiconductor test structure may further include: at least two third plugs 42 disposed outside the test cell array and spaced apart from each other, each third plug 42 corresponding to a third conductive connection line 41, and each third plug 42 electrically connected to a corresponding third conductive connection line 41 to form an electrically independent test circuit. Specifically, different third plugs 42 are insulated and separated by a dielectric material such as, but not limited to, oxide, and different third conductive connection lines 41 are also insulated and separated by a dielectric material such as, but not limited to, oxide. Thus, each third plug 42 is electrically connected only to its corresponding third conductive connection line 41, and is insulated and separated from other third conductive connection lines 41 by a dielectric material, thereby being electrically independent of each other.

[0159] Furthermore, the top heights of the at least two first plugs 22, the at least two second plugs 32, and the at least two third plugs 42 in a direction perpendicular to the surface of the semiconductor substrate are all greater than the top heights of the at least two first conductive connection lines 21, the at least two second conductive connection lines 31, and the at least two third conductive connection lines 41. Specifically, the top heights of all first plugs 22 are higher than the top heights of all first conductive connection lines 21, the second conductive connection lines 31, and the third conductive connection lines 41, and the top heights of all second plugs 32 are higher than the top heights of all first conductive connection lines 21, the second conductive connection lines 31, and the third conductive connection lines 41. For details, please refer to the corresponding descriptions of the first plugs 22 and the second plugs 32 above.

[0160] Furthermore, the top height of all third plugs 42 is higher than the top height of all first conductive connection lines 21, second conductive connection lines 31, and third conductive connection lines 41. That is, the top height of each third plug 42, in a direction perpendicular to the surface of the semiconductor substrate, is higher than the top heights of at least two first conductive connection lines 21, at least two second conductive connection lines 31, and at least two third conductive connection lines 41. This provides an independent lead-out circuit for each third conductive connection line 41. Consequently, when polishing the semiconductor test structure from top to bottom, the tops of the first plugs 22, second plugs 32, and third plugs 42 are exposed before the tops of the first conductive connection lines 21, second conductive connection lines 31, and third conductive connection lines 41.

[0161] Exemplary, reference Figure 3 The third plug 42 and the first plug 22 are respectively located on two opposite sides of the test unit array.

[0162] It should be noted that the third plug 42 and the third conductive connection line 41 can be electrically connected in a variety of ways, some of which are exemplified below.

[0163] Exemplary, reference Figure 3 The bottom of the third plug 42 can be in direct contact and electrically connected to a corresponding third conductive connection line 41 , thereby achieving electrical connection between the third plug 42 and the third conductive connection line 41 .

[0164] However, sometimes, due to the spatial arrangement and process sequence in the manufacturing process, the bottom of the third plug 42 will not be directly electrically connected to the corresponding third conductive connection line 41. In other embodiments, the bottom of the third plug 42 can also be indirectly electrically connected to the corresponding third conductive connection line 41 through a third transfer structure composed of a third transfer line 45 and a third transfer plug 46 disposed on the semiconductor substrate. It is only necessary to ensure that the third transfer structures corresponding to different third plugs 42 are electrically independent of each other and separated by insulating material to ensure that the electrically independent function of the independent test circuit is not lost.

[0165] For example, sometimes the third adapter plug 46 connected to the third conductive connection line 41 is not directly connected upward, but is first connected to the third adapter line 45 located at the lower layer of the third conductive connection line 41, and then connected to the upper layer through the third plug 42, that is, the bottom of the third plug 42 is lower than the third conductive connection line 41.

[0166] The present application is not limited thereto. In some embodiments, the third transfer structure includes a plurality of third transfer wires 45 and a plurality of third transfer plugs 46 . The third transfer wires 45 and the third transfer plugs 46 are alternately connected in series between the third plugs 42 and the third conductive connection line 41 .

[0167] Exemplary, reference Figure 6 The semiconductor test structure further includes at least two third transfer lines 45, each extending along the third direction and spaced apart along the fourth direction. Exemplarily, the first direction is parallel to the third direction, and the second direction is parallel to the fourth direction. Each third transfer line 45 corresponds to a third conductive connection line 41 and is located below the corresponding third conductive connection line 41. Adjacent third transfer lines 45 are insulated and separated by dielectric material, thereby maintaining electrical independence from each other. Each third transfer line 45 is electrically connected to the corresponding third conductive connection line 41 via a third transfer plug 46, but is not connected to any other third conductive connection lines 41, and is therefore electrically independent from each other. Furthermore, each third transfer line 45 corresponds to a third plug 42 and is directly in electrical contact with the bottom of the corresponding third plug 42, but is not connected to any other third plugs 42, and is therefore electrically independent from each other. Thus, the bottom of the third plug 42 is electrically connected to the corresponding third conductive connection line 41 via the corresponding third transfer line 45 and third transfer plug 46, sequentially, to form an electrically independent test circuit.

[0168] For example, the third transition line 45 may be located in an adjacent metal layer below the third conductive connection line 41, with the adjacent metal layers being insulated and separated by a dielectric layer. For example, at least one metal layer may be located between the third transition line 45 and the third conductive connection line 41, i.e., the third transition line 45 and the third conductive connection line 41 are not adjacent to each other in the metal layer.

[0169] Exemplary, reference Figure 6 The semiconductor test structure may further include: a fifth common conductive line 43 located on top of the third plugs 42 and extending along the second direction, the fifth common conductive line 43 electrically connecting at least two third plugs 42 .

[0170] The above embodiment has the following beneficial effects: by forming a fifth common conductive line 43 electrically connecting at least two third plugs 42 on top of the third plugs 42, it is convenient to apply a voltage such as but not limited to a voltage V through the fifth common conductive line 43 to perform a test, for example, to test the current flowing through the test unit array, thereby determining whether a dielectric layer breakdown occurs.

[0171] It should be noted that the fifth common conductive line 43 can be electrically connected to the at least two third plugs 42 in a variety of ways, some of which are exemplified below.

[0172] Exemplary, reference Figure 6 , the fifth common conductive line 43 can be in direct contact and electrically connected with the top of the third plug 42 , thereby achieving direct electrical connection between the fifth common conductive line 43 and the third plug 42 .

[0173] In other embodiments, the fifth common conductive line 43 may be electrically connected to the third plug 42 via an interconnect structure composed of a conductive connection line and a metal plug disposed on the semiconductor substrate, thereby achieving indirect electrical connection between the fifth common conductive line 43 and the third plug 42 .

[0174] Exemplary, reference Figure 6 The semiconductor test structure may further include: a fifth test pad 44 electrically connected to the fifth common conductive line 43 .

[0175] The above embodiment has the following beneficial effects: by providing a fifth test pad 44 electrically connected to the fifth common conductive line 43, when applying a voltage such as but not limited to a voltage V to the fifth common conductive line 43, the difficulty of applying a voltage such as but not limited to a voltage V to the fifth common conductive line 43 can be reduced with the help of the fifth test pad 44.

[0176] It should be noted that the fifth common conductive line 43 and the fifth test pad 44 may be electrically connected in a variety of ways.

[0177] In some embodiments, reference Figure 6 A direct contact electrical connection may be adopted between the fifth common conductive line 43 and the fifth test pad 44. For example, the fifth common conductive line 43 and the fifth test pad 44 may be provided on the same metal layer of the semiconductor substrate.

[0178] In some other embodiments, the fifth common conductive line 43 may also be electrically connected to the fifth test pad 44 through an interconnection structure formed by a conductive connection line and a metal plug disposed on the semiconductor substrate.

[0179] Preferably, the fifth common conductive line 43 and the fifth test pad 44 are both arranged on the top metal layer. Therefore, when the fifth common conductive line 43 and the fifth test pad 44 are removed to form an independent circuit of the third plug 42, the interconnection structure of other metal layers of the test structure may not be affected.

[0180] Correspondingly, in the aforementioned embodiment in which the third conductive connection line 41 and the third plug 42 are provided, the following arrangement may also be adopted.

[0181] Exemplary, reference Figure 8 The semiconductor test structure may further include a sixth common conductive line 47 extending along a fourth direction. The sixth common conductive line 47 is located on a side of the third plug 42 away from the test unit array and electrically connects the first ends of at least two third conductive connection lines 41. The sixth common conductive line 47 and the at least two third conductive connection lines 41 form a third comb-tooth structure. Exemplarily, the second direction is arranged parallel to the fourth direction.

[0182] Specifically, refer to Figure 8 A sixth common conductive line 47 is also disposed on the semiconductor substrate. The sixth common conductive line 47 extends along the fourth direction and is located on a side of the third plug 42 away from the test cell array. Specifically, the third plug 42 is located between the test cell array and the sixth common conductive line 47. The electrical connection point between the third plug 42 and a corresponding third conductive connection line 41 is located between the sixth common conductive line 47 and the test cell array. Furthermore, the sixth common conductive line 47 is electrically connected to the first ends of at least two third conductive connection lines 41, thereby forming a third comb-tooth structure with the at least two third conductive connection lines 41. Specifically, the sixth common conductive line 47 and the at least two third conductive connection lines 41 are located on the same metal layer, and are directly electrically connected to the third conductive connection lines 41.

[0183] The above embodiment has the following beneficial effects: by providing a sixth common conductive line 47 on the basis of the third plug 42, the sixth common conductive line 47 is located on the side of the third plug 42 away from the test unit array and is electrically connected to the first ends of at least two third conductive connection lines 41, and the sixth common conductive line 47 and the at least two third conductive connection lines 41 form a third comb-tooth structure, so that the third plug 42 can be used as a redundant plug to facilitate locating failed test units 10 when performing electrical failure analysis on the semiconductor test structure.

[0184] The above embodiment is similar to the existing test structure in that each regularly arranged third conductive connection line 41 is electrically connected to the sixth common conductive line 47 on the same layer. The above embodiment differs from the existing test structure in that an electrically independent third plug 42 is designed on each regularly arranged third conductive connection line 41 and between the test cell array and the sixth common conductive line 47 to provide electrical connection. This structure is characterized by providing an electrically independent test circuit for each test cell 10 in the test cell array after the sixth common conductive line 47 is removed by cutting or other means, facilitating rapid location of failed test cells 10.

[0185] The third plug 42 may be extended upward by at least one metal layer until the top height of the third plug 42 is higher than the top height of the test unit 10. The third plug 42 may be directly extended to the top metal layer of the semiconductor test structure, providing an electrically independent test circuit for each third conductive connection line 41, thereby cooperating with the second conductive connection line 31 to provide an electrically independent test circuit for each test unit 10.

[0186] Exemplary, reference Figure 8 The semiconductor test structure may further include a sixth test pad 48 electrically connected to the sixth common conductive line 47 .

[0187] The above embodiment has the following beneficial effects: by providing a sixth test pad 48 electrically connected to the sixth common conductive line 47, when applying a voltage such as but not limited to a voltage V to the sixth common conductive line 47, the sixth test pad 48 can be used to reduce the difficulty of applying a voltage such as but not limited to a voltage V to the sixth common conductive line 47.

[0188] It should be noted that the sixth common conductive line 47 and the sixth test pad 48 may be electrically connected in a variety of ways.

[0189] In some embodiments, reference Figure 8 The sixth common conductive line 47 and the sixth test pad 48 may be electrically connected in direct contact. For example, the sixth common conductive line 47 and the sixth test pad 48 may be disposed on the same metal layer of the semiconductor substrate.

[0190] In other embodiments, the sixth common conductive line 47 may be electrically connected to the sixth test pad 48 via an interconnect structure formed by a conductive connection line and a metal plug disposed on the semiconductor substrate. Preferably, the sixth test pad 48 may be disposed on the top metal layer to further reduce the difficulty of applying the injection voltage V.

[0191] Then, in other embodiments, referring to Figure 9 and Figure 10The first conductive connection lines 21 and the second conductive connection lines 31 are located in the same layer and are parallel and staggered. In this case, the first conductive connection lines 21 and the second conductive connection lines 31 can be staggered along a horizontal direction perpendicular to the extension direction of the first conductive connection lines 21 or the second conductive connection lines 31 and parallel to the surface of the semiconductor substrate, thereby dividing the space between adjacent first conductive connection lines 21 and second conductive connection lines 31 in the horizontal direction into one or more staggered spaces. Specifically, if a test unit 10 is set in the space between adjacent first conductive connection lines 21 and second conductive connection lines 31, the space between the adjacent first conductive connection lines 21 and second conductive connection lines 31 is regarded as a staggered space to set one test unit 10. If multiple test units 10 are set in the space between adjacent first conductive connection lines 21 and second conductive connection lines 31, the space between the adjacent first conductive connection lines 21 and second conductive connection lines 31 is further divided into multiple subspaces, each subspace being regarded as a staggered space to set one test unit 10.

[0192] For example, reference Figure 9 and Figure 10 The first conductive connection lines 21 and the second conductive connection lines 31 are located on the same layer. The first conductive connection lines 21 and the second conductive connection lines 31 both extend in the first direction. A plurality of first conductive connection lines 21 and a plurality of second conductive connection lines 31 are arranged in a staggered manner along the second direction, thereby forming staggered spaces for arranging one or more test units 10 within the horizontal spacing between adjacent first conductive connection lines 21 and second conductive connection lines 31. The manner in which the first conductive connection lines 21 and the second conductive connection lines 31 are electrically connected to the test units 10 can be referred to the aforementioned manner and will not be repeated here.

[0193] Exemplary, reference Figure 9 The first common conductive line 23 and the second common conductive line 33 both extend along the second direction and are disposed on either side of the test unit array in the first direction. The arrangement of the first common conductive line 23, the second common conductive line 33, the first test pad 24, the second test pad 34, the first plug 22, and the second plug 32 can be referred to in the description of the previous embodiment and will not be repeated here.

[0194] Exemplary, reference Figure 10 The third common conductive line 27 and the fourth common conductive line 37 both extend along the second direction and are disposed on either side of the test unit array in the first direction. The arrangement of the third common conductive line 27, the fourth common conductive line 37, the third test pad 28, the fourth test pad 38, the first plug 22, and the second plug 32 can be referred to in the description of the previous embodiment and will not be repeated here.

[0195] The lead-out method of the first plug 22 and the second plug 32 in this embodiment can also be applied to the arrangement method of the first common conductive line 23, the first test pad 24, the third common conductive line 27, the third test pad 28, the first adapter line 25, the first adapter plug 26, the second common conductive line 33, the second test pad 34, the fourth common conductive line 37, the fourth test pad 38, the second adapter line 35, and the second adapter plug 36. It is only necessary to adaptively adjust the arrangement positions and extension directions of the first common conductive line 23, the first test pad 24, the third common conductive line 27, the third test pad 28, the first adapter line 25, the first adapter plug 26, the second common conductive line 33, the second test pad 34, the fourth common conductive line 37, the fourth test pad 38, the second adapter line 35, and the second adapter plug 36.

[0196] Exemplarily, the materials of the aforementioned conductive connecting wires, conductive wires, transition wires, metal plugs, and plugs may all include any one or more of aluminum (Al), copper (Cu), tungsten (W), gold, silver, and tin. Of course, it should be noted that the materials of the conductive connecting wires, conductive wires, transition wires, metal plugs, and plugs are not limited to the materials shown above. In addition, other conductive structures that are conductive and contain metal materials may also be used. For example, materials such as, but not limited to, polycrystalline silicon, a conductive layer formed by doping ions in single-crystal silicon, and the like may be used to prepare the aforementioned conductive connecting wires, conductive wires, transition wires, metal plugs, and plugs.

[0197] For example, the conductive connecting wires, conductive wires, metal plugs, and plugs can be made of the same material to facilitate implementation in semiconductor manufacturing processes. Of course, in other embodiments, different materials can be used to fill the conductive connecting wires, conductive wires, metal plugs, and plugs in special circumstances. Example 2

[0198] This embodiment provides a testing method based on some of the above-mentioned semiconductor test structures. The testing method mainly includes: refer to Figure 1A and Figure 1B After confirming that there is a failed test cell 10 in the test cell array, performing a planarization process on the semiconductor test structure to expose the tops of the first plugs 22 and the second plugs 32 in a direction perpendicular to the surface of the semiconductor substrate; The first test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two first plugs 22 , and the second test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two second plugs 32 , and several test units 10 are tested in sequence to find failed test units 10 .

[0199] Various types of tests can be performed on the semiconductor test structure. For example, the semiconductor test structure can be used to perform any one or more of the following tests: reliability test, leakage current test, capacitance test, transistor current test, threshold voltage test, short circuit test, breakdown voltage test, dielectric layer breakdown test over time, and dielectric layer leakage test.

[0200] That is, the semiconductor test structure can be used not only for reliability testing, but also for performing other related electrical tests on the test unit array in addition to reliability testing, such as but not limited to leakage current testing, capacitance value testing when the test unit 10 is a capacitor structure, transistor current and threshold voltage testing, etc. Example 3

[0201] This embodiment provides a testing method based on some of the above-mentioned semiconductor test structures. The testing method mainly includes: refer to 7A to 7D After confirming that there is a failed test cell 10 in the test cell array, cutting the semiconductor test structure along the area between the first plug 22 and the third common conductive line 27 to disconnect the electrical connection between the third common conductive line 27 and the first plug 22; refer to Figure 7C and Figure 7D , exposing the tops of the first plug 22 and the second plug 32 in a direction perpendicular to the surface of the semiconductor substrate; The first test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two first plugs 22 , and the second test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two second plugs 32 , and several test units 10 are tested in sequence to find failed test units 10 .

[0202] The specific testing method can be referred to the description of the above-mentioned embodiment 1 and embodiment 2, which will not be repeated here. Example 4

[0203] This embodiment provides a testing method based on some of the above-mentioned semiconductor test structures. The testing method mainly includes: refer to 7A to 7D After confirming that a failed test cell 10 exists in the test cell array, the semiconductor test structure is cut along the region between the first plug 22 and the third common conductive line 27 and the region between the second plug 32 and the fourth common conductive line 37 to disconnect the electrical connection between the third common conductive line 27 and the first plug 22 and the electrical connection between the fourth common conductive line 37 and the second plug 32; refer to Figure 7Cand Figure 7D , exposing the tops of the first plug 22 and the second plug 32 in a direction perpendicular to the surface of the semiconductor substrate; A first test probe of the test device is sequentially electrically contacted with the top of one of the at least two first plugs 22 , and a second test probe of the test device is sequentially electrically contacted with the top of one of the at least two second plugs 32 , and several test units 10 are tested in sequence to find a failed test unit 10 among the several test units 10 .

[0204] The specific testing method can be referred to the description of the above-mentioned embodiment 1, embodiment 2 and embodiment 3, and will not be repeated here.

[0205] The present application has been described through the above-described embodiments, but it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present application to the described embodiments. In addition, it will be understood by those skilled in the art that the present application is not limited to the above-described embodiments, and that various variations and modifications may be made based on the teachings of the present application, all of which fall within the scope of protection claimed in the present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A semiconductor test structure, characterized in that: include: semiconductor substrates; a first conductive connection structure and a second conductive connection structure located on the semiconductor substrate, the first conductive connection structure comprising a plurality of first conductive connection lines arranged parallel to each other and horizontally, the second conductive connection structure comprising a plurality of second conductive connection lines arranged parallel to each other and horizontally, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure being arranged in an interlaced and spaced manner to form interlaced spaces between the interlaced first conductive connection lines and the second conductive connection lines; a plurality of test units located on the semiconductor substrate, the plurality of test units being arranged in a horizontal array to form a test unit array, the test units being disposed corresponding to the interleaved spaces, the test units comprising a first electrode and a second electrode, the first electrode and the second electrode being respectively connected to the first conductive connection line and the second conductive connection line forming the corresponding interleaved spaces; At least two first plugs are disposed outside the test unit array and spaced apart from each other, each first plug being disposed corresponding to one of the first conductive connection lines, and each first plug being electrically connected to the corresponding first conductive connection line; At least two second plugs are disposed outside the test unit array and spaced apart from each other, each second plug being disposed corresponding to one second conductive connection line, and each second plug being electrically connected to a corresponding second conductive connection line; The top heights of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate are higher than the tops of the at least two first conductive connecting lines and the at least two second conductive connecting lines.

2. The semiconductor test structure according to claim 1, wherein: The first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged in an interlaced and spaced manner to form an interlaced space between the interlaced first conductive connection lines and the second conductive connection lines, comprising: The extension directions of the first conductive connection line and the second conductive connection line intersect, the first conductive connection line and the second conductive connection line are located in different layers, the staggered space is located at the intersection of the first conductive connection line and the second conductive connection line, and a plurality of the staggered spaces are arranged in an array.

3. The semiconductor test structure according to claim 1, wherein: The first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged in an interlaced and spaced manner to form an interlaced space between the interlaced first conductive connection lines and the second conductive connection lines, comprising: The extension direction of the first conductive connection line is parallel to that of the second conductive connection line, the first conductive connection line and the second conductive connection line are located in the same or different layers, the first conductive connection line and the second conductive connection line are adjacent to each other in a one-to-one correspondence so as to be staggered, and one or more staggered spaces are formed between the adjacent first conductive connection lines and the second conductive connection lines.

4. The semiconductor test structure according to claim 1, wherein: Also includes: A first common conductive line is located on top of the first plugs, and the first common conductive line electrically connects the at least two first plugs.

5. The semiconductor test structure according to claim 4, wherein: Also includes: A second common conductive line is located on top of the second plugs, and the second common conductive line electrically connects the at least two second plugs.

6. The semiconductor test structure according to claim 5, wherein: The first common conductive line and the second common conductive line have the same height in a direction perpendicular to the surface of the semiconductor substrate.

7. The semiconductor test structure according to claim 5, wherein: Also includes: A first test pad electrically connected to the first common conductive line, and a second test pad electrically connected to the second common conductive line, wherein the first test pad and the second test pad are at the same height in a direction perpendicular to the surface of the semiconductor substrate.

8. The semiconductor test structure according to claim 5, wherein: The first common conductive line and the second common conductive line are both located in a top metal layer of the semiconductor test structure.

9. The semiconductor test structure according to claim 1, wherein: Also includes: The third common conductive line is located on a side of the first plug away from the test unit array and electrically connects at least two of the first conductive connection lines. The third common conductive line and the at least two first conductive connection lines form a first comb structure.

10. The semiconductor test structure according to claim 9, wherein: Also includes: A fourth common conductive line is located on a side of the second plug away from the test unit array and electrically connected to at least two second conductive connection lines. The fourth common conductive line and the at least two second conductive connection lines form a second comb-tooth structure.

11. The semiconductor test structure according to claim 1, wherein , each of the first plugs is electrically connected to the corresponding first conductive connection line through a first transfer structure; The first adapter structure includes at least one first adapter plug and at least one first adapter wire, and the first adapter plug and the first adapter wire are connected in series on a conductive path between the first plug and the first conductive connection wire.

12. The semiconductor test structure according to claim 11, wherein: A bottom of the first plug has a height in a direction perpendicular to the surface of the semiconductor substrate that is higher or lower than a top of the first conductive connection line.

13. The semiconductor test structure according to claim 11, wherein: Each second plug is electrically connected to the corresponding second conductive connection line through a second adapter structure, and the second adapter structure includes at least one second adapter plug and at least one second adapter line. The second adapter plug and the second adapter line are connected in series on the conductive path between the second plug and the second conductive connection line.

14. The semiconductor test structure according to claim 13, wherein: A bottom of the second plug has a height in a direction perpendicular to the surface of the semiconductor substrate that is higher or lower than a top of the second conductive connection line.

15. The semiconductor test structure according to any one of claims 11 to 14, wherein: In a direction perpendicular to the surface of the semiconductor substrate, a bottom height of the first plug is the same as a bottom height of the second plug.

16. The semiconductor test structure according to claim 1, wherein: The top heights of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate are both higher than the top of the test unit.

17. The semiconductor test structure according to claim 16, wherein: The test unit includes a transistor, the transistor includes a source, a gate, a drain and a channel region, the first electrode and the second electrode respectively include one of the source, the gate and the drain; or, The test unit includes a capacitor structure including a first capacitor plate and a second capacitor plate, the first electrode includes the first capacitor plate, and the second electrode includes the second capacitor plate.

18. A testing method based on the semiconductor test structure according to any one of claims 4 to 7, characterized in that: include: After confirming that a failed test cell exists in the test cell array, performing a planarization process on the semiconductor test structure to expose tops of the first plug and the second plug in a direction perpendicular to a surface of the semiconductor substrate; The first test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two first plugs, and the second test probe of the test equipment is sequentially electrically contacted with the top of one of the at least two second plugs, and the several test units are tested in sequence to find the failed test unit.

19. A testing method based on the semiconductor test structure according to claim 10, characterized in that: include: After confirming that a failed test cell exists in the test cell array, cutting the semiconductor test structure along a region between the first plug and the third common conductive line, and a region between the second plug and the fourth common conductive line, so as to disconnect the electrical connection between the third common conductive line and the first plug, and disconnect the electrical connection between the fourth common conductive line and the second plug; exposing the tops of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate; The first test probe of the test device is sequentially electrically contacted with the top of one of the at least two first plugs, and the second test probe of the test device is sequentially electrically contacted with the top of one of the at least two second plugs, and the plurality of test units are tested in sequence to find a failed test unit among the plurality of test units.

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