Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises an array substrate, a first protective film and a second protective film, wherein the first protective film and the second protective film are arranged on the array substrate; the array substrate comprises a display area and a fan-out area, and the orthographic projection of the first protective film on the array substrate is overlapped with the orthographic projection of the fan-out area on the array substrate; the orthographic projection of the second protective film on the array substrate is arranged to be overlapped with the orthographic projection of the display area on the array substrate; the orthographic projection of the first protective film on the array substrate and the orthographic projection of the second protective film on the array substrate are not overlapped. The display device comprises the display panel. By adding the first protective film in the area outside the display area, the stress capacity and the scratch resistance can be improved, and the product yield is improved.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display devices, and in particular to a display panel and a display apparatus. Background Art

[0002] Currently, the functionality of Android-based e-paper tablets is comparable to that of conventional LCD tablets. Combined with the unique advantages of e-paper ink screens, such as energy saving and eye protection, e-paper tablets are expected to gradually expand their market share. The thinness and lightness of flexible e-paper is a key advantage, making it highly competitive in portable learning notebook applications. Flexible e-paper typically consists of an array substrate, microcapsules, and a protective film. The circuit layer on the array substrate and the paper film are connected by electrical conduction to form upper and lower electrodes, driving the movement of electrophoretic particles within the microcapsules to achieve the desired display effect.

[0003] The array substrate is usually thin, which also brings the disadvantage of weak force-bearing capacity, especially on the data pad (DP) side. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display panel and a display device, which can improve the force-bearing capacity and scratch resistance and improve the product yield by adding a first protective film in the area outside the display area.

[0006] At least one embodiment of the present disclosure provides a display panel, comprising an array substrate, and a first protective film and a second protective film disposed on the array substrate;

[0007] The array substrate includes a display area and a fan-out area;

[0008] The orthographic projection of the first protective film on the array substrate is arranged to overlap with the orthographic projection of the fan-out area on the array substrate;

[0009] The orthographic projection of the second protective film on the array substrate is arranged to overlap with the orthographic projection of the display area on the array substrate;

[0010] An orthographic projection of the first protective film on the array substrate and an orthographic projection of the second protective film on the array substrate do not overlap.

[0011] In some exemplary embodiments, the first protection film includes an organic film.

[0012] In some exemplary embodiments, the array substrate includes a circuit layer and an insulating layer stacked in sequence in a direction perpendicular to the array substrate, and the thickness of the organic film is set to be greater than the thickness of the insulating layer;

[0013] The ratio of the thickness of the organic film to the thickness of the insulating layer is not less than 2.

[0014] In some exemplary embodiments, the thickness of the organic film is set to be greater than 1 micrometer.

[0015] In some exemplary embodiments, the array substrate further includes a binding area, and the display area, the fan-out area, and the binding area are sequentially arranged in a first direction, and the first direction is parallel to the array substrate;

[0016] The orthographic projection of the first protective film on the array substrate is located between the orthographic projection of the display area on the array substrate and the orthographic projection of the binding area on the array substrate;

[0017] The orthographic projection of the first protective film on the array substrate is arranged to be spaced apart from the orthographic projection of the display area on the array substrate;

[0018] And / or, the orthographic projection of the first protective film on the array substrate is arranged to be spaced apart from the orthographic projection of the binding area on the array substrate.

[0019] In some exemplary embodiments, a distance between an orthographic projection of the first protective film on the array substrate and an orthographic projection of the display area on the array substrate is not less than 500 micrometers;

[0020] A distance between an orthographic projection of the first protective film on the array substrate and an orthographic projection of the binding area on the array substrate is not less than 500 micrometers.

[0021] In some exemplary embodiments, an extension dimension of the orthographic projection of the first protective film on the array substrate in the first direction is set to L1, an extension dimension of the orthographic projection of the binding area on the array substrate in the first direction is set to L4, and an extension dimension of the orthographic projection of the fan-out area on the array substrate in the first direction is set to L5, wherein L1≥1.2×L4, L1≥0.5×L5.

[0022] In some exemplary embodiments, an orthographic projection of the first protection film on the array substrate extends in the first direction to a size no less than 1000 micrometers.

[0023] In some exemplary embodiments, a plurality of fan-out areas are provided, and the plurality of fan-out areas are arranged at intervals along a second direction, and the second direction is parallel to the array substrate and perpendicular to the first direction;

[0024] The first protective film is configured to extend along the second direction and be parallel to the array substrate, and an orthographic projection of the first protective film on the array substrate is configured to overlap with an orthographic projection of the plurality of fan-out areas on the array substrate;

[0025] Alternatively, the first protection film includes at least two independent protection units, the protection units correspond to the fan-out areas one-to-one, and the orthographic projections of the protection units on the array substrate are located within the orthographic projections of the fan-out areas on the array substrate.

[0026] In some exemplary embodiments, the array substrate includes a circuit layer, a first insulating layer, and a second insulating layer sequentially stacked in a direction perpendicular to the array substrate, and the first protective film is sandwiched between the first insulating layer and the second insulating layer.

[0027] In some exemplary embodiments, the first protection film and the second protection film are provided in the same layer and are spaced apart in a direction parallel to the array substrate;

[0028] The material of the first protective film is the same as that of the second protective film, and the thickness of the first protective film is the same as that of the second protective film.

[0029] In some exemplary embodiments, there are a plurality of fan-out areas, and the plurality of fan-out areas are spaced apart in a second direction, the second direction is parallel to the array substrate, and a gap between two adjacent fan-out areas is a blank area;

[0030] The display panel further includes a reinforcement structure, which is disposed on the array substrate. The orthographic projection of the reinforcement structure on the array substrate is located within the orthographic projection of the blank area on the array substrate.

[0031] In some exemplary embodiments, a distance between an orthographic projection of the reinforcement structure on the array substrate and an orthographic projection of the fan-out region on the array substrate is set to be greater than 500 micrometers.

[0032] In some exemplary embodiments, the reinforcement structure includes a reinforcement layer parallel to the array substrate, or includes a plurality of reinforcement units arranged at intervals in a direction parallel to the array substrate.

[0033] In some exemplary embodiments, the plurality of reinforcing units are parallel to each other and arranged at equal intervals in a direction parallel to the array substrate, or the plurality of reinforcing units are arranged in an array on a plane parallel to the array substrate.

[0034] In some exemplary embodiments, the array substrate includes a circuit layer and an insulating layer stacked in sequence in a direction perpendicular to the array substrate, and the reinforcement structure and the circuit layer are arranged in the same layer.

[0035] In some exemplary embodiments, the circuit layer includes a first trace located in the fan-out region, the material of the reinforcement structure is set to be the same as that of the first trace, and the thickness of the reinforcement structure is set to be the same as that of the first trace.

[0036] In some exemplary embodiments, the reinforcement structure includes a plurality of metal layers sequentially arranged in a direction perpendicular to the array substrate, wherein the plurality of metal layers are arranged in a stacked arrangement, or the plurality of metal layers are staggered in a direction parallel to the array substrate;

[0037] Alternatively, the reinforcement structure is configured as a multi-layer composite material structure.

[0038] In some exemplary embodiments, a first circuit board is further included.

[0039] The array substrate includes a plurality of first binding areas for binding with the first circuit board, wherein the plurality of first binding areas are spaced apart in a second direction, the second direction is parallel to the array substrate, and the area between two adjacent first binding areas of the array substrate is a middle area;

[0040] The array substrate is provided with a connecting piece in the middle area, and the array substrate is connected to the first circuit board through the connecting piece.

[0041] In some exemplary embodiments, there are a plurality of the connecting members, each of which is configured as a dummy pin, and the plurality of dummy pins are arranged at intervals in the second direction;

[0042] The array substrate is provided with pins in the first binding area that are connected to the first circuit board;

[0043] The material of the dummy pin is set to be the same as the material of the pin, and the thickness of the dummy pin is set to be consistent with the thickness of the pin.

[0044] In some exemplary embodiments, the array substrate includes a circuit layer and an insulating layer, the circuit layer includes the pins, the pins and the dummy pins pass through the insulating layer, and the dummy pins include a gate metal layer, a source / drain metal layer, a third metal layer and a transparent conductive layer stacked in sequence.

[0045] At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0046] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0048] Figure 1 is a schematic diagram of a display panel of this exemplary embodiment;

[0049] Figure 2 for Figure 1 Schematic diagram of the array substrate in FIG.

[0050] Figure 3 for Figure 2 A partial schematic diagram of

[0051] Figure 4 for Figure 1 Schematic diagram of the display panel projection;

[0052] Figure 5 for Figure 1 A first cross-sectional schematic diagram of the array substrate in FIG.

[0053] Figure 6 for Figure 1 A second cross-sectional schematic diagram of the array substrate in FIG.

[0054] Figure 7 is a schematic diagram of another display panel of this exemplary embodiment;

[0055] Figure 8 for Figure 7 A schematic projection diagram of the array substrate in FIG.

[0056] Figure 9 is a schematic diagram of another display panel according to this exemplary embodiment;

[0057] Figure 10 for Figure 9 A schematic projection diagram of the array substrate in FIG.

[0058] Figure 11 is a schematic diagram of another array substrate according to this exemplary embodiment;

[0059] Figure 12 is a schematic diagram of another array substrate according to this exemplary embodiment;

[0060] Figure 13is a schematic cross-sectional view of yet another array substrate according to this exemplary embodiment;

[0061] Figure 14 is a schematic cross-sectional view of another array substrate according to this exemplary embodiment;

[0062] Figure 15 is a schematic cross-sectional view of yet another array substrate according to this exemplary embodiment;

[0063] Figure 16 is a schematic cross-sectional view of yet another array substrate according to this exemplary embodiment;

[0064] Figure 17 A schematic diagram of the disassembly of the relevant display panel;

[0065] Figure 18 is a schematic diagram of another disassembled display panel of this exemplary embodiment;

[0066] Figure 19 for Figure 18 Schematic cross-section of the connector.

[0067] Description of the accompanying drawings:

[0068] 1-array substrate; 2-second protective film; 3-glue point;

[0069] 4-chip; 5-flexible circuit board; 6-first protective film;

[0070] 1a-display area; 1b-fan-out area; 1c-blank area;

[0071] 1d-binding area; 1e-circuit binding area; 1f-chip binding area;

[0072] 1g-first binding region; 1h-middle region;

[0073] 7-circuit layer; 8-first trace; 9-insulation layer;

[0074] 10-first insulating layer; 11-second insulating layer; 12-protection unit;

[0075] 13-reinforcement structure; 14-reinforcement layer; 15-reinforcement unit;

[0076] 16-first metal layer; 17-metal layer; 18-second metal layer;

[0077] 19-semiconductor layer; 20-gold finger; 21-pin;

[0078] 22-connector; 23-dummy pin; 24-gate metal layer;

[0079] 25-source / drain metal layer; 26-third metal layer; 27-transparent conductive layer. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0081] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only structural schematics, and one embodiment of the present disclosure is not limited to the shapes or values shown in the figures.

[0082] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0083] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0084] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0085] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0086] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0087] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0088] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0089] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0090] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0091] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values within the range of process and measurement errors.

[0092] Currently, array substrates are typically yellow polyimide substrates with a circuit layer. Array substrates are typically less than 100μm thick, with the thinnest being only 17μm. This thinness also comes with the disadvantage of weak stress-bearing capacity, making them susceptible to damage. The data pad (DP) side, where the array substrate is bonded to the flexible printed circuit board (FPC) and chip, is particularly vulnerable to damage during the manufacturing process. The DP side of the array substrate has poor scratch resistance, making it susceptible to damage to the traces. Furthermore, during the production process, module materials and processes are prone to stress concentration, leading to cracks. When cracks extend to active traces, display failure occurs. Current processes primarily prevent crack propagation by thinning the inorganic layer on the array substrate, but this thinning also weakens the protective layer. Furthermore, the film peeling is also prone to tension from the FPC at the junction where the array substrate and FPC are bonded.

[0093] Figure 1 is a schematic diagram of a display panel of this exemplary embodiment, Figure 2 for Figure 1 Schematic diagram of the array substrate in FIG. Figure 3 for Figure 2 A partial schematic diagram of Figure 4 for Figure 1 Schematic diagram of display panel projection in the embodiment of the present disclosure provides a display panel, such as Figures 1 to 4 As shown, the display panel can be used for flexible electronic paper, and the display panel may include an array substrate 1, and a first protective film 6 and a second protective film 6 arranged on the array substrate 1, wherein the array substrate 1 includes a display area 1a and a fan-out area 1b, and the orthographic projection of the first protective film 6 on the array substrate 1 is set to overlap with the orthographic projection of the fan-out area 1b on the array substrate 1. The orthographic projection of the second protective film 6 on the array substrate 1 is set to overlap with the orthographic projection of the display area 1a on the array substrate 1. The orthographic projection of the first protective film 6 on the array substrate 1 and the orthographic projection of the second protective film 2 on the array substrate 1 do not overlap. Therefore, the display panel of this example can improve the force-bearing capacity and scratch resistance by adding the first protective film 6 in the area outside the display area, thereby improving the product yield.

[0094] In some exemplary embodiments, Figures 1 to 4As shown, the display panel includes an array substrate 1, a microcapsule (not shown in the figure), a paper film, a chip 4, a first circuit board 5 and a first protective film 6, wherein the array substrate 1 may be provided with an array circuit film layer, and the microcapsule (not shown in the figure) is located between the paper film and the array substrate 1. The array circuit film layer and the paper film on the array substrate 1 can be connected through glue dots 3 to form upper and lower electrodes. The material of the glue dots 3 can be silver (Ag). The upper and lower electrodes drive the movement of electrophoretic particles in the microcapsule (not shown in the figure) to achieve the corresponding display effect.

[0095] In some exemplary embodiments, Figures 1 to 4 As shown, the array substrate 1 can be divided into a display area 1a, a fan-out area 1b, and a bonding area 1d in a direction parallel to the array substrate 1. The display area 1a, fan-out area 1b, and bonding area 1d are arranged sequentially in a first direction parallel to the array substrate 1. The bonding area 1d can include a chip bonding area 1f and a circuit bonding area 1e. The chip 4 can be bonded to the chip bonding area 1f, and the first circuit board 5 can be bonded to the circuit bonding area 1e. The chip bonding area 1f is located on the side of the circuit bonding area 1e near the display area 1a. There can be multiple chip bonding areas 1f, spaced apart in a second direction parallel to the array substrate 1 and perpendicular to the first direction. Furthermore, a fan-out area 1b is located between each chip bonding area 1f and the display area 1a, resulting in a plurality of fan-out areas 1b, spaced apart in the second direction. The gap between each two fan-out areas 1b is a blank area 1c. In this example, there may be two chip-bonding areas 1f, two fan-out areas 1b, and one blank area 1c on the array substrate 1. However, this is not limiting. For example, there may be three chip-bonding areas 1f and three fan-out areas 1b, and the array substrate 1 may have two blank areas 1c. Another example is that there may be four chip-bonding areas 1f and four fan-out areas 1b, and the array substrate 1 may have three blank areas 1c. Another example is that there may be five chip-bonding areas 1f and five fan-out areas 1b, and the array substrate 1 may have four blank areas 1c. Furthermore, the circuit-bonding area 1e may include a first bonding area 1g and a middle area 1h. There may be multiple first bonding areas 1g, which are spaced apart in the second direction, with the area between every two first bonding areas 1g constituting the middle area 1h. In this example, there may be two first binding areas 1g, and the array substrate 1 has one middle area 1h, but it is not limited thereto. For example, there may be three first binding areas 1g, and the array substrate 1 has two middle areas 1h; for another example, there may be four first binding areas 1g, and the array substrate 1 has three middle areas 1h; for another example, there may be five first binding areas 1g, and the array substrate 1 has four middle areas 1h.

[0096] In some exemplary embodiments, Figures 1 to 4As shown, a first protective film 6 and a second protective film 2 are provided on the array substrate 1. The second protective film 2 covers the array substrate 1 and corresponds to the display area 1a. The orthographic projection of the second protective film 2 on the array substrate 1 can overlap with the orthographic projection of the display area 1a on the array substrate 1. The second protective film 2 improves the scratch resistance of the display area 1a and also increases the storage capacitance. The second protective film 2 can be an organic film. When the second protective film 2 covers the array substrate 1, the area outside the display area 1a can be hollowed out to prevent the hydrophilic nature of the organic film from introducing moisture that may affect the characteristics of the display panel.

[0097] In some exemplary embodiments, Figures 1 to 4 As shown, the first protective film 6 is a single piece and may extend along the second direction. The first protective film 6 is parallel to the array substrate 1. The width of the first protective film 6 is L1, which is the extension dimension of the orthogonal projection of the first protective film 6 on the array substrate 1 in the first direction. The extension dimension of the orthogonal projection of the binding area 1d on the array substrate 1 in the first direction is L4. The extension dimension of the orthogonal projection of the fan-out area 1b on the array substrate 1 in the first direction is set to L5, where L1 ≥ 1.2 × L4 and L1 ≥ 0.5 × L5. L1 ≥ 1000 microns. In this example, L1 = 2700 microns, but this is not limited to this. The width of the first protective film 6 is such that it covers the fan-out area 1b as much as possible, for example, L1 = 2000 microns, L1 = 3000 microns, or L1 = 4000 microns.

[0098] In some exemplary embodiments, Figures 1 to 4As shown, the first protective film 6 is located between the second protective film 2 and the chip 4, and is spaced from the second protective film 2 and the chip 4, respectively. This prevents the hydrophilicity of the organic first protective film 6 from introducing moisture that could affect the bonding between the paper film and the chip 4. The orthographic projection of the display area 1a on the array substrate 1 is the first projection (S1), the orthographic projection of the fan-out area 1b on the array substrate 1 is the second projection (S2), the orthographic projection of the chip bonding area 1f on the array substrate 1 is the third projection (S3), the orthographic projection of the circuit bonding area 1e on the array substrate 1 is the fourth projection (S4), and the orthographic projection of the first protective film 6 on the array substrate 1 is the fifth projection (S5). The fifth projection (S5) is located between the first projection (S1) and the third projection (S3), meaning that the orthographic projection (S5) of the first protective film 6 on the array substrate 1 is between the orthographic projection (S1) of the display area 1a on the array substrate 1 and the orthographic projection (S3) of the chip bonding area 1f on the array substrate 1. Moreover, the fifth projection (S5) is spaced apart from the first projection (S1), and the fifth projection (S5) is also spaced apart from the third projection (S3), that is, the orthographic projection (S5) of the first protective film 6 on the array substrate 1 is spaced apart from the orthographic projection (S1) of the display area 1a on the array substrate 1, and the orthographic projection (S5) of the first protective film 6 on the array substrate 1 is spaced apart from the orthographic projection (S3) of the chip bonding area 1f on the array substrate 1. The distance between the fifth projection (S5) and the first projection (S1) is L2, that is, the minimum distance between the edge of the fifth projection (S5) and the edge of the first projection (S1), where L2 ≥ 500 microns. The distance between the fifth projection (S5) and the third projection (S3) is L3, that is, the minimum distance between the edge of the fifth projection (S5) and the edge of the third projection (S3), where L3 ≥ 500 microns. Therefore, the orthographic projection (S5) of the first protective film 6 on the array substrate 1 overlaps with the orthographic projection (S2) of all fan-out areas 1b on the array substrate 1, and the first protective film 6 also covers part of the blank area 1c between the two fan-out areas 1b.

[0099] Figure 5 for Figure 1 A first cross-sectional schematic diagram of the array substrate in FIG. Figure 5 The cross section in FIG is a local cross section of the fan-out region of the array substrate where the first protective film 6 is not provided. Figure 6 for Figure 1 A second cross-sectional schematic diagram of the array substrate in FIG. Figure 6 The cross section in FIG is a local cross section where the first protective film 6 is provided in the fan-out region of the array substrate. In some exemplary embodiments, as shown in FIG. Figure 1 、 Figure 2 、 Figure 5 and Figure 6As shown, the array substrate 1 includes a circuit layer 7 and an insulating layer 9 stacked sequentially in a direction perpendicular to the array substrate 1. The insulating layer 9 is located on the side of the circuit layer 7 close to the second protective film 2. The insulating layer 9 further includes a first insulating layer 10 and a second insulating layer 11 stacked sequentially in a direction away from the circuit layer 7. The circuit layer 7 typically has circuit traces and thin-film transistors, while the insulating layer 9 provides protection for the circuit layer 7. The materials of the first insulating layer 10 and the second insulating layer 11 can both be inorganic materials. The first insulating layer 11 can be called a gate insulating layer (GI), and the second insulating layer 12 can be called a passivation layer (PVX). Considering that inorganic materials are prone to cracking due to aggregation, the inorganic insulating layer is designed to be as thin as possible in film thickness design. A thinner insulating layer 9 does not provide ideal protection, but the first and second protective films compensate for this deficiency. The first protective film 6 can absorb external stress and improve the bending resistance of the single-layer area.

[0100] In some exemplary embodiments, Figure 1 、 Figure 2 、 Figure 5 and Figure 6 As shown, the first protective film 6 can be an organic film, such that the material of the first protective film 6 is the same as the material of the second protective film 2, and the thickness of the first protective film 6 is the same as the thickness of the second protective film 2. The first protective film 6 and the second protective film 2 are arranged in the same layer for easy processing. The thickness mentioned above and in the following content refers to the dimension of the component in a direction perpendicular to the array substrate 1. The thickness of the organic film is set to be greater than the thickness of the insulating layer 9, and the ratio of the thickness of the organic film to the thickness of the insulating layer 9 is not less than 2. The thickness of the first protective film 6 can be not less than 1 micron. In this example, the thickness of the first protective film 6 is 2 microns, but the thickness is not limited to this. For example, the thickness of the first protective film 6 can be 1.5 microns, 1.8 microns, or 2.5 microns. Based on the above description of the materials and thicknesses of the first protective film 6 and the second protective film 2, it is not limited to this. For example, the material of the first protective film 6 and the material of the second protective film 2 are different, the thickness of the first protective film 6 and the thickness of the second protective film 2 are different, or the material of the first protective film 6 and the thickness of the second protective film 2 are different.

[0101] In some exemplary embodiments, Figure 5 and Figure 6As shown, the circuit layer 7 of the array substrate 1 has a first metal trace 8 in the fan-out region 1b, and an insulating layer 9 covers the circuit layer 7 to provide protection. A first protective film 6 is sandwiched between a first insulating layer 10 and a second insulating layer 11. The thickness of the first insulating layer 10 is approximately 0.35 microns, and the thickness of the second insulating layer 11 is approximately 0.25 microns. The array substrate 1 has an independent first protective film 6 in the fan-out region. In the fan-out region 1b of the array substrate 1, the portion of the circuit layer 7 not protected by the first protective film 6 is only covered by the insulating layer 9, providing a protective layer thickness of approximately 0.6 microns. The portion of the circuit layer 7 protected by the first protective film 6, in addition to being covered by the insulating layer 9, also has a laminated first protective film 6, providing a protective layer thickness of approximately 2.6 microns. This significantly increases the thickness of the protective layer, significantly improving the scratch resistance of the array substrate 1 in the fan-out region 1b from the original 16 mN to over 50 mN, demonstrating a significant improvement in scratch resistance.

[0102] Figure 7 is another schematic diagram of a display panel according to this exemplary embodiment. Figure 8 for Figure 7 In some exemplary embodiments, as shown in FIG. Figure 7 and Figure 8 As shown, the first protective film 6 includes at least two separate protective units 12, each protective unit 12 is independent of each other, the number of protective units 12 and the fan-out area 1b are consistent and one-to-one corresponding, and the positive projection of the protective unit 12 on the array substrate 1 is the sixth projection (S6), wherein the sixth projection (S6) is located within the second projection (S2), so that the blank area 1c is not covered by the first protective film 6, and the first protective film 6 can absorb external stress to enhance the bending resistance of the single-layer area.

[0103] Figure 9 is another schematic diagram of a display panel according to this exemplary embodiment. Figure 10 for Figure 9 In some exemplary embodiments, as shown in FIG. Figure 2 、 Figure 9 and Figure 10 As shown, the display panel further includes a reinforcement structure 13, which is disposed on the array substrate 1 and located in the blank area 1c. The orthographic projection of the reinforcement structure 13 on the array substrate 1 is the seventh projection (S7), and the seventh projection (S7) is located within the orthographic projection of the blank area 1c on the array substrate 1. The blank area 1c of the array substrate 1 has no metal traces, but is deposited with an inorganic insulating layer. If cracks are generated here due to stress, they will rapidly expand to the metal traces in the fan-out area, posing a very high risk of progressive damage. In this example, the reinforcement structure 13 is added to break up the large-area inorganic material aggregation, providing greater toughness and improving the crack resistance in this area.

[0104] In some exemplary embodiments, Figure 2 、 Figure 9 and Figure 10 As shown, the orthographic projection of the reinforcement structure 13 on the array substrate 1 is the seventh projection (S7), the orthographic projection of the fan-out area 1b on the array substrate 1 is the second projection (S2), the orthographic projection of the chip bonding area 1f on the array substrate 1 is the third projection (S3), and the orthographic projection of the circuit bonding area 1e on the array substrate 1 is the fourth projection (S4). The reinforcement structure 13 can be made of metal. The distance between the seventh projection (S7) and the second projection (S2) is L4, which is the minimum distance between the edge of the seventh projection (S7) and the edge of the second projection (S2). L4 is ≥ 500 microns. This separates the reinforcement structure 13 from the metal traces of the fan-out area 1a, preventing electrostatic risks caused by large metal areas. The distance between the seventh projection (S7) and the third projection (S3) is L5, which is the minimum distance between the edge of the seventh projection (S7) and the edge of the third projection (S3). L5 is ≥ 500 microns. This separates the reinforcement structure 13 from the metal traces of the chip bonding area 1f, preventing electrostatic risks caused by large metal areas. The distance between the seventh projection (S7) and the fourth projection (S4) is L6, that is, the minimum distance between the edge of the seventh projection (S7) and the edge of the fourth projection (S4), where L6 ≥ 500 microns, so that the metal traces of the reinforcement structure 13 and the circuit binding area 1e are separated to avoid the risk of static electricity caused by large areas of metal.

[0105] In some exemplary embodiments, Figure 2 、 Figure 5 、 Figure 9 and Figure 10 As shown, the reinforcement structure 13 is an integral part. The reinforcement structure 13 includes a reinforcement layer 14 parallel to the array substrate 1. The reinforcement layer 14 is laid flat on the array substrate 1 and is on the same layer as the circuit layer 7. The reinforcement layer 14 can be made of the same material and have the same thickness as the first trace 8, but is not limited thereto. For example, the reinforcement layer 14 can be made of a different material than the first trace 8, or have a different thickness than the first trace 8, or have a different material and thickness than the first trace 8. In addition, the reinforcement structure 13 can be connected to no signal, or to a ground or reference voltage signal. In this example, the reinforcement structure 13 can be connected to a reference voltage signal to prevent ESD (Electrostatic Discharge).

[0106] Figure 11 This is another schematic diagram of an array substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 11As shown, reinforcement structure 13 includes multiple reinforcement units 15 spaced apart in a direction parallel to array substrate 1. Reinforcement units 15 can be made of metal and are strip-shaped. Multiple reinforcement units 15 are independent of each other and parallel to each other and spaced evenly apart in a direction parallel to array substrate 1. The independence of multiple reinforcement units 15 prevents large metal blocks from gathering together and attracting ESD, thereby creating numerous ESD discharge paths. This minimizes the probability of damaging surrounding active metal traces.

[0107] Figure 12 This is another schematic diagram of an array substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 12 As shown, the reinforcement structure 13 includes multiple reinforcement units 15 spaced apart in a direction parallel to the array substrate 1. The reinforcement units 15 can be made of metal and are block-shaped. The multiple reinforcement units 15 are independent of each other and arranged in an array on a plane parallel to the array substrate 1. The independence of the multiple reinforcement units 15 prevents large metal blocks from attracting ESD and generating numerous ESD discharge paths, minimizing the probability of damaging surrounding active metal traces.

[0108] Figure 13 is a cross-sectional schematic diagram of another array substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 5 and Figure 13 As shown, the reinforcement structure 13 can be made of metal material. The reinforcement structure 13 is a single-layer structure. The reinforcement structure 13 includes a first metal layer 16. The first metal layer 16 and the circuit layer 7 are on the same layer, and the thickness and material of the first trace 8 of the first metal layer 16 are consistent. The material of the first metal layer 16 can be aluminum (Al) or molybdenum (Mo).

[0109] Figure 14 is a cross-sectional schematic diagram of another array substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 5 and Figure 14 As shown, the reinforcement structure 13 can be made of metal material. The reinforcement structure 13 is a multi-layer structure. The reinforcement structure 13 includes a plurality of metal layers 17 arranged in sequence in a direction perpendicular to the array substrate 1. The plurality of metal layers 17 are arranged in a stacked arrangement, and the insulating layer covers the plurality of metal layers 17. In this example, the reinforcement structure 13 includes two stacked metal layers 17, namely a first metal layer 16 and a second metal layer 18. The material of the first metal layer 16 can be aluminum (Al) or molybdenum (Mo), and the material of the second metal layer 18 can be different from that of the first metal layer 16. The second metal layer 18 is located on the side of the first metal layer 16 close to the insulating layer 9, and the second insulating layer 11 covers the side of the second metal layer 18 away from the first metal layer 16. However, the present invention is not limited thereto. For example, the metal layer 17 can be a stacked three layers or more, and three or more metal layers 17 can be stacked.

[0110] Figure 15 is a cross-sectional schematic diagram of another array substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 15 As shown, the reinforcement structure 13 can be made of metal and has a multi-layer structure. The reinforcement structure 13 includes multiple metal layers 17 arranged in a staggered arrangement perpendicular to the array substrate 1. The multiple metal layers 17 are covered by an insulating layer. In this example, the reinforcement structure 13 includes two metal layers 17: a first metal layer 16 and a second metal layer 18. The material of the first metal layer 16 can be aluminum (Al) or molybdenum (Mo), and the material of the second metal layer 18 can be different from that of the first metal layer 16. The second metal layer 18 is located on the side of the first metal layer 16 closest to the insulating layer 9. The first insulating layer 10 covers the first metal layer 16, and the second metal layer 18 is located between the first insulating layer 10 and the second insulating layer 11. The orthographic projection of the first metal layer 16 on the array substrate 1 does not overlap with the orthographic projection of the second metal layer 18 on the array substrate 1, resulting in a staggered arrangement of the first metal layer 16 and the second metal layer 18. However, this is not limiting. For example, the metal layers 17 can be stacked in three or more layers, with the three or more metal layers 17 being staggered.

[0111] Figure 16 is a cross-sectional schematic diagram of another array substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 15 As shown, the reinforcement structure 13 can be a multi-layer composite structure, including a first metal layer 16, a semiconductor layer 19, and a second metal layer 18 stacked in a direction perpendicular to the array substrate 1, forming a structure similar to a thin film transistor. The insulating layer 9 includes a first insulating layer 10 and a second insulating layer 11 stacked together, with the first metal layer 18 located on the side of the first insulating layer 10 away from the second insulating layer 11, and the semiconductor layer 19 and the second metal layer 18 located between the first insulating layer 10 and the second insulating layer 11.

[0112] Figure 17 is a schematic diagram of the splitting of the relevant display panel, such as Figure 17 As shown, the first circuit board 5 is a flexible circuit board with gold fingers 20. The gold fingers 20 of the first circuit board 5 can be bonded to the first binding area 1g on the array substrate 1, enabling electrical signal transmission from the first circuit board 5 to the array substrate 1. The middle area 1 of the array substrate 1 does not have any components connecting to the first circuit board 5. During the manufacturing process, it is inevitable to pull the first circuit board 5 for plug-in inspection. During this process, the first circuit board 5 will pull on the metal film layer on the array substrate 1. In addition, the flexible array substrate 1 has low stress tolerance, and the contact point between the first circuit board 5 and the array substrate 1 is a weak point, which is very prone to peeling.

[0113] Figure 18FIG. 1 is a schematic diagram of another disassembled display panel according to this exemplary embodiment. Figure 19 for Figure 18 A schematic cross-sectional view of a connector in FIG. 1 , in some exemplary embodiments, as shown in FIG. Figure 2 、 Figure 18 and Figure 19 As shown, the array substrate 1 may include a first binding area 1g and a middle area 1h. Multiple first binding areas 1g may be provided, spaced apart in the second direction, with the area between each two first binding areas 1g forming the middle area 1h. In this example, two first binding areas 1g may be provided, and the array substrate 1 has one middle area 1h. Pins 21 are provided within the first binding area 1g to connect to the gold fingers 20 of the first circuit board 5. These pins 21 are evenly spaced along the second direction. Connectors 22 are also provided within the middle area 1h, spaced evenly apart in the second direction. The distance between adjacent connectors 22 is the same as the distance between adjacent pins 21, forming a continuous linear arrangement along the second direction. These connectors 22 are dummy pins, constructed using the same structure and material as the pins 21 to ensure stress uniformity. As a result, compared to existing products, the array substrate 1 adds dummy pins in the middle area 1h. The first circuit board 5 is also adjusted to a continuous gold finger 20 corresponding to the dummy pins. The array substrate 1 is connected not only to the gold finger 20 of the first circuit board 5 via pins 21, but also to the gold finger 20 of the first circuit board 5 via dummy pins. This increases the contact area between the first circuit board 5 and the array substrate 1, reduces deformation caused by tensile stress, and prevents film peeling. The dummy pins do not actually transmit signals and do not affect the actual function of the product. They only serve to share the pulling force from the first circuit board 5.

[0114] In some exemplary embodiments, Figure 18 and Figure 19As shown, the array substrate 1 includes an insulating layer 9, which further includes a stacked first insulating layer 10 and a second insulating layer 11. The dummy pin 23 passes through the insulating layer 9. The materials of the first insulating layer 10 and the second insulating layer 11 can both be inorganic materials. The first insulating layer 11 can be called a gate insulating layer (GI), which can be silicon nitride and can have a thickness of 0.35 microns. The second insulating layer 12 can be called a passivation layer (PVX), and can have a thickness of 0.25 microns. The dummy pin 23 includes a gate metal layer 24, a source / drain metal layer 25, a third metal layer 26, and a transparent conductive layer 27 stacked in sequence. The gate metal layer 24 may be made of aluminum (Al) or molybdenum (Mo), and may have a thickness of 0.08 to 0.3 microns. The source / drain metal layer 25 may be made of aluminum (Al) or molybdenum (Mo), and may have a thickness of 0.015 to 0.3 microns. The third metal layer 26 may be made of molybdenum (Mo), and may have a thickness of 0.2 microns. The transparent conductive layer 27 may be made of amorphous indium tin oxide (a-ITO), and may have a thickness of 0.07 microns.

[0115] In some exemplary embodiments, Figure 9 and Figure 18 Schematic diagram, the display panel of this example, by adding a first protective film 6, adding a reinforcement structure and adding dummy pins, improves the force-bearing capacity of the display panel in three directions, optimizes the force buffering capacity of the single-layer area, and protects the metal wiring on the array substrate 1 from damage and failure.

[0116] In some exemplary embodiments, a display device includes the above-mentioned display panel, and the display device may be flexible electronic paper.

[0117] In combination with the above embodiments, the display panel of this example can improve its force-bearing capacity and scratch resistance by adding a first protective film 6 in an area outside the display area, thereby protecting the wiring and improving the product yield. The first protective film 6 and the second protective film are separated. Even if the first protective film 6 absorbs water later, the water vapor will not affect the display area 1a. At the same time, the binding area of the first protective film 6 is separated to prevent water vapor from affecting the binding effect. The display panel breaks the state of large-scale accumulation of inorganic materials in the blank area by adding a reinforcing structure 13 in the blank area. The reinforcing structure 13 uses a metal material with better toughness. The introduction of a metal with better toughness can improve the crack resistance here. The spacing between the reinforcing structure 13 and the surrounding metal wiring is more than 500 microns to prevent static electricity from breaking through the surrounding metal wiring. The display panel increases the contact area between the first circuit board and the array substrate 1 by adding dummy pins in the middle area and connecting the first circuit board through the dummy pins, reducing the deformation caused by tensile stress and avoiding the occurrence of film shedding.

[0118] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A display panel, characterized in that: It includes an array substrate, and a first protective film and a second protective film arranged on the array substrate; The array substrate includes a display area and a fan-out area; The orthographic projection of the first protective film on the array substrate is arranged to overlap with the orthographic projection of the fan-out area on the array substrate; The orthographic projection of the second protective film on the array substrate is arranged to overlap with the orthographic projection of the display area on the array substrate; An orthographic projection of the first protective film on the array substrate and an orthographic projection of the second protective film on the array substrate do not overlap.

2. The display panel according to claim 1, wherein: The first protective film includes an organic film.

3. The display panel according to claim 2, wherein: The array substrate comprises a circuit layer and an insulating layer stacked in sequence in a direction perpendicular to the array substrate, and the thickness of the organic film is set to be greater than the thickness of the insulating layer; The ratio of the thickness of the organic film to the thickness of the insulating layer is not less than 2.

4. The display panel according to claim 3, wherein: The thickness of the organic film is set to be greater than 1 micron.

5. The display panel according to claim 1, wherein: The array substrate further includes a binding area, the display area, the fan-out area, and the binding area are sequentially arranged in a first direction, and the first direction is parallel to the array substrate; The orthographic projection of the first protective film on the array substrate is located between the orthographic projection of the display area on the array substrate and the orthographic projection of the binding area on the array substrate; The orthographic projection of the first protective film on the array substrate is arranged to be spaced apart from the orthographic projection of the display area on the array substrate; And / or, the orthographic projection of the first protective film on the array substrate is arranged to be spaced apart from the orthographic projection of the binding area on the array substrate.

6. The display panel according to claim 5, wherein: The distance between the orthographic projection of the first protective film on the array substrate and the orthographic projection of the display area on the array substrate is not less than 500 microns; A distance between an orthographic projection of the first protective film on the array substrate and an orthographic projection of the binding area on the array substrate is not less than 500 micrometers.

7. The display panel according to claim 5, wherein: An extension dimension of the orthographic projection of the first protective film on the array substrate in the first direction is set to L1, an extension dimension of the orthographic projection of the binding area on the array substrate in the first direction is set to L4, and an extension dimension of the orthographic projection of the fan-out area on the array substrate in the first direction is set to L5, wherein L1≥1.2×L4, L1≥0.5×L5.

8. The display panel according to claim 7, wherein: The orthographic projection of the first protective film on the array substrate extends in the first direction to a size not less than 1000 micrometers.

9. The display panel according to claim 5, wherein: There are a plurality of fan-out areas, and the plurality of fan-out areas are arranged at intervals along a second direction, and the second direction is parallel to the array substrate and perpendicular to the first direction; The first protective film is configured to extend along the second direction and be parallel to the array substrate, and an orthographic projection of the first protective film on the array substrate is configured to overlap with an orthographic projection of the plurality of fan-out areas on the array substrate; Alternatively, the first protection film includes at least two independent protection units, the protection units correspond to the fan-out areas one-to-one, and the orthographic projections of the protection units on the array substrate are located within the orthographic projections of the fan-out areas on the array substrate.

10. The display panel according to claim 5, wherein: The array substrate includes a circuit layer, a first insulating layer, and a second insulating layer stacked in sequence in a direction perpendicular to the array substrate, and the first protective film is sandwiched between the first insulating layer and the second insulating layer.

11. The display panel according to claim 2, wherein: The first protective film and the second protective film are provided in the same layer and are spaced apart in a direction parallel to the array substrate; The material of the first protective film is the same as that of the second protective film, and the thickness of the first protective film is the same as that of the second protective film.

12. The display panel according to claim 1, wherein There are a plurality of fan-out areas, and the plurality of fan-out areas are spaced apart in a second direction, the second direction is parallel to the array substrate, and a gap between two adjacent fan-out areas is a blank area; The display panel further includes a reinforcement structure, which is disposed on the array substrate. The orthographic projection of the reinforcement structure on the array substrate is located within the orthographic projection of the blank area on the array substrate.

13. The display panel according to claim 12, wherein: The distance between the orthographic projection of the reinforcement structure on the array substrate and the orthographic projection of the fan-out region on the array substrate is set to be greater than 500 microns.

14. The display panel according to claim 12, wherein: The reinforcement structure includes a reinforcement layer parallel to the array substrate, or includes a plurality of reinforcement units arranged at intervals in a direction parallel to the array substrate.

15. The display panel according to claim 14, wherein: The plurality of reinforcing units are parallel to each other and arranged at equal intervals in a direction parallel to the array substrate, or the plurality of reinforcing units are arranged in an array on a plane parallel to the array substrate.

16. The display panel according to claim 14, wherein: The array substrate comprises a circuit layer and an insulating layer which are sequentially stacked in a direction perpendicular to the array substrate, and the reinforcement structure and the circuit layer are arranged in the same layer.

17. The display panel according to claim 16, wherein: The circuit layer includes a first routing line located in the fan-out area. The material of the reinforcement structure is set to be the same as that of the first routing line, and the thickness of the reinforcement structure is set to be the same as that of the first routing line.

18. The display panel according to claim 16, wherein: The reinforcement structure includes a plurality of metal layers sequentially arranged in a direction perpendicular to the array substrate, wherein the plurality of metal layers are arranged in a stacked arrangement, or the plurality of metal layers are arranged in a staggered arrangement in a direction parallel to the array substrate; Alternatively, the reinforcement structure is configured as a multi-layer composite material structure.

19. The display panel according to claim 1, wherein Also includes a first circuit board, The array substrate includes a plurality of first binding areas for binding with the first circuit board, wherein the plurality of first binding areas are spaced apart in a second direction, the second direction is parallel to the array substrate, and the area between two adjacent first binding areas of the array substrate is a middle area; The array substrate is provided with a connecting piece in the middle area, and the array substrate is connected to the first circuit board through the connecting piece.

20. The display panel according to claim 19, wherein There are a plurality of the connecting members, each of which is configured as a dummy pin, and the plurality of the dummy pins are arranged at intervals in the second direction; The array substrate is provided with pins in the first binding area that are connected to the first circuit board; The material of the dummy pin is set to be the same as the material of the pin, and the thickness of the dummy pin is set to be consistent with the thickness of the pin.

21. The display panel according to claim 20, wherein: The array substrate includes a circuit layer and an insulating layer, the circuit layer includes the pins, the pins and the dummy pins pass through the insulating layer, and the dummy pins include a gate metal layer, a source / drain metal layer, a third metal layer and a transparent conductive layer stacked in sequence.

22. A display device, characterized in that: Comprising the display panel according to any one of claims 1 to 21.

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