Data processing device, method, storage medium and program product

Abstract

The present application discloses a data processing device, method, storage medium and program product, which relate to the field of data processing technology. The data processing device includes a programmable logic unit, a first memory and a second memory, and the programmable logic unit is connected to the first memory and the second memory respectively. After receiving a data access request, the programmable logic unit determines whether the target data corresponding to the data access request is stored in the first memory based on the mapping relationship between the data in the first memory and the data in the second memory, thereby avoiding wasting time by directly querying in the first memory when the target data is not stored in the first memory. In addition, when the target data is not stored in the first memory, the target data is cached from the second memory to the first memory where data processing is faster, which is conducive to speeding up the query speed of the target data and reducing the access delay of the target data.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to data processing devices, methods, storage media, and program products. Background Art

[0002] In some data processing scenarios, such as artificial intelligence (AI) training, high requirements are placed on data access latency and memory capacity.

[0003] In these data processing scenarios, how to reduce data access latency while ensuring large-capacity memory requirements is an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a data processing device, method, storage medium and program product to at least solve the problem in the related art of reducing data access latency while ensuring large-capacity memory requirements.

[0005] The present application provides a data processing device, comprising: a programmable logic device, a first memory and a second memory, wherein:

[0006] The programmable logic device is connected to the first memory and the second memory respectively, and the data processing speed of the first memory is greater than the data processing speed of the second memory;

[0007] The programmable logic device is used to receive a data access request and determine whether target data corresponding to the data access request is stored in the first memory based on the data access request and the mapping relationship between the data in the first memory and the data in the second memory. If the target data is not stored in the first memory, the target data is stored from the second memory to the first memory, the mapping relationship is updated, and the target data is obtained by querying in the first memory.

[0008] This application provides a data processing method, including:

[0009] receiving data access requests;

[0010] determining, based on the data access request and a mapping relationship between data in the first memory and data in the second memory, whether target data corresponding to the data access request is stored in the first memory, and a data processing speed of the first memory is greater than a data processing speed of the second memory;

[0011] If the target data is not stored in the first memory, the target data is stored from the second memory to the first memory, the mapping relationship is updated, and the target data is obtained by querying in the first memory.

[0012] The present application also provides a data processing device, comprising:

[0013] A transceiver module, configured to receive a data access request;

[0014] a processing module, configured to determine, based on the data access request and a mapping relationship between the data in the first memory and the data in the second memory, whether target data corresponding to the data access request is stored in the first memory, and a data processing speed of the first memory is greater than a data processing speed of the second memory;

[0015] The processing module is further configured to store the target data from the second memory to the first memory if the target data is not stored in the first memory, update the mapping relationship, and query the first memory to obtain the target data.

[0016] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0017] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned data processing methods when executed by a processor.

[0018] Through the present application, after receiving a data access request, the programmable logic device can quickly determine whether the target data corresponding to the data access request is stored in the first memory based on the mapping relationship between the data in the first memory and the data in the second memory, thereby avoiding wasting time by directly querying in the first memory when the target data is not stored in the first memory. In addition, when the target data is not stored in the first memory, the target data is cached from the second memory to the first memory where data processing is faster, which is conducive to speeding up the query speed of the target data and reducing the access delay of the target data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is one of the structural diagrams of the data processing device provided in the embodiment of the present application;

[0021] Figure 2 The second structural diagram of the data processing device provided in the embodiment of the present application;

[0022] Figure 3One of the structural diagrams of the programmable logic device provided in the embodiment of the present application;

[0023] Figure 4 The second structural diagram of the programmable logic device provided in the embodiment of the present application;

[0024] Figure 5A A schematic diagram of a storage structure of the address of the first storage page provided in an embodiment of the present application;

[0025] Figure 5B A schematic diagram of a storage structure of the address of the second storage page provided in an embodiment of the present application;

[0026] Figure 6A An exemplary schematic diagram of the storage structure of a sub-mapping table provided in an embodiment of the present application;

[0027] Figure 6B A schematic diagram of the storage structure of the mapping table provided in an embodiment of the present application;

[0028] Figure 7 This is a flowchart of a data processing method according to an embodiment of the present invention.

[0029] Figure 8 A schematic diagram of the address mapping relationship provided in the embodiment of the present application;

[0030] Figure 9 A schematic diagram of changes in the access order index of each first storage page in the sub-mapping table provided in an embodiment of the present application;

[0031] Figure 10 The second flowchart of the data processing method provided in the embodiment of the present application;

[0032] Figure 11 A schematic diagram of a storage state change of a target storage page provided in an embodiment of the present application;

[0033] Figure 12 A schematic diagram of a change in the working state of a storage unit provided in an embodiment of the present application;

[0034] Figure 13 The third flowchart of the data processing method provided in the embodiment of the present application;

[0035] Figure 14 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0038] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, processing, transmission, provision, disclosure and application of relevant data comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0039] In some data processing scenarios (for example, AI training), high requirements are placed on data access latency and memory capacity. In these data processing scenarios, reducing data access latency while ensuring large memory capacity is a pressing issue.

[0040] During data processing, two types of memory can be used: first-class memory and second-class memory.

[0041] Class-I memories process data at a high speed, resulting in shorter data access latency. However, the storage capacity of a single Class-I memory is relatively small. In scenarios requiring large amounts of memory, if all Class-I memories are used for data processing, multiple Class-I memories would be required, resulting in excessively high data processing costs. For example, Class-I memories may include, but are not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0042] Compared to first-type memory, second-type memory has higher storage capacity and lower cost. However, its data processing speed is slower than that of first-type memory, meaning it has longer data access latency. In scenarios where large-capacity memory is required, using second-type memory directly as memory expansion for data processing will result in longer data access latency during data processing. For example, second-type memory may include, but is not limited to, solid-state drives (SSDs).

[0043] During the research process, it was found that if the first type of memory and the second type of memory are reasonably combined, the data processing speed of the first type of memory and the storage capacity of the second type of memory can be utilized, thereby achieving the purpose of reducing data access latency in data processing scenarios with large-capacity memory requirements.

[0044] Based on the above research, an embodiment of the present application provides a data processing device, which includes a programmable logic unit, a first memory, and a second memory, wherein the programmable logic unit is connected to the first memory and the second memory respectively, and the data processing speed of the first memory is greater than the data processing speed of the second memory. In the data processing device, the first memory can be the above-mentioned first-type memory, and the second memory can be the above-mentioned second-type memory, that is, the first memory has a higher data processing speed and a lower data access latency than the second memory, and the second memory has a larger storage capacity and a lower cost than the first memory. The first memory can be used to store part of the data of the second memory, and the programmable logic unit can flexibly adjust the data of the second memory stored in the first memory, so that both the data processing speed of the first-type memory and the storage capacity of the second-type memory can be utilized.

[0045] In the above-mentioned data processing device, after receiving a data access request, the programmable logic unit can quickly determine whether the target data corresponding to the data access request is stored in the first memory based on the mapping relationship between the data in the first memory and the data in the second memory, thereby avoiding wasting time by directly querying in the first memory when the target data is not stored in the first memory; and, when the target data is not stored in the first memory, the target data is cached from the second memory to the first memory so that the target data can be quickly queried through the first memory, which is beneficial to reducing the access delay of the target data.

[0046] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0047] In order to facilitate understanding of the data processing method provided in the embodiment of the present application, Figures 1 to 4 , describing the specific hardware architecture on which the execution of the combined data processing method depends.

[0048] First, combine Figure 1 and Figure 2 , the structure of the data processing device provided in the embodiment of the present application is described in detail.

[0049] Figure 1 This is one of the structural diagrams of a data processing device provided in an embodiment of the present application. The data processing device 10 may include a programmable logic device 100, a first memory 101, and a second memory 102, wherein the programmable logic device 100 is connected to the first memory 101 and the second memory 102 respectively, and the data processing speed of the first memory 101 is greater than the data processing speed of the second memory 102.

[0050] It should be understood that Figure 1 The number and form of the devices shown are for example only and do not constitute a limitation on the embodiments of the present application. In actual applications, the number of programmable logic devices, first memories, and second memories in the data processing device can be two or more. Figure 1 The data processing device shown is merely shown as an example including a programmable logic device, a first memory, and a second memory.

[0051] Exemplarily, the first memory may include but is not limited to DDR.

[0052] Illustratively, the second memory may include but is not limited to an SSD or a hard disk drive (HDD).

[0053] Illustratively, the programmable logic device may include, but is not limited to, one of the following: a field programmable gate array (FPGA), a complex programmable logic device (CPLD), and a microcontroller unit (MCU).

[0054] In the data processing device provided in the embodiment of the present application, the programmable logic unit 100 can be used to receive a data access request and, based on the data access request and the mapping relationship between the data in the first memory 101 and the data in the second memory 102, determine whether the first memory 101 stores the target data corresponding to the data access request. If the target data is not stored in the first memory 101, the target data is stored from the second memory 102 to the first memory 101, the mapping relationship is updated, and the target data is obtained by querying the first memory 101. The data processing device can use the programmable logic unit to quickly query the target data corresponding to the data access request in the first memory, avoiding wasting time by directly querying the first memory when the target data is not stored in the first memory. Moreover, when the target data is not stored in the first memory, the target data is cached from the second memory to the first memory, which has faster data processing speed, thereby accelerating the query speed of the target data and reducing the access latency of the target data.

[0055] In some embodiments, the structure of the data processing device can also be as follows Figure 2 shown. Figure 2 For the second structural diagram of the data processing device provided in the embodiment of the present application, please refer to Figure 2 ,exist Figure 1 Based on the structure of the data processing device 10 shown, the data processing device 10 may further include a processor 103 , a data transmission interface 104 and a control interface 105 .

[0056] like Figure 2 As shown, the processor 103 can be connected to the programmable logic device 100 .

[0057] Exemplarily, the processor 103 may be a central processing unit (CPU).

[0058] In the data processing device 10 , the processor 103 may be configured to send a data access request to the programmable logic device 100 and receive target data sent by the programmable logic device 100 .

[0059] In some embodiments, the data processing device 10 can receive a data access request sent by a client through the processor 103, and forward the data access request to the programmable logic device 100 through the processor 103, and receive target data sent by the programmable logic device 100 through the processor 103, and send the target data to the client through the processor 103.

[0060] The data transmission interface 104 can be connected to the processor 103 and the programmable logic device 100 respectively. The data transmission interface 104 can be used to transmit data access requests and target data. In other words, the processor 103 can send data access requests to the programmable logic device 100 through the data transmission interface 104, and receive target data sent by the programmable logic device 100 through the data transmission interface 104.

[0061] The data transmission interface 104 may perform data transmission based on the Compute Express Link (CXL) protocol. For example, the data transmission interface may be a CXL.mem (or CXL.memory) interface.

[0062] In some embodiments, the processor 103 can read and write data in units of cache lines through the data transmission interface 104, which are typically 64 bytes long. The format of the data read and write command requests issued by the data transmission interface 104 to the programmable logic device 100 may have the following requirements: the offset address is aligned to 64 bytes, the length is 64 bytes (i.e., one cache line), and the offset address starts at 0. The 64-byte alignment of the offset address means that the offset address must be a multiple of 64; the 64-byte length means that the length of each read or write data is 64 bytes; and the 0-starting offset address means that the offset address starts at 0.

[0063] In the data processing device 10 , the processor 103 may also be configured to send a configuration command to the programmable logic device 100 . The configuration command may be used to configure parameters of the programmable logic device 100 .

[0064] The control interface 105 is connected to the processor 103 and the programmable logic unit 100 respectively, and can be used to transmit configuration commands. In other words, the processor 103 can send configuration commands to the programmable logic unit 100 through the control interface 105 to configure the parameters of the programmable logic unit 100 through the configuration commands.

[0065] For example, the parameters of the programmable logic device 100 may include, but are not limited to, parameters for initializing the programmable logic device and parameters for setting a working mode of the programmable logic device.

[0066] The control interface 105 may also transmit configuration commands based on the CXL protocol. For example, the control interface 105 may be a CXL.io interface.

[0067] The data processing device provided in the embodiment of the present application can set a data transmission interface 104 for data transmission and a control interface 105 for configuration command transmission between the processor 103 and the programmable logic device 100, so as to separate the data transmission process and the configuration process between the processor 103 and the programmable logic device 100 to avoid mutual interference between the two processes.

[0068] Secondly, combined Figure 3 and Figure 4 , the structure of the programmable logic device 100 in the above-mentioned data processing device is described in detail.

[0069] Figure 3 This is one of the structural diagrams of the programmable logic device provided in the embodiment of this application. Figure 3 The programmable logic device 100 includes a request processing unit 1000 and a storage unit 1001.

[0070] like Figure 3 As shown, the request processing unit 1000 is connected to the first memory 101 and the storage unit 1001 respectively, and the storage unit 1001 is also connected to the second memory 102.

[0071] The request processing unit 1000 may be configured to receive a data access request and obtain target data from the first memory 101 through the storage unit 1001 .

[0072] The request processing unit 1000 can be connected to the processor 103 through the data transmission interface 104. The request processing unit 1000 can receive the data access request sent by the processor 103 through the data transmission interface 104, and obtain the target data from the first memory 101 through the storage unit 1001, and send the target data corresponding to the data access request to the processor 103 through the data transmission interface 104.

[0073] The storage unit 1001 can be used to determine whether the target data is stored in the first memory 101 based on the data access request and the mapping relationship between the data in the first memory 101 and the data in the second memory 102; if the target data is not stored in the first memory 101, the target data is stored from the second memory 102 to the first memory 101, and the mapping relationship is updated, and the request processing unit 1000 is assisted in querying and obtaining the target data from the first memory 101.

[0074] In some embodiments, the terms "request processing unit" and "CXL processing unit" or "CXL processing module" are interchangeable, and the terms "storage unit" and "cache unit", "cache module", "Cache unit" or "cache module" are interchangeable.

[0075] In some embodiments, the structure of the programmable logic device 100 can also be as follows: Figure 4 shown. Figure 4 This is the second structural diagram of the programmable logic device provided in the embodiment of the present application. Figure 4 ,exist Figure 3 Based on the structure of the programmable logic device shown, the programmable logic device 100 may further include: a page layering unit 1002 , an access prediction unit 1003 , a recycling unit 1004 , a first read / write unit 1005 and a second read / write unit 1006 .

[0076] like Figure 4 As shown, the page layering unit 1002 is connected to the request processing unit 1000 and the access prediction unit 1003 respectively, the access prediction unit 1003 is also connected to the storage unit 1001, the recycling unit 1004 is connected to the page layering unit 1002 and the storage unit 1001 respectively, the first read-write unit 1005 is connected to the request processing unit 1000 and the first memory 101 respectively, and the second read-write unit 1006 is connected to the storage unit 1001 and the second memory 102 respectively.

[0077] It should be noted that the specific working processes of the page layering unit 1002, the access prediction unit 1003, the recycling unit 1004, the first read-write unit 1005 and the second read-write unit 1006 will be described in detail in subsequent method embodiments.

[0078] In order to facilitate understanding of the data processing method provided in the embodiment of the present application, before describing the data processing method provided in the embodiment of the present application, the mapping relationship between the data of the first memory and the data of the second memory in the present application is explained.

[0079] Data can be stored in the first memory or the second memory in units of pages. The first memory may include multiple first storage pages, and the second memory may include multiple second storage pages. In other words, the mapping relationship between data in the first memory and data in the second memory can be represented by the mapping relationship between multiple first storage pages and multiple second storage pages.

[0080] Optionally, the programmable logic device may establish a mapping relationship between the first storage page and the second storage page based on a mapping ratio between the first storage and the second storage configured by the processor. Assuming that the mapping ratio between the first storage and the second storage is N:M, it means that N first storage pages are used to map and store data of M second storage pages, where N and M are both positive integers and M is greater than N. For example, a mapping ratio of 4:64 means that 4 first storage pages are used to map and store data of 64 second storage pages, that is, data of 4 second storage pages out of the 64 second storage pages are stored in 4 first storage pages of the first memory at a time.

[0081] For example, the first memory is DDR with a storage capacity of 1GB; the second memory can be an SSD with a storage capacity of 16GB. The mapping ratio between the first memory and the second memory is 4:64. When caching data from a 16GB SSD using 1GB of DDR, data can be stored in pages from the SSD to the DDR. Four DDR pages (i.e., the first storage pages) are mapped to cache data from 64 SSD pages (i.e., the second storage pages). In other words, data from four of the 64 SSD pages is stored in four DDR pages of the first memory at a time.

[0082] Exemplarily, the processor 103 may configure a mapping ratio between the first memory and the second memory through the control interface 105 , and the mapping ratio may be used by the programmable logic device to perform mapping processing on multiple first storage pages of the first memory and multiple second storage pages of the second memory.

[0083] In some embodiments, the mapping relationship between multiple first storage pages and multiple second storage pages can be stored in a mapping table, which may include multiple mapping information corresponding to multiple first storage pages. For any first storage page, the mapping information corresponding to the first storage page can be used to indicate the second storage page mapped by the first storage page.

[0084] In some embodiments, the programmable logic device may divide multiple first storage pages in the first memory into multiple cache groups, each of which may include at least one first storage page, wherein each first storage page in the at least one first storage page may map to multiple second storage pages. While maintaining a constant mapping ratio between the first memory and the second memory, the number of cache groups corresponding to the first memory may vary as the storage capacity of the second memory changes.

[0085] Optionally, the programmable logic device can split multiple mapping information in the mapping table to obtain multiple sub-mapping tables, each of which can include at least one mapping information corresponding to at least one first storage page, and the at least one first storage page belongs to the same cache group.

[0086] In some embodiments, the mapping table may be stored in a third memory, which may be a memory in a programmable logic device. Exemplarily, the third memory may include, but is not limited to, a static random access memory (SRAM).

[0087] The programmable logic device can determine the storage capacity required for the mapping table in the third memory based on the storage capacity required for each mapping information in the mapping table and the total number of mapping information; or, the programmable logic device can also determine the storage capacity required for the mapping table in the third memory based on the storage capacity required for each sub-mapping table in the mapping table and the total number of sub-mapping tables. For any sub-mapping table, the storage capacity required for the sub-mapping table is the sum of the storage capacity required for all mapping information in the sub-mapping table.

[0088] For example, the second memory may be an SSD with a storage capacity of 16 GB. If the mapping unit is 4 KB (4096 Bytes), the number of SSD pages (i.e., the second storage page mentioned above) can be calculated as 16 GB ÷ 4 KB = 2 22 =4194304. The first memory can be DDR, and the storage capacity of the DDR is 1GB. If it is divided into 4KB (4096Bytes) mapping units, the number of DDR pages (i.e., the first storage page mentioned above) can be calculated as 1GB ÷ 4KB = 2 18 =262144. If 4 DDR pages are used as a cache group, the number of cache groups can be calculated as 262144÷4=2 16 =65536. When caching data from a 16GB SSD using 1GB of DDR, the programmable logic device can create a mapping table containing 262,144 entries. This mapping table can be split into 65536 sub-mapping tables, each of which can store four entries corresponding to four DDR pages in the same cache group. Each entry requires 1.25 bytes of storage, and each sub-mapping table requires 5 bytes of storage. Therefore, the third memory capacity required for the mapping table corresponding to 1GB of DDR is 5 bytes × 65536 = 327,680 bytes, which equals 320KB.

[0089] In some embodiments, the programmable logic device can encode the address of each first storage page in the first memory. The storage structure of the encoded address of the first storage page may include the following information: the first page number of the first storage page and the offset information within the page. The first page number may include the first page identifier of the first storage page in the cache group and the identifier of the cache group where the first storage page is located. For example, if the first storage page is a DDR page, the "first page number identifier" can be expressed as "DDRTag" and the "identifier of the cache group" can be expressed as "Cache Tag".

[0090] For example, if the first memory is DDR, the storage capacity of DDR is 1GB (2 18 × 4KB), we can calculate that the number of pages of the first storage page is 2 18 In the process of encoding the address of the first storage page, the first page number of the first storage page can be identified by an 18-bit code, and the offset information within the page can be identified by a 12-bit code. 2 ) DDR pages are divided into a cache group. The first page identifier (DDR Tag) of the DDR page in the cache group can be identified by a 2-bit code; the 262144 DDR pages in 1GB of DDR can be divided into 2 16 Cache groups, each cache group's identifier (CacheTag) can be identified by a 16-bit code.

[0091] Figure 5A This is a schematic diagram of the storage structure of the address of the first storage page provided in the embodiment of the present application. Figure 5A The address of the first memory page (DDR page) consists of 30 bits. The upper two bits (29-28) store the first page identifier (DDR Tag) of the DDR page, the middle 16 bits (27-12) store the cache tag of the cache group where the DDR page resides, and the lower 12 bits (11-0) store the offset within the DDR page. The first page number of a DDR page can be composed of the DDR Tag and the Cache Tag.

[0092] In some embodiments, the programmable logic device may encode an address of each second memory page in the second memory, where the address of the second memory page is an address of the first memory mapped from the second memory address range, starting from offset 0.

[0093] The storage structure of the encoded address of the second storage page may include the following information: the second page number of the second storage page and the offset information within the page. The second page number may include the second page identifier of the second storage page and the identifier of the cache group to which the first storage page mapped by the second storage page is located. For example, if the second storage page is an SSD page, the "second page identifier" may be represented as "SSD Tag" and the "cache group identifier" may be represented as "Cache Tag".

[0094] For example, if the second memory is an SSD, the storage capacity of the SSD is 16 GB (2 22 × 4KB), we can calculate that the number of pages in the second storage page is 2 22 In the process of encoding the address of the second storage page, the second page number of the second storage page can be identified by a 22-bit code, and the offset information within the page can be identified by a 12-bit code. If a 1GB DDR cache is used for the 16GB SSD, the 262144 DDR pages in the 1GB DDR can be divided into 2 16 Cache groups, each cache group's identifier (Cache Tag) can be identified by a 16-bit code, and the 4 DDR pages in each cache group can map 64 (i.e., 2 6 ) SSD pages, the second page identifier of the second storage page can be identified by a 6-bit code.

[0095] Figure 5B This is a schematic diagram of the storage structure of the address of the second storage page provided in the embodiment of the present application. Figure 5B The SSD page address consists of 34 bits. The upper 6 bits (33-28) store the SSD page's second page identifier (SSD Tag), the middle 16 bits (27-12) store the cache group identifier (Cache Tag) of the DDR page mapped to the SSD page, and the lower 12 bits (11-0) store the page offset. The SSD page's second page number can be composed of the SSD Tag and the Cache Tag.

[0096] In the process of address encoding, the second page numbers of the second storage pages corresponding to the same cache group differ by 2 28 Bytes; the first page numbers of the first storage pages corresponding to the same cache group differ by 2 28Bytes; the first page numbers of the first storage pages corresponding to adjacent cache groups are continuous, that is, there is no gap between the first page number of the last first storage page in a cache group (for example, cache group 0) and the first page number of the first first storage page in the next cache group (for example, cache group 1); the second page numbers of the second storage pages corresponding to adjacent cache groups are continuous, that is, there is no gap between the second page number of the second storage page mapped by the last first storage page in a cache group (for example, cache group 0) and the second page number of the second storage page mapped by the first first storage page in the next cache group (for example, cache group 1). This address encoding process is based on the principle of locality. When the addresses of the second storage pages (for example, SSD addresses) are continuous, the addresses of the first storage pages (for example, DDR addresses) are also continuous. When accessing adjacent continuous addresses, this ensures that the second storage page (for example, SSD page) will not be replaced out of the first memory (for example, DDR).

[0097] In the process of mapping the first storage page and the second storage page, the identifier of the cache group where the first storage page is located and the intra-page offset information in the storage structure of the address of the first storage page are the same information as the identifier and intra-page offset information of the cache group where the first storage page mapped by the second storage page is located in the storage structure of the address of the second storage page. Therefore, in the process of storing the mapping relationship between the first storage page and the second storage page, it is not necessary to store the same information to save the storage space occupied by the mapping table. In view of this, an embodiment of the present application also provides a storage structure of a sub-mapping table, and the storage structure of the sub-mapping table may include: the identifier of the cache group corresponding to the sub-mapping table, the first page identifier of each first storage page in at least one first storage page in the cache group corresponding to the sub-mapping table, and the storage domain corresponding to each first page identifier.

[0098] For any first page identifier, the storage domain corresponding to the first page identifier may include a page identifier domain, an index domain, and a status information domain. The page identifier domain may be used to store a second page identifier of a second storage page mapped to the first storage page; the index domain may be used to store an access sequence index of the first storage page; and the status information domain may be used to store status information of the first storage page, which may include a first flag bit and a second flag bit.

[0099] Exemplarily, in the sub-mapping table, each first page identifier may occupy 2 bits; the page identifier field may occupy 6 bits; the index field may occupy 2 bits; and the status information field may occupy 2 bits, wherein the first flag bit and the second flag bit each occupy 1 bit.

[0100] In the storage structure of the sub-mapping table, the programmable logic device can determine the least recently used first storage page in the first storage pages corresponding to at least one first page identifier based on the access sequence index of the first storage page in the index field corresponding to at least one first page identifier.

[0101] The state information of the first storage page can be used to indicate the storage state of the first storage page. Figure 11 Detailed description is given in .

[0102] Figure 6A For an exemplary schematic diagram of the storage structure of the sub-mapping table provided in the embodiment of the present application, see Figure 6A The cache group corresponding to the sub-mapping table is identified as cache group 0. Cache group 0 includes four first cache pages. The first page identifiers of these four first storage pages are 0, 1, 2, and 3, respectively representing the first first storage page, the second first storage page, the third first storage page, and the fourth first storage page in cache group 0. The storage structure of the sub-mapping table may include four storage fields corresponding to these four first page identifiers. Each storage field may include a page identifier field, an index field, and a status information field. The status information field includes a first flag bit and a second flag bit.

[0103] Figure 6B For a schematic diagram of the storage structure of the mapping table provided in the embodiment of this application, please refer to Figure 6B The storage structure of the mapping table may include storage structures of multiple sub-mapping tables arranged in order (from large to small or from small to large).

[0104] The size of the mapping information in the mapping table may vary with the mapping ratio between the first memory and the second memory, but may not vary with the storage capacity of the second memory. For example, if the mapping ratio between the first memory and the second memory is 4GB:64GB, the first page identifier (DDR Tag) in the address of the first storage page occupies 2 bits, and the second page identifier (SSD Tag) in the address of the second storage page occupies 6 bits.

[0105] Below, in combination with the data processing method provided in the embodiment of the present application, the working process of the above-mentioned data processing device 10, programmable logic device 100, and the request processing unit 1000, storage unit 1001, page layering unit 1002, access prediction unit 1003, recycling unit 1004, first read-write unit 1005 and second read-write unit 1006 in the programmable logic device 100 are described in detail.

[0106] Figure 7 This is one of the flow charts of the data processing method provided in the embodiment of the present application, such as Figure 7As shown, the embodiment of the present application provides a data processing method, which is described in detail as follows:

[0107] S701: Receive a data access request.

[0108] See Figure 2 , the processor 103 can send a data access request to the programmable logic device 100 through the data transmission interface 104 .

[0109] In some embodiments, the "data access request" may also be referred to as a "Host access request" or a "Host memory page access message."

[0110] In some embodiments, the processor 103 may also send a data access request to the programmable logic device 100 through the data transmission interface 104. Specifically, the processor 103 may send a data access request to the request processing unit 1000 in the programmable logic device 100 through the data transmission interface 104.

[0111] S702: Determine whether target data corresponding to the data access request is stored in the first memory according to the data access request and a mapping relationship between the data in the first memory and the data in the second memory.

[0112] The mapping relationship includes at least one first page identifier and a second page identifier corresponding to each first page identifier; at least one first page identifier is used to indicate at least one first storage page of the first memory; for any first page identifier, the second page identifier corresponding to the first page identifier is used to indicate the second storage page in the second memory, and the data mapping in the second storage page is stored in the first storage page indicated by the first page identifier.

[0113] The mapping relationship may further include an access sequence index and status information of at least one first storage page indicated by at least one first page identifier.

[0114] Optionally, the mapping relationship between the data in the first memory and the data in the second memory can be stored in a mapping table, which can include multiple sub-mapping tables. These multiple sub-mapping tables can be correspondingly stored in multiple storage units 1001, and each storage unit is used to manage data access requests in the corresponding sub-mapping table. For example, the mapping table may include 2 16 Sub-mapping tables, correspondingly, 2 can be set in the programmable logic device 100 16 Storage unit 1001.

[0115] The data processing device 10 may execute step S702 through the programmable logic device 100. The request processing unit 1000 in the programmable logic device 100 may send the received data access request to the storage unit 1001, and obtain the target data from the first memory 101 through the storage unit 1001.

[0116] Each storage unit 1001 in the programmable logic device 100 can support multiple data access requests simultaneously. For any storage unit 1001, if a second data access request comes while the storage unit 1001 is processing a first data access request, the storage unit 1001 can handle the request in the following two ways:

[0117] Case 1: The second data access request and the first data access request request access the same target data, that is, the second data access request and the first data access request both need to access data in the same second storage page.

[0118] In case 1, the storage unit 1001 may continue to process the first data access request until the processing of the first data access request is completed, and then may process the second data access request.

[0119] Case 2: The target data requested to be accessed by the second data access request is different from that requested to be accessed by the first data access request, that is, the second data access request and the first data access request need to access data in different second storage pages.

[0120] In case 2, the storage unit 1001 can determine whether the target data corresponding to the second data access request is stored in the first memory based on the second data access request and the sub-mapping table stored in the storage unit 1001; if the target data corresponding to the second data access request is stored in the first memory, the second data access request is processed; if the target data corresponding to the second data access request is not stored in the first memory, the second data access request is forwarded to other storage units 1001 so that the second data access request can be processed by other storage units 1001.

[0121] After receiving the data access request, the data processing device 10 (or the programmable logic device 100 in the data processing device 10, or the storage unit 1001 in the programmable logic device 100) may be configured to perform the following steps: parsing the data access request to obtain a target second page identifier, where the target second page identifier is used to indicate a second storage page in the second memory for storing the target data; if at least one second page identifier corresponding to at least one first page identifier in the mapping relationship includes the target second page identifier, determining that the target data is stored in the first memory; and if the at least one second page identifier does not include the target second page identifier, determining that the target data is not stored in the first memory.

[0122] The data access request may include the address of the first memory (also referred to as "host CXL memory"), where the first memory address = CXL offset + the address of the second memory page. The second memory page address is the address of the second memory address range mapped to the first memory, starting at offset 0. The second memory page address includes the second page identifier (SSDTag), the cache group identifier (Cache Tag), and the cache line identifier (Line Tag).

[0123] Figure 8 This is a diagram of the address mapping relationship provided in this application embodiment. Figure 8 Taking the second memory as a 16GB SSD as an example, the address of the second storage page can be 34 bits, including: 6-bit second page identifier (SSDTag), 16-bit cache group identifier (Cache Tag), 6-bit cache line identifier (Line Tag) and 6-bit line offset value (Cache Line), and the line offset value occupies 64 bytes. The address of the first storage page can be 30 bits, including: 2-bit first page identifier (DDR Tag), 16-bit cache group identifier (Cache Tag) and 12-bit page offset information. Figure 8 As shown, there is a mapping relationship between the sub-mapping table, the address of the first storage page, and the address of the second storage page.

[0124] For example, the request processing unit 1000 may receive a data access request from the processor 103 through the data transmission interface 104, and forward the data access request to the storage unit 1001. The data access request may include a CXL read / write command. The storage unit 1001 may process the address (e.g., Figure 8 The CXL read / write command is parsed and processed to determine a target second page identifier corresponding to the CXL read / write command. The target second page identifier can be used to indicate a second storage page in the second memory, which is used to store the target data to be read or written by the CXL read / write command in the second memory. The storage unit 1001 can compare the target second page identifier corresponding to the CXL read / write command with at least one second page identifier stored in the sub-mapping table. If the target second page identifier is included in the at least one second page identifier stored in the sub-mapping table, it indicates that the target data is stored in the first memory. If the target second page identifier is not included in the at least one second page identifier stored in the sub-mapping table, it indicates that the target data is not stored in the first memory.

[0125] If it is determined that the target data is stored in the first memory, the data processing device or programmable logic unit may further be configured to perform the following steps: based on the target second page identifier and the mapping relationship, determine the first page identifier of the first storage page mapped by the second storage page in the first memory, and send the first page identifier to the request processing unit 1000. Specifically, the storage unit 1001 may search the sub-mapping table for the first page identifier corresponding to the target second page identifier.

[0126] If it is determined that the target data is not stored in the first memory, the storage unit 1001 may continue to execute step S703.

[0127] After receiving the first page identifier sent by the storage unit 1001 , the request processing unit 1000 can query the first memory 101 through the first read-write unit 1005 to obtain the target data.

[0128] The first read / write unit 1005 can be used to request the processing unit 1000 to read or write data from the first memory 101. The request processing unit 1000 can send a read / write command to the first read / write unit 1005. The read / write command can include a first page identifier. The first read / write unit 1005 can query the first storage page corresponding to the first page identifier based on the first page identifier to obtain the target data required for the read / write command, and send the target data to the request processing unit 1000. The request processing unit 1000 can send the target data to the processor 103 via the data transmission interface 104.

[0129] S703: If the target data is not stored in the first memory, the target data is stored from the second memory to the first memory, the mapping relationship is updated, and the target data is obtained by querying in the first memory.

[0130] The data processing device 10 may execute step S703 via the programmable logic unit 100. Specifically, if the target data is not stored in the first memory, the storage unit 1001 in the programmable logic unit 100 may be configured to execute the following steps: store the target data from the second memory to the first memory, update the mapping relationship, and assist the requesting processing unit in querying the target data from the first memory.

[0131] Optionally, the data processing device 10 (or the programmable logic unit 100 in the data processing device 10) can be used to perform the following steps: determine a target storage page in at least one first storage page of the first memory, the target storage page being the least recently used first storage page in the at least one first storage page; determine the storage status of the target storage page; store the target data from the second memory to the target storage page according to the storage status; and update the mapping relationship according to the first page identifier of the target storage page and the second page identifier of the second storage page in the second memory for storing the target data.

[0132] The following describes the process of determining the target storage page.

[0133] In some embodiments, the mapping relationship may further include an access sequence index of at least one first storage page indicated by at least one first page identifier. The programmable logic device 100 (or storage unit 1001) may determine a target storage page from the at least one first storage page corresponding to the at least one first page identifier using a least recently used (LRU) algorithm based on the access sequence index of the at least one first storage page.

[0134] like Figure 6B As shown, the mapping relationship is stored in a mapping table, which includes multiple sub-mapping tables. The storage structure of the sub-mapping table includes an index field corresponding to the first page identifier, and the index field stores the access sequence index of the first storage page corresponding to the first page identifier.

[0135] The storage unit 1001 in the programmable logic device 100 can use the LRU algorithm to sort the access sequence index of at least one first storage page stored in the sub-mapping table in the storage unit 1001 to determine the target storage page in the at least one first storage page, and the access sequence index value of the target storage page is the largest.

[0136] If the number of at least one first storage page is N, where N is an integer greater than 1. After each data access request is received, the storage unit 1001 may dynamically update the access sequence indexes of the N first storage pages as follows: the access sequence index of the target storage page accessed by the data access request is set to the minimum value, the access sequence index of the first storage page to be updated is increased by 1, and the first storage page to be updated is the first storage page among the N first storage pages, excluding the target storage page, and whose access sequence index is less than or equal to the access sequence index of the target storage page.

[0137] Optionally, if the number of the at least one first storage page is N, where N is an integer greater than 1, the minimum value may be set to 0, and the maximum value may be set to N-1.

[0138] Next, combine Figure 9, taking the access sequence indexes of 4 first storage pages stored in the sub-mapping table as an example, the change of the access sequence indexes of the 4 first storage pages in the sub-mapping table is described.

[0139] Figure 9 This is a schematic diagram of the access order index changes of each first storage page in the sub-mapping table provided in the embodiment of the present application. Figure 9 In the initial state, the access sequence indexes of the four first storage pages (first storage page 1 to first storage page 4) in the sub-mapping table in the storage unit 1001 are all set to 3.

[0140] If the storage unit 1001 receives a data access request for the first storage page 1, the access sequence index of the first storage page 1 is set to 0, and the access sequence indexes of the other three first storage pages are not processed. In this case, the target storage pages can be the first storage page 2 to the first storage page 4.

[0141] Afterwards, if the storage unit 1001 receives a data access request for the first storage page 2, the access sequence index of the first storage page 2 is set to 0, and the access sequence index of the first storage page 1 is increased by 1. After updating the access sequence index, the target storage pages can be the first storage page 3 and the first storage page 4.

[0142] Afterwards, if the storage unit 1001 continues to receive data access requests for the first storage page 2, the access sequence indexes of the four first storage pages remain unchanged. In this case, there is no need to update the access sequence indexes, and the target storage pages are still the first storage page 3 and the first storage page 4.

[0143] Afterwards, if the storage unit 1001 receives a data access request for the first storage page 3, the access sequence index of the first storage page 3 is set to 0, and the access sequence index of the first storage page 1 and the first storage page 2 is increased by 1. After updating the access sequence index, the target storage page is the first storage page 4.

[0144] Afterwards, if the storage unit 1001 receives a data access request for the first storage page 4, the access sequence index of the first storage page 4 is set to 0, and the access sequence index of the first storage page 1 to the first storage page 3 is increased by 1. After updating the access sequence index, the target storage page is the first storage page 1.

[0145] Afterwards, if the storage unit 1001 receives a data access request for the first storage page 3, the access sequence index of the first storage page 3 is set to 0. Since the access sequence indexes of the first storage page 1 and the first storage page 2 are greater than the access sequence index before the first storage page 3 is updated, the access sequence indexes of the first storage page 1 and the first storage page 2 will not be changed at this time, but the access sequence index of the first storage page 4 will be increased by 1. After updating the access sequence index, the target storage page is still the first storage page 1.

[0146] Afterwards, if the storage unit 1001 receives a data access request for the first storage page 1, the access sequence index of the first storage page 1 is set to 0. At this time, the access sequence indexes of the first storage page 2 to the first storage page 4 are all less than 3, so the access sequence indexes of the first storage page 2 to the first storage page 4 are all increased by 1. After updating the access sequence index, the target storage page is the first storage page 2.

[0147] Next, combine Figure 10 , a process of determining the storage status of a target storage page is described.

[0148] Figure 10 The second flow chart of the data processing method provided in the embodiment of the present application is as follows: Figure 10 As shown, the embodiment of the present application provides a data processing method, which is described in detail as follows:

[0149] S1001. Obtain status information of a target storage page.

[0150] The status information includes a first flag bit and a second flag bit.

[0151] like Figure 6A As shown in FIG6B , the storage structure of the sub-mapping table includes a status information field, and the storage unit 1001 can obtain the status information of the target storage page from the status information field corresponding to the target storage page.

[0152] S1002: Determine the storage status of the target storage page according to the status information of the target storage page.

[0153] If the value of the first flag bit is the first numerical value and the value of the second flag bit is the first numerical value, the storage state of the target storage page is determined to be the first state; if the value of the first flag bit is the second numerical value and the value of the second flag bit is the first numerical value, the storage state of the target storage page is determined to be the second state; if the value of the first flag bit is the second numerical value and the value of the second flag bit is the second numerical value, the storage state of the target storage page is determined to be the third state.

[0154] For example, the first value may be 0, and the second value may be 1.

[0155] In some embodiments, the "first flag bit" can be represented as a "valid bit", the "second flag bit" can be represented as a "Dirty bit", the "first state" can be represented as "Invalid", the "second state" can be represented as "Clean", and the "third state" can be represented as "Dirty".

[0156] Next, combine Figure 11 , describing the changes in the storage status of the target storage page. Figure 11 This is a schematic diagram of the change in storage state of a target storage page provided in an embodiment of the present application. Figure 11 , the target storage page includes three storage states: a first state, a second state and a third state.

[0157] In the initial case, the first flag bit and the second flag bit in the status information are both set to 0, that is, the storage status of the target storage page is the first state. At this time, the data of the second storage page is not mapped and stored in the target storage page, and the second page identifier in the page identifier field corresponding to the target storage page in the sub-mapping table stored in the storage unit 1001 is an invalid identifier.

[0158] In the case where the data access request needs to access the second storage page, the storage unit 1001 needs to store the data in the second storage page in the target storage page. After the storage is completed, the storage unit 1001 updates the second page identifier in the page identifier field corresponding to the target storage page in the sub-mapping table to the second page identifier of the second storage page that the data access request needs to access, and updates the value of the first flag bit in the status information of the target storage page from 0 to 1. At this time, the storage status of the target storage page is updated to the second status.

[0159] When the target storage page is modified, the storage unit 1001 may update the value of the second flag bit in the status information of the target storage page from 0 to 1. At this time, the storage status of the target storage page is updated to the third status.

[0160] When the data in the target storage page is written back to the second storage page, the storage unit 1001 may update the value of the second flag bit in the status information of the target storage page from 1 to 0. At this time, the storage status of the target storage page is restored to the second status.

[0161] When the target storage page is being recycled, if the value of the first flag bit is 1, the storage unit 1001 can modify the status information in the following two ways:

[0162] Method 1: If the storage state of the target storage page is the second state, that is, the second flag bit value is 0, the storage unit 1001 can update the first flag bit value in the status information of the target storage page from 1 to 0. At this time, the storage state of the target storage page is restored to the first state.

[0163] Method 2: If the storage state of the target storage page is the third state, that is, the value of the second flag bit is 1, the storage unit 1001 can perform the following steps: write the data in the target storage page back to the second storage page; after the write back is successful, first update the value of the second flag bit from 1 to 0, at this time, the storage state of the target storage page is restored to the second state; then update the value of the first flag bit from 1 to 0, at this time, the storage state of the target storage page is restored to the first state.

[0164] If the storage state is the first state, the storage unit 1001 stores the target data in the target storage page based on the first state; if the storage state is the second state, the storage unit 1001 updates the storage state to the first state, and stores the target data in the target storage page based on the first state; if the storage state is the third state, the storage unit 1001 writes the data currently stored in the target storage page into the second memory, and after the writing is completed, updates the storage state to the first state, and stores the target data in the target storage page based on the first state.

[0165] In some embodiments, storing the target data in the target storage page based on the first state includes the following steps: reading the target data from the second memory into the target storage page; and updating the value of the first flag bit to the second value after the reading is completed.

[0166] Next, combine Figure 12 , explaining the changes in the working status of the storage unit. Figure 12 This is a schematic diagram of the change in the working state of a storage unit provided in an embodiment of the present application. Figure 11 ,The working states of the storage unit include the following four states: idle state, comparison state, read-in state, and write-back state.

[0167] When the storage unit does not process a data access request, that is, the storage unit is not accessed, the storage unit is in an idle state.

[0168] When the storage unit receives a data access request sent by the request processing unit, the storage unit first reads the target second page identifier in the data access request and compares the target second page identifier with at least one second page identifier stored in the sub-mapping table of the storage unit. At this time, the storage unit is in a comparison state.

[0169] After the comparison is completed, the following results are obtained:

[0170] A. If the target second page identifier (e.g., SSD Tag) is found in the sub-mapping table of the storage unit, it indicates a hit, and the storage unit refreshes the access order index of each first page identifier in the sub-mapping table according to the LRU algorithm (e.g., Figure 9 As shown), and sends the first page identifier (for example, DDR Tag) corresponding to the target second page identifier to the request processing unit, and then the storage unit enters the idle state;

[0171] B. If the target second page identifier (e.g., SSD Tag) is not found in the sub-mapping table of the storage unit, it indicates a miss. The storage unit needs to find the target storage page in at least one first storage page corresponding to at least one first page identifier in the sub-mapping table according to the LRU algorithm. The target storage page is the least recently used first storage page, and the access order index of each first page identifier in the sub-mapping table is refreshed. The subsequent operations are as follows:

[0172] Case 1: If the values ​​of the first flag bit and the second flag bit in the status information of the target storage page in the sub-mapping table are both the first value (e.g., 0), the operating state of the storage unit switches from the comparison state to the read state. In the read state, the storage unit reads the data from the second storage page corresponding to the target second page identifier in the second memory into the target storage page. After the read is completed, the storage unit updates the value of the first flag bit in the status information of the target storage page to the second value (e.g., 1), updates the second page identifier corresponding to the target storage page in the sub-mapping table to the target second page identifier, and the operating state of the storage unit returns from the read state to the comparison state.

[0173] Case 2: If the value of the first flag bit in the status information of the target storage page in the sub-mapping table is the second value (for example, 1), and the value of the second flag bit is the first value (for example, 0), the storage unit updates the value of the first flag bit in the status information of the target storage page to the first value, and the working state of the storage unit changes from the comparison state to the read state. The subsequent operation is the same as the operation of the storage unit after the read state in Case 1.

[0174] Case 3: If the value of the first flag bit in the status information of the target storage page in the sub-mapping table is the second value (for example, 1), and the value of the second flag bit is the second value (for example, 1), the working state of the storage unit is changed from the comparison state to the write-back state, and the storage unit writes the data in the target storage page back to the second memory, and after the write-back is completed, the value of the first flag bit and the value of the second flag bit in the status information of the target storage page are both updated to the first value, and the working state of the storage unit is changed from the comparison state to the read-in state, and the subsequent operations are the same as the operations of the storage unit after the read-in state in Case 1.

[0175] C. The storage unit enters the comparison state again under the access of the new data access request. If, after comparison, the target second page identifier in the new data access request exists in the sub-mapping table of the storage unit, it indicates a hit. The subsequent operation of the storage unit can refer to the operation of the storage unit after the hit in step A.

[0176] In some cases, if a storage unit receives a new data access request, but data reading fails when it was previously in the read-in state, the storage unit needs to continue to be in the read-in state; or, if data reading fails when it was previously in the write-back state, the storage unit needs to continue to be in the write-back state.

[0177] In one example, the storage unit can use 4 first storage pages to map and cache 64 second storage pages during design, and the sub-mapping table of the storage unit can include 4 mapping information corresponding to the 4 first storage pages. When the storage unit is not accessed, it is in an idle state. When the request processing unit enables the storage unit request, that is, the request processing unit sends a data access request to the storage unit, the storage unit first reads the target second page identifier in the data access request, and compares the target second page identifier with the second page identifiers in the 4 mapping information stored in the sub-mapping table; if the second page identifiers in the 4 mapping information include the target second page identifier, that is, a hit, the storage unit refreshes the access order index of each first page identifier in the sub-mapping table according to the LRU algorithm (such as Figure 9 As shown), the first page identifier corresponding to the target second page identifier is returned to the request processing unit. If the second page identifiers in the four mapping information do not include the target second page identifier, the target mapping information is determined from the four mapping information according to the LRU algorithm. The target mapping information is the least recently used mapping information in the four mapping information. If the storage state of the first storage page indicated by the target mapping information is the first state, the storage unit executes Figure 12 The operation in case 1 shown in FIG. 1; if the storage state of the first storage page indicated by the target mapping information is the second state, the storage unit performs Figure 12 The operation in case 2 shown in FIG. 2; if the storage state of the first storage page indicated by the target mapping information is the third state, the storage unit performs Figure 12 The operation in case 3 is shown.

[0178] like Figure 4 As shown, the programmable logic device 100 is provided with a second read / write unit 1006, which can be used for the storage unit to read and write data from the second memory. The storage unit 1001 in the programmable logic device 100 can use the second read / write unit 1006 to write data from the first memory back to the second memory, or read data from the second memory into the first memory.

[0179] The data processing method provided in the embodiment of the present application can quickly determine whether the target data corresponding to the data access request is stored in the first memory based on the mapping relationship between the data in the first memory and the data in the second memory and the data access request, thereby avoiding wasting time by directly querying in the first memory when the target data is not stored in the first memory. In addition, when the target data is not stored in the first memory, the target data is cached from the second memory to the first memory to facilitate rapid query of the target data through the first memory, which is beneficial to reducing the access latency of the target data.

[0180] Figure 13 The third flow chart of the data processing method provided in the embodiment of the present application is as follows: Figure 13 As shown, the embodiment of the present application provides a data processing method, which is described in detail as follows:

[0181] S1301: Determine heat values ​​of multiple second storage pages of a second memory.

[0182] In some embodiments, the data processing device 10 or the programmable logic device 100 in the data processing device can be used to perform step S1301. Figure 4 As shown, the programmable logic device 100 is provided with a page layering unit 1002 , and the page layering unit 1002 can be used to determine the heat values ​​of multiple second storage pages in the second memory.

[0183] Optionally, the page layering unit 1002 may periodically determine the heat values ​​of the plurality of second storage pages in the second memory.

[0184] A user may configure the page layering unit of the data processing device to determine the period (i.e., unit time interval) of the heat value. For example, the user may trigger the data processing device to cause the processor 103 in the data processing device to issue a configuration command to the programmable logic device 100 via the control interface 105 (e.g., the CXL.io interface). The configuration command includes a period (e.g., 50 milliseconds) of the heat value. The page layering unit 1002 in the programmable logic device 100 may then periodically determine the heat values ​​of the plurality of second storage pages in the second memory based on the period indicated in the configuration command.

[0185] In some embodiments, for any second storage page among multiple second storage pages in the second memory, the page layering unit 1002 can determine the heat value of the second storage page by performing the following steps: if the second storage page is accessed within the first time length, the heat value of the second storage page is updated from the first heat value to the second heat value, and the second heat value is the sum of the first heat value and the heat offset value; if the second storage page is not accessed within the second time length, the heat value of the second storage page is updated from the first heat value to the third heat value, and the third heat value is the difference between the first heat value and the heat offset value; wherein, the second time length is M times the first time length, and M is an integer greater than 1.

[0186] For example, the thermal offset value may be set to 1 and M may be set to 2.

[0187] In some embodiments, the page layering unit may use two clocks to record the first duration and the second duration respectively. For example, the duration measured by clock 1 is the first duration, and the duration measured by clock 2 is the second duration.

[0188] For any second storage page, the heat value update process of the second storage page can be as follows:

[0189] Heat value counting process: When the falling edge of clock 1 is triggered, it is determined whether the second storage page is accessed within the first time length recorded by clock 1. If it is accessed, the heat value is increased by 1; otherwise, it remains unchanged.

[0190] Heat value count reduction process: When the falling edge of clock 2 is triggered, it is determined whether the second storage page is accessed within the second time length recorded by clock 2. If it is not accessed, the heat value is reduced by 1; otherwise, it remains unchanged.

[0191] The page stratification unit 1002 can stratify multiple second storage pages of the second memory according to the hotness or coldness of processor accesses. The hotness value of the second storage page can be used to indicate the hotness or coldness of the processor accesses to the second storage page. The more times the processor accesses the second storage page, that is, the hotter the accesses to the second storage page, the larger the hotness value of the second storage page; the fewer times the processor accesses the second storage page, that is, the colder the accesses to the second storage page, the smaller the hotness value of the second storage page.

[0192] For example, the heat value ranges from 0 to 99. The initial heat value of all second storage pages is 0. After the heat value increases to 99, it no longer increases. After the heat value decreases to 0, it no longer decreases. Based on the heat value range, the multiple second storage pages of the second memory can be divided into 100 layers, and the heat values ​​corresponding to the 100 layers are 0 to 99. 100 linked lists can be set up accordingly. These 100 linked lists are used to store the data of the second storage pages of these 100 layers, and one linked list is used to store the data of the second storage pages of one layer. For any second storage page, if the heat value of the second storage page is increased by 1, the data of the second storage page is stored from the linked list corresponding to the current heat value (for example, the linked list corresponding to the heat value 95) to the linked list corresponding to the higher heat value (for example, the linked list corresponding to the heat value 96); if the heat value of the second storage page is decreased by 1, the data of the second storage page is stored from the linked list corresponding to the current heat value (for example, the linked list corresponding to the heat value 95) to the linked list corresponding to the lower heat value (for example, the linked list corresponding to the heat value 94).

[0193] The maximum value of the heat value can be configured. After the maximum value of the heat value of the data processing device is configured, the data processing device needs to be restarted. Generally, the larger the maximum value of the heat value, the higher the management cost of the data processing device.

[0194] S1302: Update the data of the second memory stored in the first memory according to the heat values ​​and heat thresholds of the plurality of second storage pages.

[0195] In some embodiments, the data processing device 10 or the programmable logic device 100 in the data processing device can be used to perform step S1302. Figure 4 As shown, the programmable logic device 100 is provided with an access prediction unit 1003, which can be used to update the data of the second memory stored in the first memory through the storage unit 1001 according to the heat values ​​and heat thresholds of multiple second storage pages.

[0196] After performing hot and cold stratification processing on multiple second storage pages in the second memory, the data in the second storage page with a high heat value can be stored in the first memory. However, the processor's access to the data in the second memory has a certain randomness, so that the first memory may also store some data of the second storage page with a lower heat value. In this case, the access prediction unit 1003 can start from the second storage page with the highest heat value to determine whether the data of the second storage page is cached in the first memory. If the data of the second storage page is not cached in the first memory, the access prediction unit 1003 can trigger the storage unit to store the data of the second storage page in the first memory in advance.

[0197] In some embodiments, the access prediction unit 1003 can update the data of the second memory stored in the first memory by performing the following steps: determining multiple hot storage pages among multiple second storage pages, and the heat value of the hot storage page is greater than the heat threshold; determining whether the data of multiple hot storage pages is stored in the first memory based on the mapping relationship; if there is at least one hot storage page among the multiple hot storage pages whose data is not stored in the first memory, then updating the data of the second memory stored in the first memory.

[0198] Exemplarily, the access prediction unit 1003 can execute the following process: start searching for the second storage page from the linked list with a heat value of 99, and determine whether the data in the second storage page is stored in the first memory based on the mapping relationship; if the data in the second storage page is stored in the first memory, continue to process the next second storage page after the second storage page; if the data in the second storage page is not stored in the first memory, the access prediction unit 1003 can trigger the storage unit corresponding to the second storage page to store the data of the second storage page in the first memory in advance; after the second storage page in the linked list with a heat value of 99 is processed, continue to process the linked list with a heat value of 98, and repeat this cycle until the heat value is less than the preset heat value or exceeds the pre-read range, and the access prediction unit 1003 stops operating.

[0199] A user can configure the preset popularity value or pre-read range for access prediction unit 1003 through a data processing device. For example, the user can trigger the data processing device to cause processor 103 within the data processing device to issue a configuration command to programmable logic device 100 via control interface 105 (e.g., CXL.io interface). This configuration command includes the preset popularity value and / or pre-read range. For example, the preset popularity value can be 90, and the pre-read range can be 90-99.

[0200] S1303: If a preset condition is met, determine a recycled storage page in at least one first storage page of the first memory, and write data stored in the recycled storage page back from the first memory to the second memory.

[0201] Optionally, the heat value of the recovered storage page is less than a heat threshold, and / or the storage state of the recovered storage page is a third state.

[0202] In some embodiments, the data processing device 10 or the programmable logic device 100 in the data processing device can be used to perform step S1303. Figure 4 As shown, the programmable logic device 100 is provided with a recycling unit 1004 , and the recycling unit 1004 can be used to execute step S1303 .

[0203] The preset condition may include at least one of the following: the number of first storage pages in the at least one first storage page whose storage state is the third state is greater than a number threshold, and the page usage rate of the first memory is greater than a usage rate threshold.

[0204] In the case where there are multiple reclaimed storage pages that meet the preset conditions, the reclaiming unit may preferentially reclaim the reclaimed storage page with the lowest heat value.

[0205] The user can configure the preset conditions of the access prediction unit 1003 through the data processing device. The configuration process is the same as the configuration process of the preset heat value and other parameters, which will not be repeated here.

[0206] In some embodiments, if the page usage of the first storage page is greater than a usage threshold, the processing priority of the recycling unit can be increased. That is, if the access prediction unit and the recycling unit simultaneously call the storage unit, the recycling unit can prioritize calling the storage unit to write the data stored in the recycled storage page from the first memory back to the second memory. If the page usage of the first storage page is less than or equal to the usage threshold, the processing priority of the recycling unit can be lowered.

[0207] There may be some data stored in the first storage page in the first memory that has not been accessed for a long time. In this case, if the data in this part of the first storage page is written back to the second memory in advance when the storage unit is in an idle state, space on the first storage page can be freed up, and the step of writing back the data of this part of the first storage page can be reduced in the process of subsequent storage units processing data access requests, thereby shortening the processing time of data access requests.

[0208] During a long data access process, the storage state of the plurality of first storage pages in the first memory may be the third state, such as Figure 11 As shown in Method 3, if the storage state of the first storage page is the third state, the storage unit needs to write the data in the first storage page back to the second memory before storing the data in the first storage page. If the data in the first storage page with the third storage state is written back to the second memory in advance when the storage unit is idle, the step of writing back the data of this part of the first storage page can be reduced when the storage unit processes the data access request subsequently, thereby shortening the processing time of the data access request.

[0209] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0210] Figure 14This is a schematic diagram of the structure of the data processing device provided in the embodiment of the present application. Figure 14 As shown, the embodiment of the present application further provides a data processing device. The data processing device 140 may include: a transceiver module 141 and a processing module 142, wherein:

[0211] The transceiver module 141 is configured to receive a data access request;

[0212] a processing module 142, configured to determine, based on the data access request and a mapping relationship between the data in the first memory and the data in the second memory, whether target data corresponding to the data access request is stored in the first memory, and a data processing speed of the first memory is greater than a data processing speed of the second memory;

[0213] The processing module 142 is further configured to store the target data from the second memory to the first memory if the target data is not stored in the first memory, update the mapping relationship, and query the first memory to obtain the target data.

[0214] In one implementation, the mapping relationship includes at least one first page identifier and a second page identifier corresponding to each first page identifier;

[0215] At least one first page identifier is used to indicate at least one first storage page of the first memory;

[0216] For any first page identifier, the second page identifier corresponding to the first page identifier is used to indicate a second storage page in the second memory, and the data mapping in the second storage page is stored in the first storage page indicated by the first page identifier.

[0217] In one implementation, the processing module 142 is specifically configured to:

[0218] Parsing the data access request to obtain a target second page identifier, where the target second page identifier is used to indicate a second storage page in the second memory for storing target data;

[0219] If at least one second page identifier corresponding to at least one first page identifier in the mapping relationship includes a target second page identifier, it is determined that the target data is stored in the first memory;

[0220] If the at least one second page identifier does not include the target second page identifier, it is determined that the target data is not stored in the first memory.

[0221] In one implementation, the processing module 142 is further configured to:

[0222] determining a target storage page in at least one first storage page of the first memory, where the target storage page is a least recently used first storage page in the at least one first storage page;

[0223] Determine the storage status of the target storage page;

[0224] storing the target data from the second memory to the target memory page according to the storage state;

[0225] The mapping relationship is updated according to the first page identifier of the target storage page and the second page identifier of a second storage page in the second memory for storing the target data.

[0226] In one implementation, the processing module 142 is further configured to:

[0227] Obtaining status information of a target storage page, where the status information includes a first flag bit and a second flag bit;

[0228] If the first flag bit takes the first value and the second flag bit takes the first value, determining that the storage state of the target storage page is the first state;

[0229] If the value of the first flag bit is the second value and the value of the second flag bit is the first value, determining that the storage state of the target storage page is the second state;

[0230] If the value of the first flag bit is the second value and the value of the second flag bit is the second value, it is determined that the storage state of the target storage page is the third state.

[0231] In one implementation, the processing module 142 is further configured to:

[0232] If the storage state is the first state, storing the target data in the target storage page based on the first state;

[0233] If the storage state is the second state, updating the storage state to the first state, and storing the target data in the target storage page based on the first state;

[0234] If the storage state is the third state, the data currently stored in the target storage page is written into the second memory, and after the writing is completed, the storage state is updated to the first state, and the target data is stored in the target storage page based on the first state.

[0235] In one implementation, the processing module 142 is further configured to:

[0236] Reading target data from the second memory into a target memory page;

[0237] After the reading is completed, the value of the first flag is updated to the second value.

[0238] In one implementation, the processing module 142 is further configured to:

[0239] determining heat values ​​of a plurality of second storage pages of the second memory;

[0240] The data of the second memory stored in the first memory is updated according to the heat values ​​and heat thresholds of the plurality of second storage pages.

[0241] In one implementation, for any second storage page of the second memory, the processing module 142 is further configured to:

[0242] If the second storage page is accessed within the first time period, updating the heat value of the second storage page from the first heat value to a second heat value, where the second heat value is the sum of the first heat value and the heat offset value;

[0243] If the second storage page has not been accessed within the second time period, updating the heat value of the second storage page from the first heat value to a third heat value, where the third heat value is the difference between the first heat value and the heat offset value;

[0244] The second duration is M times the first duration, where M is an integer greater than 1.

[0245] In one implementation, the processing module 142 is further configured to:

[0246] Determining a plurality of hot storage pages from the plurality of second storage pages, wherein the heat values ​​of the hot storage pages are greater than a heat threshold;

[0247] Determining whether data of a plurality of hot storage pages is stored in the first memory according to the mapping relationship;

[0248] If data of at least one hot storage page among the plurality of hot storage pages is not stored in the first memory, the data of the second memory stored in the first memory is updated.

[0249] In one implementation, the processing module 142 is further configured to:

[0250] When a preset condition is met, determining a recycled storage page in at least one first storage page of the first memory, and writing data stored in the recycled storage page back from the first memory to the second memory;

[0251] The preset condition includes at least one of the following: the number of first storage pages in at least one first storage page whose storage state is the third state is greater than a quantity threshold, and the page usage rate of the first memory is greater than a usage rate threshold.

[0252] For the description of the features in the embodiments corresponding to the data processing device, reference can be made to the relevant description of the embodiments corresponding to the data processing method, and no further details will be given here.

[0253] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0254] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0255] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0256] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned data processing method embodiments when run.

[0257] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0258] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above data processing method embodiments are implemented.

[0259] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data processing method embodiments are implemented.

[0260] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0261] The above is a detailed introduction to a data processing device, method, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data processing device, characterized in that include: A programmable logic device, a first memory and a second memory, wherein: The programmable logic device is connected to the first memory and the second memory respectively, and the data processing speed of the first memory is greater than the data processing speed of the second memory; The programmable logic device is configured to receive a data access request and parse the data access request to obtain a target second page identifier, where the target second page identifier is used to indicate a second storage page in the second memory for storing target data corresponding to the data access request; If at least one second page identifier corresponding to at least one first page identifier in the mapping relationship includes the target second page identifier, it is determined that the target data is stored in the first memory, the at least one first page identifier is used to indicate at least one first storage page of the first memory, and for any first page identifier, the second page identifier corresponding to the first page identifier is used to indicate a second storage page in the second memory, and the data in the second storage page is mapped and stored in the first storage page indicated by the first page identifier; If the target second page identifier is not included in the at least one second page identifier, it is determined that the target data is not stored in the first memory, the target data is stored from the second memory to the first memory, the mapping relationship is updated, and the target data is queried in the first memory.

2. The data processing device according to claim 1, characterized in that The programmable logic device includes a request processing unit and a storage unit, wherein: The request processing unit is connected to the first memory and the storage unit respectively, and the storage unit is also connected to the second memory; The request processing unit is used to receive the data access request and obtain the target data from the first memory through the storage unit; The storage unit is used to determine whether the target data is stored in the first memory based on the data access request and the mapping relationship. If the target data is not stored in the first memory, the target data is stored from the second memory to the first memory, and the mapping relationship is updated, and the request processing unit is used to query and obtain the target data from the first memory.

3. The data processing device according to claim 2, characterized in that The programmable logic device also includes a page layering unit and an access prediction unit, wherein: The page layering unit is connected to the request processing unit and the access prediction unit respectively, and the access prediction unit is also connected to the storage unit; The page layering unit is used to determine the heat values ​​of a plurality of second storage pages in the second memory; The access prediction unit is configured to update the data of the second memory stored in the first memory through the storage unit according to the heat values ​​and heat thresholds of the plurality of second storage pages.

4. The data processing device according to claim 3, characterized in that Storing the target data from the second memory to the first memory and updating the mapping relationship includes: determining a target storage page in at least one first storage page of the first memory, wherein the target storage page is a least recently used first storage page in the at least one first storage page; Determining a storage state of the target storage page; storing the target data from the second memory to the target storage page according to the storage state; The mapping relationship is updated according to the first page identifier of the target storage page and the second page identifier of a second storage page in the second memory for storing the target data.

5. The data processing device according to claim 4, characterized in that Determining the storage state of the target storage page includes: Acquire status information of the target storage page, where the status information includes a first flag bit and a second flag bit; If the first flag bit takes a first value and the second flag bit takes a first value, determining that the storage state of the target storage page is a first state; If the first flag bit takes the second value and the second flag bit takes the first value, determining that the storage state of the target storage page is the second state; If the first flag bit takes the second value and the second flag bit takes the second value, it is determined that the storage state of the target storage page is the third state.

6. The data processing device according to claim 5, characterized in that The programmable logic device also includes a recovery unit; The recycling unit is connected to the page layering unit and the storage unit respectively; The recycling unit is configured to, when a preset condition is met, determine a recycled storage page in at least one first storage page of the first memory, and write data stored in the recycled storage page back from the first memory to the second memory; The preset condition includes at least one of the following: the number of first storage pages in the at least one first storage page whose storage state is the third state is greater than a quantity threshold, and a page usage rate of the first memory is greater than a usage rate threshold.

7. The data processing device according to claim 3, characterized in that The programmable logic device further includes a first read-write unit and a second read-write unit, wherein: The first read-write unit is connected to the request processing unit and the first memory respectively, and the first read-write unit is used for the request processing unit to read and write data from the first memory; The second read-write unit is connected to the storage unit and the second memory respectively, and is used for the storage unit to read and write data from the second memory.

8. The data processing device according to any one of claims 1 to 7, characterized in that: The data processing device further includes a processor connected to the programmable logic device; The processor is configured to send a data access request to the programmable logic device and receive the target data sent by the programmable logic device; The processor is further configured to send a configuration command to the programmable logic device, where the configuration command is used to configure parameters of the programmable logic device.

9. The data processing device according to claim 8, characterized in that The data processing device also includes a data transmission interface and a control interface; The data transmission interface is connected to the processor and the programmable logic unit respectively, and the data transmission interface is used to transmit the data access request and the target data; The control interface is connected to the processor and the programmable logic unit respectively, and the control interface is used to transmit the configuration command.

10. A data processing method, characterized in that: include: receiving data access requests; parsing the data access request to obtain a target second page identifier, where the target second page identifier is used to indicate a second storage page in the second memory for storing target data corresponding to the data access request; If at least one second page identifier corresponding to at least one first page identifier in the mapping relationship includes the target second page identifier, it is determined that the target data is stored in the first memory, the at least one first page identifier is used to indicate at least one first storage page of the first memory, for any first page identifier, the second page identifier corresponding to the first page identifier is used to indicate a second storage page in the second memory, the data in the second storage page is mapped and stored in the first storage page indicated by the first page identifier, and a data processing speed of the first memory is greater than a data processing speed of the second memory; If the target second page identifier is not included in the at least one second page identifier, it is determined that the target data is not stored in the first memory, the target data is stored from the second memory to the first memory, the mapping relationship is updated, and the target data is queried in the first memory.

11. The method according to claim 10, characterized in that Storing the target data from the second memory to the first memory and updating the mapping relationship includes: determining a target storage page in at least one first storage page of the first memory, wherein the target storage page is a least recently used first storage page in the at least one first storage page; Determining a storage state of the target storage page; storing the target data from the second memory to the target storage page according to the storage state; The mapping relationship is updated according to the first page identifier of the target storage page and the second page identifier of a second storage page in the second memory for storing the target data.

12. The method according to claim 11, characterized in that Determining the storage state of the target storage page includes: Acquire status information of the target storage page, where the status information includes a first flag bit and a second flag bit; If the first flag bit takes a first value and the second flag bit takes a first value, determining that the storage state of the target storage page is a first state; If the first flag bit takes the second value and the second flag bit takes the first value, determining that the storage state of the target storage page is the second state; If the first flag bit takes the second value and the second flag bit takes the second value, it is determined that the storage state of the target storage page is the third state.

13. The method according to claim 12, characterized in that Storing the target data from the second memory to the target storage page according to the storage state includes: If the storage state is the first state, storing the target data in the target storage page based on the first state; If the storage state is the second state, updating the storage state to the first state, and storing the target data in the target storage page based on the first state; If the storage state is the third state, the data currently stored in the target storage page is written into the second memory, and after the writing is completed, the storage state is updated to the first state, and the target data is stored in the target storage page based on the first state.

14. The method according to claim 13, characterized in that Storing the target data in the target storage page based on the first state includes: Reading the target data from the second memory into the target storage page; After the reading is completed, the value of the first flag is updated to a second value.

15. The method according to claim 10, characterized in that The method further comprises: determining heat values ​​of a plurality of second storage pages of the second memory; The data of the second memory stored in the first memory is updated according to the heat values ​​and heat thresholds of the plurality of second storage pages.

16. The method according to claim 15, characterized in that for any second storage page of the second memory; Determining the heat value of the second storage page includes: If the second storage page is accessed within the first time period, updating the heat value of the second storage page from the first heat value to a second heat value, where the second heat value is the sum of the first heat value and the heat offset value; If the second storage page has not been accessed within a second time period, updating the heat value of the second storage page from the first heat value to a third heat value, where the third heat value is the difference between the first heat value and the heat offset value; The second duration is M times the first duration, where M is an integer greater than 1.

17. The method according to claim 15, characterized in that Updating the data of the second memory stored in the first memory according to the heat values ​​and heat thresholds of the plurality of second storage pages includes: determining a plurality of hot storage pages from the plurality of second storage pages, wherein the heat values ​​of the hot storage pages are greater than the heat threshold; determining, according to the mapping relationship, whether data of the plurality of hot storage pages is stored in the first memory; If data of at least one hot storage page among the plurality of hot storage pages is not stored in the first memory, the data of the second memory stored in the first memory is updated.

18. The method according to claim 12, characterized in that The method further comprises: If a preset condition is met, determining a recycled storage page in at least one first storage page of the first memory, and writing data stored in the recycled storage page back from the first memory to the second memory; The preset condition includes at least one of the following: the number of first storage pages in the at least one first storage page whose storage state is the third state is greater than a quantity threshold, and a page usage rate of the first memory is greater than a usage rate threshold.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the data processing method according to any one of claims 10 to 18 are implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data processing method according to any one of claims 10 to 18 are implemented.

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