Flash memory anti-interference method in power-on stage of processor, processor and storage medium

Abstract

The invention discloses a processor power-on stage flash memory anti-interference method, a processor and a storage medium, the processor power-on stage flash memory anti-interference method comprises the following steps: monitoring power supply voltage fluctuation in real time after power-on, and obtaining a real-time voltage value of a power supply; subtracting the real-time voltage value from a threshold voltage value to obtain a voltage difference value, and comparing the voltage difference value with a preset difference value; when the voltage difference value is greater than a preset difference value, dynamically adjusting the waiting time of the flash memory by adopting an exponential back-off algorithm; and when the voltage difference value is smaller than or equal to a preset difference value, controlling the flash memory to work. The problem that the flash memory works due to voltage fluctuation before the flash memory works in the power-on stage of the processor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded system storage security, and in particular to a flash memory anti-interference method during a processor power-on phase, a processor, and a storage medium. Background Art

[0002] Current processors rely on a fixed wait time after power-up before operating flash memory. This approach is not adaptable to fluctuating power supply environments and results in long startup times. For example, in high-interference scenarios such as automotive electronics or industrial control, power supply fluctuations can easily affect the working state of flash memory. Furthermore, using a fixed wait time can result in ineffective waiting times and lead to efficiency losses. Summary of the Invention

[0003] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a flash memory anti-interference method, processor and storage medium during the processor power-on phase, so as to solve the problem that voltage fluctuations occur before the flash memory works during the processor power-on phase, thereby affecting the flash memory operation.

[0004] The technical solutions of the present invention are as follows:

[0005] A method for anti-interference of flash memory during the power-on phase of a processor, comprising the following steps:

[0006] After power-on, monitor the power supply voltage fluctuation in real time and obtain the real-time voltage value of the power supply;

[0007] Subtracting the real-time voltage value from the threshold voltage value to obtain a voltage difference value, and comparing the voltage difference value with a preset difference value;

[0008] When the voltage difference is greater than a preset difference, an exponential backoff algorithm is used to dynamically adjust the flash memory waiting time;

[0009] When the voltage difference is less than or equal to the preset difference, the flash memory is controlled to operate.

[0010] Optionally, the step of dynamically adjusting the flash memory waiting time by using an exponential backoff algorithm specifically includes:

[0011] When power is turned on, the timing is started and a basic waiting time of the flash memory is set, and after the timing time reaches the initial waiting time, the voltage difference is compared with the preset difference;

[0012] If the voltage difference is greater than the preset difference, the waiting time is increased according to the preset ratio to obtain a new waiting time;

[0013] After the timing time reaches the new waiting time, the process returns to the step of comparing the voltage difference with the preset difference.

[0014] Optionally, the calculation formula of the exponential backoff algorithm is specifically:

[0015] T_wait=T_base×(1+K×(|dV / V_ref)); where T_wait is the new waiting time, T_base is the basic waiting time, K is the proportional coefficient, |dV| is the absolute value of the voltage change, and V_ref is the reference voltage.

[0016] Optionally, the method further includes the following steps:

[0017] After reading the flash memory data, parity check and CRC-32 check are performed to detect logical errors;

[0018] Temporarily store data in a static random access memory double buffer and compare the consistency of the two buffers. If the difference between the two buffers exceeds a threshold, a reread is triggered;

[0019] BCH encoding is used for data to perform multi-bit error correction.

[0020] Optionally, after power-on and before executing the step of controlling the flash memory operation, the method further includes:

[0021] Disable non-essential peripherals, perform a forced reset of peripheral registers, and enable the Direct Memory Access channel lock function.

[0022] Optionally, the step of controlling the operation of the flash memory specifically includes a flash memory reading phase and a flash memory writing phase, wherein data is read from the flash memory during the flash memory reading phase and data is written to the flash memory during the flash memory writing phase.

[0023] Optionally, the steps in the flash memory reading stage specifically include:

[0024] Load data from the flash memory into the double buffer, compare the two buffers and transmit them to the application layer after the two buffers are consistent;

[0025] After reading the flash memory data, the data is verified and BCH decoding is performed on the data that fails the verification, marking the error sector and automatically avoiding the error sector during subsequent writing.

[0026] Optionally, the steps in the flash memory writing phase specifically include:

[0027] Before writing data, the debug interface is forced to be closed and the flash memory write protection lock is enabled;

[0028] First erase the target sector and verify that the data is all 0xFF, then write the data and read it back for verification.

[0029] The present invention also proposes a processor, including a voltage detection module, a control chip and a memory, wherein the voltage detection module is used to detect the power supply voltage and output a voltage detection signal to the control chip, the memory stores a flash memory anti-interference program during the processor power-on phase, and the control chip is used to implement the above-mentioned processor power-on phase flash memory anti-interference method when executing the processor power-on phase flash memory anti-interference program.

[0030] The present invention also proposes a storage medium, which stores a flash memory anti-interference program during the processor power-on phase. When the processor power-on phase flash memory anti-interference program is executed by the processor, the processor power-on phase flash memory anti-interference method described above is implemented.

[0031] The technical solution of the present invention can monitor the power supply voltage fluctuation in real time after the processor is powered on, and obtain the real-time voltage value of the power supply; then the real-time voltage value is subtracted from the threshold voltage value to obtain a voltage difference, and compared with a preset difference; when the voltage difference is greater than the preset difference, an exponential backoff algorithm is used to dynamically adjust the flash memory waiting time; when the voltage difference is less than or equal to the preset difference, the flash memory is controlled to work; this solution controls the flash memory to work when the voltage difference is less than or equal to the preset difference, which can make the waiting time before the flash memory works in the processor power-on stage the shortest, and there is no need to wait for a fixed time before working, which can reduce efficiency loss, link the operation of the flash memory with power management, and also reduce the impact of power supply fluctuations on flash memory reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0033] Figure 1 This is a flow chart of the method steps of an embodiment of a flash memory anti-interference method during the processor power-on phase of the present invention.

[0034] Figure 2 This is a flowchart of the method steps of another embodiment of the flash memory anti-interference method during the processor power-on phase of the present invention.

[0035] Figure 3 This is a flowchart of the method steps of another embodiment of the flash memory anti-interference method during the processor power-on phase of the present invention.

[0036] Figure 4 This is a flow chart of the method steps of another embodiment of the flash memory anti-interference method during the processor power-on phase of the present invention.

[0037] Figure 5This is a flowchart of the method steps of another embodiment of the flash memory anti-interference method during the processor power-on phase of the present invention.

[0038] Figure 6 This is a flowchart of the method steps of another embodiment of the flash memory anti-interference method during the processor power-on phase of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0041] It should be further understood that the term "comprising" as used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more associated listed items.

[0042] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0043] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0044] Current processors rely on a fixed wait time after power-up before operating flash memory. This approach is inadequate for fluctuating power conditions and results in long startup times. For example, in high-interference scenarios like automotive electronics or industrial control, power fluctuations can easily affect the working state of flash memory. Furthermore, using a fixed wait time can result in long, ineffective wait times and a loss of efficiency. Furthermore, there are issues with a single checksum mechanism, which relies on parity or ECC and can only correct single-bit errors, failing to cope with multi-bit sudden interference.

[0045] In order to solve the above problems, the present invention proposes a flash memory anti-interference method during the processor power-on phase.

[0046] Reference Figure 1 In one embodiment, the flash memory anti-interference method during the processor power-on phase includes the following steps:

[0047] S100, after power-on, monitor the power supply voltage fluctuation in real time and obtain the real-time voltage value of the power supply;

[0048] S200, subtracting the real-time voltage value from the threshold voltage value to obtain a voltage difference, and comparing the voltage difference with a preset difference;

[0049] S300, when the voltage difference is greater than a preset difference, dynamically adjusting the flash memory waiting time using an exponential backoff algorithm;

[0050] S400 , when the voltage difference is less than or equal to a preset difference, controlling the flash memory to operate.

[0051] In this embodiment, after the processor is powered on, the voltage of the power supply in the processor can be monitored in real time. For example, a high-precision ADC module is integrated in the processor to detect and obtain the voltage value of the power supply. The real-time voltage value is then subtracted from the threshold voltage value, and the resulting voltage difference is compared with a preset difference. When the voltage difference is greater than the preset difference, it indicates that the voltage fluctuation is large, which may affect the normal operation of the flash memory. Therefore, an exponential backoff algorithm is used to dynamically adjust the flash memory waiting time, that is, to extend the waiting time before the flash memory operates, thereby preventing the large voltage fluctuation from affecting the working state of the flash memory. When the voltage difference is less than or equal to the preset difference, it indicates that the voltage fluctuation is small and will not affect the normal operation of the flash memory, and the flash memory operation can be controlled. The threshold voltage value and the preset difference can be set according to the actual processor hardware configuration and user needs. For example, if the threshold voltage value is set to 3.5V and the preset difference is set to 0.1V, then when the real-time voltage value is within the range of 3.4V to 3.6V, it indicates that the voltage fluctuation is small, and the flash memory can be controlled to perform reading and writing operations. When the real-time voltage value is outside the range of 3.4V to 3.6V, it indicates that the voltage fluctuation is large, which may affect the working state of the flash memory. Therefore, an exponential backoff algorithm can be used to dynamically adjust the flash memory waiting time until the real-time voltage value is within the range of 3.4V to 3.6V. This can avoid interference of large voltage fluctuations on the operation of the flash memory and reduce efficiency loss caused by long waiting time before the flash memory starts working.

[0052] The technical solution of the present invention can monitor the power supply voltage fluctuation in real time after the processor is powered on, and obtain the real-time voltage value of the power supply; then the real-time voltage value is subtracted from the threshold voltage value to obtain a voltage difference, and compared with a preset difference; when the voltage difference is greater than the preset difference, an exponential backoff algorithm is used to dynamically adjust the flash memory waiting time; when the voltage difference is less than or equal to the preset difference, the flash memory is controlled to work; this solution controls the flash memory to work when the voltage difference is less than or equal to the preset difference, which can make the waiting time before the flash memory works in the processor power-on stage the shortest, and there is no need to wait for a fixed time before working, which can reduce efficiency loss, link the operation of the flash memory with power management, and also reduce the impact of power supply fluctuations on flash memory reading and writing.

[0053] Reference Figure 2 In one embodiment, the step of dynamically adjusting the flash memory waiting time using an exponential backoff algorithm specifically includes:

[0054] S310, starting timing and setting a basic waiting time for the flash memory when power is turned on, and comparing the voltage difference with a preset difference after the timing time reaches the initial waiting time;

[0055] S320: If the voltage difference is greater than the preset difference, increase the waiting time according to a preset ratio to obtain a new waiting time;

[0056] S330: After the timing time reaches the new waiting time, return to the step of comparing the voltage difference with the preset difference.

[0057] In this embodiment, a timer begins when the processor is powered on and sets a basic wait time for the flash memory. After the timer reaches the initial wait time, the voltage difference is compared with a preset difference. If the voltage difference is greater than the preset difference, it indicates that the power supply voltage is fluctuating significantly, which could affect the flash memory's operating state. In this case, the wait time is increased by a preset ratio to obtain a new wait time, and the wait time is continued. After the timer reaches the new wait time, the process returns to the step of comparing the voltage difference with the preset difference, determining the difference between the two. This process continues until the voltage difference is less than or equal to the preset difference, indicating that the voltage fluctuation is small and will not affect the normal operation of the flash memory. The flash memory can then be controlled to operate. For example, if the basic wait time is 10ms, the voltage difference is compared with the preset difference 10ms after powering on. If the voltage difference is greater than the preset difference, the wait time can be increased by 50% each time, i.e., to 15ms, 20ms, and so on. This process continues until the voltage difference is less than or equal to the preset difference, at which point the flash memory can be controlled to operate. This minimizes the wait time before the flash memory operates during the processor power-on phase, eliminating the need to wait for a fixed time before operating and reducing efficiency losses.

[0058] Furthermore, in one embodiment, the calculation formula of the exponential backoff algorithm is specifically:

[0059] T_wait = T_base × (1 + K × (|dV / V_ref)); where T_wait is the new wait time, T_base is the base wait time, K is the proportional coefficient, i.e., the preset ratio in the above embodiment, |dV| is the voltage change, i.e., the absolute value of the voltage difference, and V_ref is the reference voltage. In this embodiment, the proportional coefficient and reference voltage can be set according to actual conditions and usage requirements.

[0060] Reference Figure 3 In one embodiment, the flash memory anti-interference method during the processor power-on phase further includes the following steps:

[0061] S500: After reading the flash memory data, perform parity check and CRC-32 check to detect logic errors;

[0062] S600, temporarily storing the data in a static random access memory double buffer, comparing the consistency of the two buffers, and triggering a reread if the difference between the two buffers exceeds a threshold;

[0063] S700: Use BCH encoding on the data to perform multi-bit error correction.

[0064] In this embodiment, after reading data from the flash memory, logical errors can be detected by performing a data check. Specifically, parity checks and CRC-32 checks can be used. Parity checks determine whether the data is odd or even by counting the number of 1s in the data, thereby generating a check bit. CRC (Cyclic Redundancy Check) is a data transmission error detection function, and CRC-32 is a commonly used standard that generates a 32-bit check value. Comparing the consistency of the two buffers can be performed by performing a byte-by-byte comparison of the same address units in the two static random access memory buffers to count the number of bytes that differ. This method is suitable for scenarios with high data consistency requirements, but it consumes a lot of computing resources. Alternatively, block check comparison can be performed, using a checksum (such as CRC32), a hash algorithm (such as MD5), or an XOR operation to generate a unique check value for each buffer. The two check values are then compared to ensure consistency. This method is more efficient but may ignore local differences. The specific comparison method can be selected based on actual conditions and user needs. Bose–Chaudhuri–Hocquenghem coding (BCH coding) is a linear block code used for error correction. BCH codes can be designed to correct multiple errors. The specific error correction capability depends on the code parameters. By choosing the appropriate polynomial and code length, different error correction capabilities can be achieved.

[0065] Reference Figure 4 In one embodiment, after powering on and before executing the step of controlling the flash memory operation, the method further includes:

[0066] S10. Turn off non-essential peripherals, perform a forced reset of peripheral registers, and enable the direct memory access channel locking function.

[0067] In this embodiment, turning off non-essential peripherals (such as ADC, PWM) before controlling the flash memory operation can reduce the electromagnetic interference of peripheral noise on the flash memory interface and reduce the overall power consumption of the system. And during the flash memory operation, ensuring that the peripherals are in the off state can reduce the risk of data corruption. The write and erase operations of the flash memory are very sensitive to voltage and time. Any interference from the peripherals may cause data write failure or data corruption. Performing a forced reset of the peripheral registers can ensure that all peripherals are in a known initial state. It helps to avoid potential problems caused by inconsistent peripheral states. For example, some peripherals may require a specific initialization sequence after power-on or reset. If a reset is not performed, the flash memory operation may fail. Enabling the direct memory access channel locking function can prevent bus conflicts from interfering with the bus timing of the flash memory.

[0068] In one embodiment, the step of controlling the operation of the flash memory specifically includes a flash memory reading phase and a flash memory writing phase. The flash memory is read during the flash memory reading phase, and data is written to the flash memory during the flash memory writing phase.

[0069] In this embodiment, the flash memory operation process can be specifically divided into a read phase and a write phase. The flash memory read phase primarily extracts stored data from the flash memory and can also be used to verify the integrity and correctness of the data, such as through a checksum or CRC. The flash memory write phase primarily writes new or updated data to the flash memory and can be used to update existing data, such as modifying configuration parameters or storing new user data.

[0070] Reference Figure 5 In one embodiment, the steps of the flash memory reading phase specifically include:

[0071] S411, loading data from the flash memory into the double buffer, comparing the two buffers to ensure consistency and then transmitting to the application layer;

[0072] S412: After reading the flash memory data, verify the data and perform BCH decoding on the data that fails the verification, mark the error sector, and automatically avoid the error sector during subsequent writing.

[0073] In this embodiment, during the flash memory read phase, data can be loaded from the flash memory into a dual buffer. After the two buffers are compared for consistency, they are transferred to the application layer for subsequent processing. The details of comparing the two buffers for consistency can be found in the above-mentioned embodiments. This consistency check can help detect errors that may occur during the read process, such as data corruption or read errors, thereby improving data reliability. The use of a dual buffer also allows data processing or transmission to occur simultaneously with reading, reducing latency. Performing BCH decoding on data that fails verification marks the error sector, automatically avoiding the error sector during subsequent writes. This ensures that even if bit flips or other types of errors occur in the flash memory, data can still be recovered, thereby improving data reliability. Marking error sectors prevents the system from attempting to write to these sectors again during subsequent operations, thereby avoiding potential data corruption and system crashes. Furthermore, by avoiding error sectors, the system can more effectively manage flash memory usage, avoid frequent writes to the same sector, and thus extend the overall lifespan of the flash memory. Verification during data reads ensures data consistency and prevents application-layer issues caused by erroneous data. By automatically repairing and marking error sectors, the system maintains data integrity. In this way, through effective error detection and repair mechanisms, users will encounter fewer failures when using the device, thereby improving user experience and satisfaction.

[0074] Reference Figure 6In one embodiment, the steps of the flash memory writing phase specifically include:

[0075] S421, before writing data, the debug interface is forcibly closed and the flash memory write protection lock is enabled;

[0076] S422, first erase the target sector and after verifying that the data is all 0xFF, write the data and read back for verification.

[0077] In this embodiment, disabling the debug interface prevents external attackers or unauthorized users from accessing the system through debugging tools, thus preventing illegal reading or modification of flash memory data. Enabling the flash memory write protection lock prevents accidental or malicious data modification during the write process. Furthermore, if the debug interface is enabled during data writing, debug information interference or erroneous operation may occur, thereby affecting the write process. Disabling the debug interface reduces this risk and ensures the stability and reliability of the write operation. Erasing the target sector first ensures data consistency. By erasing the target sector first and verifying that the data is all 0xFF, the foundation for the write operation is ensured. Directly writing data without first erasing the target sector may result in data corruption or inconsistency, as flash memory write operations perform bit-by-bit flipping rather than direct overwriting. Ensuring that the target sector has been erased can avoid this. Verifying the post-erasure data state ensures that the flash memory cells are in a writable state, thereby increasing the success rate of write operations and reducing the likelihood of write failures. Performing a readback check after writing ensures that the written data is consistent with the original data. This is an important step in verifying the success of the write operation and can promptly detect any errors that may occur during the write process.

[0078] The present invention also provides a processor comprising a voltage detection module, a control chip, and a memory. The voltage detection module is configured to detect a power supply voltage and output a voltage detection signal to the control chip. The memory stores a flash memory anti-interference program for the processor during power-up. The control chip is configured to implement the aforementioned flash memory anti-interference method during power-up when executing the flash memory anti-interference program. In this embodiment, the voltage detection module may be composed of a digital-to-analog converter and an analog-to-digital converter to perform conversion between analog and digital signals.

[0079] The present invention also provides a storage medium storing a flash memory anti-interference program for processor power-up. When executed by a processor, the flash memory anti-interference program implements the aforementioned flash memory anti-interference method for processor power-up. In this embodiment, the storage medium refers to a physical lighting device or material used to store data and information. The storage medium may be a magnetic storage medium, a solid-state storage medium, an optical storage medium, or a memory storage medium.

[0080] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A flash memory anti-interference method during the processor power-on phase, characterized in that: The following steps are involved: After power-on, monitor the power supply voltage fluctuation in real time and obtain the real-time voltage value of the power supply; Subtracting the real-time voltage value from the threshold voltage value to obtain a voltage difference value, and comparing the voltage difference value with a preset difference value; When the voltage difference is greater than a preset difference, an exponential backoff algorithm is used to dynamically adjust the flash memory waiting time; When the voltage difference is less than or equal to the preset difference, the flash memory is controlled to operate.

2. The method for anti-interference of flash memory during the processor power-on phase according to claim 1, wherein: The step of dynamically adjusting the flash memory waiting time using the exponential backoff algorithm specifically includes: When power is turned on, the timing is started and a basic waiting time of the flash memory is set, and after the timing time reaches the initial waiting time, the voltage difference is compared with the preset difference; If the voltage difference is greater than the preset difference, the waiting time is increased according to the preset ratio to obtain a new waiting time; After the timing time reaches the new waiting time, the process returns to the step of comparing the voltage difference with the preset difference.

3. The method for anti-interference of flash memory during the processor power-on phase according to claim 2, wherein: The calculation formula of the exponential backoff algorithm is specifically: T_wait=T_base×(1+K×(|dV / V_ref)); where T_wait is the new waiting time, T_base is the basic waiting time, K is the proportional coefficient, |dV| is the absolute value of the voltage change, and V_ref is the reference voltage.

4. The method for anti-interference of flash memory during the processor power-on phase according to claim 1, wherein: The following steps are also included: After reading the flash memory data, parity check and CRC-32 check are performed to detect logical errors; Temporarily store data in a static random access memory double buffer and compare the consistency of the two buffers. If the difference between the two buffers exceeds a threshold, a reread is triggered; BCH encoding is used for data to perform multi-bit error correction.

5. The method for anti-interference of flash memory during processor power-on phase according to claim 1, wherein: After power-on and before executing the step of controlling the flash memory operation, the method further includes: Disable non-essential peripherals, perform a forced reset of peripheral registers, and enable the Direct Memory Access channel lock function.

6. The method for anti-interference of flash memory during processor power-on phase according to claim 1, wherein: The steps of controlling the operation of the flash memory specifically include a flash memory reading phase and a flash memory writing phase. The flash memory is read during the flash memory reading phase, and data is written to the flash memory during the flash memory writing phase.

7. The flash memory anti-interference method during the processor power-on phase according to claim 6, wherein: The steps of the flash memory reading stage specifically include: Load data from the flash memory into the double buffer, compare the two buffers and transmit them to the application layer after the two buffers are consistent; After reading the flash memory data, the data is verified and BCH decoding is performed on the data that fails the verification, marking the error sector and automatically avoiding the error sector during subsequent writing.

8. The method for anti-interference of flash memory during the processor power-on phase according to claim 6, wherein: The steps of the flash memory writing stage specifically include: Before writing data, the debug interface is forced to be closed and the flash memory write protection lock is enabled; First erase the target sector and verify that all data is 0xFF, then write data and read back for verification.

9. A processor, characterized in that: It includes a voltage detection module, a control chip and a memory, the voltage detection module is used to detect the power supply voltage and output a voltage detection signal to the control chip, the memory stores a flash memory anti-interference program for the processor power-on stage, and the control chip is used to implement the processor power-on stage flash memory anti-interference method as described in any one of claims 1 to 8 when executing the processor power-on stage flash memory anti-interference program.

10. A storage medium, characterized in that: The storage medium stores a flash memory anti-interference program during the processor power-on phase, which, when executed by the processor, implements the flash memory anti-interference method during the processor power-on phase according to any one of claims 1 to 8.

Images