Memory and test system

Abstract

The embodiment of the invention provides a memory and a test system, the memory comprises a first group of memory banks, a second group of memory banks and a plurality of read-write control circuits, and one memory bank in the first group of memory banks and one memory bank in the second group of memory banks share the same read-write control circuit; a memory configured to receive a command address signal and a data signal from outside; in the target mode, if the command address signal indicates the write operation, sequentially executing the first internal write operation and the second internal write operation; the target mode indicates all the memory banks to jointly execute write operation, the first internal write operation refers to writing target data into the first group of memory banks through each read-write control circuit, the second internal write operation refers to writing target data into the second group of memory banks through each read-write control circuit, and the target data comprises data signals; in the testing process, it is ensured that actual write-in data is consistent with expected write-in data, and the testing efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a memory and a test system. Background Art

[0002] Dynamic Random Access Memory (DRAM) consists of multiple banks, each of which is organized into multiple column pairs (CPs). Each bank includes data blocks for storage and redundant blocks (CCR CPs) for repair. Redundant blocks with the same number within each bank share the same read / write circuitry. After fuse repair, if the memory is tested in compressed write or read mode with error correction (ECC) enabled, the actual written data may not match the expected data because redundant blocks in different banks share the same read / write circuitry. This can cause the test results to fail to reflect the true repair situation. Summary of the Invention

[0003] The present disclosure provides a memory and a test system, which can ensure that actual written data is consistent with expected written data when the error correction function is turned on and the memory is tested in a compressed read-write mode, thereby improving test efficiency.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, comprising a first group of memory banks, a second group of memory banks, and a plurality of read / write control circuits, wherein a memory bank in the first group of memory banks and a memory bank in the second group of memory banks share the same read / write control circuit;

[0006] The memory is configured to receive a command address signal and a data signal from the outside; in a target mode, if the command address signal indicates a write operation, then sequentially performing a first internal write operation and a second internal write operation;

[0007] In which, the target mode indicates that all storage bodies perform a write operation together, the first internal write operation refers to writing target data to the first group of storage bodies through each of the read-write control circuits, and the second internal write operation refers to writing the target data to the second group of storage bodies through each of the read-write control circuits, and the target data includes the data signal.

[0008] In some embodiments, the memory further comprises:

[0009] a command decoder configured to decode the command address signal and generate an initial write instruction when the decoding result indicates a write operation;

[0010] a shift circuit connected to the command decoder and configured to, in target mode, delay the initial write instruction by N clock cycles to generate a shift write instruction; the clock cycle is a period of a clock signal in the memory, and N is a positive integer;

[0011] Each of the read-write control circuits is connected to the shift circuit, one of the first group of storage bodies, and one of the second group of storage bodies, and is configured to perform the first internal write operation in response to the initial write instruction; and to perform the second internal write operation in response to the shift write instruction.

[0012] In some embodiments, the memory further comprises an address module;

[0013] The address module is connected to the shift circuit and configured to generate an address selection signal; and, in response to the initial write instruction, flip the level state of the address selection signal; in response to the shift write instruction, flip the level state of the address selection signal;

[0014] Each of the read-write control circuits is also connected to the address module and configured to receive the address selection signal, and write the target data to one of the connected storage bodies in response to the initial write instruction and the address selection signal in the first level state; and write the target data to another of the connected storage bodies in response to the shift write instruction and the address selection signal in the second level state.

[0015] In some embodiments, the target data further includes a check code generated by calculating the data signal;

[0016] The memory further comprises:

[0017] An ECC error correction module configured to perform a logical operation on the data signal to generate the check code;

[0018] The data latch module is connected to the ECC error correction module and is configured to latch the data signal and the check code in response to the initial write instruction to generate the target data.

[0019] In some embodiments, the shift circuit comprises:

[0020] a shift unit connected to the command decoder and configured to receive the initial write instruction; in a target mode, delay the initial write instruction by N clock cycles to generate the shift write instruction;

[0021] an integration unit connected to the shift unit, configured to integrate the initial write instruction and the shift write instruction into the same signal channel and output a write operation signal;

[0022] Wherein, in the target mode, two adjacent pulses of the write operation signal correspond to the initial write instruction and the shift write instruction respectively.

[0023] In some embodiments, the data latch module includes:

[0024] a first flip unit connected to the shift circuit and configured to output an initial latch signal; in a target mode, in response to the initial write instruction, adjust the initial latch signal to a non-enabled state; and in response to the shift write instruction, adjust the initial latch signal to an enabled state;

[0025] a shielding unit connected to the first flip unit, configured to output the write operation signal as a latch flag signal in response to the initial latch signal in a disabled state; and shield the write operation signal to keep the level of the latch flag signal unchanged in response to the initial latch signal in an enabled state; wherein the pulse of the latch flag signal corresponds to the initial write instruction;

[0026] The latch unit is connected to the shielding unit and is configured to latch the data signal and the check code using the pulse of the latch flag signal to generate the target data.

[0027] In some embodiments, the address module includes:

[0028] a second flip unit configured to generate a write flag signal; in a target mode, flip the level state of the write flag signal in response to the initial write instruction; and flip the level state of the write flag signal in response to the shift write instruction;

[0029] The sampling unit is connected to the second flip unit and is configured to sample the write flag signal to form the address selection signal in response to the delayed initial write instruction; and to sample the write flag signal to form the address selection signal in response to the delayed shift write instruction.

[0030] In some embodiments, the command decoder outputs a decoding result signal, and a pulse in the decoding result signal indicates the initial write instruction;

[0031] The shift unit is configured to receive a mode flag signal and the decoding result signal; if the mode flag signal is in an enabled state, delay the decoding result signal to generate a first intermediate signal; if the mode flag signal is in a disabled state, maintain an output level of the first intermediate signal unchanged;

[0032] The integration unit includes a first OR gate, which performs an OR operation on the command decoding signal and the first intermediate signal to generate the write operation signal;

[0033] Wherein, in the target mode, the mode flag signal is in an enabled state; in other modes except the target mode, the mode flag signal is in a disabled state.

[0034] In some embodiments, the shift unit includes a first flip-flop, a second flip-flop, and a first latch; an input terminal of the first flip-flop receives the decoding result signal, the first flip-flop, the second flip-flop, and the first latch are sequentially cascaded, clock terminals of the first flip-flop, the second flip-flop, and the first latch are connected to respective input terminals, and the first latch outputs the first intermediate signal;

[0035] In response to the mode flag signal in the disabled state, the output terminals of the first flip-flop, the second flip-flop, and the first latch maintain a preset level.

[0036] In some embodiments, the first flip-flop includes a second NOT gate and a third flip-flop, wherein the output terminal of the third flip-flop is connected to the input terminal of the third flip-flop via the second NOT gate; the clock terminal of the third flip-flop receives the write operation signal, and the second NOT gate outputs the initial latch signal; in response to the mode flag signal in the disabled state, the output of the third flip-flop maintains a preset level;

[0037] The shielding unit performs an OR operation on the initial latch signal and the inverted signal of the write operation signal to generate the latch flag signal;

[0038] The latch unit includes a second latch, and the second latch performs a latching process on the target data using the latch flag signal.

[0039] In some embodiments, the second flip-flop includes a fourth flip-flop and a third NOT gate; a clock terminal of the fourth flip-flop receives the write operation signal, an output terminal of the fourth flip-flop is connected to an input terminal of the fourth flip-flop via the third NOT gate, and the third NOT gate outputs the write flag signal; in response to a mode flag signal in a disabled state, the output terminal of the fourth flip-flop maintains a preset level;

[0040] The sampling unit includes a fifth trigger; the fifth trigger samples the write flag signal using the delayed write operation signal and outputs the address selection signal.

[0041] In some embodiments, the read / write control circuit includes a plurality of multiplexing write units, each of the multiplexing write units being connected to the same bit line selection signal line in the same numbered memory blocks of the first memory bank and the second memory bank, respectively. The first memory bank is a memory bank in the first group of memory banks, and the second memory bank is a memory bank in the second group of memory banks.

[0042] The multiplexing write unit is configured to receive a first signal and a second signal, perform an OR operation on the first signal and the second signal to generate data to be written; in response to the initial write instruction, transmit the data to be written to the same root bit line selection signal line of the first memory bank to be written into a selected memory column in the first memory bank; in response to the shift write instruction, transmit the data to be written to the same root bit line selection signal line of the second memory bank to be written into a selected memory column in the second memory bank;

[0043] In which, in response to the initial write instruction, the first signal carries the data in the target data corresponding to the storage column address selected in the first storage body, and the second signal does not carry valid data; in response to the shift write instruction, the second signal carries the data in the target data corresponding to the storage column address selected in the second storage body, and the first signal does not carry valid data.

[0044] In some embodiments, the memory further satisfies one or more of the following conditions:

[0045] (1) In the target mode, the column delay of the memory is greater than or equal to 2N clock cycles;

[0046] (2) N = 2;

[0047] (3) The memory is in a stage after fuse repair;

[0048] (4) The error correction function is turned on in the target mode;

[0049] (5) The first group of memory banks includes odd-numbered memory banks; the second group of memory banks includes even-numbered memory banks;

[0050] (6) The memory is a dynamic random access memory.

[0051] In a second aspect, an embodiment of the present disclosure provides a test system, comprising a test machine and a memory as described in the first aspect, wherein the test machine is used to output a command address signal and a data signal to the memory; the memory comprises M groups of memory bodies; a memory body in each group of memory bodies shares the same read-write control circuit; the memory is configured to receive a command address signal and a data signal from the outside; in a target mode, if the command address signal indicates a write operation, M internal write operations are performed in sequence; wherein the target mode instructs all memory bodies to perform a write operation together, and the mth internal write operation refers to writing target data to the mth group of memory bodies through each of the read-write control circuits, and the target data includes the data signal; here, M is a positive integer greater than or equal to 2, m is a positive integer, and m≤M.

[0052] The disclosed embodiment provides a memory and a test system. For a write operation to all storage banks, the memory internally performs a first internal write operation and a second internal write operation, respectively. When performing the first internal write operation, the data corresponding to the storage bank is written to a connected storage bank through the read-write control circuit 11. When performing the second internal write operation, the data corresponding to the storage bank is written to another connected storage bank through the read-write control circuit 11. As a result, each storage bank is written with its corresponding data, which is consistent with the expected written data. The test result can indicate whether the fuse repair is successful or not, thereby improving test efficiency and saving test time. Therefore, when testing the memory in the compressed read-write mode, regardless of whether the error correction function (ECC) is turned on, it can be ensured that the actual written data is consistent with the expected written data, thereby improving test efficiency and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figures 1 to 4 A schematic diagram of a block structure of a memory provided in an embodiment of the present disclosure;

[0054] Figures 5 to 14 A schematic diagram of a circuit structure of a memory provided in an embodiment of the present disclosure;

[0055] Figure 15 A signal timing diagram provided in an embodiment of the present disclosure;

[0056] Figure 16 A schematic diagram of the structure of a test system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions of the drawings related to the related applications are shown. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may interchangeably represent a specific order or sequential sequence, where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0058] Dynamic Random Access Memory (DRAM);

[0059] Synchronous Dynamic Random Access Memory (SDRAM);

[0060] Double Data Rate SDRAM (DDR);

[0061] Low Power DDR (LPDDR).

[0062] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0063] It should be understood that the memory includes multiple memory banks, and the number and arrangement of the memory banks can be flexibly selected. For example, see Figure 1 , which shows a schematic structural diagram of the memory 10. Figure 1 In the example shown, the memory includes 16 memory banks, Bank 0 to Bank 15, arranged in 2 rows and 8 columns. In other embodiments, the memory may also include memory bank groups. The number of memory banks may also be 32 or other numbers.

[0064] During chip testing, memory 10 enters compression mode. This involves performing simultaneous read or write operations on multiple memory banks through compressed read or write operations. Error information from all memory blocks (CP) within a particular bank or across all banks is combined and output, enabling rapid and efficient chip functionality testing. Furthermore, in compression mode, the Error Correcting Code (ECC) function is typically disabled, ensuring that the data sequences written to different memory blocks are identical.

[0065] As mentioned above, each memory bank includes multiple data blocks and redundant blocks (CCPs). If a memory block (such as a data block) is damaged, a fuse is blown to replace the damaged block with a redundant block, implementing redundancy repair. To save space, the redundant blocks of multiple memory banks share the same read / write control circuit. For example, during a write operation, the read / write control circuit writes the corresponding data to the redundant blocks of the connected memory banks synchronously after performing an OR operation.

[0066] In the compression mode, taking the compression write mode as an example, the test efficiency is improved by performing the All Bank write operation. For the redundant blocks of two banks sharing the read and write control circuit, please refer to Figure 1 In this architecture, taking the read / write control circuit shared by Bank0 and Bank1 as an example, the first signal (which may be a data sequence) to be written to Redundant Block 0 of Bank1 and the second signal (which may be a data sequence) to be written to Redundant Block 1 of Bank1 are logically ORed to generate the data to be written (which may also be a data sequence). The data to be written is then written to Redundant Block 0 of Bank1 and Bank0, respectively. In compression mode, the data sequences written to different storage blocks (Normal CP) are identical, that is, the values of the first and second signals are the same, so write errors will not occur.

[0067] However, after the fuse repair (post-fuse) phase, the memory activates the ECC function and performs read and write tests in compressed mode to verify the success of the fuse repair. With ECC enabled, a portion of the memory block (called the Normal block, or CP) is used to store data signals, while another portion (called the ECCCP) is used to store the checksum calculated from the data signal. This means that the data sequences written to different memory blocks may not be identical. For example, assuming that the redundant block 0 of Bank0 is used to repair the normal block Normal CP, and the redundant block 0 of Bank1 is used to repair the check block ECC CP, when performing a write operation oriented to the entire storage body, the first signal expected to be written to the redundant block 0 of Bank0 is 0101, and the second signal expected to be written to the redundant block 0 of Bank1 is 1010. After the OR logic, the data to be written is 1111. Then, the redundant blocks 0 of Bank0 and Bank1 are both written with the signal 1111, which does not match the expected written value. At this time, the output test result will indicate that the repair of the redundant block 0 of Bank0 and Bank1 has failed, but this is not the case in reality. Therefore, the test result cannot reflect the actual repair situation, which increases the complexity of the test and error correction (Debug) and increases the test time.

[0068] The embodiments of the present disclosure are intended to solve this problem, and the following is a detailed description.

[0069] like Figure 1 As shown, the memory 10 includes a first group of memory banks Bank0 / 2 / 4 / 6 / 8 / 10 / 12 / 14 and a second group of memory banks Bank1 / 3 / 5 / 7 / 9 / 11 / 13 / 15. A memory bank in the first group of memory banks and a memory bank in the second group of memory banks share the same read-write control circuit 11, Bank0 and Bank1 share the same read-write control circuit 11, and Bank2 and Bank3 share the same read-write control circuit 11, thereby reducing the circuit area occupied.

[0070] The memory 10 is configured to receive a command address signal and a data signal DQ from the outside. In the target mode, if the command address signal indicates a write operation, a first internal write operation and a second internal write operation are performed in sequence. The target mode indicates that all storage bodies perform a write operation together (i.e., a write operation for all storage bodies). The first internal write operation refers to writing target data to the first group of storage bodies through each read-write control circuit 11. The second internal write operation refers to writing target data to the second group of storage bodies through each read-write control circuit 11. The target data includes the data signal DQ received from the outside.

[0071] It should be noted that the memory 10 in the embodiment of the present disclosure includes at least DRAM, such as DDR, LPDDR, HBM, etc.

[0072] Here, the command address signal includes two parts: a command signal Command and an address signal Address. The command signal Command is used to indicate what operation the memory needs to perform, and the address signal is used to indicate the address of the storage unit of this operation.

[0073] In one example, whether the memory 10 is in the target mode can be determined based on a command address signal (received this time or previously). In another example, the memory 10 also receives a test control signal to instruct the memory 10 to enter or exit the target mode. In another example, the memory 10 can also determine whether to enter or exit the target mode based on the value of a mode register.

[0074] In this way, for a write operation command directed to the entire storage body, the memory 10 internally executes a first internal write operation and a second internal write operation respectively. When executing the first internal write operation, the data corresponding to the connected storage body is written to the read-write control circuit 11. When executing the second internal write operation, the data corresponding to the connected storage body is written to the other connected storage body through the read-write control circuit 11. In this way, each storage body writes its corresponding data through different write operations, which is consistent with the expected written data. The test results can indicate whether the fuse repair is successful or not, thereby improving test efficiency and saving test time.

[0075] Please note that, see Figure 2 Each storage body includes multiple storage blocks CP, where CP0, CP1... are data blocks for implementing storage functions, CCR CP0 is a redundant block for implementing repair functions, and ECC CP0 is an error correction block for implementing error correction functions and storing check codes. Each storage block CP includes multiple storage columns, and each storage column is connected to a corresponding bit line selection line CSL. Here, one storage column is connected to one bit line selection line CSL, or multiple storage columns share the same bit line selection line CSL. For example, 8 storage columns are connected to the same bit line selection line CSL, so that 8 storage columns can be selected for reading and writing at one time. In some embodiments, the storage block CP may also include more than one redundant block, for example, it may include CCR CP0, CCR CP1...; the storage block CP may also include more than one check block, for example, it may include ECC CP0 and ECC CP1.

[0076] like Figure 2 As shown, the read / write control circuit 11 includes a plurality of multiplexed write units, each of which is connected to the same root bit line selection signal line CSL of the same numbered memory block in the first memory bank (a memory bank in the first group of memory banks) and the second memory bank (a memory bank in the second group of memory banks). For example, see Figure 3Multiplex write unit 0 is connected to CSL0 in CCR CP0 in Bank0 and CSL0 in CCR CP0 in Bank1.

[0077] like Figure 3 As shown, the multiplexing write unit is configured to receive a first signal and a second signal, perform an OR operation on the first signal and the second signal, and generate data to be written; when performing a first internal write operation, the data to be written is transmitted to the same root bit line selection signal line of the first storage body to be written into the selected storage column in the first storage body; when performing a first internal write operation, the data to be written is transmitted to the same root bit line selection signal line of the second storage body to be written into the selected storage column in the second storage body.

[0078] Here, during the process of executing the first internal write operation, the first signal carries the data in the target data corresponding to the storage column address selected in the first storage body, and the second signal does not carry valid data; during the process of executing the second internal write operation, the second signal carries the data in the target data corresponding to the storage column address selected in the second storage body, and the first signal does not carry a valid number.

[0079] Thus, still for the scenario of the aforementioned example, for ECC enabled and a write operation to the entire storage body, the target data includes the externally received data signal DQ and the check code calculated by the data signal DQ. Assuming that the redundant block 0 of Bank0 is used to repair the normal block Normal CP, and the redundant block 0 of Bank1 is used to repair the check block ECC CP, when performing the first internal write operation, the first signal carries the data sequence 0101 written to the normal block Normal CP, and the second signal does not carry a valid signal, that is, the data to be written is 0101, so 0101 is written to the redundant block 0 in Bank0; when performing the second internal write operation, the first signal does not carry a valid signal, and the second signal carries the check code sequence 1010 written to the check block ECC CP, that is, the data to be written is 1010, so 1010 is written to the redundant block 0 in Bank1. The first signal and the second signal will not carry valid signals at the same time, resulting in an error in the data to be written, ensuring that the written data is the expected data.

[0080] like Figure 2 As shown, a data block (CP0, CP1, ...) of the first memory bank and a data block of the second memory bank share a set of multiplexed write units, a redundancy block (CCR CP0) of the first memory bank and a redundancy block of the second memory bank share a set of multiplexed write units, and a parity block (ECC CP0) of the first memory bank and a parity block of the second memory bank share a set of multiplexed write units. In this way, the data blocks, redundancy blocks, and parity blocks of the first and second memory banks all share write circuits.

[0081] In another possible architecture, see Figure 4 The read / write control circuit 11 includes multiple independent write units and multiple shared write units. A data block in each memory bank is connected to a set of independent write units, while a redundant block in the first memory bank and a redundant block in the second memory bank share a set of shared write units. Thus, the data blocks in the first and second memory banks each have independent write units, with only the redundant blocks sharing the write circuit.

[0082] The read-write control circuit 11 is specifically configured to write target data into the data block of the first storage body through a part of the independent write units and all the multiplexed write units when performing the first internal write operation; and write target data into the data block of the second storage body through another part of the independent write units and all the multiplexed write units.

[0083] In some embodiments, see Figure 5 , the memory 10 further includes:

[0084] a command decoder 12 configured to decode the command address signal and generate an initial write instruction if the decoding result indicates a write operation;

[0085] The shift circuit 13 is connected to the command decoder 12 and is configured to delay the initial write instruction by N clock cycles in the target mode to generate a shift write instruction; the clock cycle is the period of the clock signal in the memory, and N is a positive integer.

[0086] Correspondingly, each read / write control circuit 11 is connected to the shift circuit 12, a memory bank in the first group of memory banks and a memory bank in the second group of memory banks, and is configured to perform a first internal write operation in response to an initial write instruction; and to perform a second internal write operation in response to a shift write instruction.

[0087] Specifically, the aforementioned multiplexed write unit is specifically configured to, in response to an initial write instruction, transmit the data to be written to the same root bit line selection signal line of the first storage body to write into the selected storage column in the first storage body; and in response to a shift write instruction, transmit the data to be written to the same root bit line selection signal line of the second storage body to write into the selected storage column in the second storage body.

[0088] In this way, the memory 10 internally delays the initial write instruction to generate another new write instruction, namely the shift write instruction, and then uses the initial write instruction and the shift write instruction to perform two internal write operations respectively, which is equivalent to splitting an external write command into two operations.

[0089] It should be noted that the initial write instruction may have various manifestations in the circuit, such as a single pulse, continuous pulses, or a certain level value on a signal channel. Furthermore, the manifestation of the initial write instruction may be different for different signal channels.

[0090] It should be noted that the command address signal carries a large amount of information, and the command decoder 12 only needs to decode part of the information to confirm whether this is a write operation.

[0091] For a specific example, see Figure 6 Command decoder 12 decodes the chip select signal CS and a portion of the sampled command address signal, such as CaR0N, CaR1, and CaR2, and outputs a decoded result signal. Here, chip select signal CS indicates whether memory 10 is selected, and the initial write instruction is reflected as a pulse of the decoded result signal. The logic components of command decoder 12 only need to conform to the decoding rules for write operations.

[0092] In a specific example, in target mode, the column delay tccd of the memory is greater than or equal to 2N clock cycles, where N is a positive integer; tCCD is a timing parameter in DRAM operation, which indicates the minimum time interval between two consecutive column operations (such as reading or writing) in a memory bank.

[0093] In this way, the initial write instruction is delayed by N clock cycles to obtain a shift write instruction, so that the first internal write operation is performed using the 1st to Nth clock cycles, and the second internal write operation is performed using the N+1th to 2Nth clock cycles, which meets the timing requirements of DRAM and will not affect the next operation. In a specific scenario, according to the JEDEC regulations, for 16B operating mode, burst length (Burst Length, BL) = 16 and low frequency, the minimum tccd is 4 clock cycles; when the memory 10 enters the compressed operating mode (i.e., target mode) during the test phase, it is also 16B mode, BL = 16, and the minimum tccd is consistent with the regulations, which is also 4 clock cycles, so N = 2 can be taken. That is, the shift write instruction is obtained by delaying the initial write instruction by 2 clock cycles, which meets the JEDEC timing and does not affect the next operation.

[0094] In one example, for a memory 10 employing on-chip error correction, the memory 10 further includes an ECC error correction module configured to perform a logical operation on an externally received data signal to generate a check code. That is, the check code is generated by an internal circuit of the memory 10 based on the data signal.

[0095] In another example, for the memory 10 that does not adopt on-chip error correction, the check code may be generated by external calculation, and the memory 10 receives the data signal and the check code from the outside.

[0096] In some embodiments, see Figure 5 The memory 10 further includes an address module 15 and a data latch module 14 .

[0097] The address module 15 is connected to the shift circuit 13 and is configured to generate an address selection signal; and, in response to an initial write instruction, flip the level state of the address selection signal; in response to a shift write instruction, flip the level state of the address selection signal;

[0098] The data latch module 14 is connected to the ECC error correction module and is configured to latch the data signal and the check code in response to the initial write instruction to generate target data.

[0099] Each read-write control circuit 11 is also connected to the address module 15 and the data latch module 14, and is configured to receive an address selection signal, and write the target data to a connected storage body in response to an initial write instruction and an address selection signal in a first level state; and write the target data to another connected storage body in response to a shift write instruction and an address selection signal in a second level state.

[0100] In this way, the data latch module 14 only performs data latching in response to the initial write instruction, and does not work in response to the shift write instruction, that is, each write operation only latches data once; the address module 15 flips the state of the address selection signal in response to the initial write instruction and the shift write instruction, thereby writing the latched target data into the first group of storage bodies and the second group of storage bodies, respectively.

[0101] In some embodiments, the first group of memory banks includes odd-numbered memory banks, and the second group of memory banks includes even-numbered memory banks. Thus, the address selection signal in the first level state is used to select the odd-numbered memory banks, and the address selection signal in the second level state is used to select the even-numbered memory banks.

[0102] See Figure 7 , which provides a Figure 5 The signal circuit design of the shift circuit 13 receives the decoding result signal output by the command decoder, see Figure 15 The signal timing diagram provided, the pulse on the decoding result signal can be regarded as the initial write instruction; the shift circuit 13 outputs the write operation signal wrcmd based on the decoding result signal, see Figure 15 The signal timing diagram provided shows that two adjacent pulses on the write operation signal wrcmd are respectively regarded as the initial write instruction and the shift write instruction, and the subsequent data latch module 14 and the address module 15 both operate according to the write operation signal.

[0103] In some embodiments, see Figure 8 , the shift circuit 13 includes:

[0104] The shift unit 131 is connected to the command decoder 12 and is configured to receive an initial write instruction; in the target mode, delay the initial write instruction by N clock cycles to generate a shift write instruction;

[0105] The integration unit 132 is connected to the shift unit 131 and is configured to integrate the initial write instruction and the shift write instruction into the same signal channel and output a write operation signal wrcmd.

[0106] In this way, the shift unit 131 delays the initial write instruction to generate a shift write instruction, and the integration unit 132 integrates the two write instructions into the same signal channel, thereby forming the total control signal of the subsequent modules.

[0107] Specifically, a mode flag signal is provided in the memory 10 to indicate whether the memory 10 is in the target mode, and the processing logic of the shift unit 131 is designed accordingly. Figure 9 ,

[0108] The shift unit 131 is configured to receive a mode flag signal and a decoding result signal; if the mode flag signal is in an enabled state, delay the decoding result signal to generate a first intermediate signal; if the mode flag signal is in a disabled state, maintain the output level of the first intermediate signal unchanged;

[0109] The integration unit 132 includes a first OR gate 201, which performs an OR operation on the command decoding signal and the first intermediate signal to generate a write operation signal wrcmd;

[0110] In the target mode, the mode flag signal is in an enabled state; in modes other than the target mode, the mode flag signal is in a disabled state.

[0111] Here, the enabled state may be either a high level or a low level, and the disabled state may be the other of the high level or the low level; the levels of the enabled states of different signals may be different.

[0112] It should be understood that Figure 9 , the initial write instruction and the shift write instruction are both positive pulses, so the core of the integration unit 132 uses an OR gate. In other cases, the initial write instruction and the shift write instruction are both negative pulses, and the core of the integration unit 132 can use an AND gate. Of course, the pulse types of the initial write instruction and the shift write instruction can also be different.

[0113] That is to say, due to the diversity of circuit components, the component composition structure of each circuit unit cannot be exhaustively listed. Similarly, the following only provides an example of a specific circuit component composition of a shift unit 131.

[0114] In some embodiments, see Figure 9 The shift unit 131 includes a first trigger 202, a second trigger 203 and a first latch 204; the input end of the first trigger 202 receives the decoding result signal, and the first trigger 202, the second trigger 203 and the first latch 204 sequentially cascade the output first intermediate signal of the first latch 204; in response to the non-enabled mode flag signal, the output ends of the first trigger 202, the second trigger 203 and the first latch maintain the preset level unchanged, that is, the shift unit does not work.

[0115] Due to the diversity of flip-flops, the signal connection method of the clock terminal of the flip-flop matches the selection of the flip-flop. In one possibility, the clock terminals of the first flip-flop 202, the second flip-flop 203 and the first latch 204 are connected to their own input terminals.

[0116] In another possibility, the clock terminals of the first flip-flop 202 , the second flip-flop 203 and the first latch 204 all receive the clock signal Clk inside the memory 10 .

[0117] exist Figure 9 In the figure, the OR gate is composed of the NOR gate and the NOT gate, and the AND gate is composed of the NAND gate and the NOT gate.

[0118] See Figure 9 The shift unit 131 also includes a first NAND gate 205 and a first NOT gate 206 connected in sequence. The first NAND gate 205 receives the mode flag signal and the reset inverted signal ResetN respectively. The output end of the first NOT gate 206 is connected to the reset ends of the first trigger 202 and the second trigger 203. The output end of the first NAND gate 205 is connected to the reset end of the first latch 204.

[0119] Simply put, in target mode, the mode flag signal is high; when the memory 10 performs a reset operation, the reset inverting signal ResetN is low, the reset terminals of the first flip-flop 202 and the second flip-flop 203 are both low-level reset, and the reset terminal of the first latch 204 is high-level reset. Thus, in target mode and when the memory 10 does not perform a reset operation, the reset terminals of the first flip-flop 202, the second flip-flop 203, and the first latch 204 are inactive, and the shift unit 131 operates normally. In non-target mode or when the memory 10 performs a reset operation, the first flip-flop 202, the second flip-flop 203, and the first latch 204 are in the reset state, that is, the shift unit 131 does not operate.

[0120] In some embodiments, see Figure 10 , the data latch module 14 includes:

[0121] The first flip unit 141 is connected to the shift circuit 13 and configured to output an initial latch signal; in the target mode, in response to the initial write instruction, the initial latch signal is adjusted to a non-enabled state; in response to the shift write instruction, the initial latch signal is adjusted to an enabled state;

[0122] The shielding unit 142 is connected to the first flip unit 141 and is configured to output the write operation signal wrcmd as a latch flag signal in response to the initial latch signal in the disabled state; and to shield the write operation signal wrcmd to keep the level of the latch flag signal unchanged in response to the initial latch signal in the enabled state; wherein the pulse of the latch flag signal corresponds to the initial write instruction;

[0123] The latch unit 143 is connected to the shielding unit 142 and is configured to latch the data signal and the check code using the pulse of the latch flag signal to generate target data.

[0124] so, Figure 15 The timing diagram of the inverted signal CompWrDataLatch of the latch flag signal is provided. For each initial write instruction, a pulse is generated in the latch flag signal to latch the data signal and the check code. That is, for a write operation targeting all memory banks, there is only one data latch process.

[0125] It should be understood that the data latching process achieved through the collaboration of the above circuit units not only supports data latching in target mode, but also enables data latching in other write modes, reducing signal paths and circuit area. For example, in non-target mode, for each external write command, the write operation signal wrcmd only has one pulse, and the first flip unit 141 and shielding unit 142 are inoperative. The latch flag signal replicates the pulse of the write operation signal wrcmd, and data latching is still achieved using latch unit 143.

[0126] In a specific circuit structure, such as Figure 11 As shown, the first flip-flop 141 includes a second NOT gate 207 and a third flip-flop 208, the output end of the third flip-flop 208 is connected to the input end of the third flip-flop 208 via the second NOT gate 207; the clock end of the third flip-flop 208 receives the write operation signal wrcmd, and the second NOT gate outputs the initial latch signal Dbus1st; in response to the mode flag signal of the non-enabled state, the output of the third flip-flop 208 maintains the preset level unchanged.

[0127] The third flip-flop 208 may be a D-type flip-flop, which samples the input terminal at the rising edge of the clock terminal and outputs the sampling result at the output terminal.

[0128] In some implementations, the mask unit 142 performs an OR operation on the initial latch signal Dbus1st and the inverted signal wrcmdN of the write operation signal to generate CompWrDataLatchN. Figure 9 As shown, shielding unit 142 includes a second OR gate 209. The inputs of second OR gate 209 receive the initial latch signal Dbus1st and the inverted write operation signal wrcmdN, respectively. The output of second OR gate 209 outputs the latch flag signal CompWrDataLatchN. In this scenario, second OR gate 209 can sample a two-input OR gate. The inverted write operation signal wrcmdN is generated by passing the write operation signal wrcmdN through a NOT gate.

[0129] In other embodiments, see Figure 11 The shielding unit 142 is further configured to receive the auxiliary control signal fnCompN and output the latch flag signal CompWrDataLatchN in response to the auxiliary control signal fnCompN in the enabled state; and shield the pulse of the latch flag signal CompWrDataLatchN in response to the auxiliary control signal fnCompN in the disabled state. In this scenario, the second OR gate 209 needs to be a three-input OR gate, and the third input terminal of the second OR gate 209 receives the auxiliary control signal fnCompN.

[0130] Here, the auxiliary control signal fnCompN can provide richer control logic, so that the overall circuit matches other functional requirements of the memory 10.

[0131] It should be noted that in order to meet the corresponding timing requirements, the latch flag signal CompWrDataLatchN can be obtained after delay, that is, the shielding unit 142 is specifically configured to perform an OR operation and delay processing on the initial latch signal and the inverted signal of the write operation signal wrcmd (wrcmd) (implemented by the delay unit in the middle of the second OR gate 209) to generate the latch flag signal CompWrDataLatchN.

[0132] like Figure 11 As shown, the latch unit 143 includes a second latch 210. The second latch 210 latches the target data using the latch flag signal CompWrDataLatchN. Here, the number of second latches 210 is the same as the total number of bits of the data signal and the check code. That is, Write Data is one bit in the data signal / check code, and Data is one bit of the target data signal.

[0133] The second latch 210 can be a composite latch that latches data at the falling edge of the clock terminal (Lat) and outputs the latched data at the rising edge of the clock terminal. Of course, the second latch 210 can also use other types of latches, but the signal connection method and logic need to match the selection of the latch.

[0134] In some embodiments, see Figure 12 The address module 15 includes a fourth flip-flop 211 and a third NOT gate 212, which is equivalent to a counter composed of a single D-type flip-flop; the clock end of the fourth flip-flop 211 receives the write operation signal wrcmd, and the output end of the fourth flip-flop 211 is connected to the input end of the fourth flip-flop 211 through the third NOT gate 212, and the third NOT gate 212 outputs the address selection signal BAaddress; in response to the mode flag signal in the disabled state, the output end of the fourth flip-flop 211 maintains a preset level unchanged.

[0135] So, see Figure 15 The signal timing provided is that in response to the initial write instruction, the address selection signal BAaddress is in one level state, the EVENBank Add signal generates a pulse, Bank0 / 2 / 4 / 6 / 8 / 10 / 12 / 14 is selected, and the latched target data is written to Bank0 / 2 / 4 / 6 / 8 / 10 / 12 / 14; in response to the shift write instruction, the address selection signal BAaddress is in another level state, the ODDBank Add signal generates a pulse, and the latched target data is written to another group of storage bodies Bank1 / 3 / 5 / 7 / 9 / 11 / 13 / 15.

[0136] In other embodiments, see Figure 13 , the address module 15 includes:

[0137] The second flip unit 151 is configured to generate a write flag signal WrIntFlag; in the target mode, in response to the initial write instruction, flip the level state of the write flag signal WrIntFlag; in response to the shift write instruction, flip the level state of the write flag signal WrIntFlag;

[0138] The sampling unit 152 is connected to the second flip unit and is configured to sample the write flag signal WrIntFlag to form the address selection signal BAaddress in response to the delayed initial write instruction; and to sample the write flag signal WrIntFlag to form the address selection signal BAaddress in response to the delayed shift write instruction.

[0139] That is, the sampling unit 152 is used to sample the output signal of a single counter to generate the address selection signal BAaddress, so that the pulse edge of the address selection signal BAaddress is more synchronized with the pulse edge of the write operation signal, thereby improving timing accuracy.

[0140] In a specific circuit structure, see Figure 14 The second flip-flop 151 includes a fourth flip-flop 211 and a third NOT gate 212; the clock end of the fourth flip-flop 211 receives the write operation signal wrcmd (wrcmd), and the output end of the fourth flip-flop 211 is connected to the input end of the fourth flip-flop 211 through the third NOT gate 212, and the third NOT gate 212 outputs the write flag signal WrIntFlag; in response to the non-enabled mode flag signal, the output end of the fourth flip-flop 211 maintains a preset level unchanged; the sampling unit 152 includes a fifth flip-flop 214; the fifth flip-flop 214 uses the delayed write operation signal wrcmdDly to sample the write flag signal WrIntFlag and outputs the address selection signal BAaddress.

[0141] See Figure 14 The second flip unit 151 may further include a first AND gate 213. The input terminal of the first AND gate 213 receives the mode flag signal and the reset inverted signal ResetN. The output terminal of the first AND gate 213 is connected to the set terminal of the fourth flip-flop 211, which is active low. Thus, in the target mode and when the reset operation is not being performed, the first AND gate 213 outputs a high level, the set terminal is inactive, and the fourth flip-flop 211 operates normally. In the non-target mode or when the reset operation is being performed, the first AND gate 213 outputs a low level, the set terminal is active, and the fourth flip-flop 211 does not operate.

[0142] In summary, please refer to Figure 15After receiving the write command sent from the outside, the command decoder 12 compiles the initial write instruction (reflected as the pulse on the decoding result signal and the first pulse of the two adjacent pulses in the write operation signal wrcmd), and the shift circuit 13 internally delays the initial write instruction by 2 clock cycles to generate a shifted write instruction (reflected as the second pulse of the two adjacent pulses in the write operation signal wrcmd), which is integrated into the same channel and recorded as wrcmd. For the data latch module 14, the first pulse of the write operation signal wrcmd triggers the generation of the latch flag signal CompWrDataLatchN to sample the data signal and the check code to form the target data AA. At this time, the BA address is the default address, so the first pulse of the write operation signal wrcmd will write the target data AA into half of the storage bodies Bank0 / 2 / 4 / 6 / 8 / 10 / 12 / 14, for example; after the second pulse of the write operation signal wrcmd passes through the data latch module 14, the latch flag signal CompWrDataLatchN does not generate a pulse (that is, the target data will no longer be sampled), but the second pulse of the write operation signal wrcmd triggers the level flip of the address selection signal BAaddress after passing through the address module 15, and the previously latched target data AA can be written into the remaining storage bodies Bank1 / 3 / 5 / 7 / 9 / 11 / 13 / 15, thereby achieving the purpose of writing all storage bodies at the same time.

[0143] It should be noted that the above description is based on two memory banks sharing a read-write control circuit. In other memory architectures, more memory banks can share a read-write control circuit. That is, the memory includes M groups of memory banks, and one memory bank in each group of memory banks shares the same read-write control circuit; the memory 10 is configured to receive a command address signal and a data signal from the outside; in the target mode, if the command address signal indicates a write operation, M internal write operations are performed in sequence; wherein the target mode instructs all memory banks to perform a write operation together, and the mth internal write operation refers to writing target data to the mth group of memory banks through each read-write control circuit, and the target data includes a data signal. Here, M is a positive integer greater than or equal to 2, m is a positive integer, and m is 1, 2, ..., M in sequence.

[0144] Figure 16 FIG. 4 shows a schematic structural diagram of a memory 10 with M=4.

[0145] The disclosed embodiment minimizes circuit area and wiring without changing the structure of the shared read / write control circuit of the storage body, without adding test steps, and without affecting the operation timing specified by JEDEC, thereby meeting test requirements and reducing test time and complexity.

[0146] In another embodiment of the present disclosure, see Figure 16, which shows a schematic diagram of the structure of a test system 50 provided by an embodiment of the present disclosure. Figure 16 As shown, the test system 50 includes at least the aforementioned memory 10 and a test machine 51, wherein the test machine 51 is configured to output command address signals and data signals to the memory 10; the memory 10 includes M groups of memory banks; a memory bank in each group of memory banks shares the same read / write control circuit; the memory is configured to receive a command address signal (CA) and a data signal from the outside; in target mode, if the command address signal (CA) indicates a write operation, M internal write operations are sequentially performed; wherein the target mode indicates that all memory banks perform a write operation together, and the mth internal write operation refers to writing target data to the mth group of memory banks through each read / write control circuit, the target data including the data signal. Here, M is a positive integer greater than or equal to 2, m is a positive integer, and m≤M.

[0147] Thus, for a memory 10 with multiple banks sharing a read / write control circuit, a write operation to all banks is divided into multiple internal write operations. Each internal write operation uses the read / write control circuit to write the target data to a connected bank. When the error correction function is enabled and the memory is tested in compressed read / write mode, the actual written data is ensured to match the expected written data, improving the testing efficiency of the post-fuse stage and quickly determining whether the redundancy repair is successful.

[0148] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The above serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: The memory includes a first group of memory banks, a second group of memory banks, and a plurality of read-write control circuits, wherein a memory bank in the first group of memory banks and a memory bank in the second group of memory banks share the same read-write control circuit; The memory is configured to receive a command address signal and a data signal from the outside; in a target mode, if the command address signal indicates a write operation, then sequentially performing a first internal write operation and a second internal write operation; In which, the target mode indicates that all storage bodies perform a write operation together, the first internal write operation refers to writing target data to the first group of storage bodies through each of the read-write control circuits, and the second internal write operation refers to writing the target data to the second group of storage bodies through each of the read-write control circuits, and the target data includes the data signal.

2. The memory according to claim 1, wherein The memory further comprises: a command decoder configured to decode the command address signal and generate an initial write instruction when the decoding result indicates a write operation; a shift circuit connected to the command decoder and configured to, in target mode, delay the initial write instruction by N clock cycles to generate a shift write instruction; the clock cycle is a period of a clock signal in the memory, and N is a positive integer; Each of the read-write control circuits is connected to the shift circuit, one of the first group of storage bodies, and one of the second group of storage bodies, and is configured to perform the first internal write operation in response to the initial write instruction; and to perform the second internal write operation in response to the shift write instruction.

3. The memory according to claim 2, wherein: The memory further includes an address module; The address module is connected to the shift circuit and configured to generate an address selection signal; and, in response to the initial write instruction, flip the level state of the address selection signal; in response to the shift write instruction, flip the level state of the address selection signal; Each of the read-write control circuits is also connected to the address module and configured to receive the address selection signal, and write the target data to one of the connected storage bodies in response to the initial write instruction and the address selection signal in the first level state; and write the target data to another of the connected storage bodies in response to the shift write instruction and the address selection signal in the second level state.

4. The memory according to claim 3, wherein: The target data also includes a check code generated by calculating the data signal; The memory further comprises: An ECC error correction module configured to perform a logical operation on the data signal to generate the check code; The data latch module is connected to the ECC error correction module and is configured to latch the data signal and the check code in response to the initial write instruction to generate the target data.

5. The memory according to claim 4, wherein: The shift circuit comprises: a shift unit connected to the command decoder and configured to receive the initial write instruction; in a target mode, delay the initial write instruction by N clock cycles to generate the shift write instruction; an integration unit connected to the shift unit, configured to integrate the initial write instruction and the shift write instruction into the same signal channel and output a write operation signal; Wherein, in the target mode, two adjacent pulses of the write operation signal correspond to the initial write instruction and the shift write instruction respectively.

6. The memory according to claim 5, wherein: The data latch module includes: a first flip unit connected to the shift circuit and configured to output an initial latch signal; in a target mode, in response to the initial write instruction, adjust the initial latch signal to a non-enabled state; and in response to the shift write instruction, adjust the initial latch signal to an enabled state; a shielding unit connected to the first flip unit, configured to output the write operation signal as a latch flag signal in response to the initial latch signal in a disabled state; and shield the write operation signal to keep the level of the latch flag signal unchanged in response to the initial latch signal in an enabled state; wherein the pulse of the latch flag signal corresponds to the initial write instruction; The latch unit is connected to the shielding unit and is configured to latch the data signal and the check code using the pulse of the latch flag signal to generate the target data.

7. The memory according to claim 6, wherein: The address module includes: a second flip unit configured to generate a write flag signal; in a target mode, flip the level state of the write flag signal in response to the initial write instruction; and flip the level state of the write flag signal in response to the shift write instruction; The sampling unit is connected to the second flip unit and is configured to sample the write flag signal to form the address selection signal in response to the delayed initial write instruction; and to sample the write flag signal to form the address selection signal in response to the delayed shift write instruction.

8. The memory according to claim 5, wherein: The command decoder outputs a decoding result signal, wherein a pulse in the decoding result signal indicates the initial write instruction; The shift unit is configured to receive a mode flag signal and the decoding result signal; If the mode flag signal is in an enabled state, delay processing is performed on the decoding result signal to generate a first intermediate signal; if the mode flag signal is in a disabled state, the output level of the first intermediate signal is maintained unchanged; The integration unit includes a first OR gate, which performs an OR operation on the command decoding signal and the first intermediate signal to generate the write operation signal; Wherein, in the target mode, the mode flag signal is in an enabled state; in other modes except the target mode, the mode flag signal is in a disabled state.

9. The memory according to claim 8, wherein: The shift unit includes a first flip-flop, a second flip-flop, and a first latch; an input end of the first flip-flop receives the decoding result signal, the first flip-flop, the second flip-flop, and the first latch are cascaded in sequence, the clock ends of the first flip-flop, the second flip-flop, and the first latch are connected to their respective input ends, and the first latch outputs the first intermediate signal; In response to the mode flag signal in the disabled state, the output terminals of the first flip-flop, the second flip-flop, and the first latch maintain a preset level.

10. The memory according to claim 6, wherein: The first flip unit includes a second NOT gate and a third flip-flop, wherein the output terminal of the third flip-flop is connected to the input terminal of the third flip-flop via the second NOT gate; the clock terminal of the third flip-flop receives the write operation signal, and the second NOT gate outputs the initial latch signal; In response to the mode flag signal in the disabled state, the output of the third flip-flop remains unchanged at a preset level; The shielding unit performs an OR operation on the initial latch signal and the inverted signal of the write operation signal to generate the latch flag signal; The latch unit includes a second latch, and the second latch latches the target data using the latch flag signal.

11. The memory according to claim 7, wherein: The second flip-flop includes a fourth flip-flop and a third NOT gate; a clock terminal of the fourth flip-flop receives the write operation signal, an output terminal of the fourth flip-flop is connected to an input terminal of the fourth flip-flop through the third NOT gate, and the third NOT gate outputs the write flag signal; In response to the mode flag signal in the disabled state, the output terminal of the fourth trigger maintains a preset level; The sampling unit includes a fifth trigger; the fifth trigger samples the write flag signal using the delayed write operation signal and outputs the address selection signal.

12. The memory according to any one of claims 2 to 11, characterized in that: The read / write control circuit includes a plurality of multiplexing write units, each of the multiplexing write units is connected to the same root bit line selection signal line in the same numbered memory block of the first memory bank and the second memory bank, the first memory bank is a memory bank in the first group of memory banks, and the second memory bank is a memory bank in the second group of memory banks; The multiplexing write unit is configured to receive a first signal and a second signal, perform an OR operation on the first signal and the second signal, and generate data to be written; In response to the initial write instruction, the data to be written is transmitted to the same root bit line selection signal line of the first memory bank to be written into the selected memory column in the first memory bank; in response to the shift write instruction, the data to be written is transmitted to the same root bit line selection signal line of the second memory bank to be written into the selected memory column in the second memory bank; In which, in response to the initial write instruction, the first signal carries the data in the target data corresponding to the storage column address selected in the first storage body, and the second signal does not carry valid data; in response to the shift write instruction, the second signal carries the data in the target data corresponding to the storage column address selected in the second storage body, and the first signal does not carry valid data.

13. The memory according to any one of claims 2 to 11, characterized in that: The memory also satisfies one or more of the following conditions: (1) In the target mode, the column delay of the memory is greater than or equal to 2N clock cycles; (2)N＝2； (3) The memory is in a stage after fuse repair; (4) The error correction function is turned on in the target mode; (5) The first group of memory banks includes odd-numbered memory banks; the second group of memory banks includes even-numbered memory banks; (6) The memory is a dynamic random access memory.

14. A testing system, characterized in that: The test system comprises a test machine and the memory according to claim 1-13, wherein the test machine is configured to output a command address signal and a data signal to the memory; the memory comprises M groups of memory banks; a memory bank in each group of memory banks shares the same read / write control circuit; The memory is configured to receive a command address signal and a data signal from the outside; in a target mode, if the command address signal indicates a write operation, then sequentially perform M internal write operations; In which, the target mode instructs all storage bodies to perform a write operation together, and the mth internal write operation refers to writing target data to the mth group of storage bodies through each of the read-write control circuits, and the target data includes the data signal; here, M is a positive integer greater than or equal to 2, m is a positive integer, and m≤M.

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