An IC package structure and a packaging method

Abstract

The application relates to the technical field of integrated circuit packaging, and particularly relates to an IC packaging structure and a packaging method, which comprise a packaging shell, a substrate, a chip group, an insulating layer and a heat dissipation assembly, the substrate comprises a base and a main plate, and the base is provided with an electrical connection assembly; the chip group comprises a chip main body and a pin, the pin is arranged on one side of the chip main body, the chip main body is buckled on the main plate, so that the pin faces the outside and is electrically connected with the electrical connection assembly; the insulating layer is arranged between the chip main body and the main plate, so as to cover the chip main body towards one side of the main plate; and the heat dissipation assembly is arranged on the packaging shell and is in heat conduction connection with the chip group, so that multiple chips or modules with different functions are integrated in a compact space, the sealing treatment and the heat dissipation effect of the heat dissipation assembly effectively improve the heat dissipation effect, the performance and the reliability when facing a complex working environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit packaging technology, and in particular to an IC packaging structure and a packaging method. BACKGROUND

[0002] With the rapid development of integrated circuit technology, electronic products are developing towards miniaturization, high performance and multi-function, which puts forward higher requirements for IC packaging structures. The traditional IC packaging structure gradually fails to meet the growing market demand in terms of functional integration, heat dissipation performance, electrical performance and reliability.

[0003] In terms of functional integration, there are several technical difficulties in IC packaging, including heat dissipation problems, performance problems, and reliability when facing complex working environments. The traditional IC packaging structure in the existing packaging structure can only realize single or a few functions, and it is difficult to integrate chips or modules with multiple different functions in a compact space, which limits the development of multi-functional electronic products. SUMMARY

[0004] The present application aims to at least improve the functional integration, improve the heat dissipation performance, improve the electrical performance and enhance the reliability to some extent. To this end, the present application provides an IC packaging structure and a packaging method.

[0005] In a first aspect, the present application provides an IC packaging structure, comprising a packaging shell, and further comprising:

[0006] a substrate, the substrate comprising a base and a main plate, the base being provided with an electrical connection component;

[0007] a chip set comprising a chip main body and a pin, the pin being arranged on one side of the chip main body, the chip main body being buckled on the main plate so that the pin is directed to the outside and electrically connected with the electrical connection component;

[0008] an insulating layer arranged between the chip main body and the main plate to cover the chip main body towards the side of the main plate;

[0009] a heat dissipation component arranged on the packaging shell and in thermal conductive connection with the chip set.

[0010] In some embodiments, the electrical connection component comprises a plurality of wiring layers, pads, vias and connectors, the plurality of wiring layers being electrically conductive through the vias, the chip set being electrically connected with the wiring layers through the pads, and the connectors being electrically connected with external circuits.

[0011] In some embodiments, the heat dissipation assembly comprises an inner heat dissipation fin and a heat pipe, the package shell is provided with a heat dissipation fin, the inner heat dissipation fin is arranged on one side of the chip set, and the heat pipe is in thermal conductive connection with the inner heat dissipation fin and the heat dissipation fin at two ends thereof.

[0012] In some embodiments, the package shell is provided with an electric shielding layer.

[0013] In some embodiments, a sealing layer is arranged between the substrate and the package shell.

[0014] In the second aspect, the embodiments of the present application provide a packaging method, comprising:

[0015] Substrate preparation, forming a base and a main plate by using a preset material, and forming a plurality of wiring layers and pads on the surface of the substrate;

[0016] Chip set installation, electrically connecting and fixing the chip set and the pads on the substrate by using a preset installation method;

[0017] Heat dissipation assembly installation, connecting the inner heat dissipation fin with the chip set, and connecting one end of the heat pipe with the inner heat dissipation fin and the other end of the heat pipe with the package shell;

[0018] Connector installation, connecting the connector with the corresponding pad;

[0019] Package shell installation, installing the entire structure into the package shell, and sealingly connecting the entire substrate and the package shell.

[0020] In some embodiments, the packaging method further comprises:

[0021] Package testing, testing the entire structure, at least including electrical performance testing, heat dissipation performance testing and reliability testing.

[0022] In some embodiments, the substrate preparation comprises:

[0023] Base processing, forming a base and a main plate by using a preset material;

[0024] Manufacturing wiring layers and pads, manufacturing a plurality of wiring layers and pads on the substrate by using a photoetching and etching process to form an electrical connection path;

[0025] Surface treatment, carrying out copper plating and gold plating treatment on the surface of the base to form the substrate.

[0026] In some embodiments, when the chip set is installed, the preset installation method is a flip chip technology or a wire bonding technology.

[0027] By the packaging structure and the packaging method provided in the application, a plurality of chips or modules with different functions are integrated in a compact space, so that the whole structure has high functional integration degree, the heat dissipation performance is significantly enhanced by the sealing treatment and the heat dissipation effect of the heat dissipation assembly, the electrical performance is improved, and the sealing effectively protects, an integrated circuit packaging structure with good electrical performance, mechanical performance and environmental adaptability is realized, the needs of different application scenarios are met, and the needs of small size, high performance, multi-function and high reliability of electronic products are met. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figure 1 The schematic diagram of the packaging structure in the application is shown;

[0030] Figure 2 The working flowchart of the heat dissipation assembly in the application is shown;

[0031] Figure 3 The flowchart of the packaging method in the application is shown.

[0032] The drawings are as follows: 1, packaging shell; 2, substrate; 21, main plate; 22, base; 3, chip set; 31, chip main body; 32, pin; 4, heat dissipation assembly; 41, inner heat dissipation plate; 42, heat pipe; 5, insulation layer; 6, sealing layer; 7, connecting ball. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the application will be described clearly and completely in the following with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0034] It should be noted that all directional indications in the embodiments of the application are only used to explain the relative position relationship, movement condition and the like between components in a certain posture, and if the certain posture changes, the directional indications also change accordingly.

[0035] In the present application, unless otherwise explicitly specified and limited, the terms "connection", "fixation" and the like should be understood in a broad sense, for example, "fixation" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium, can be internal communication of two elements or interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. In addition, the description such as "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of those skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the scope of protection required by the present application.

[0036] The present application will be described below in conjunction with the accompanying drawings and specific embodiments: with the rapid development of integrated circuit technology, electronic products are developing towards miniaturization, high performance and multi-function, which puts forward higher requirements on IC packaging structure. The traditional IC packaging structure gradually fails to meet the growing market demand in terms of functional integration, heat dissipation performance, electrical performance and reliability, etc.

[0037] In terms of functional integration, existing packaging structures often can only realize single or a few functions, and it is difficult to integrate chips or modules with multiple different functions in a compact space, which limits the multi-functional development of electronic products. For example, in some devices that need to have signal processing, data storage and wireless communication functions at the same time, due to the limitation of packaging structure, multiple independent packaging modules have to be used, which not only increases the volume and cost of the product, but also reduces the overall reliability of the system.

[0038] Heat dissipation has always been an important challenge for IC packaging. With the continuous improvement of chip integration, more and more heat is generated during the operation of the chip. If the heat cannot be dissipated in time and effectively, the temperature of the chip will be too high, which will affect the performance and life of the chip. The heat dissipation design of the traditional packaging structure is often not perfect, the heat dissipation path is long, and the heat dissipation efficiency is low, which cannot meet the heat dissipation needs of high-performance chips.

[0039] In terms of electrical performance, as the working frequency of electronic products continues to increase, the electrical performance requirements of IC packaging structures are also becoming higher and higher. The leads, solder joints and other components in traditional packaging structures can introduce parasitic inductance and capacitance, affecting the transmission speed and integrity of signals, leading to problems such as signal distortion, delay, and limiting the high-speed development of electronic products.

[0040] In addition, the reliability of traditional IC packaging structures is poor when facing complex working environments such as high temperature, high humidity, mechanical vibration, etc., and problems such as packaging cracking, solder joint falling off, chip damage, etc. may occur, affecting the normal use of electronic products.

[0041] In summary, it is of great practical significance to develop a multifunctional IC packaging structure that can improve the functional integration, improve the heat dissipation performance, enhance the electrical performance, and enhance the reliability.

[0042] Embodiment one

[0043] Therefore, the embodiment one of the present application provides an IC packaging structure, referring to Figure 1 , comprising a packaging shell 1, further comprising a substrate 2, a chip set 3, an insulating layer 5 and a heat dissipation component 4.

[0044] The packaging shell 1 is made of plastic (often reinforced with glass fiber) or metal material, and the plastic shell ensures the sealing and certain mechanical strength; the metal shell has good heat dissipation performance and electromagnetic shielding performance. The connection between the packaging shell 1 and the substrate 2 is sealed with sealant to prevent dust and moisture from entering from the outside.

[0045] The substrate 2 is the basic support component of the entire packaging structure, and the electrical connection components are constructed on the surface of the substrate 2 for connection with the chip and external circuit, and the substrate 2 includes a base 22 and a main plate 21. The base 22 is used to connect with the external circuit, and may be provided with a pin 32 or a solder ball and other connection structures; the main plate 21 is used to carry the chip and other components, and provides a mechanical support and an electrical connection for the chip and other internal elements. The base 22 is provided with electrical connection components, wherein ceramic, multi-layer printed circuit board (PCB) and other materials are usually used, which have good electrical insulation performance, mechanical strength and thermal stability to meet various performance requirements of the packaging structure.

[0046] Among them, the main plate 21 is provided with a connecting ball 7 for realizing the electrical connection between the packaging structure and the external circuit, which can be used as a form of lead pin and connected with the solder pad on the external circuit board through welding to realize the transmission of signals and power. The connecting ball 7 is usually made of tin-lead alloy, lead-free alloy (such as SAC305, etc.), which has good weldability and conductivity to ensure reliable electrical connection.

[0047] The chip set 3 can be an IC chip set 3, including a chip body 31 and pins 32, the chip body 31 is the core component to realize the circuit function, integrating various electronic elements and circuits, the pins 32 are used to realize the electrical connection of the chip with the substrate 2 and other external circuits, and the signals inside the chip body 31 are led out or introduced.

[0048] The pins 32 are arranged on one side of the chip body 31, the chip body 31 is buckled on the main body plate 21, so that the pins 32 are oriented outward and electrically connected with the electrical connection assembly, and the chip set 3 can be mounted on the substrate 2 by flip chip technology or wire bonding technology. In the flip chip technology, the pins 32 can be downward, connected with the electrical connection assembly of the substrate 2 through solder balls, the electrical connection distance is shortened, and the parasitic inductance and capacitance are reduced. The wire bonding technology uses a metal wire (such as a gold wire) to connect the pins 32 with the electrical connection assembly, which is suitable for chips with fewer pins or relatively lower electrical performance requirements.

[0049] The chip set 3 can be mounted on the substrate 2 by flip chip technology or wire bonding technology. In the flip chip technology, the pins 32 are downward, and the chip pins 32 are connected with the substrate 2 pads through solder balls, which can realize a shorter electrical connection path and higher integration. The wire bonding technology connects the pins 32 with the substrate 2 pads through a metal wire (such as a gold wire).

[0050] When integrating the chip set 3, multiple functional chips such as processor chips, memory chips, and communication chips can be integrated on the substrate 2. According to the functional relationship of the chips and the signal interaction, the related functional chips are placed adjacent to each other to shorten the signal transmission distance and improve the overall performance of the system.

[0051] The substrate 2 integrates multiple functional IC chips, among which the processor chip is located at the center of the substrate 2, and the memory chip and the communication chip are respectively located on both sides of the processor chip. Between the chips, electrical connection is made through the electrical connection assembly on the substrate 2. At the same time, some passive elements such as resistors and capacitors are also integrated on the substrate 2, which are directly made on the substrate 2 by printed circuit board technology, forming a complete circuit system with the surrounding chips.

[0052] At the same time, resistors, capacitors, inductors and other passive elements are directly made on the substrate 2 by printed circuit board technology or thin film process, reducing the use of external elements, further improving the integration of the packaging structure, and meeting the high precision requirements of specific circuits on electrical performance. Among them, high-precision, high-performance nanoscale resistors, capacitors and inductors can be made on the substrate 2, not only the size is reduced by more than one order of magnitude compared with traditional elements, but also the electrical performance is more stable and accurate, which can meet the stringent requirements of high-end electronic products on small size and ultra-high electrical performance precision.

[0053] When integrating multiple functional chips on the substrate 2, advanced 3D packaging technology is adopted to vertically stack the chip groups 3 of different functional layers, such as stacking a memory chip above a processor chip. This not only further reduces the packaging size, but also significantly improves the data transmission speed by using shorter vertical interconnections between chips. Through this 3D stacking technology, compared with traditional planar packaging, the number of integrated functional chips can be increased by 30%-50% in the same packaging area, greatly improving the functional integration of the system.

[0054] The insulating layer 5 is arranged between the chip body 31 and the main body plate 21 to cover the chip body 31 towards the side of the main body plate 21, playing a role of electrical insulation and physical protection. It can prevent short circuits between the chip and surrounding components, and protect the chip from external environmental factors such as moisture and dust.

[0055] The insulating layer 5 is generally made of materials with high insulation performance and good adhesion, such as epoxy resin and polyimide. These materials can form a reliable insulation and protection barrier around the chip.

[0056] The heat dissipation component 4 is arranged on the packaging shell 1 and is in thermal contact with the chip group 3, for quickly conducting heat to the outside of the packaging structure.

[0057] By integrating multiple IC chips and passive components of different functions on the substrate 2 and reserving external interfaces, high integration of multiple functions is achieved, reducing the number of packaging modules in electronic products, reducing the size and cost of products, and improving the overall performance and reliability of the system. By arranging the heat dissipation component 4, the heat generated by the IC chip can be quickly and effectively dissipated, reducing the temperature of the chip and improving the performance and life of the chip, meeting the heat dissipation needs of high-performance chips. The packaging shell 1 effectively improves the sealing performance of the entire packaging structure, and by improving the welding process and enhancing the mechanical strength design, the packaging structure can operate stably in complex working environments, reducing failures caused by environmental factors and mechanical stress, and improving the reliability and service life of the product.

[0058] The packaging structure provided by the embodiments of the present application integrates multiple chips or modules of different functions in a compact space to achieve high functional integration of the entire structure. The sealing process and the heat dissipation effect of the heat dissipation component significantly enhance the heat dissipation performance, improve the electrical performance, and effectively protect the sealing. An integrated circuit packaging structure with good electrical performance, mechanical performance and environmental adaptability is achieved, meeting the needs of different application scenarios and meeting the needs of small size, high performance, multi-function and high reliability of electronic products.

[0059] In some embodiments, the electrical connection assembly includes a plurality of wiring layers, pads, vias and connectors, the plurality of wiring layers are electrically connected through the vias, the chip set 3 is electrically connected with the wiring layers through the pads, and the connectors are electrically connected with external circuits.

[0060] The wiring layers are designed in multiple layers, and the wiring is reasonably planned according to the chip function and signal transmission requirements to reduce the signal transmission path length and bending degree, and wide line width and low impedance wiring materials are used to reduce the line resistance and inductance. The vias realize electrical connection between different wiring layers. The connectors adopt the forms of ball grid array (BGA) and pin 32 grid array (PGA), etc., to realize the connection between the packaging structure and external circuits.

[0061] In some embodiments, the heat dissipation assembly 4 includes an inner heat sink and a heat pipe 42, and the packaging shell 1 is provided with heat dissipation fins, the inner heat sink is arranged on one side of the chip set 3, and the two ends of the heat pipe 42 are respectively in thermal conductive connection with the inner heat sink and the heat dissipation fins.

[0062] The packaging shell 1 is in the shape of a rectangle and can be made of metal materials, and the surface is provided with heat dissipation fins for increasing the heat dissipation area. The bottom of the packaging shell 1 is tightly connected with the substrate 2 through sealing glue to ensure the sealing of the packaging structure. One end of the heat pipe 42 extends out of the top of the packaging shell 1, and the other end of the heat pipe 42 is connected with the inner heat sink which is located above the chip set 3 and is in close contact with the chip set 3 through thermal conductive silicone grease.

[0063] The heat dissipation fins on the packaging shell 1 are composed of a plurality of parallel fins with a certain spacing between the fins to increase the heat dissipation area and air flow. The heat pipe 42 penetrates the heat dissipation fins, and the inside of the heat pipe 42 is filled with working medium, which is similar to the working principle of the heat pipe 42. Figure 2 When the chip set 3 generates heat, the heat is transferred to the inner heat sink through the thermal conductive silicone grease, the inner heat sink absorbs the heat, and then the heat is transferred to the evaporation section of the heat pipe 42, the working medium in the heat pipe 42 is vaporized by heat, the steam quickly flows to the condensation section, and then condenses into liquid after heat exchange with the external environment, and then returns to the evaporation section to complete the heat transfer process.

[0064] The heat dissipation assembly 4 can use new heat dissipation materials, such as graphene heat dissipation fins and carbon nanotube heat pipes 42. The graphene heat dissipation fins have ultra-high thermal conductivity, and their heat dissipation capacity is 5-10 times that of traditional metal heat dissipation fins, which can more quickly absorb the heat generated by the chip. The unique structure of the carbon nanotube heat pipe 42 makes its heat conduction efficiency 2-3 times higher than that of ordinary heat pipes 42, which can more efficiently conduct heat to the outside of the package, and can reduce the working temperature of the chip by 15-20℃, effectively improving the performance and service life of the chip.

[0065] In some embodiments, an electric shielding layer is arranged in the packaging shell 1. Inside the packaging structure, an electromagnetic shielding layer made of metal materials such as copper foil and aluminum foil is arranged on the surface of the substrate 2 or inside the packaging shell 1 to shield the internal circuit, prevent electromagnetic interference from occurring and spreading, and improve signal transmission integrity.

[0066] In some embodiments, a sealing layer 6 is arranged between the substrate 2 and the packaging shell 1. The sealing layer 6 is used to seal the entire structure and prevent external environmental factors such as moisture, gas, dust, etc. from entering the inside of the package, thereby protecting the normal operation of the internal chip set 3 and other components. The reliability and stability of the packaging structure can be enhanced, the service life of the product can be prolonged, and the sealing layer 6 can be made of silicone rubber, epoxy resin, etc. These materials have good sealing performance, weather resistance and mechanical properties, and can maintain good sealing effect under different environmental conditions.

[0067] The sealing layer 6 can use self-repairing sealant technology. When it is slightly damaged, it can automatically repair the cracks in the sealing layer 6 and maintain the sealing performance of the packaging structure. The internal humidity of the packaging structure using self-repairing sealant is only 30-50% of that of traditional sealant, effectively protecting the internal chips and components. Self-repairing sealant usually contains microcapsules or reversible cross-linked polymers, and the microcapsules are filled with repair agents. When the sealant is slightly damaged and cracks appear, the stress at the crack will cause the microcapsules to break, releasing the repair agent. The repair agent quickly fills the crack and reacts chemically under the action of a catalyst or environmental conditions to re-form a material with sealing properties, thereby repairing the sealing layer 6.

[0068] Embodiment two

[0069] The embodiments of the present application provide a packaging method to form the packaging structure provided in embodiment one. Referring to Figure 3 , the method comprises the following steps:

[0070] S1, substrate preparation, forming a base and a main plate using a predetermined material, and forming a plurality of wiring layers and pads on the surface of the substrate;

[0071] S2, chip set installation, electrically connecting and fixing the chip set to the pads on the substrate by a predetermined installation method;

[0072] S3, heat dissipation component installation, connecting the inner heat dissipation fin to the chip set, and connecting one end of the heat pipe to the inner heat dissipation fin and the other end to the packaging shell;

[0073] S4, connector installation, connecting the connector to the corresponding pad;

[0074] S5, packaging shell installation, installing the entire structure into the packaging shell, and sealingly connecting the entire substrate to the packaging shell.

[0075] In some embodiments, the packaging method further comprises:

[0076] S6, packaging test, testing the whole structure, including at least electrical performance test, heat dissipation performance test and reliability test.

[0077] In some embodiments, the substrate preparation comprises:

[0078] S11, substrate processing, forming a substrate and a main plate by using a preset material;

[0079] S12, making wiring layers and pads, making multiple wiring layers and pads on the substrate by photolithography, etching and other processes to form an electrical connection path;

[0080] S13, surface treatment, carrying out copper plating, gold plating and other treatments on the substrate surface to form the substrate.

[0081] In some embodiments, when the chip set is installed, the preset installation method can be flip chip technology or wire bonding technology.

[0082] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

Claims

1. An IC package structure comprising a package housing (1), characterized in that, include: The substrate (2) includes a base (22) and a main plate (21), and an electrical connection assembly is disposed on the base (22); The chipset (3) includes a chip body (31) and pins (32), the pins (32) being disposed on one side of the chip body (31), the chip body (31) being fastened to the main body plate (21) so that the pins (32) face outward and are electrically connected to the electrical connection assembly; An insulating layer (5) is disposed between the chip body (31) and the main board (21) to cover the chip body (31) facing the main board (21); A heat dissipation component (4) is disposed on the package shell (1) and is thermally connected to the chipset (3). The heat dissipation component (4) includes an inner heat sink and a heat pipe (42). The package shell (1) is provided with heat dissipation fins. The inner heat sink is disposed on one side of the chipset (3). The two ends of the heat pipe (42) are thermally connected to the inner heat sink and the heat dissipation fins, respectively.

2. The package structure of claim 1, wherein, The electrical connection assembly includes multiple wiring layers, pads, vias, and connectors. The multiple wiring layers are electrically connected through the vias. The chipset (3) is electrically connected to the wiring layers through the pads. The connector is electrically connected to an external circuit.

3. The package structure of claim 1, wherein, An electrical shielding layer is provided inside the encapsulation shell (1).

4. The package structure of claim 1, wherein, A sealing layer (6) is provided between the substrate (2) and the packaging shell (1).

5. A packaging method, characterized by, include: Substrate preparation involves forming a substrate and a main board using a preset material, and forming multiple wiring layers and pads on the surface of the substrate. Chipset mounting involves electrically connecting and securing the chipset to the pads on the substrate using a preset mounting method. The heat dissipation assembly is installed by connecting the inner heat sink to the chipset, and connecting one end of the heat pipe to the inner heat sink and the other end to the package shell; Connector installation: Connect the connector to the corresponding pad. The encapsulation housing is installed by mounting the entire structure into the encapsulation housing and sealing the connection between the entire substrate and the encapsulation housing.

6. The packaging method according to claim 5, wherein, The encapsulation method further includes: Packaging testing involves testing the entire structure, including at least electrical performance testing, thermal performance testing, and reliability testing.

7. The packaging method of claim 5, wherein, Substrate fabrication includes: Substrate processing involves using pre-set materials to form the substrate and main body panel. Fabricate wiring layers and pads: Use photolithography and etching processes to create multiple wiring layers and pads on the substrate to form electrical connection paths; Surface treatment involves plating the substrate surface with copper or gold to form a substrate.

8. The packaging method according to claim 5, wherein, When installing the chipset, the default installation method is either flip-chip technology or wire bonding technology.

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