Low-power-consumption RC oscillator

Abstract

The invention discloses a low-power-consumption RC oscillator. The low-power-consumption RC oscillator comprises a starting circuit, a current source circuit and a core oscillation circuit. The starting circuit is responsible for enabling the whole circuit to successfully reach a designed working point, and is turned off after being started; the current source circuit is responsible for generating a PTAT current; the core oscillation circuit is responsible for generating square wave oscillation. By adopting an AVDD / AVSS dual-power supply architecture and a multi-path current mirror structure, the technical bottlenecks of starting delay, temperature drift, power consumption efficiency compromise and the like of a traditional RC oscillator are effectively solved through the collaborative optimization design of the core oscillation circuit and the buffer output stage while the oscillation frequency stability is ensured, and the stability of the RC oscillator is improved. And a novel solution is provided for the power management module of a miniaturized electronic system.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an ultra-low power consumption oscillator circuit based on a dual power supply architecture. Background Art

[0002] Given the urgent need for ultra-low-power clock sources in cutting-edge applications such as IoT terminals, biomedical implants, and miniaturized wireless sensor nodes, current mainstream RC oscillators face a sharp conflict between quiescent current and frequency stability in the subthreshold operating region. In traditional single-supply architectures, transistor subthreshold leakage current is typically greater than 5μA, making it difficult to meet the nanoamp-level power consumption requirements of coin-cell battery-powered scenarios. Furthermore, employing a deep-cutoff bias strategy can lead to significant startup delays (greater than 10ms) and temperature drift (greater than 5000ppm / °C). Summary of the Invention

[0003] This invention provides a low-power RC oscillator that utilizes a multi-current mirror design to significantly reduce power consumption and startup delay. The oscillator has a temperature coefficient of 2322 ppm / °C over the -40°C to 125°C range, and a total output noise of 2.57 mV. The invention features low power consumption, low noise, and low latency, making it suitable for use in button cell battery-powered circuits.

[0004] The low-power RC oscillator provided by the present invention includes a startup circuit, a current source circuit, and a core oscillator circuit. The startup circuit is responsible for ensuring that the entire circuit successfully reaches the designed operating point and shuts down after startup; the current source circuit is responsible for generating a PTAT current; and the core oscillator circuit is responsible for generating square wave oscillations.

[0005] The startup circuit includes: PMOS transistors M0 and M1; NMOS transistors M2, M3, M4, M5, M6 and M7; the sources of M0 and M1 are connected to the power supply VDD terminal, the gate of M0 is connected to the node VBP, the drain of M0 is connected to the drain of M2, the source of M2 is connected to the drain of M3, the source of M3 is connected to the drain of M4, the source of M4 is connected to the drain of M5, the source of M5 is connected to the drain of M6, and the source of M6 is connected to the drain of M7; the gates of M2, M3, M4, M5, M6 and M7, the drain of M2 and the gate of M1 are mutually connected to a node labeled VStartup_off; the drain of M1 is connected to a node labeled VStart_up.

[0006] The current source circuit includes: PMOS transistors M10 and M11; NMOS transistors M8, M9 and resistor R0; the sources of M10 and M11 are connected to the power supply voltage VDD, the gates of M10 and M11, and the drains of M8 and M10 are all connected to the node VBP; the drains of M9 and M11, and the gates of M8 and M9 are all connected to the node VStart_up; the source of M9 is connected to the power supply VSS terminal; the source of M8 is connected to one end of the resistor R0, and the other end of the resistor R0 is connected to the power supply VSS terminal.

[0007] The core oscillation circuit includes: PMOS transistors M12 and M13; NMOS transistors M15, M16 and M17; capacitor C0, Schmitt trigger I0 and inverter I1; the sources of M12 and M13 are connected to the power supply VDD terminal; the gates of M12 and M13 are connected to the node VBP; the drain of M12 is connected to the drain of M15; the source of M15, the drain of M17, the gate of M17 and the gate of M16 are connected to each other; the sources of M16 and M17 are connected to the power supply VSS terminal; the drain of M13, the drain of M16, one end of capacitor C0 and the input end of Schmitt trigger I0 are connected to each other; the output end of Schmitt trigger I0 is connected to the input end of inverter I1; the other end of capacitor C0 and the gate of M15 are connected to the output end of inverter I1 and serve as the output port of the RC oscillator.

[0008] A resistor may be connected to the tail end of the Schmitt trigger to prevent a latch-up effect when the trigger is suddenly turned on.

[0009] The technical features and effects of the present invention are as follows:

[0010] The innovative integration of the Widlar current source module, Schmitt trigger shaping circuit and adaptive startup control unit, combined with the MOS tube configuration strategy in the constant current working area, achieves low power consumption.

[0011] In particular, the AVDD / AVSS dual power supply architecture and multi-path current mirror structure ensure the stability of the oscillation frequency. Through the coordinated optimization design of the core oscillation circuit and the buffer output stage, it effectively solves the technical bottlenecks of traditional RC oscillators, such as startup delay, temperature drift and power consumption efficiency compromise, and provides a new solution for the power management module of miniaturized electronic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a circuit principle diagram of the present invention;

[0013] Figure 2 、 Figure 3 It is the simulation parameter setting and part of the output results of the present invention;

[0014] Figure 4 The offset voltage result simulated by the present invention;

[0015] Figure 5 This is the noise result simulated by the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments for better understanding.

[0017] like Figure 1 As shown in the figure, at the beginning, the current in the Widlar current source is detected by the M0 transistor. If the chip enters the merger point after power-on, resulting in no bias current generated in the Widlar current source, that is, VBP is high, so the PMOS transistor M0 is in the cut-off state, then Vstartup_off is low, so the PMOS transistor M1 is turned on, and the current generated by the M1 transistor is injected into the current source from the VStart_up node:

[0018]

[0019] That is, the voltage at the VStart_up node gradually increases, causing the NMOS transistor in the Widlar current source to be turned on, thereby generating the set PTAT current.

[0020] Secondly, when the current source generates current normally, the PMOS tube M1 in the startup circuit is turned on, thereby mirroring the PTAT current in the Widlar current source. This current flows into an equivalent resistor (composed of NMOS tubes of the same size connected in series, with the overall size W unchanged, and L being the sum of the Ls of all NMOS tubes. The NMOS diode connection is equivalent to a resistance of 1 / gm). That is, the Vstartup_off node voltage gradually increases, thereby turning off the M1 tube in the startup circuit. Therefore, after the startup is completed, the startup circuit will not affect other circuit modules.

[0021] The current source circuit provides bias current for the core oscillator circuit. Its basic operating principle is as follows: PMOS current mirrors M10 and M11 ensure that the currents in the two branches are equal. Due to the inconsistent sizes of NMOS transistors M8 and M9, the VGS of the transistors are inconsistent under the condition of the same current. The difference between the two eventually falls on resistor R0, thus generating PTAT current. The magnitude of the current generated is:

[0022] The Schmitt trigger can be regarded as an inverter with hysteresis characteristics, which can suppress the influence of noise on the comparison point voltage and has strong anti-interference ability.

[0023] In the initial state, the charge on the capacitor is zero, meaning the VNET1 node voltage is low. Therefore, OSC_OUT is low, indicating that NMOS transistor M15 is off. Since M15 is off, the bottom NMOS transistors M17 and M16 are off, while PMOS transistor M13 remains on. The PTAT current mirrored by the Widlar current source charges the capacitor, causing the VNET1 node voltage to increase. When the VNET1 node voltage rises to the Schmitt trigger's flip-point, OSC_OUT transitions from low to high.

[0024] When the output OSC_OUT is high, NMOS transistor M15 turns on. After M15 turns on, M12 can mirror the PTAT current in the Widlar current source. This current provides a bias voltage for M16 through the diode-connected M17, turning M16 on. Since M16 is twice the size of M17 and the upper M13 can only provide half the current, M16 also draws current from the capacitor to meet the following requirements: This means that the VNET1 node voltage will gradually decrease. When it decreases to the flip threshold voltage of the Schmitt trigger, the output voltage OSC OUT will change from a high level to a logic low level again, thus repeating the above process again, and finally realizing the high and low level output of OSC_OUT.

Claims

1. A low-power RC oscillator, comprising a startup circuit, a current source circuit, and a core oscillation circuit, characterized in that: The startup circuit includes: PMOS transistors M0 and M1; NMOS transistors M2, M3, M4, M5, M6 and M7; the sources of M0 and M1 are connected to the power supply VDD terminal, the gate of M0 is connected to the node VBP, the drain of M0 is connected to the drain of M2, the source of M2 is connected to the drain of M3, the source of M3 is connected to the drain of M4, the source of M4 is connected to the drain of M5, the source of M5 is connected to the drain of M6, and the source of M6 is connected to the drain of M7; the gates of M2, M3, M4, M5, M6 and M7 and the drain of M2 and the gate of M1 are mutually connected to a node labeled VStartup_off; the drain of M1 is connected to a node labeled VStart_up; The current source circuit includes: PMOS transistors M10 and M11; NMOS transistors M8, M9 and resistor R0; the sources of M10 and M11 are connected to the power supply voltage VDD, the gates of M10 and M11, and the drains of M8 and M10 are all connected to the node VBP; the drains of M9 and M11, and the gates of M8 and M9 are all connected to the node VStart_up; the source of M9 is connected to the power supply VSS terminal; the source of M8 is connected to one end of the resistor R0, and the other end of the resistor R0 is connected to the power supply VSS terminal; The core oscillation circuit includes: PMOS transistors M12 and M13; NMOS transistors M15, M16 and M17; capacitor C0, Schmitt trigger I0 and inverter I1; the sources of M12 and M13 are connected to the power supply VDD terminal; the gates of M12 and M13 are connected to the node VBP; the drain of M12 is connected to the drain of M15; the source of M15, the drain of M17, the gate of M17 and the gate of M16 are connected to each other; the sources of M16 and M17 are connected to the power supply VSS terminal; the drain of M13, the drain of M16, one end of capacitor C0 and the input end of Schmitt trigger I0 are connected to each other; the output end of Schmitt trigger I0 is connected to the input end of inverter I1; the other end of capacitor C0 and the gate of M15 are connected to the output end of inverter I1 and serve as the output port of the RC oscillator.

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