A direct spread spectrum signal digital correlator and parallel fast acquisition method

Abstract

The present application relates to the technical field of digital communication systems, and more particularly to a direct spread spectrum signal digital correlator and a parallel fast capture method. The direct spread spectrum signal digital correlator comprises: a parallel PN code generation unit for simultaneously generating multiple different long PN sequences; a parallel correlator array comprising multiple correlator elements for performing correlation operations on a received DSSS signal in parallel with corresponding sequences from multiple different long PN sequences over a series of code phases; a frequency offset estimation and compensation unit for estimating and compensating the frequency offset between the received DSSS signal and a local reference; and a multi-dimensional peak detection and code deambiguation logic unit for processing the output from the parallel correlator array to detect the presence of a signal, identifying one or more captured PN codes from multiple different long PN sequences, and estimating the corresponding code phases and frequency offsets to achieve parallel fast capture. The method can significantly shorten the system's capture time while processing complex DSSS signals.

Description

Technical Field

[0001] The present application relates to the technical field of digital communication systems, and in particular to a direct spread spectrum signal digital correlator and a parallel fast capture method. Background Art

[0002] Direct Sequence Spread Spectrum (DSSS) is an important communications technology that uses pseudo-random noise (PN) codes to spread narrowband signals over a wider bandwidth. DSSS offers excellent anti-interference capabilities, a low probability of intercept, and can effectively mitigate multipath effects and support code division multiple access (CDMA).

[0003] The capture process of DSSS signals is crucial to the operation of the entire system. The core of capture lies in synchronizing the PN code replica generated locally by the receiver with the received signal in two dimensions: code phase and carrier frequency. This is essentially a two-dimensional search problem. Traditional serial search methods have excessively long capture times. When long spreading sequences are used, the code phase search space increases dramatically, significantly increasing capture complexity. In multi-code DSSS or CDMA systems, the receiver needs to capture signals from multiple users or multiple different codes assigned to a single user, which introduces the problem of inter-code interference. In addition, in dynamic environments, the relative motion between the transmitter and receiver can cause significant Doppler frequency deviation, which further complicates capture in the frequency search dimension.

[0004] Existing correlator architectures and acquisition technologies have limitations in addressing these challenges. While serial correlators are simple in structure, they are slow and are particularly unsuitable for long codes. Fully parallel correlators are the fastest for a single code, but they also have extremely high hardware complexity. Fast Fourier transform (FFT)-based acquisition techniques can simultaneously search for code phase and carrier frequency. However, the length of the FFT increases with the required frequency accuracy, resulting in a significant increase in computational load and hardware resources. In summary, existing technologies are deficient in simultaneously meeting the requirements of long sequence processing, multi-code parallelism, fast acquisition, and hardware resource controllability. Therefore, there is an urgent need for an efficient DSSS digital correlator that can achieve parallel and rapid acquisition of multiple different code signals using long spreading sequences. Summary of the Invention

[0005] The purpose of this application is to overcome the problem in the prior art that it is difficult to achieve parallel and fast capture of multiple long-sequence DSSS signals under the premise of limited hardware resources, and to provide a direct spread spectrum signal digital correlator and a parallel fast capture method. Through architectural innovation, it is possible to significantly shorten the system capture time while processing complex DSSS signals.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] In a first aspect, the present application proposes a direct spread spectrum signal digital correlator for rapidly capturing multiple long sequences in parallel, comprising: a control unit, and a preprocessing unit, a parallel PN code generation unit, a parallel correlator array, a frequency offset estimation and compensation unit, and a multidimensional peak detection and code defuzzification logic unit, each electrically connected to the control unit. The parallel correlator array is electrically connected to the preprocessing unit, the parallel PN code generation unit, the frequency offset estimation and compensation unit, and the multidimensional peak detection and code defuzzification logic unit, respectively. The frequency offset estimation and compensation unit is electrically connected to the multidimensional peak detection and code defuzzification logic unit.

[0008] The parallel PN code generating unit is used to simultaneously generate a plurality of different long PN sequences;

[0009] The parallel correlator array includes a plurality of correlator elements for performing correlation operations on the received DSSS signal with corresponding sequences of a plurality of different long PN sequences in parallel over a series of code phases;

[0010] The frequency offset estimation and compensation unit is configured to estimate and compensate for the frequency offset between the received DSSS signal and a local reference;

[0011] The multi-dimensional peak detection and code defuzzification logic unit is used to process the output from the parallel correlator array to detect the presence of a signal, identify one or more captured PN codes from multiple different long PN sequences, and estimate the corresponding code phase and frequency offset to achieve parallel fast capture.

[0012] Preferably, the parallel PN code generating unit comprises a reconfigurable LFSR array, wherein the reconfigurable LFSR array comprises a plurality of LFSRs, and the LFSRs can be used to generate long PN sequences with different generator polynomials or initial states.

[0013] Preferably, the correlator element adopts a parallel matched filter structure or a segmented correlation structure for processing the long PN sequence.

[0014] Preferably, the parallel correlator array adopts a resource sharing architecture, and the resource sharing architecture adopts at least one of a shared FFT engine, a reconfigurable correlator, and a multiplexed FIR filter group; the shared FFT engine is used to perform FFT-based correlation operations or frequency analysis, the reconfigurable correlator can be time-shared by different PN sequences, and the multiplexed FIR filter group is used to perform multiple code correlation operations.

[0015] Preferably, the frequency offset estimation and compensation unit estimates the frequency offset using an FFT output of a parallel correlator array, or uses a CORDIC algorithm to perform phase correction at a tap of each correlator element to compensate for the frequency offset.

[0016] Preferably, the multidimensional peak detection and code defuzzification logic unit adopts at least one of dynamic threshold-based peak detection, multi-hypothesis peak testing, peak to sidelobe ratio (PSR) analysis, and algorithms for identifying valid peaks in code-phase-frequency multidimensional space.

[0017] In a second aspect, the present application proposes a parallel fast capture method for capturing multiple long sequences, comprising the following steps:

[0018] Acquire and pre-process the DSSS signal, and generate multiple different PN sequences in parallel;

[0019] performing parallel correlation operations on the pre-processed DSSS signal and corresponding sequences of a plurality of different long PN sequences at a series of code phases, and estimating and compensating frequency offsets in parallel for the parallel correlation operations;

[0020] The output of the parallel correlation operation is processed to detect the presence of a signal, identify one or more captured PN codes from multiple different long PN sequences, and estimate the corresponding code phase and frequency offset to achieve parallel fast acquisition.

[0021] Preferably, the parallel correlation operation includes: for each PN sequence, using a parallel matched filter structure or a segmented correlation method to process the pre-processed DSSS signal.

[0022] Preferably, the parallel correlation operations and / or the parallel estimation and compensation of frequency offsets include processing data from multiple correlation paths using a shared fast FFT engine.

[0023] Preferably, processing the output of the parallel correlation operation to detect the presence of a signal comprises applying a multi-dimensional peak search algorithm and making a decision based on the peak to sidelobe ratio and a preset threshold to distinguish between true signal peaks and noise or false alarms.

[0024] The beneficial effects of this application are:

[0025] 1. Significantly improves acquisition speed: Compared with traditional methods, the time required to capture multiple long DSSS codes is greatly shortened.

[0026] 2. True multi-code parallel processing: Ability to search and capture a group of different long codes at the same time.

[0027] 3. Scalable architecture: The design allows for expansion based on different code numbers and sequence lengths, with predictable resource requirements.

[0028] 4. Enhanced robustness: Due to the use of efficient integration and search strategies, the performance in low signal-to-noise ratio or dynamic environments is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a detailed block diagram of a digital correlator for direct spread spectrum signals.

[0031] Figure 2 is a block diagram of a DSSS communication system including the proposed direct spread spectrum signal digital correlator.

[0032] Figure 3 The present invention is an architectural diagram of a parallel PN code generating unit of a direct spread spectrum signal digital correlator.

[0033] Figure 4 A schematic diagram of a single correlator element in a parallel correlator array of a digital correlator for direct spread spectrum signals.

[0034] Figure 5 The diagram is a schematic diagram of a resource sharing mechanism within a parallel correlator array of a direct spread spectrum signal digital correlator.

[0035] Figure 6 The present invention is a block diagram of the multi-dimensional peak detection and code defuzzification logic of a direct spread spectrum signal digital correlator.

[0036] Figure 7 is a timing diagram showing an example of multi-code acquisition of a parallel fast acquisition method. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0038] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0039] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0040] refer to Figure 1-Figure 7 The present invention provides a direct spread spectrum signal digital correlator.

[0041] refer to Figure 1 A direct spread spectrum signal digital correlator includes: a preprocessing unit, a parallel PN code generating unit, a parallel correlator array, a frequency offset estimation and compensation unit, a multi-dimensional peak detection and code defuzzification logic unit, and a control unit.

[0042] The control unit is electrically connected to the preprocessing unit, the parallel PN code generation unit, the parallel correlator array, the frequency offset estimation and compensation unit, and the multi-dimensional peak detection and code defuzzification logic unit. The parallel correlator array is electrically connected to the preprocessing unit, the parallel PN code generation unit, the frequency offset estimation and compensation unit, and the multi-dimensional peak detection and code defuzzification logic unit. The frequency offset estimation and compensation unit is electrically connected to the multi-dimensional peak detection and code defuzzification logic unit.

[0043] The pre-processing unit is configured to pre-process the DSSS signal received by the receiving module as an input signal. The parallel PN code generation unit is configured to simultaneously generate multiple different long PN sequences. The parallel correlator array is coupled to the parallel PN code generation unit. The parallel correlator array includes multiple correlator elements configured to perform correlation operations on the received DSSS signal in parallel with corresponding sequences of multiple different long PN sequences over a series of code phases. The frequency offset estimation and compensation unit is integrated with the parallel correlator array and configured to estimate and compensate for the frequency offset between the received DSSS signal and the local reference. The multi-dimensional peak detection and code deambiguation logic unit is configured to process the output from the parallel correlator array to detect the presence of a signal, identify one or more captured PN codes from multiple different long PN sequences, and estimate the corresponding code phase and frequency offset, thereby achieving parallel rapid capture.

[0044] refer to Figure 2 The DSSS signal is transmitted by the transmitter module over a wireless channel. The DSSS signal, accompanied by noise and interference, is received by the receiver module. The input signal can be a digitized intermediate frequency (IF) or baseband DSSS signal, or a control signal specifying the code to be searched. The output signals include acquisition status, estimated code phase, frequency offset, and identified acquired codes.

[0045] During the preprocessing of the received DSSS signal, if the input signal is an analog IF signal, the preprocessing unit first converts the analog signal into a digital signal using an analog-to-digital converter (ADC). If the input signal is a digital baseband signal, the ADC step can be skipped or only interface matching can be performed. Subsequently, if the input signal is an IF signal, the digital downconverter (DDC) in the preprocessing unit converts it to a baseband signal. The DDC includes a numerically controlled oscillator (NCO) and a mixer, which shifts the signal spectrum to near zero IF. Next, digital filtering is performed to remove out-of-band noise and interference and limit the signal bandwidth. Following digital filtering, decimation is performed to reduce the sampling rate, thereby reducing the computational load on subsequent processing units. Furthermore, conditioning operations such as sample amplitude adjustment or format conversion are also performed to ensure that the signal characteristics meet the requirements of the subsequent correlator array.

[0046] refer to Figure 3 The core challenge of a parallel PN code generator lies in the need to efficiently and simultaneously generate multiple, different, and long PN sequences. Traditional linear feedback shift registers (LFSRs) are typically used to generate a single PN sequence. The design of this unit is crucial for systems that need to process a large number of parallel correlation channels. To address this challenge, the parallel PN code generator proposed in this invention can be implemented using a variety of approaches. In this application, this is achieved by constructing an array of multiple independent LFSRs, each generating a specific long code.

[0047] Specifically, different Gold code sequences can be generated by setting different generator polynomials and initial states for each LFSR. When processing very long PN sequences, the parallel PN code generation unit must also consider how to efficiently manage the code length and the number of codes generated in parallel. A key feature of the parallel PN code generation unit is the scalability of its PN code generation architecture. This architecture can effectively scale with increasing code quantity and length, avoiding linear or even higher-order growth in hardware resources with each new code addition. This is achieved by employing a master-slave generator architecture, transform domain technology, and a highly optimized shared logic LFSR array.

[0048] Furthermore, for high-speed parallel systems, it is necessary to ensure that all parallel LFSRs operate synchronously and provide the correct chip sequence to their corresponding correlator elements at the correct time. Especially when the code length is very long and the number of codes being processed in parallel is large, the complexity of the chip timing and distribution network increases dramatically. The present invention includes a specific clock distribution network and data distribution mechanism to ensure that large amounts of PN code data can be accurately and quickly transmitted to each correlator element in the parallel correlator array. The multiple parallel PN code sequences generated are then fed to the corresponding correlator elements in the parallel correlator array for correlation with the received signal.

[0049] refer to Figure 3 and Figure 4 The parallel correlator array is responsible for performing parallel correlation operations on the input DSSS signal with multiple locally generated long PN sequences. The parallel correlator array is composed of multiple correlator elements. Depending on the specific implementation, each correlator element is assigned to process a specific code phase of a specific PN code, or each correlator element in a correlator group is responsible for searching all possible phases of a specific PN code.

[0050] refer to Figure 4 Given the requirements for fast acquisition and long codes, a single correlator element tends to adopt a parallel matched filter structure rather than a pure sliding correlator. This parallel matched filter performs parallel correlations between the input signal and a complete period of the local PN code. It internally contains multiple multipliers and accumulators. For binary PN codes (e.g., +1 / -1), the multipliers can be simplified to exclusive-NOR (XNOR) gates or selection logic. The accumulator sums the multiplication results of all code chips to obtain the correlation peak at that code phase. The length of the correlator element is a critical design parameter. For very long PN sequences, directly implementing a matched filter for the full code length would result in excessive hardware complexity. In such cases, short-term correlations (STCs) can be calculated, and these partial correlation results can then be accumulated or further processed.

[0051] Among them, in this application, the parallel processing of multiple PN codes of different lengths can be implemented in the following ways: dedicated parallel architecture, resource-sharing parallel architecture, reconfigurable correlator group, shared FFT engine, and multiplexed FIR filter.

[0052] Specifically, a dedicated parallel architecture allocates a separate, complete parallel correlator structure to each long PN code to be searched. While this approach offers the highest degree of parallelism, it also consumes the most hardware resources, especially when the number of codes and their lengths are large.

[0053] Resource-sharing parallel architecture: Figure 5As shown, in order to improve hardware resource utilization while maintaining high performance, the present invention proposes a resource sharing strategy.

[0054] Reconfigurable Correlator Bank: Design a bank of general-purpose parallel correlator engines that can be quickly reconfigured to load different long PN codes. This approach allows searching for more codes in a slightly longer time with fewer physical correlator units, or dynamically allocating correlator resources as needed.

[0055] Shared FFT engine: FFT processing for multiple codes is shared by time-division multiplexing the STC outputs from different code-specific matched filter banks into a single shared FFT engine.

[0056] Multiplexed FIR filters: Multiplexed FIR filters are used for multi-symbol detection. Different spreading codes are treated as separate channels and applied to multi-code correlation. Time-division multiplexing or multi-channel FIR filter structures can be used to perform correlation operations on multiple codes with less hardware.

[0057] The output of the parallel correlator array is a large number of correlation values, for example, corresponding to each PN code, each code phase, and possibly each frequency unit. When designing a parallel correlator array, it is necessary to consider whether its parallelism is homogeneous or heterogeneous, and whether it is fixed or reconfigurable. This directly affects the scalability and resource utilization of the system. The present invention uses an array composed of reconfigurable parallel correlators, which can more effectively adapt to different multi-code scenarios, which is very beneficial for achieving parallel and rapid capture of long sequence multi-codes.

[0058] Another key challenge is data flow and memory management. With long codes and extensive parallel operation, there is a need to efficiently manage the input sample data stream and the local PN code chip stream, as well as how to store intermediate correlation results. Furthermore, there is an inherent trade-off between resource sharing and acquisition latency. A fully parallel, shared-nothing system has the lowest latency but the highest resource consumption. Sharing resources can reduce hardware usage but may introduce processing bottlenecks or scheduling complexity. The fast acquisition claims of this invention need to be evaluated in the context of its degree of resource sharing.

[0059] In addition to code phase synchronization, DSSS signal acquisition requires estimating and compensating the frequency offset between the received signal and the local oscillator, particularly in dynamic environments where the Doppler effect is present. The frequency offset estimation and compensation unit of the present invention is tightly integrated with the parallel correlator array to enable joint or parallel frequency search of multiple codes.

[0060] One key approach is to use FFTs. If the parallel correlator array uses an FFT-based architecture, different FFT output bins naturally correspond to different frequency offsets. The search is then performed in a multidimensional space composed of code phases, frequency bins, and code indices.

[0061] Another approach is to set up independent, frequency-compensated correlation paths for different test frequency offsets. A CORDIC (Coordinate Rotation Digital Computer)-based phase rotator can be used at each correlator tap to correct the frequency offset before or during the correlation operation. The CORDIC algorithm can achieve precise phase rotation through a series of iterative shift and add operations to compensate for carrier frequency mismatch. For highly dynamic environments, a dedicated Doppler compensation mechanism is required. The core issue is whether the estimation of code phase, frequency and code index is performed jointly or sequentially. The multidimensional search process is a key innovation of the present invention. The output of this unit is the estimated frequency offset value, which can be used to correct the carrier frequency of the received signal or directly compensated during the correlation operation to maximize the correlation peak and thus improve the capture performance.

[0062] refer to Figure 6 After the parallel correlator array performs parallel correlation on multiple long PN codes, multiple code phases, and possibly multiple frequency offsets, a vast number of correlation output values ​​are generated. The core task of the multidimensional peak detection and code defuzzification logic unit is to accurately detect the valid correlation peaks corresponding to the real signal from this large number of outputs and determine which PN codes were successfully captured, as well as their respective code phases and frequency offsets. This is crucial for multi-code recognition. The present invention proposes the use of an advanced peak detection algorithm to achieve reliable peak detection and code recognition.

[0063] When performing detection in such a large parallel search space, even if the probability of false alarm (PFA) of a single test is low, the cumulative PFA of the entire system can become high. Therefore, the decision logic must be robust to this situation. Simple single-peak detection may not be sufficient. The present invention employs a joint detection scheme that considers the patterns between the outputs of multiple correlators to improve reliability. Another factor to consider is the near-far effect, or uneven received signal power. If multiple codes arrive at the receiver at significantly different power levels, a strong signal may mask a weak signal, or the sidelobes of a strong signal may be mistaken for the peaks of a weak signal. While the correlators themselves provide processing gain, the peak detection logic may require additional intelligence to effectively handle such situations in a multi-code environment. The final output of this multi-dimensional peak detection and code deambiguation logic unit is a declaration of acquisition success or failure, identifying the acquired PN code or codes, and providing their estimated code phase and frequency offset parameters for subsequent tracking loops.

[0064] In this application, the control unit coordinates and manages the operations of the preprocessing unit, parallel PN code generation unit, parallel correlator array, frequency offset estimation and compensation unit, and multi-dimensional peak detection and code defuzzification logic unit to achieve efficient and accurate parallel fast acquisition. Its main functions include the following.

[0065] The first is PN code management: controlling the parallel PN code generation units to load the correct PN sequence. This involves selecting the parameters (such as the generator polynomial, initial state, etc.) of the specific long PN code to be generated based on a preset search list or external instructions.

[0066] The second is correlator configuration: if the parallel correlator array contains reconfigurable correlator elements, the control unit is responsible for configuring these elements at run time, for example, assigning them specific PN codes, setting the correlation length (if variable), or adjusting other correlation parameters.

[0067] The third aspect is acquisition search strategy control: managing the search strategy for the entire acquisition process. For example, this involves controlling the frequency offset estimation and compensation unit to scan different Doppler frequency offset ranges and step sizes. It also involves controlling the parallel correlator array to search for different code phases. This can involve a predefined search sequence or an adaptive search strategy based on intermediate results.

[0068] The fourth component is data flow management: controlling the flow of input DSSS signal data between the preprocessing unit, the parallel correlator array, and other modules. This ensures that data is delivered to the appropriate processing units at the correct rate and timing. It also manages the large amount of correlation output data generated by the parallel correlator array and efficiently transmits it to the multidimensional peak detection and code defuzzification logic units.

[0069] The fifth is timing and synchronization control: providing precise clock signals and synchronization control for the entire digital correlator to ensure the coordination and consistency of all parallel operations.

[0070] The sixth is peak detection and decision coordination: interacting with the multi-dimensional peak detection and code defuzzification logic unit, for example, providing the current search parameters (such as the code being tested, frequency, etc.), and receiving the detection results, and also participating in the setting or adjustment of the threshold.

[0071] The seventh is interface management: responsible for communicating with system components outside the digital correlator. This includes receiving commands from the upper-layer controller (such as starting acquisition and specifying search parameter sets) and reporting acquisition status to the upper layer (such as acquisition success / failure, acquired code ID, code phase, frequency offset, etc.).

[0072] The eighth is status monitoring and error handling: monitoring the operating status of each module and executing corresponding processing procedures when errors or abnormal situations are detected.

[0073] The design of the control unit is crucial to achieving the parallel fast acquisition claimed by the present invention. It needs to efficiently schedule resources, minimize processing delays, and ensure the completeness and accuracy of the search process in complex long-sequence multi-code environments.

[0074] Based on the same inventive concept, the present invention also provides a parallel fast capture method.

[0075] refer to Figure 7 , a parallel fast capture method, comprising the following steps:

[0076] S1: Initialization and configuration based on external instructions or preset parameters.

[0077] The control unit configures the parallel PN code generators based on external instructions or preset parameters to generate a set of different long PN sequences to be searched. If the correlator array is reconfigurable, it is configured to allocate corresponding correlation resources for each PN sequence. The initial frequency search range and step size, as well as the code phase search range, are set.

[0078] S2: Acquire and pre-process the DSSS signal, and generate multiple different PN sequences in parallel.

[0079] The pre-processing unit acquires the DSSS signal and performs sampling, digitization and necessary conditioning on the received DSSS signal. The parallel PN code generation unit simultaneously outputs the current chips of M different long PN sequences.

[0080] For each PN sequence, a parallel matched filter structure or a segmented correlation method is used to process the received DSSS signal. The parallel PN code generation unit uses a reconfigurable LFSR array and configures different parameters for each LFSR in the reconfigurable LFSR array to generate a unique long PN sequence.

[0081] S3: performing parallel correlation operations on the pre-processed DSSS signal and corresponding sequences among a plurality of different long PN sequences at a series of code phases, and estimating and compensating frequency offsets in parallel for the parallel correlation operations.

[0082] The parallel correlator array receives the pre-processed DSSS signal and M PN sequences. Each logical section in the array performs parallel correlation on all code phases of its assigned PN sequence. This is typically implemented using a matched filter or equivalent parallel structure.

[0083] At the same time, the frequency offset estimation and compensation unit applies a series of trial frequency offsets to each correlation path for compensation. This can be achieved through FFT calculations or CORDIC-based tap-by-tap phase correction.

[0084] S4: Process the output of the parallel correlation operation to detect the presence of the signal, identify one or more captured PN codes from multiple different long PN sequences, and estimate the corresponding code phase and frequency offset to achieve parallel fast capture.

[0085] The output of the parallel correlation operation is processed to detect the presence of the signal using a multi-dimensional peak search algorithm, and a decision is made based on the peak-to-sidelobe ratio and a preset threshold to distinguish between true signal peaks and noise or false alarms.

[0086] Within a certain coherent integration time (one or several PN code periods), the outputs of each correlation path are coherently accumulated to improve the signal-to-noise ratio. To further enhance weak signal detection, the results of multiple coherent accumulations can be non-coherently accumulated. Non-coherent integrators typically include a storage buffer to store intermediate results.

[0087] After accumulation, the parallel correlator array outputs a large data set representing correlation values ​​for all searched code, code phase, and frequency offset combinations. These correlation values ​​are processed by a multidimensional peak detection and code defuzzification logic unit. First, potential peaks are screened by comparison with a threshold. These candidate peaks are then subjected to more sophisticated detection algorithms, such as peak-to-sidelobe ratio analysis and peak shape analysis, to eliminate false alarms.

[0088] Once one or more true correlation peaks are identified, the logic unit needs to determine which of the M PN sequences each peak corresponds to. At the same time, based on the position of the peak in the correlation output data structure, the precise code phase and frequency offset of the corresponding code are estimated.

[0089] If a valid peak is detected that meets all decision criteria, acquisition is declared successful. The control unit outputs an acquisition success signal, along with the acquired code ID, estimated code phase, and frequency offset. These parameters are used to initialize the subsequent tracking loop. If no valid peak is detected within a complete search cycle, acquisition is declared unsuccessful and the search is restarted or a failure status is reported.

[0090] The entire process manages data flow through a high degree of parallelization and pipelining, significantly reducing the total acquisition time. This approach is particularly suitable for long sequence multi-code scenarios because it avoids purely serial attempts at every code, every phase, and every frequency, and instead parallelizes most of the search tasks.

[0091] It should be understood that the parallel fast acquisition method described in this application has been partially described in the aforementioned direct spread spectrum signal digital correlator, and to ensure the brevity of the specification, it will not be repeated here.

[0092] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A direct spread spectrum signal digital correlator for rapidly capturing multiple long sequences in parallel, characterized in that: include: a control unit, and a preprocessing unit, a parallel PN code generating unit, a parallel correlator array, a frequency offset estimation and compensation unit, and a multi-dimensional peak detection and code defuzzification logic unit, respectively electrically connected to the control unit, wherein the parallel correlator array is respectively electrically connected to the preprocessing unit, the parallel PN code generating unit, the frequency offset estimation and compensation unit, and the multi-dimensional peak detection and code defuzzification logic unit, and the frequency offset estimation and compensation unit is electrically connected to the multi-dimensional peak detection and code defuzzification logic unit; The parallel PN code generating unit is used to simultaneously generate a plurality of different long PN sequences, wherein the parallel PN code generating unit comprises a reconfigurable LFSR array, wherein the reconfigurable LFSR array comprises a plurality of LFSRs, and the LFSRs are capable of generating long PN sequences with different generating polynomials or initial states; The parallel correlator array includes a plurality of correlator elements for performing correlation operations on the received DSSS signal in parallel with corresponding sequences of a plurality of different long PN sequences at a series of code phases, wherein the correlator elements adopt a parallel matched filter structure or a segmented correlation structure for processing the long PN sequence; The parallel correlator array adopts a resource sharing architecture, and the resource sharing architecture adopts at least one of a shared FFT engine, a reconfigurable correlator, and a multiplexed FIR filter bank; the shared FFT engine is used to perform FFT-based correlation operations or frequency analysis, the reconfigurable correlator can be time-division multiplexed by different PN sequences, and the multiplexed FIR filter bank is used to perform multiple code correlation operations; The frequency offset estimation and compensation unit is configured to estimate and compensate the frequency offset between the received DSSS signal and a local reference, wherein the frequency offset estimation and compensation unit estimates the frequency offset using an FFT output of a parallel correlator array or performs phase correction using a CORDIC algorithm at a tap of each correlator element to compensate for the frequency offset; The multidimensional peak detection and code defuzzification logic unit is used to process the output from the parallel correlator array to detect the presence of a signal, identify one or more captured PN codes from multiple different long PN sequences, and estimate the corresponding code phase and frequency offset to achieve parallel rapid capture. The multidimensional peak detection and code defuzzification logic unit uses at least one of dynamic threshold-based peak detection, multi-hypothesis peak testing, peak to sidelobe ratio analysis, and an algorithm for identifying valid peaks in the code-phase-frequency multidimensional space.

2. A parallel fast acquisition method, applied to the direct spread spectrum signal digital correlator of claim 1, for capturing multiple long sequences, characterized in that: The following steps are involved: Acquire and pre-process the DSSS signal, and generate multiple different PN sequences in parallel; performing parallel correlation operations on the pre-processed DSSS signal and corresponding sequences of a plurality of different long PN sequences at a series of code phases, and estimating and compensating frequency offsets in parallel for the parallel correlation operations; The output of the parallel correlation operation is processed to detect the presence of a signal, identify one or more captured PN codes from multiple different long PN sequences, and estimate the corresponding code phase and frequency offset to achieve parallel fast acquisition.

3. The parallel fast capture method according to claim 2, wherein: The parallel correlation operation includes: for each PN sequence, using a parallel matched filter structure or a segmented correlation method to process the pre-processed DSSS signal.

4. The parallel fast capture method according to claim 2, wherein: The parallel correlation operations and / or the parallel estimation and compensation of frequency offsets include processing data from multiple correlation paths using a shared fast FFT engine.

5. The parallel fast capture method according to claim 2, wherein: Processing the output of the parallel correlation operation to detect the presence of a signal includes applying a multi-dimensional peak search algorithm and making a decision based on the peak-to-sidelobe ratio and a preset threshold to distinguish between true signal peaks and noise or false alarms.

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