Semiconductor structure, memory system and manufacturing method of semiconductor structure

Abstract

The embodiment of the invention provides a semiconductor structure, a memory system and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a stacking structure having a stacking direction; the insulating layer is positioned on one side of the stacking structure in the stacking direction; the first grid line isolation structure penetrates through the stacking structure and the insulating layer, a first isolation part, located in the stacking structure, of the first grid line isolation structure continuously extends in the first direction, and the side wall of the first isolation part is in a concave-convex shape on the plane perpendicular to the stacking direction; a second isolation part, located in the insulating layer, of the first grid line isolation structure intermittently extends in the first direction; wherein the first direction intersects with the stacking direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a memory system, and a method for manufacturing the semiconductor structure. Background Art

[0002] In order to improve the integration of semiconductor structures, the size of the semiconductor structures in the vertical direction continues to increase, which will affect the structural stability of the semiconductor structures and affect the yield. Summary of the Invention

[0003] The present application provides a semiconductor structure, a memory system, and a method for manufacturing a semiconductor structure that can at least partially solve the above-mentioned problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes: a stacked structure having a stacking direction; an insulating layer located on one side of the stacked structure in the stacking direction; and a first gate line isolation structure extending through the stacked structure and the insulating layer, wherein a first isolation portion of the first gate line isolation structure located in the stacked structure extends continuously along a first direction, and a sidewall of the first isolation portion has a concave-convex shape in a plane perpendicular to the stacking direction; and a second isolation portion of the first gate line isolation structure located in the insulating layer extends discontinuously along the first direction; wherein the first direction intersects the stacking direction.

[0005] In an exemplary embodiment, in the stacking direction, the first isolation portion includes a plurality of sub-first isolation portions, wherein the sizes of the sub-first isolation portions in the second direction decrease along a direction opposite to the stacking direction; wherein the first direction, the second direction and the stacking direction intersect each other.

[0006] In an exemplary embodiment, a dimension of the second isolation portion in the second direction decreases along a direction opposite to the stacking direction.

[0007] In an exemplary embodiment, a dimension in the second direction of an end portion of the second isolating portion in contact with the first isolating portion is smaller than a dimension in the second direction of an end portion of the first isolating portion in contact with the second isolating portion.

[0008] In an exemplary embodiment, the semiconductor structure further includes: a channel structure penetrating the stack structure; and a channel connection structure extending in at least a portion of the insulating layer along the stacking direction and connected to the channel structure.

[0009] In an exemplary embodiment, the channel structure includes a plurality of sub-channel structures in the stacking direction, and the size of the sub-channel structures on a plane perpendicular to the stacking direction decreases along the direction opposite to the stacking structure, wherein the number of stacking layers penetrated by the plurality of sub-channel structures is respectively the same as the number of stacking layers penetrated by the plurality of sub-first isolation portions.

[0010] In an exemplary embodiment, a plurality of first gate line isolation structures are arranged along the second direction, and first isolation portions in adjacent first gate line isolation structures divide the stack structure into memory blocks; wherein the first direction, the second direction, and the stacking direction intersect with each other.

[0011] In an exemplary embodiment, the second isolation portions in adjacent first gate line isolation structures are staggered.

[0012] In an exemplary embodiment, the semiconductor structure also includes a second gate line isolation structure, which penetrates the stacked structure and extends continuously along the first direction; a plurality of second gate line isolation structures are arranged along the second direction, and at least one first gate line isolation structure is located between adjacent second gate line isolation structures, wherein the second gate line isolation structure and the first isolation portion in the first gate line isolation structure divide the stacked structure into storage blocks, or the first isolation portion in the adjacent first gate line isolation structure divides the stacked structure into storage blocks; wherein the first direction, the second direction and the stacking direction intersect with each other.

[0013] In an exemplary embodiment, the first gate line isolation structure includes a polysilicon body and a silicon oxide layer covering sidewalls and a bottom of the polysilicon body.

[0014] In a second aspect, some embodiments of the present application provide a memory system comprising: a memory including a semiconductor structure as described in any of the above embodiments; and a controller coupled to the memory and configured to control the memory to store data.

[0015] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The method includes: forming a first slit portion extending through an initial stacked structure, wherein the first slit portion extends continuously along a first direction and has a concave-convex sidewall; forming an insulating layer on one side of the initial stacked structure in the stacking direction; forming a second slit portion extending through the insulating layer and communicating with the first slit portion, wherein the second slit portion extends discontinuously along the first direction; and forming a first gate line isolation structure in the first slit portion and the second slit portion; wherein the first direction intersects the stacking direction.

[0016] In an exemplary embodiment, before forming an insulating layer on one side of the initial stacking structure in its stacking direction, the manufacturing method further includes: forming a sacrificial material layer in the first gap portion; wherein, forming an insulating layer on one side of the initial stacking structure in its stacking direction includes: forming an insulating layer covering the initial stacking structure and the sacrificial material layer; wherein, after forming a second gap portion that passes through the insulating layer and is connected to the first gap portion, the manufacturing method further includes: removing the sacrificial material layer in the first gap portion.

[0017] In an exemplary embodiment, a dimension of an end portion of the second slit portion contacting the sacrificial material layer in the second direction is smaller than a dimension of an end portion of the sacrificial material layer contacting the second slit portion in the second direction, wherein the first direction, the second direction, and the stacking direction intersect with each other.

[0018] In an exemplary embodiment, the initial stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the manufacturing method further includes replacing the sacrificial layers in the initial stacked structure with gate layers using the first slit portion and the second slit portion.

[0019] In an exemplary embodiment, forming the first slit portion through the initial stacking structure includes: forming a plurality of holes through the initial stacking structure and arranged at intervals along the first direction; and etching the initial stacking structure using the plurality of holes so that the plurality of holes are connected to each other to form the first slit portion.

[0020] In an exemplary embodiment, the manufacturing method further includes forming a channel hole penetrating the initial stacked structure, wherein the channel hole and the plurality of holes are formed using a same mask.

[0021] In an exemplary embodiment, the manufacturing method further includes: forming a channel structure in the channel hole; and forming a channel connection structure extending in the stacking direction in at least a portion of the insulating layer.

[0022] In an exemplary embodiment, forming an insulating layer on one side of an initial stacking structure in its stacking direction includes: forming a first insulating portion of the insulating layer on one side of the initial stacking structure in its stacking direction; and forming a second insulating portion of the insulating layer on the surface of the first insulating portion; wherein, forming a channel connection structure extending along the stacking direction in at least a portion of the insulating layer includes: forming a channel connection structure passing through the first insulating portion.

[0023] In an exemplary embodiment, forming the first gate line isolation structure in the first and second slit portions includes: forming a silicon oxide layer on inner walls of the first and second slit portions; and forming a polysilicon body inside the silicon oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0025] Figure 1 is a perspective cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present application;

[0026] Figure 2A is a perspective cross-sectional schematic diagram of a semiconductor structure provided by another embodiment of the present application;

[0027] Figure 2B yes Figure 2A A schematic plan cross-sectional view of a semiconductor structure is shown;

[0028] Figures 3A to 3D Each of them is a top view schematic diagram of a first gate line isolation structure included in a semiconductor structure;

[0029] Figure 3E is a cross-sectional schematic diagram of a second gate line isolation structure included in a semiconductor structure;

[0030] Figure 4 is a schematic plan cross-sectional view of a semiconductor structure provided by yet another embodiment of the present application;

[0031] Figure 5 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0032] 6A to 13B Schematic diagrams of a cross-section and a top view of a semiconductor structure during the manufacturing process provided by an embodiment of the present application;

[0033] Figures 14A to 17B 1 is a schematic plan cross-sectional view and a schematic top view of a semiconductor structure during the manufacturing process provided by another embodiment of the present application;

[0034] Figure 18 is a block diagram of a system having a memory system provided by an embodiment of the present application; and

[0035] Figure 19A and Figure 19B Schematic diagram of a memory system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features, and in particular do not represent any order of precedence. Therefore, without departing from the teachings of this application, the first gate line isolation structure discussed in this application may also be referred to as the second gate line isolation structure, and vice versa.

[0038] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0039] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0040] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0041] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application may be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but may be performed in any order or in parallel.

[0042] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0043] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0044] Some embodiments of the present application provide a semiconductor structure. Figure 1 is a perspective cross-sectional diagram of a semiconductor structure provided by an embodiment of the present application. For example, Figure 1 The semiconductor structure 100 shown and the semiconductor structures provided in the following embodiments may all be part of a 3D NAND memory.

[0045] It should be noted that, hereinafter, the x-direction, y-direction, and z-direction in the various figures illustrate the spatial relationships of the various components in the semiconductor structure. For example, the z-direction may also be referred to as the stacking direction of the stacked structure (or initial stacked structure), and the x-direction and y-direction are two directions that intersect (e.g., are perpendicular to) each other on a plane that intersects (e.g., is perpendicular to) the stacking direction. The x-direction may also be referred to as the first direction, and the y-direction may also be referred to as the second direction. The same concepts will be used throughout this application to describe the spatial relationships of the various components in the semiconductor structure.

[0046] like Figure 1 As shown, semiconductor structure 100 includes a stacked structure 111, a first gate line isolation structure 113, and a channel structure 115. Stacked structure 111 includes alternating dielectric layers 1111 and gate layers 1112. First gate line isolation structure 113 penetrates stacked structure 111 and extends discontinuously along the x-direction. For example, first gate line isolation structure 113 may include a first portion 1131 and a second portion 1132. First portion 1131 and second portion 1132 are disconnected in the x-direction, with stacked structure 111 located between first portion 1131 and second portion 1132. Channel structure 115 penetrates stacked structure 111 to implement a storage function.

[0047] In this embodiment, the first gate line isolation structure 113 is intermittently extended to reinforce the stack structure 111, and can improve the tipping problem during the process of forming the stack structure 111 (for example, "gate replacement"), thereby optimizing the structural stress of the semiconductor structure 100 and improving the stability and yield of the semiconductor structure 100.

[0048] As the number of stacked layers increases, the number of gate layers 1112 in the stacked structure 111 increases. Since the gate layers 1112 on both sides of the first gate line isolation structure 113 extend continuously, they are not electrically isolated by the first gate line isolation structure 113. The channel structures 115 on both sides of the first gate line isolation structure 113 are controlled by the continuously extending gate layers 1112, which increases the difficulty of control. On the other hand, the increase in the number of stacked layers will also aggravate the tipping problem. Therefore, the increase in the number of stacked layers brings dual challenges to control operation and structural stability.

[0049] In view of this, the following embodiments of the present application provide a semiconductor structure to optimize the above-mentioned semiconductor structure 100 . Figure 2A 2 is a perspective cross-sectional schematic diagram of a semiconductor structure provided by another embodiment of the present application. Figure 2B yes Figure 2A A schematic plan cross-sectional view of a semiconductor structure is shown.

[0050] like Figure 2AAs shown, the semiconductor structure 200 includes a stacked structure 211 , an insulating layer 212 and a first gate line isolation structure 213 .

[0051] In some embodiments, the stacked structure 211 may include alternately stacked dielectric layers 2111 and gate layers 2112. For example, the dielectric layers 2111 and the gate layers 2112 may extend laterally along the x-direction and the y-direction. The material of the dielectric layer 2111 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the dielectric layer 2111 may be silicon oxide (SiO2). The material of the gate layer 2112 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polycrystalline silicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru) or any other suitable conductive material. Optionally, at least a portion of the outer surface of the gate layer 2112 may also be covered with a high dielectric constant layer (not shown) to improve the electrical isolation effect. Among them, the high dielectric constant material may include but is not limited to aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3) and hafnium oxide (HfO2).

[0052] The insulating layer 212 is located on one side of the stacked structure 211 in the z direction. For example, the insulating layer 212 may be located on the surface of the stacked structure 211 in the z direction and contact the dielectric layer 2111 in the stacked structure 211. For another example, in the z direction, the size (e.g., thickness) of the insulating layer 212 may be greater than the size (e.g., thickness) of the dielectric layer 2111. The material of the insulating layer 212 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. In the case where the material of the insulating layer 212 is the same as the material of the dielectric layer 2111, there is no obvious interface between the two.

[0053] The first gate line isolation structure 213 passes through the stacked structure 211 and the insulating layer 212. The first gate line isolation structure 213 includes a first isolation portion 2131 located in the stacked structure 211 and a second isolation portion 2132 located in the insulating layer 212. The first isolation portion 2131 extends continuously along the x-direction, and the second isolation portion 2132 extends discontinuously along the x-direction. On a plane perpendicular to the z-direction, the sidewall of the first isolation portion 2131 is concave and convex. The material of the portion of the first gate line isolation structure 213 in contact with the stacked structure 211 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOx N y ) or any other suitable insulating material. In one embodiment, the first gate line isolation structure 213 may include polysilicon bodies 2133-1, 2133-2 and silicon oxide layers 2134-1, 2134-2 covering the sidewalls and bottoms of the polysilicon bodies 2133-1, 2133-2. For example, the first isolation portion 2131 may include a first polysilicon body 2133-1 and a first silicon oxide layer 2134-1 covering the sidewalls and bottom of the first polysilicon body 2133-1. The second isolation portion 2132 may include a second polysilicon body 2133-2 and a second silicon oxide layer 2134-2 covering the sidewalls of the second polysilicon body 2133-2. The first polysilicon body 2133-1 and the second polysilicon body 2133-2 are in contact with each other and form an integral structure, and the first silicon oxide layer 2134-1 and the second silicon oxide layer 2134-2 are in contact with each other and form an integral structure. The first gate line isolation structure 213 uses a material combination of silicon oxide (SiO 2 ) and polysilicon (poly-Si) to help optimize stress distribution.

[0054] In this embodiment, compared to the previous embodiment, the first isolation portion 2131 located in the stacked structure 211 and extending continuously along the x-direction can electrically isolate the stacked structure 211, allowing the stacked structures 211 located on both sides thereof to be individually controlled, thereby facilitating reduced operational control difficulty. The second isolation portion 2132 located in the insulating layer 212 and extending intermittently along the x-direction, as well as the first isolation portion 2131 having concave-convex sidewalls, both reinforce the stacked structure 211 and address the problem of tipping, thereby improving the stability and yield of the semiconductor structure 200. In addition, during the formation of the first gate line isolation structure 213, the continuously extending first isolation portion 2131 has a relatively uniform pattern, which can effectively alleviate the etching stress problem caused by the non-uniform pattern.

[0055] In some embodiments, as Figure 2BAs shown, in the z-direction, the first isolation portion 2131 includes a plurality of (e.g., two) sub-first isolation portions 21311 and 21312. For example, each of the sub-first isolation portions 21311 and 21312 extends continuously along the x-direction. For another example, each of the sub-first isolation portions 21311 and 21312 is connected to each other. In the semiconductor structure 200, along the negative z-direction, the size (e.g., width) of each of the sub-first isolation structures 21311 and 21312 in the y-direction decreases. For example, for the sub-first isolation portion 21311 closest to the second isolation portion 2132, the size (e.g., width) d2 of its end portion close to the second isolation portion 2132 in the y-direction is greater than the size (e.g., width) d3 of its end portion close to the other sub-first isolation portion 21312 in the y-direction.

[0056] It should be pointed out that Figure 2B The number of sub-first isolation portions 21311 and 21312 shown is merely an example. In other examples, the first isolation portion 2131 may include a greater number of sub-first isolation portions. Generally speaking, as the number of stacked layers in the stacked structure 211 increases, the manufacturing difficulty of the first isolation portion 2131 increases accordingly. By including multiple sub-first isolation portions 21311 and 21312 connected to each other in the z-direction, the manufacturing difficulty of the first isolation portion 2131 can be reduced overall.

[0057] In some embodiments, as Figure 2B As shown, the dimension (e.g., width) of the second isolation portion 2132 in the y direction decreases along the negative z-direction. For example, the dimension (e.g., width) d4 in the y direction of the end of the second isolation portion 2132 facing away from the first isolation portion 2131 is greater than the dimension (e.g., width) d1 in the y direction of the end of the second isolation portion 2132 closer to the first isolation portion 2131.

[0058] In some embodiments, as Figure 2B As shown, a dimension (e.g., width) d1 in the y-direction at the end of the second isolation portion 2132 in contact with the first isolation portion 2131 (e.g., a sub-first isolation portion 21311 closest to the second isolation portion 2132) is smaller than a dimension (e.g., width) d2 in the y-direction at the end of the first isolation portion 2131 (e.g., a sub-first isolation portion 21311 closest to the second isolation portion 2132) in contact with the second isolation portion 2132. The smaller width of the second isolation portion 2132 can reduce the planar footprint of the second isolation portion 2132 while providing reinforcement.

[0059] In some embodiments, again referring to Figure 2AThe semiconductor structure 200 may further include a channel structure 215 penetrating the stacked structure 211. For example, on a plane perpendicular to the z direction, a plurality of channel structures 215 may be arranged at intervals along the x direction and the y direction. Figure 2B The internal structure of the channel structure 215 is described with an example. Figure 2B As shown, the channel structure 215 may include a blocking layer 216, a charge trapping layer 217, a tunneling layer 218, and a channel layer 219, arranged sequentially from the outside to the inside. For example, the blocking layer 216, the charge trapping layer 217, the tunneling layer 218, and the channel layer 219 all penetrate the stacked structure 211, and the channel layer 219 protrudes from the stacked structure 211. The blocking layer 216, the charge trapping layer 217, and the tunneling layer 218 may be referred to as functional layers. For example, the materials of the blocking layer 216, the charge trapping layer 217, and the tunneling layer 218 may include silicon oxide (SiO2), silicon nitride (Si3O4), and silicon oxide (SiO2), respectively. The material of the channel layer 219 may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material.

[0060] In some embodiments, the portion of the channel structure 215 surrounded by a gate layer 2112 and a portion of the gate layer 2112 constitute a memory cell. Multiple memory cells are arranged in series along the extension direction of the channel structure 215 (e.g., the z-direction) to form a memory string and share the channel layer 219. The remaining portion of the gate layer 2112 can serve as a word line connecting multiple memory cells at the same height in different memory strings.

[0061] In some embodiments, as Figure 2B As shown, in the z-direction, the channel structure 215 may include multiple (e.g., two) sub-channel structures 2151 and 2152. For example, the sub-channel structures 2151 and 2152 are connected to each other. In the semiconductor structure 200, along the negative z-direction, the size (e.g., diameter) of each sub-channel structure 2151 and 2152 on a plane perpendicular to the z-direction decreases. Generally speaking, as the number of stacked layers of the stacked structure 211 increases, the processing difficulty of the channel structure 215 increases accordingly. By making the channel structure 215 include multiple sub-channel structures 2151 and 2152 connected to each other in the z-direction, the processing difficulty of the channel structure 215 can be reduced as a whole.

[0062] In some embodiments, the number of stacked layers penetrated by the multiple sub-channel structures 2151 and 2152 is the same as the number of stacked layers penetrated by the multiple sub-first isolation portions 21311 and 21312. For example, the number of stacked layers penetrated by the sub-channel structure 2151 closest to the second isolation portion 2132 (e.g., the number of dielectric layers 2111 and gate layers 2112) is the same as the number of stacked layers penetrated by the sub-first isolation portion 21311 closest to the second isolation portion 2132 (e.g., the number of dielectric layers 2111 and gate layers 2112). In this embodiment, some manufacturing processes (e.g., etching processes) for the sub-channel structures and sub-first isolation portions penetrating the same number of stacked layers can be performed in a single step, which is beneficial for improving manufacturing efficiency and reducing manufacturing costs.

[0063] In some embodiments, the semiconductor structure 200 may further include a semiconductor layer 214. The semiconductor layer 214 may be located on a side (e.g., a surface) of the stacked structure 211 facing away from the insulating layer 212. For example, the semiconductor layer 214 may extend laterally along the x-direction and the y-direction. The portion of the channel layer 219 protruding from the stacked structure 211 may be located in the semiconductor layer 214. For example, each channel layer 219 in the plurality of channel structures 215 may be located in the semiconductor layer 214. The material of the semiconductor layer 214 may include single crystal silicon (s-Si), polycrystalline silicon (poly-Si), amorphous silicon (α-Si), or any other suitable semiconductor material. When the material of the semiconductor layer 214 is the same as that of the channel layer 219, there is no obvious interface between the portion of the channel layer 219 located in the semiconductor layer 214 and the semiconductor layer 214.

[0064] In some embodiments, the semiconductor structure 200 may further include a trench connection structure 220. The trench connection structure 220 extends in the insulating layer 212 along the z-direction and is connected to the trench structure 215. For example, the trench connection structure 220 penetrates the insulating layer 212. The material of the trench connection structure 220 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polycrystalline silicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), or any other suitable conductive material. The trench connection structure 220 may be used to lead the trench structure 215 out of the z-direction.

[0065] Figures 3A to 3D It is a schematic top view of a first gate line isolation structure included in a semiconductor structure. Figure 3E is a cross-sectional schematic diagram of a second gate line isolation structure included in a semiconductor structure. For example, Figure 3E Can be along Figure 3A The cross-sectional view taken along line AA' is shown. To clearly illustrate the components in the semiconductor structure, Figures 3A to 3D The stacking structure and the insulating layer are omitted from illustration, wherein the relative positional relationship between the stacking structure and the insulating layer has been described above.

[0066] like Figure 3A and Figure 3E As shown, the semiconductor structure 300a may further include a second gate line isolation structure 321 that penetrates the stacked structure 311. The second gate line isolation structure 321 may extend continuously along the x-direction. For example, the second gate line isolation structure 321 may further extend into the insulating layer 312 along the z-direction (not shown). The material of the portion of the second gate line isolation structure 321 that contacts the stacked structure 311 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials. A plurality of (for example, three) second gate line isolation structures 321 are arranged at intervals along the x-direction, and a first gate line isolation structure 313 is located between adjacent second gate line isolation structures 321. The first isolation portion in the second gate line isolation structure 321 and the first gate line isolation structure 313 can divide the stacked structure into storage blocks 301. In this embodiment, since the first isolation portion in the second gate line isolation structure 321 and the first gate line isolation structure 313 both extend continuously along the x-direction, the gate layer in the stacked structure between the second gate line isolation structure 321 and the first gate line isolation structure 313 can extend continuously and be electrically isolated from the gate layer in the stacked structure outside the second gate line isolation structure 321 and the first gate line isolation structure 313. The gate layer in each storage block 301 can be controlled individually, which can break through the limitation of the number of stacked layers on the difficulty of control operation.

[0067] like Figure 3B As shown, multiple (e.g., two) second gate line isolation structures 321 are arranged at intervals along the x-direction, and two first gate line isolation structures 313 arranged at intervals along the x-direction are located between adjacent second gate line isolation structures 321. The second gate line isolation structures 321 and the first isolation portions in the first gate line isolation structures 313 can divide the stacked structure into memory blocks 301, or the first isolation portions in adjacent first gate line isolation structures 313 can also divide the stacked structure into memory blocks 301. In this embodiment, not only can the limitation of the number of stacked layers on the difficulty of control operations be overcome, but the structural stability of the semiconductor structure 300b can also be improved by increasing the number of first gate line isolation structures 313.

[0068] like Figure 3CAs shown, multiple (e.g., two) second gate line isolation structures 321 are arranged at intervals along the x-direction, and three first gate line isolation structures 313 are arranged at intervals along the x-direction and located between adjacent second gate line isolation structures 321. The second gate line isolation structures 321 and the first isolation portions in the first gate line isolation structures 313 can divide the stacked structure into memory blocks 301, or the first isolation portions in adjacent first gate line isolation structures 313 can also divide the stacked structure into memory blocks 301. In this embodiment, not only can the limitation of the number of stacked layers on the difficulty of control operations be overcome, but the structural stability of the semiconductor structure 300c can also be further improved by increasing the number of first gate line isolation structures 313.

[0069] It should be pointed out that Figures 3A to 3C The number of second gate line isolation structures 321 and the number of first gate line isolation structures 313 between adjacent second gate line isolation structures 321 are shown for illustrative purposes only. In other examples, the number of first gate line isolation structures 313 between adjacent second gate line isolation structures 321 may be greater (e.g., greater than three). As the number of first gate line isolation structures between adjacent second gate line isolation structures increases, the overall stability and yield of the semiconductor structure improve.

[0070] like Figure 3D As shown, a plurality of first gate line isolation structures 313 are arranged at intervals along the x direction, and the first isolation portions of adjacent first gate line isolation structures 313 divide the stacked structure into memory blocks 301. In this embodiment, the semiconductor structure 300d does not include a second gate line isolation structure 321 (refer to FIG. Figures 3A to 3C ), the memory blocks 301 are divided by the first isolation portions in the first gate line isolation structures 313. This not only overcomes the limitation of the number of stacked layers on the difficulty of control operations, but also further improves the structural stability of the semiconductor structure 300d. Optionally, the second isolation portions in adjacent first gate line isolation structures 313 are staggered to optimize structural stress. For example, the discontinuities 302 in the second isolation portions in adjacent first gate line isolation structures 313 are non-collinearly arranged in the x-direction.

[0071] Figure 4 1 is a schematic planar cross-sectional view of a semiconductor structure provided by another embodiment of the present application. For the purpose of brevity, the present application will not repeat the same contents as the previous embodiment.

[0072] like Figure 4As shown, the semiconductor structure 400 includes a stacked structure 411, an insulating layer 412, and a first gate line isolation structure 413. The insulating layer 412 is located on one side (e.g., the surface) of the stacked structure 411 in the z-direction. The first gate line isolation structure 413 penetrates the stacked structure 411 and the insulating layer 412. A first isolation portion 4131 of the first gate line isolation structure 413, located in the stacked structure 411, extends continuously along the x-direction, and a second isolation portion 4132 of the first gate line isolation structure 413, located in the insulating layer 412, extends discontinuously along the x-direction. On a plane perpendicular to the z-direction, the sidewalls of the first isolation portion 4131 have a concave-convex shape (not shown).

[0073] In some embodiments, the semiconductor structure 400 may further include a channel structure 415 and a channel connection structure 420. The channel structure 415 may extend through the stacked structure 411. The channel connection structure 420 may extend in the z-direction in the insulating layer 412 and be connected to the channel structure 415. For example, a separation distance d5 is defined between an end surface of the channel structure connection 420 facing away from the channel structure 415 and a surface of the insulating layer 412 facing away from the stacked structure 411. In other words, a separation distance is defined between an end surface of the channel structure connection 420 facing away from the channel structure 415 and a surface of the second isolation portion 4132 facing away from the first isolation portion 4131. For example, the second isolation portion 4132 may be formed after the channel connection structure 420 is formed, which helps increase process flexibility in forming the second isolation portion 4132 and the channel connection structure 420.

[0074] Some embodiments of the present application also provide a method for manufacturing a semiconductor structure. Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. Figure 5 As shown, a method 500 for manufacturing a semiconductor structure (hereinafter referred to as manufacturing method 500 ) may include the following steps.

[0075] S510 , forming a first slit portion penetrating the initial stacked structure, wherein the first slit portion continuously extends along a first direction, and a sidewall thereof has a concave-convex shape.

[0076] S520 , forming an insulating layer on one side of the initial stacking structure in the stacking direction.

[0077] S530 , forming a second slit portion penetrating the insulating layer and communicating with the first slit portion, wherein the second slit portion extends discontinuously along the first direction.

[0078] S540 , forming a first gate line isolation structure in the first slit portion and the second slit portion.

[0079] According to the manufacturing method of the semiconductor structure provided by this embodiment, by forming a first slit portion that penetrates the initial stacking structure and extends continuously, it can be used to electrically isolate the stacking structure in subsequent process engineering, so that the stacking structures located on both sides thereof can be controlled separately, thereby helping to reduce the difficulty of operation control. By forming a first slit portion with a concave-convex sidewall and forming a second slit portion that penetrates the insulating layer and extends intermittently, both play a role in reinforcing the initial stacking structure and can deal with the problem of tipping, thereby improving the stability and yield of the semiconductor structure after manufacturing is completed. In addition, the continuously extending first slit portion has a relatively uniform pattern, which can effectively alleviate the etching stress problem caused by the non-uniform pattern.

[0080] 6A to 13B Schematic diagrams of the cross section and top view of the semiconductor structure during the manufacturing process provided by the embodiment of the present application. For example, 6A to 13B Can be used to form Figure 2A and Figure 2B The semiconductor structure 200 is shown. 6A to 13B The manufacturing method including steps S510 to S540 is exemplarily described.

[0081] S510

[0082] Figure 6A and Figure 6B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 600 a after the channel hole 615 ′ and the plurality of holes 625 are formed. Figure 7A and Figure 7B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 600 b after the first gap portion 622 is formed.

[0083] In some embodiments, as Figure 6A and Figure 6B As shown, the initial stacked structure 611' may include alternating dielectric layers 6111 and sacrificial layers 6113. For example, the dielectric layers 6111 and the sacrificial layers 6113 may be alternately formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the dielectric layer 6111 and the material of the sacrificial layer 6113 are different, so that they have different etching selectivities with respect to the same etching material. For example, the material of the dielectric layer 6111 may include silicon oxide (SiO2), and the material of the sacrificial layer 6113 may include silicon nitride (Si3N4).

[0084] In some embodiments, the initial stacked structure 611' may be formed on one side of a substrate 628. For example, the substrate 628 may include a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). For another example, the semiconductor substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. For example, during the manufacturing process, the substrate 628 may serve as a support and may be removed in subsequent processes.

[0085] In some embodiments, continue with reference to Figure 6A and Figure 6B , an etching process (eg, dry etching and / or wet etching) may be used to form a plurality of holes 625 that penetrate the initial stacked structure 611' and are spaced apart along the x-direction. For example, the plurality of holes 625 are located at Figure 6B Optionally, during the formation of the plurality of holes 625, a channel hole 615' penetrating the initial stacked structure 611' can be formed using the same mask and in the same etching process to reduce process costs. For example, the channel hole 615' can extend into the substrate 628.

[0086] In some embodiments, the channel hole 615' may include a plurality of sub-channel holes 6151', 6152' connected to each other in the z-direction. The hole 625 may include a plurality of sub-holes 6251, 6252 connected to each other in the z-direction. For example, first, a sub-initial stacking structure 6114' may be formed, and the sub-channel hole 6152' and the sub-hole 6252 passing through the sub-initial stacking structure 6114' may be formed using the same mask. Optionally, a sacrificial material may be filled in the sub-channel hole 6152' and the sub-hole 6252. Next, another sub-initial stacking structure 6115' covering the sub-initial stacking structure 6114' and the sacrificial material in the sub-channel hole 6152' and the sub-hole 6252 may be formed. Then, the sub-channel hole 6151' and the sub-hole 6251 passing through the sub-initial stacking structure 6115' may be formed using the same mask. The sub-channel holes 6151' and 6152' are at least partially aligned, and the sub-holes 6251 and 6252 are at least partially aligned. Subsequently, the sacrificial material filled in the sub-channel hole 6152' and the sub-hole 6252 can be removed to form Figure 6A and Figure 6B The channel hole 615' and the hole 625 are shown. It should be noted that the sub-stack structure and the sub-channel holes and sub-holes can be repeatedly formed according to the above process method until a predetermined number of sub-channel holes and sub-holes are formed. The present application does not limit the number of sub-channel holes contained in each channel hole and the number of sub-holes contained in each hole. In this embodiment, when the number of stacked layers of the stack structure is large, the process method of forming the channel holes and holes by multi-step etching can reduce the process difficulty.

[0087] In some embodiments, as Figures 6A to 7B , a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially form a blocking layer 616, a charge trapping layer 617, a tunneling layer 618 and a channel layer 619 on the inner wall of the channel hole 615'. Optionally, an insulating column 626 may be formed inside the channel layer 619 and close to the substrate 628. The material of the insulating column 626 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Optionally, a channel plug 629 may be formed on the inner side of the channel layer 619 and away from the substrate 628. The channel plug 629 may be in contact with the channel layer 619 and the insulating pillar 626. The material of the channel plug 629 may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material. When the channel layer 619 and the channel plug 629 are made of the same material, the two are an integrated structure and there is no obvious interface.

[0088] In some embodiments, continue with reference to Figures 6A to 7B , the initial stacked structure 611' can be etched (e.g., wet-etched) using the plurality of holes 625, so that the plurality of holes 625 are connected to each other to form a first slit portion 622. Thus, the first slit portion 622 can extend continuously along the x-direction, and its sidewalls have a concave-convex shape. Optionally, before etching the initial stacked structure 611' using the plurality of holes 625, an oxide layer 624 can be formed at the bottom of the plurality of holes 625 to reduce the risk of damage to the substrate 628. In this embodiment, forming the first slit portion 622 with a concave-convex sidewall can effectively relieve etching stress and reduce etching difficulty.

[0089] Figure 8A and Figure 8B 6 and 7 are schematic cross-sectional views and top views of the intermediate structure 600c after forming the sacrificial material layer 627. Figures 7A to 8B As shown, before performing step S520, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a sacrificial material layer 627 in the first slit portion 622. The sacrificial material layer 627 may include polycrystalline silicon (poly-Si), amorphous silicon (α-Si), carbon (C), or any other suitable easily removable material.

[0090] S520

[0091] Figure 9A and Figure 9B 6 and 7 are schematic cross-sectional views and top views of the intermediate structure 600d after the insulating layer 612 is formed. Figures 8A to 9B As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form an insulating layer 612 on one side of the initial stacked structure 611' in the z direction. For example, the insulating layer 612 covers the initial stacked structure 611' and the sacrificial material layer 627. The insulating layer 612 may extend laterally along the x-direction and the y-direction.

[0092] S530

[0093] Figure 10A and Figure 10B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 600e after the second gap portion 623 is formed. Figure 11A and Figure 11B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 600 f after the sacrificial material layer is removed. Figure 12A and Figure 12B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 600g after the gate layer 6112 is formed.

[0094] In some embodiments, as 9A to 10B As shown, an etching (eg, wet etching and / or dry etching) process may be used to form a second slit portion 623 penetrating the insulating layer 612 to the sacrificial material layer 627. The second slit portion 623 extends discontinuously along the x-direction. In other words, as Figure 10B As shown, the insulating layer 612 at the discontinuity 602 of the second slit portion 623 is not etched. For example, the dimension (e.g., width) d1 in the y-direction at the end of the second slit portion 623 in contact with the sacrificial material layer 627 is smaller than the dimension (e.g., width) d2 in the y-direction at the end of the sacrificial material layer 627 in contact with the second slit portion 623. The smaller dimension of the second slit portion 623 in the y-direction can provide reinforcement while reducing the occupied area.

[0095] In some embodiments, as Figures 10A to 11B As shown, after forming the second slit portion 623 , an etching (eg, wet etching) process may be used to remove the sacrificial material layer 627 through the second slit portion 623 , so that the first slit portion 622 is exposed again and communicates with the second slit portion 623 .

[0096] In some embodiments, as Figures 11A to 12BAs shown, the sacrificial layer 6113 in the initial stacked structure 611' can be replaced with a gate layer 6112 using a first slit portion 622 and a second slit portion 623. For example, an etching (e.g., wet etching) process can be used to remove the sacrificial layer 6113 in the initial stacked structure 611' and form a plurality of gaps (not shown). Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a plurality of gate layers 6112 in the plurality of gaps. After the above-mentioned process, the initial stacked structure 611' can be converted into a stacked structure 611. In this embodiment, during the process of removing the sacrificial layer 6113 in the initial stacked structure 611' and forming the plurality of gaps, the second slit portion 623 extends discontinuously along the x-direction, that is, the insulating layer 612 extends continuously on both sides of the second slit portion 623 across the discontinuity 602, which can play a reinforcing role and improve the tipping problem.

[0097] S540

[0098] Figure 13A and Figure 13B 6 and 7 are respectively a schematic plan view and a schematic top view of the intermediate structure 600h after forming the first gate line isolation structure 613. Figures 12A to 13B As shown, a silicon oxide layer 6134 can be formed on the inner wall of the first slit portion 622 and the second slit portion 623 connected to each other by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Furthermore, a polysilicon body 6133 is formed on the inner side of the silicon oxide layer 6134. The silicon oxide layer 6134 and the polysilicon body 6133 together constitute the first gate line isolation structure 613. This material combination helps to optimize structural stress. In other embodiments, silicon oxide (SiO2) can be directly filled in the first slit portion 622 and the second slit portion 623 connected to each other, or any other appropriate insulating material can be first formed on the inner wall of the first slit portion 622 and the second slit portion 623 connected to each other and then filled with other materials on the inner side of the insulating material layer. This application does not impose any specific restrictions on this.

[0099] In some embodiments, the manufacturing method 500 may further include the following steps. For example, Figure 10A and Figure 10B After the second slit portion 623 is formed, a channel connection structure 220 (see FIG. 2 ) penetrating the insulating layer 612 to the channel structure 615 may be formed. Figure 2B ). The present application does not limit the specific process sequence for forming the trench connection structure 220. For example, Figure 13A and Figure 13BAs shown, the substrate 628 can be removed and the portion of the blocking layer 616, the charge trapping layer 617, and the tunneling layer 618 protruding from the stacked structure 611 can be removed to expose the channel layer 619. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a semiconductor layer 214 connected to (e.g., in contact with) the channel layer 619 on the side of the stacked structure 611 away from the insulating layer 612 (see FIG. Figure 2B ).

[0100] Figures 14A to 17B Schematic diagrams of a cross-section and a top view of a semiconductor structure during the manufacturing process provided by another embodiment of the present application. For example, Figures 14A to 17B Can be used to form Figure 4 The semiconductor structure 400 is shown. In this embodiment, step S510 is the same as that described in the previous embodiment, and this application will not repeat it here. In addition, for the purpose of concise description, the other steps 520 to S540 are the same as those in the previous embodiment, and this application will not repeat them here. Figures 14A to 17B The manufacturing method 500 including steps S520 to S540 is exemplarily described.

[0101] S520

[0102] Figure 14A and Figure 14B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 700 a after the first insulating portion 7121 is formed. Figure 15A and Figure 15B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 700 b after the second insulating portion 7122 is formed.

[0103] In some embodiments, in forming Figure 8A and Figure 8B After the intermediate structure 600c is shown, Figure 14A 14 , a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a first insulating portion 7121 on one side of the initial stacked structure 711′ in the z-direction. For example, the first insulating portion 7121 covers the initial stacked structure 711′ and the sacrificial material layer 727. The first insulating portion 7121 can extend laterally along the x-direction and the y-direction.

[0104] In some embodiments, a channel connection structure 720 may be formed that passes through the first insulating portion 7121 to the channel structure 715. For example, an etching process (e.g., dry etching and / or wet etching) may be used to form a channel connection hole (corresponding to the outer contour of the channel connection structure 720) that passes through the first insulating portion 7121 to the channel structure 715, and a conductive material may be filled in the channel connection hole to form the channel connection structure 720.

[0105] In some embodiments, as Figures 14A to 15B As shown, a second insulating portion 7122 is formed on the surface of the first insulating portion 7121 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the second insulating portion 7122 covers the trench connection structure 720. The second insulating portion 7122 may extend laterally along the x-direction and the y-direction. The first insulating portion 7121 and the second insulating portion 7122 together constitute the insulating layer 712. When the material of the first insulating portion 7121 and the second insulating portion 7122 is the same, no obvious interface exists between the two.

[0106] S530

[0107] In some embodiments, continue with reference to Figure 15A and Figure 15B An etching (eg, wet etching and / or dry etching) process may be used to form a second slit portion 723 penetrating the insulating layer 712 to the sacrificial material layer 727. The second slit portion 723 extends discontinuously along the x-direction.

[0108] Figure 16A and Figure 16B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 700 c after the sacrificial material layer is removed. Figure 17A and Figure 17B 1 and 2 are respectively a schematic plan cross-sectional view and a schematic top view of the intermediate structure 700 d after the gate layer 7112 and the first gate line isolation structure 713 are formed.

[0109] In some embodiments, as Figures 15A to 16B As shown, after forming the second slit portion 723, an etching process (e.g., wet etching) can be used to remove the sacrificial material layer 727 through the second slit portion 723, so that the first slit portion 722 is exposed again and connected to the second slit portion 723. Optionally, the bottom of the first slit portion 722 has an oxide layer 724.

[0110] In some embodiments, as 16A to 17BAs shown, the sacrificial layer 7113 in the initial stacked structure 711' can be replaced with the gate layer 7112 using the first slit portion 722 and the second slit portion 723. After the above process, the initial stacked structure 711' can be converted into the stacked structure 711. In this embodiment, the second slit portion 723 extends discontinuously along the x-direction, that is, the insulating layer 712 extends continuously on both sides of the second slit portion 723 across the discontinuity 702, thereby providing reinforcement and improving the tilting problem.

[0111] S540

[0112] In some embodiments, continue with reference to 16A to 17B A silicon oxide layer 7134 can be formed on the inner walls of the interconnected first slit portion 722 and second slit portion 723 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Furthermore, a polysilicon body 7133 is formed inside the silicon oxide layer 7134. The silicon oxide layer 7134 and the polysilicon body 7133 together constitute the first gate line isolation structure 713. This material combination helps optimize structural stress.

[0113] In some embodiments, the manufacturing method 500 may further include the following steps. For example, Figure 17A and Figure 17B As shown, the substrate 728 can be removed and the portion of the blocking layer 716, the charge trapping layer 717, and the tunneling layer 718 protruding from the stack structure 711 can be removed to expose the channel layer 719. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a semiconductor layer 414 connected to (e.g., in contact with) the channel layer 719 on the side of the stack structure 711 away from the insulating layer 712 (see FIG. Figure 4 ).

[0114] An embodiment of the present application also provides a memory system. Figure 18 is a block diagram of a system with a memory system provided in an embodiment of the present application. Figure 19A and Figure 19B Schematic diagram of a memory system provided in an embodiment of the present application.

[0115] like Figure 18 As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 18As shown, system 11 may include a host 18 and a memory system 12 having one or more memories 14 and a controller 16. Host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 18 may be configured to send or receive data to or from memory 14.

[0116] The memory 14 may include the semiconductor structure described in any embodiment of the present application, for example, Figure 2A and 2B The semiconductor structure 200 or Figure 4 4. The semiconductor structure 400 is shown. In some embodiments, the memory 14 may further include peripheral circuitry. For example, the peripheral circuitry may be coupled to the semiconductor structure. The peripheral circuitry may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating operation of the memory cell array in the semiconductor structure. For example, the peripheral circuitry may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor).

[0117] According to some embodiments, controller 16 is coupled to memory 14 and host 18 and is configured to control memory 14. Controller 16 can manage data stored in memory 14 and communicate with host 18. In some embodiments, controller 16 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 16 is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Controller 16 can be configured to control operations of memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the memory 14, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 16 is further configured to process error correction code (ECC) associated with data read from or written to the memory 14. Any other appropriate functions may also be performed by the controller 16, such as formatting the memory 14. The controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with the external device via at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-Express, PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, and the like.

[0118] The controller 16 and the one or more memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of final electronic products. Figure 19AIn one example shown in FIG, the controller 16 and the single memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 may further include a memory card that connects the memory card 22 to a host (e.g., Figure 18 The host 18 in the memory card connector 24 is coupled. Figure 19B In another example shown in FIG, the controller 16 and the plurality of memories 14 may be integrated into an SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 18 In some embodiments, the SSD 26 has a storage capacity and / or an operating speed that is higher than that of the memory card 22.

[0119] The above description is merely an embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that include: A stacking structure having a stacking direction; an insulating layer, located on one side of the stacking structure in the stacking direction; as well as a first gate line isolation structure, extending through the stacked structure and the insulating layer, wherein a first isolation portion of the first gate line isolation structure located in the stacked structure extends continuously along a first direction, and a sidewall of the first isolation portion is concave-convex in a plane perpendicular to the stacking direction; and a second isolation portion of the first gate line isolation structure located in the insulating layer extends discontinuously along the first direction; Wherein, the first direction intersects with the stacking direction.

2. The semiconductor structure according to claim 1, wherein In the stacking direction, the first isolation portion includes a plurality of sub-first isolation portions, wherein sizes of the sub-first isolation portions in the second direction decrease gradually along a direction opposite to the stacking direction; The first direction, the second direction and the stacking direction intersect with each other.

3. The semiconductor structure according to claim 2, wherein: In a direction opposite to the stacking direction, a size of the second insulating portion in the second direction decreases.

4. The semiconductor structure according to any one of claims 1 to 3, wherein: A dimension of an end portion of the second isolating portion in contact with the first isolating portion in the second direction is smaller than a dimension of an end portion of the first isolating portion in contact with the second isolating portion in the second direction.

5. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: a channel structure penetrating the stacked structure; and A channel connection structure extends along the stacking direction in at least a portion of the insulating layer and is connected to the channel structure. The semiconductor structure according to claim 5 , wherein: The channel structure includes multiple sub-channel structures in the stacking direction, and the sizes of the sub-channel structures on the plane perpendicular to the stacking direction decrease along the direction opposite to the stacking structure, wherein the number of stacking layers penetrated by the multiple sub-channel structures is respectively the same as the number of stacking layers penetrated by the multiple sub-first isolation parts.

7. The semiconductor structure according to claim 1, wherein: A plurality of first gate line isolation structures are arranged along a second direction, and the first isolation portions in adjacent first gate line isolation structures divide the stacked structure into memory blocks; The first direction, the second direction and the stacking direction intersect with each other.

8. The semiconductor structure according to claim 7, wherein: The second isolation portions in adjacent first gate line isolation structures are staggered.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a second gate line isolation structure, wherein the second gate line isolation structure passes through the stacked structure and extends continuously along the first direction; A plurality of second gate line isolation structures are arranged along a second direction, and at least one first gate line isolation structure is located between adjacent second gate line isolation structures, wherein the second gate line isolation structure and the first isolation portion in the first gate line isolation structure divide the stacked structure into memory blocks, or the first isolation portion in the adjacent first gate line isolation structure divides the stacked structure into the memory blocks; The first direction, the second direction and the stacking direction intersect with each other.

10. The semiconductor structure according to claim 1, wherein The first gate line isolation structure includes a polysilicon body and a silicon oxide layer covering the sidewalls and the bottom of the polysilicon body.

11. A memory system, characterized in that: include: A memory comprising the semiconductor structure according to any one of claims 1 to 10; as well as The controller is coupled to the memory and is used to control the memory to store data.

12. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first slit portion penetrating the initial stacked structure, wherein the first slit portion continuously extends along a first direction and has a sidewall in a concave-convex shape; forming an insulating layer on one side of the initial stacking structure in a stacking direction thereof; forming a second slit portion penetrating the insulating layer and communicating with the first slit portion, wherein the second slit portion extends discontinuously along the first direction; and forming a first gate line isolation structure in the first slit portion and the second slit portion; Wherein, the first direction and the stacking direction intersect.

13. The manufacturing method according to claim 12, wherein: Before forming an insulating layer on one side of the initial stacking structure in the stacking direction, the manufacturing method further includes: forming a sacrificial material layer in the first gap portion; Wherein, forming an insulating layer on one side of the initial stacking structure in the stacking direction thereof comprises: forming the insulating layer covering the initial stacked structure and the sacrificial material layer; After forming the second slit portion penetrating the insulating layer and communicating with the first slit portion, the manufacturing method further includes: The sacrificial material layer in the first slit portion is removed.

14. The manufacturing method according to claim 13, wherein: A dimension of the end portion of the second gap portion in contact with the sacrificial material layer in the second direction is smaller than a dimension of the end portion of the sacrificial material layer in contact with the second gap portion in the second direction, wherein the first direction, the second direction and the stacking direction intersect with each other.

15. The manufacturing method according to claim 13, wherein: The initial stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the manufacturing method further includes: The sacrificial layer in the initial stacked structure is replaced with a gate layer by utilizing the first slit portion and the second slit portion.

16. The manufacturing method according to claim 12, wherein: Forming a first gap portion penetrating the initial stacked structure includes: forming a plurality of holes penetrating the initial stacked structure and arranged at intervals along the first direction; The initial stack structure is etched using the plurality of holes so that the plurality of holes are connected to each other to form the first slit portion.

17. The manufacturing method according to claim 16, wherein: The manufacturing method further comprises: A channel hole is formed through the initial stacked structure, wherein the channel hole and the plurality of holes are formed using a same mask.

18. The manufacturing method according to claim 17, wherein: The manufacturing method further comprises: forming a channel structure in the channel hole; and A trench connection structure extending along the stacking direction is formed in at least a portion of the insulating layer.

19. The manufacturing method according to claim 18, wherein: Forming an insulating layer on one side of the initial stacking structure in a stacking direction thereof comprises: forming a first insulating portion of the insulating layer on one side of the initial stack structure in a stacking direction thereof; and forming a second insulating portion of the insulating layer on a surface of the first insulating portion; The trench connection structure formed in at least a portion of the insulating layer and extending along the stacking direction includes: The trench connection structure is formed to penetrate the first insulating portion.

20. The manufacturing method according to claim 12, wherein: Forming a first gate line isolation structure in the first slit portion and the second slit portion includes: forming a silicon oxide layer on inner walls of the first slit portion and the second slit portion; and A polysilicon body is formed inside the silicon oxide layer.

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