Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises a first substrate comprising a plurality of first steps; the first laminated structure comprises first dielectric layers and first gate layers which are alternately stacked, the first laminated structure covers the first step and extends on one side of the first substrate in the first direction, the first surface, away from the first substrate in the stacking direction of the first laminated structure, of the first laminated structure is located at the same height, and the first direction intersects with the stacking direction; and the first contact structure extends to the first gate layer closest to the first surface on the first step along a second direction opposite to the stacking direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for manufacturing the semiconductor structure, a memory, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the demand for higher storage density in semiconductor structures, such as three-dimensional semiconductor memory devices, is increasing. However, as the number of stacked layers in a semiconductor structure increases, the process for forming the contact structures used to connect the gate layers in different stacks becomes increasingly difficult, which can lead to a decrease in the overall performance of the semiconductor structure. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a semiconductor structure. The semiconductor structure includes: a first substrate including a plurality of first steps; a first stacked structure including alternating first dielectric layers and first gate layers, covering the first steps and extending along a first direction on one side of the first substrate, wherein portions of the first stacked structure that are away from a first surface of the first substrate along a stacking direction of the first stacked structure are located at the same height, and the first direction intersects the stacking direction; and a first contact structure extending along a second direction opposite to the stacking direction to the first gate layer closest to the first surface on the first step.

[0005] In one embodiment, the plurality of first contact structures extend along the second direction respectively to the first gate layer closest to the first surface on the plurality of first steps.

[0006] In one embodiment, the first gate layer in the plurality of different stacks of the first stacked structure is located on the first surface, wherein the plurality of first contact structures respectively extend to the first gate layer in the plurality of different stacks located on the first surface.

[0007] In one embodiment, the semiconductor structure further includes: a preset layer covering the first substrate and extending along the first direction on one side of the first substrate, wherein the highest portion of the preset layer covering the first substrate is located on the first surface, and the first stacked structure is located on the surface of the remaining portion of the preset layer, wherein the forming material of the preset layer is different from the forming material of the first dielectric layer and the first gate layer.

[0008] In one embodiment, the semiconductor structure further includes: a second substrate, located on one side of the first surface, including a plurality of second steps, wherein the second steps are spaced apart from the first steps along the first direction; a second stacked structure, including a second dielectric layer and a second gate layer alternately stacked along the stacking direction, covering the second steps and extending along the first direction on one side of the second substrate, wherein the second surface of the second stacked structure away from the second substrate along the stacking direction is located at the same height; and a second contact structure, extending along the second direction to the second gate layer closest to the second surface on the second step.

[0009] In one embodiment, the first contact structure penetrates the second substrate along the second direction and extends to the first gate layer on the first step closest to the first surface.

[0010] In one embodiment, the plurality of second contact structures extend along the second direction respectively to the second gate layer closest to the second surface on the plurality of second stair steps.

[0011] In one embodiment, the second gate layer in multiple different stacks of the second stacked structure is located on the second surface, wherein the multiple second contact structures respectively extend to the second gate layer in multiple different stacks located on the second surface.

[0012] In one embodiment, the material of the first substrate and the first dielectric layer includes oxide; the material of the first gate layer and the first contact structure includes metal; and the material of the predetermined layer includes polysilicon.

[0013] In one embodiment, the multiple first step steps include: a first sub-step, a portion extending along the first direction away from the first surface along the stacking direction and close to the first stacking structure along the first direction; and a plurality of second sub-steps adjacent to the first sub-steps; wherein the thickness of the first sub-step includes the thickness of the preset layer and the thickness of at least one stack; and the thickness of the second sub-step includes the thickness of at least one stack.

[0014] Another aspect of the present application provides a method for manufacturing a semiconductor structure. The method includes: forming an initial first stacked structure covering a plurality of first steps on a first substrate and extending along a first direction on one side of the first substrate, wherein the initial first stacked structure includes alternating first dielectric layers and first sacrificial layers, a portion of the initial first stacked structure covering the first steps and a portion of the initial first stacked structure extending along the first direction on one side of the first substrate having a height difference along the stacking direction of the initial first stacked structure, and the first direction intersects the stacking direction; removing a portion of the initial first stacked structure along a second direction opposite to the stacking direction, so that the remaining first surface of the initial first stacked structure away from the first substrate along the stacking direction is at the same height; replacing the first sacrificial layer with a first gate layer; and forming a first contact structure extending along the second direction to the first gate layer closest to the first surface on the first step.

[0015] In one embodiment, the semiconductor structure includes a plurality of first contact structures, wherein forming the first contact structure includes: forming a plurality of first contact structures extending along the second direction to the first gate layer closest to the first surface on the plurality of first steps.

[0016] In one embodiment, removing a portion of the initial first stacked structure includes: removing a portion of the initial first stacked structure along the second direction so that the first surfaces of the remaining initial first stacked structures are located at the same height, and exposing the first sacrificial layers located in different stacks in the remaining initial first stacked structure to the first surface.

[0017] In one embodiment, an initial first stacked structure is formed that includes a plurality of first step steps covering a first substrate and extending along a first direction on one side of the first substrate, including: forming a preset layer covering the first substrate and extending along the first direction on one side of the first substrate; and forming the initial first stacked structure on the surface of the preset layer.

[0018] In one embodiment, the portion of the preset layer covering the highest point of the first substrate is located on the first surface, and a portion of the initial first stacked structure is removed along the second direction, comprising: removing a portion of the initial first stacked structure along the second direction to expose the portion of the preset layer covering the highest point of the first substrate, and making the first surface of the remaining initial first stacked structure at the same height, wherein the first sacrificial layer located in different stacks in the remaining initial first stacked structure is exposed to the first surface.

[0019] In one embodiment, removing a portion of the initial first stacked structure along the second direction includes: removing a portion of the initial first stacked structure along the second direction to expose the portion of the preset layer covering the highest point of the first substrate, and making the first surface of the remaining initial first stacked structure at the same height, wherein the first dielectric layers located in different stacks in the remaining initial first stacked structure are exposed; and removing the exposed first dielectric layer to expose the first sacrificial layer located in different stacks, wherein the exposed first sacrificial layer is located at the first surface.

[0020] In one embodiment, the method further includes: forming a second substrate having a plurality of second steps on one side of the first surface, wherein the second steps are spaced apart from the first steps along the first direction; forming an initial second stacked structure covering the plurality of second steps and extending along the first direction on one side of the second substrate, wherein the initial second stacked structure includes a second dielectric layer and a second sacrificial layer alternately stacked along the stacking direction, and a portion of the initial second stacked structure covering the second steps and a portion of the initial second stacked structure extending along the first direction on one side of the second substrate have a height difference along the stacking direction; and removing a portion of the initial second stacked structure along the second direction so that the remaining initial second stacked structure is located at the same height along the stacking direction away from the second surface of the second substrate; wherein replacing the first sacrificial layer with the first gate layer includes: replacing the first sacrificial layer and the second sacrificial layer with the first gate layer and the second gate layer, respectively.

[0021] In one embodiment, forming a first contact structure of the first gate layer extending along the second direction to the first step closest to the first surface includes: forming a first contact structure of the first gate layer extending along the second direction through the second substrate and extending to the first step closest to the first surface.

[0022] In one embodiment, the method further includes forming a second contact structure extending along the second direction to a portion of the second gate layer closest to the second surface on the exposed second step.

[0023] In one embodiment, the method further includes: removing a portion of an initial first substrate to form the first substrate having a plurality of first step steps.

[0024] On the other hand, the present application provides a memory, which includes: a memory cell array including the semiconductor structure as described above; and a peripheral circuit coupled to the memory cell array.

[0025] On the other hand, the present application provides a storage system, which includes at least one memory; and a controller coupled to the memory and configured to control the memory to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0027] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0028] Figure 2 is a schematic structural diagram of forming a base and an initial first substrate according to an exemplary embodiment of the present application;

[0029] Figure 3 is a schematic structural diagram of forming a first substrate according to an exemplary embodiment of the present application;

[0030] Figure 4 is a schematic structural diagram of forming an initial first stacked structure according to an exemplary embodiment of the present application;

[0031] Figure 5 yes Figure 4 A magnified view of some structures in ;

[0032] Figure 6 is a schematic structural diagram after a portion of the initial first stacked structure is removed according to an exemplary embodiment of the present application;

[0033] Figure 7 is a schematic structural diagram of forming a second substrate and an initial second stacked structure according to an exemplary embodiment of the present application;

[0034] Figure 8 yes Figure 7 A magnified view of some structures in ;

[0035] Figure 9 is a schematic structural diagram after a portion of the initial second stacked structure is removed according to an exemplary embodiment of the present application;

[0036] Figure 10 is a schematic diagram of a structure for forming a channel hole according to an exemplary embodiment of the present application;

[0037] Figure 11 is a schematic structural diagram of forming a first gate layer, a second gate layer and a channel structure according to an exemplary embodiment of the present application;

[0038] Figure 12is a schematic structural diagram of forming a first contact structure according to an exemplary embodiment of the present application;

[0039] Figure 13 is a schematic structural diagram of forming a second contact structure and a lead-out structure according to an exemplary embodiment of the present application;

[0040] Figure 14 is a schematic block diagram of a memory according to an exemplary embodiment of the present application;

[0041] Figure 15 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0042] Figure 16A and Figure 16B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way.

[0044] It should be noted that in this specification, the terms "first," "second," "third," etc., are used solely to distinguish one feature from another and do not limit the features, and in particular do not indicate any order of precedence. Therefore, without departing from the teachings of this application, the first substrate discussed in this application may also be referred to as the second substrate, the first stacked structure may also be referred to as the second stacked structure, and vice versa.

[0045] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0046] In addition, in this document, when describing that one part is located "on" another part, the meaning of "on...", "above..." and "over..." should be interpreted in the broadest manner, so that "on..." means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above..." or "over..." does not absolutely mean being above based on the direction of gravity, nor does it mean not only "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0047] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplarily" is intended to refer to an example or illustration.

[0048] This document describes exemplary embodiments with reference to schematic diagrams. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather encompass various equivalent structures capable of performing the same functions, as well as deviations in shape and size resulting, for example, from manufacturing. The positions shown in the figures are schematic in nature and are not intended to limit the positions of components.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0050] As used herein, the term "layer" refers to a portion of a material comprising an area having a height. A layer can be an area of a uniform or non-uniform continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers.

[0051] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0052] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0053] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0054] like Figure 1 As shown, a method 1000 for manufacturing a semiconductor structure may include: (S1100) forming an initial first stacked structure covering a plurality of first stair steps of a first substrate and extending along a first direction on one side of the first substrate, wherein the initial first stacked structure includes alternating first dielectric layers and first sacrificial layers, a portion of the initial first stacked structure covering the first stair steps and a portion of the initial first stacked structure extending along the first direction on the one side of the first substrate having a height difference along a stacking direction of the initial first stacked structure, the first direction intersecting the stacking direction; (S1200) removing a portion of the initial first stacked structure along a second direction opposite to the stacking direction, such that the remaining portions of the initial first stacked structure, which are away from a first surface of the first substrate along the stacking direction, are at the same height; (S1300) replacing the first sacrificial layer with a first gate layer; and (S1400) forming a first contact structure extending along the second direction to the first gate layer closest to the first surface on the first stair steps. Steps S1100 to S1400 will be described in detail below.

[0055] Figure 4 1 is a schematic structural diagram of forming an initial first stacked structure 1100 ′ according to an exemplary embodiment of the present application. Figure 5 yes Figure 4 A magnified view of some of the structures in .

[0056] In the exemplary embodiment of the present application, Figure 4 As shown, an initial first stacked structure 1100 ′ may be formed, which covers a plurality of first stair steps 110 of the first substrate 100 and extends along the first direction X on one side of the first substrate 100 .

[0057] For example, the initial first stacked structure 1100' may include alternately stacked first dielectric layers 1110 and first sacrificial layers 1120. A portion of the initial first stacked structure 1100' covering the first step 110, such as the first portion 1100'-1, and a portion of the initial first stacked structure 1100' extending along the first direction X on one side of the first substrate 100, such as the second portion 1100'-2, may have a height difference along the stacking direction Z of the initial first stacked structure 1100'. In other words, Figure 4 As shown, the first portion 1100'-1 and the second portion 1100'-2 of the initial first stacked structure 1100' may extend to different heights along the stacking direction Z. The height of the first portion 1100'-1 may be greater than or equal to the sum of the height of the second portion 1100'-2 and the height of the first substrate 100. For example, the first direction X may intersect the stacking direction Z.

[0058] like Figures 2 to 4 , a process diagram for forming an initial first stacked structure 1100' according to an exemplary embodiment of the present application is shown. It should be understood that the process for forming the initial first stacked structure 1100' provided herein is merely an example and is not intended to be limiting. In actual practice, the process for forming the initial first stacked structure 1100' can be appropriately configured based on actual needs.

[0059] For example, Figure 2 As shown, an initial first substrate 100' can be formed on a substrate 200. The substrate 200 can be, for example, a polycrystalline silicon substrate, a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 200 can also be a multilayer structure, such as Si / SiGe. In another embodiment, the substrate 200 can also be another epitaxial structure, such as silicon germanium on insulator (SGOI). The material of the initial first substrate 100' can include, but is not limited to, insulating materials such as oxides.

[0060] For example, the base 200 and the initial first substrate 100 ′ may be sequentially formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0061] For example, Figure 3As shown, a portion of the initial first substrate 100' can be removed to form a first substrate 100 having a plurality of first stair-steps 110. The plurality of first stair-steps 110 may include a first sub-step 111, a second sub-step 112, and a third sub-step 113. The first sub-step 111 and the third sub-step 113 may be located at opposite ends of the first substrate 100, respectively, and the plurality of second sub-steps 112 may be located between the first sub-step 111 and the third sub-step 113. For example, the thickness of the first sub-step 111, the second sub-step 112, and the third sub-step 113 along the stacking direction Z may be reasonably set according to actual process requirements. The requirements for the thickness of the first sub-step 111, the second sub-step 112, and the third sub-step 113 in this application are described in detail below.

[0062] For example, the plurality of first stair-steps 110 may be formed by repeatedly performing an etch-trim process on the initial first substrate 100' using a patterned mask (not shown). The patterned mask may include a photoresist or a carbon-based polymer material and may be removed after forming the first stair-steps 110.

[0063] For example, Figure 4 As shown, forming an initial first stacked structure 1100' that includes a plurality of first stepped steps 110 covering the first substrate 100 and extending along the first direction X on one side of the first substrate 100 may include: forming a preset layer 1200 that covers the first substrate 100 and extends along the first direction X on one side of the first substrate 100; and forming the initial first stacked structure 1100' on a surface of the preset layer 1200.

[0064] For example, a preset layer 1200 may be formed on the substrate 200 and the first step 110, and a first dielectric layer 1110 and a first sacrificial layer 1120 may be alternately stacked on the preset layer 1200 to form an initial first stacked structure 1100'. For example, the preset layer 1200 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and the first dielectric layer 1110 and the first sacrificial layer 1120 may be stacked in sequence to form the initial first stacked structure 1100'. It should be understood that a layer of the first dielectric layer 1110 and a layer of the first sacrificial layer 1120 may be formed into a stack, and the initial first stacked structure 1100' may include a plurality of stacks. The number and thickness of the first dielectric layer 1110 and the first sacrificial layer 1120 are not limited to Figure 4, without departing from the concept of the present application, those skilled in the art can set any number and thickness of the first dielectric layer 1110 and the first sacrificial layer 1120 as needed. In addition, the thickness of the first sacrificial layer 1120 can be greater than the thickness of the first dielectric layer 1110. The materials of the first dielectric layer 1110 and the first sacrificial layer 1120 can be selected from suitable materials known in the art. For example, the material of the first dielectric layer 1110 may include an oxide such as silicon oxide, and the material of the first sacrificial layer 1120 may include a nitride such as silicon nitride. The preset layer 1200 can be used as a stop layer for subsequently removing part of the initial first stacked structure 1100', so the material forming the preset layer 1200 can be different from the material forming the first dielectric layer 1110 and the first sacrificial layer 1120. The material forming the preset layer 1200 may include a semiconductor material such as polysilicon.

[0065] For example, Figure 5 As shown, the thickness H1 of the first sub-step 111 may include the thickness of the predetermined layer 1200 and the thickness of at least one stacked layer. In one exemplary embodiment of the present application, the thickness H1 of the first sub-step 111 may include the thickness of the predetermined layer 1200 and the thickness of a stacked layer (i.e., one first dielectric layer 1110 and one first sacrificial layer 1120). In other words, the thickness H1 of the first sub-step 111 may be the sum of the thicknesses of the predetermined layer 1200, one first dielectric layer 1110, and the first sacrificial layer 1120. In another exemplary embodiment of the present application, the thickness H1 of the first sub-step 111 may include the thickness of the predetermined layer 1200 and the thicknesses of multiple stacked layers, such as two stacked layers (i.e., two first dielectric layers 1110 and two first sacrificial layers 1120). In other words, the thickness H1 of the first sub-step 111 may be the sum of the thicknesses of the predetermined layer 1200, two first dielectric layers 1110, and the first sacrificial layer 1120.

[0066] The thickness H2 of the second sub-step 112 may include the thickness of at least one stacked layer. In other words, the thickness H2 of the second sub-step 112 may be the sum of the thicknesses of at least one first dielectric layer 1110 and the first sacrificial layer 1120. Furthermore, this application does not impose any specific restrictions on the thickness of the third sub-step 113, and the thickness of the third sub-step 113 may be appropriately set in actual processes.

[0067] It should be noted that, for the sake of clarity and simplicity in describing this application, the figures herein illustrate only the case where the thickness H1 of the first sub-step 111 includes the thickness of the predetermined layer 1200 and the thickness of one stacked layer, and the thickness H2 of the second sub-step 112 includes the thickness of one stacked layer. Furthermore, the number of second sub-steps 112 can be adjusted as needed, depending on the number of first sacrificial layers 1120 in the initial first stacked structure 1100' and the number of stacked layers contained in each first step 110.

[0068] In the exemplary embodiment of the present application, Figure 6 As shown, a portion of the initial first stacked structure 1100' can be removed along a second direction Y opposite to the stacking direction Z, so that the first surface S1 of the remaining initial first stacked structure 1100', which is away from the first substrate 100 along the stacking direction Z, is located at the same height. For example, the first surface S1 of the remaining initial first stacked structure 1100' can be substantially flush along the first direction X. For example, the portion of the initial first stacked structure 1100' can be removed by a process such as chemical mechanical polishing (CMP).

[0069] In an exemplary embodiment of the present application, Figure 6 As shown, a portion of the initial first stacked structure 1100' can be removed along the second direction Y, so that the first surfaces S1 of the remaining initial first stacked structure 1100' are located at the same height, and the first sacrificial layers 1120 located in different stacks in the remaining initial first stacked structure 1100' are exposed to the first surface S1. Figure 6 As shown, after a portion of the initial first stacked structure 1100' is removed, first sacrificial layers 1120 in a plurality of different stacks, such as five different stacks, located on the plurality of first step steps 110 are exposed to the first surface S1. It should be understood that the first sacrificial layer 1120 exposed to the first surface S1 described in this application may refer to the portion of the first sacrificial layer 1120 covering the top surface of the first step steps 110 being exposed to the first surface S1.

[0070] For example, Figure 6 As shown, the portion of the preset layer 1200 covering the highest point of the first substrate 100 can be positioned on the first surface S1. The portion of the preset layer 1200 covering the highest point of the first substrate 100 can serve as a stop layer for removing a portion of the initial first stacked structure 1100'. For example, a portion of the initial first stacked structure 1100' can be removed along the second direction Y to expose the portion of the preset layer 1200 covering the highest point of the first substrate 100, with the first surface S1 of the remaining initial first stacked structure 1100' positioned at the same height. The first sacrificial layers 1120 located in different stacks in the remaining initial first stacked structure 1100' are exposed on the first surface S1.

[0071] In the present application, by reasonably setting the relationship between the thicknesses of the plurality of first steps 110, such as the first sub-step 111 and the second sub-step 112, the preset layer 1200, the first dielectric layer 1110, and the first sacrificial layer 1120, it is advantageous to ensure that after removing a portion of the initial first stacked structure 1100', the first sacrificial layers 1120 in different stacks of the remaining initial first stacked structure 1100' are exposed to the first surface S1. In addition, by setting the first sacrificial layers 1120 in different stacks of the remaining initial first stacked structure 1100' to be exposed to the first surface S1 having the same height, the present application is advantageous to ensure that the first gate layer 1130 ( Figure 12 , formed by replacing the first sacrificial layer 1120) Figure 12 ) have approximately the same thickness, which is beneficial to reducing the process difficulty of the first contact structure 1500 and improving the accuracy of the first contact structure 1500, thereby helping to improve the overall performance of the semiconductor structure finally formed.

[0072] In another exemplary embodiment of the present application, due to limitations in the actual manufacturing process, the thicknesses of the plurality of first stair-steps 110, such as the first sub-step 111 and the second sub-step 112, the predetermined layer 1200, the first dielectric layer 1110, and the first sacrificial layer 1120, all have a reasonable error range. This allows for the removal of a portion of the initial first stacked structure 1100' to expose the portion of the predetermined layer 1200 covering the highest point of the first substrate 100. This exposes the first dielectric layer 1110 in a different stacked layer, rather than the first sacrificial layer 1120. On this basis, the exposed first dielectric layer 1110 can be further removed to expose the first sacrificial layer 1120 in a different stacked layer.

[0073] For example, a portion of the initial first stacked structure 1100' can be removed along the second direction Y to expose the portion of the predetermined layer 1200 that covers the highest point of the first substrate 100, leaving the first surface S1 of the remaining initial first stacked structure 1100' at the same height. The first dielectric layers 1110 located in different stacked layers of the remaining initial first stacked structure 1100' are exposed. The exposed first dielectric layers 1110 can then be removed to expose the first sacrificial layers 1120 located in different stacked layers. The exposed first sacrificial layers 1120 can be located at the same height.

[0074] It should be noted that if the first dielectric layer 1110 in a different stack is exposed after removing part of the initial first stack structure 1100', the exposed first dielectric layer 1110 may not be further removed, and the first contact structure 1500 ( Figure 12) may extend to the first gate layer 1130 ( closest to the first surface S1 ) on the plurality of first stepped steps 110 . Figure 12 , formed by replacing the first sacrificial layer 1120).

[0075] In the exemplary embodiment of the present application, Figure 6 As shown, the second portion 1100'-2 ( Figure 4 ) in the substrate 200. Forming the initial channel structure 300 penetrates the initial first stacked structure 1100' and extends to the substrate 200. Exemplarily, forming the initial channel structure 300 may include: forming a plurality of first initial channel holes (not shown) that penetrate the initial first stacked structure 1100' and extend to the substrate 200; and filling the first initial channel holes with a sacrificial material to form the initial channel structure 300. Exemplarily, the sacrificial material may include a material such as carbide, which has a low density to facilitate subsequent removal.

[0076] Figure 7 1 is a schematic structural diagram of forming a second substrate 400 and an initial second stacked structure 1300 ′ according to an exemplary embodiment of the present application. Figure 8 yes Figure 7 A magnified view of some of the structures in .

[0077] In the exemplary embodiment of the present application, Figure 7 As shown, a second substrate 400 having a plurality of second stepped steps 410 may be formed on one side of the first surface S1 , wherein the second stepped steps 410 and the first stepped steps 110 may be spaced apart along the first direction X.

[0078] For example, the second substrate 400 may include the same material as the first substrate 100, such as, but not limited to, an insulating material such as oxide. For example, the second substrate 400 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, similar to the formation process of the first step 110, the plurality of second step 410 may be formed by repeated etching and trimming processes.

[0079] For example, Figure 7As shown, an initial second stacked structure 1300' may be formed that covers a plurality of second stair-steps 410 and extends along the first direction X on one side of the second substrate 400. The initial second stacked structure 1300' includes second dielectric layers 1310 and second sacrificial layers 1320 alternately stacked along the stacking direction Z. A portion of the initial second stacked structure 1300' covering the second stair-steps 410, such as the third portion 1300'-1, and a portion of the initial second stacked structure 1300' extending along the first direction X on one side of the second substrate 400, such as the fourth portion 1300'-2, may have a height difference along the stacking direction Z. In other words, as shown in FIG. Figure 7 As shown, the third portion 1300 ′- 1 and the fourth portion 1300 ′- 2 of the initial second stacked structure 1300 ′ may extend to different heights along the stacking direction Z. The height of the third portion 1300 ′- 1 may be greater than or equal to the sum of the heights of the fourth portion 1300 ′- 2 and the second substrate 400 .

[0080] For example, Figure 7 As shown, forming an initial second stacked structure 1300' covering the plurality of second stair-step steps 410 and extending along the first direction X on one side of the second substrate 400 may include: forming a pre-buried layer 1400 covering the plurality of second stair-step steps 410 and extending along the first direction X on one side of the second substrate 400; and forming the initial second stacked structure 1300' on a surface of the pre-buried layer 1400. It should be noted that the formation process, materials, and function of the pre-buried layer 1400 are similar to those of the preset layer 1200.

[0081] Exemplarily, a pre-buried layer 1400 may be formed on the first surface S1 and the second step step 410; and a second dielectric layer 1310 and a second sacrificial layer 1320 may be alternately stacked on the pre-buried layer 1400 to form an initial second stacked structure 1300'. Exemplarily, the pre-buried layer 1400 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and the second dielectric layer 1310 and the second sacrificial layer 1320 may be stacked in sequence to form the initial second stacked structure 1300'. It should be understood that a layer of the second dielectric layer 1310 and a layer of the second sacrificial layer 1320 may be formed into a stack, and the initial second stacked structure 1300' may include a plurality of stacks. The number and thickness of the second dielectric layer 1310 and the second sacrificial layer 1320 are not limited to Figure 7, without departing from the concept of the present application, those skilled in the art may set any number and thickness of the second dielectric layer 1310 and the second sacrificial layer 1320 as needed. In addition, the thickness of the second sacrificial layer 1320 may be greater than the thickness of the second dielectric layer 1310. The materials of the second dielectric layer 1310 and the second sacrificial layer 1320 may be selected from suitable materials known in the art. For example, the material of the second dielectric layer 1310 may include an oxide such as silicon oxide, and the material of the second sacrificial layer 1320 may include a nitride such as silicon nitride. The buried layer 1400 may be used as a stop layer for subsequent removal of a portion of the initial second stacked structure 1300'. Therefore, the material forming the buried layer 1400 may be different from the material forming the second dielectric layer 1310 and the second sacrificial layer 1320. The material forming the buried layer 1400 may include a semiconductor material such as polysilicon.

[0082] For example, Figure 8 As shown, the plurality of second stair-steps 410 may include a fourth sub-step 411, a fifth sub-step 412, and a sixth sub-step 413, wherein the fourth sub-step 411 and the sixth sub-step 413 may be located at two ends of the second substrate 400, respectively, and the plurality of fifth sub-steps 412 may be located between the fourth sub-step 411 and the sixth sub-step 413. For example, the thicknesses of the fourth sub-step 411, the fifth sub-step 412, and the sixth sub-step 413 along the stacking direction Z may be reasonably set according to actual process requirements.

[0083] For example, the thickness H3 of the fourth sub-step 411 may include the thickness of the embedded layer 1400 and the thickness of at least one stacked layer. In one exemplary embodiment of the present application, the thickness H3 of the fourth sub-step 411 may include the thickness of the embedded layer 1400 and the thickness of one stacked layer (i.e., one second dielectric layer 1310 and one second sacrificial layer 1320). In other words, the thickness H3 of the fourth sub-step 411 may be the sum of the thicknesses of the embedded layer 1400, one second dielectric layer 1310, and the second sacrificial layer 1320. In another exemplary embodiment of the present application, the thickness H3 of the fourth sub-step 411 may include the thickness of the embedded layer 1400 and the thickness of multiple stacked layers, such as two stacked layers (i.e., two second dielectric layers 1310 and two second sacrificial layers 1320). In other words, the thickness H3 of the fourth sub-step 411 may be the sum of the thicknesses of the embedded layer 1400, two second dielectric layers 1310, and the second sacrificial layer 1320.

[0084] The thickness H4 of the fifth sub-step 412 may include the thickness of at least one stacked layer. In other words, the thickness H4 of the fifth sub-step 412 may be the sum of the thicknesses of at least one second dielectric layer 1310 and the second sacrificial layer 1320. Furthermore, this application does not impose any specific restrictions on the thickness of the sixth sub-step 413; the thickness of the sixth sub-step 413 may be appropriately set in actual processes.

[0085] It should be noted that, for the sake of clarity and simplicity in describing this application, the figures herein illustrate only the case where the thickness H3 of the fourth sub-step 411 includes the thickness of the embedded layer 1400 and the thickness of one stacked layer, and the thickness H4 of the fifth sub-step 412 includes the thickness of one stacked layer. Furthermore, the number of fifth sub-steps 412 can be adjusted as needed, depending on the number of second sacrificial layers 1320 in the initial second stacked structure 1300' and the number of stacked layers included in each second step 410.

[0086] In the exemplary embodiment of the present application, Figure 9 As shown, a portion of the initial second stacked structure 1300' can be removed along the second direction Y, so that the second surface S2 of the remaining initial second stacked structure 1300', which is away from the second substrate 400 along the stacking direction Z, is located at the same height. For example, the second surface S2 of the remaining initial second stacked structure 1300' can be substantially flush along the first direction X. For example, the portion of the initial second stacked structure 1300' can be removed by a process such as chemical mechanical polishing.

[0087] In an exemplary embodiment of the present application, Figure 9 As shown, a portion of the initial second stacked structure 1300' can be removed along the second direction Y, so that the second surface S2 of the remaining initial second stacked structure 1300' is located at the same height, and the second sacrificial layer 1320 located in different stacks in the remaining initial second stacked structure 1300' is exposed to the second surface S2. Figure 9 As shown, after a portion of the initial second stacked structure 1300' is removed, the second sacrificial layers 1320 in the plurality of different stacks, such as five different stacks, located on the plurality of second step steps 410 are exposed to the second surface S2. It should be understood that the second sacrificial layer 1320 exposed to the second surface S2 described herein may refer to the portion of the second sacrificial layer 1320 covering the top surface of the second step steps 410 being exposed to the second surface S2.

[0088] For example, Figure 9 As shown, the portion of the embedded layer 1400 that covers the highest point of the second substrate 400 can be positioned on the second surface S2. The portion of the embedded layer 1400 that covers the highest point of the second substrate 400 can serve as a stop layer for removing a portion of the initial second stacked structure 1300'. For example, a portion of the initial second stacked structure 1300' can be removed along the second direction Y to expose the portion of the embedded layer 1400 that covers the highest point of the second substrate 400, and the second surface S2 of the remaining initial second stacked structure 1300' is positioned at the same height. The second sacrificial layers 1320 located in different stacks in the remaining initial second stacked structure 1300' are exposed on the second surface S2.

[0089] In the present application, by reasonably setting the relationship between the thicknesses of the plurality of second steps 410, such as the fourth sub-step 411 and the fifth sub-step 412, the buried layer 1400, the second dielectric layer 1310, and the second sacrificial layer 1320, it is advantageous to ensure that after removing a portion of the initial second stacked structure 1300', the second sacrificial layers 1320 in different stacks of the remaining initial second stacked structure 1300' are exposed to the second surface S2. In addition, by setting the second sacrificial layers 1320 in different stacks of the remaining initial second stacked structure 1300' to be exposed to the second surface S2 having the same height, the present application is advantageous in ensuring that the subsequently formed second gate layer 1330 ( Figure 13 , formed by replacing the second sacrificial layer 1320) Figure 13 ) have approximately the same thickness, which is beneficial to reducing the process difficulty of the second contact structure 1600 and improving the accuracy of the second contact structure 1600, thereby helping to improve the overall performance of the semiconductor structure finally formed.

[0090] In another exemplary embodiment of the present application, due to limitations in the actual manufacturing process, the thicknesses of the plurality of second stair-steps 410, such as the fourth sub-step 411 and the fifth sub-step 412, the embedded layer 1400, the second dielectric layer 1310, and the second sacrificial layer 1320 all have a reasonable error range. This allows, after removing a portion of the initial second stacked structure 1300' to expose the portion of the embedded layer 1400 covering the highest point of the second substrate 400, the second dielectric layer 1310 in a different stack is exposed, rather than the second sacrificial layer 1320. On this basis, the exposed second dielectric layer 1310 can be further removed to expose the second sacrificial layer 1320 in a different stack.

[0091] For example, a portion of the initial second stacked structure 1300' can be removed along the second direction Y to expose the portion of the pre-buried layer 1400 that covers the highest point of the second substrate 400, and the second surface S2 of the remaining initial second stacked structure 1300' is located at the same height, wherein the second dielectric layers 1310 located in different stacked layers in the remaining initial second stacked structure 1300' are exposed. Then, the exposed second dielectric layers 1310 can be removed to expose the second sacrificial layers 1320 located in different stacked layers, wherein the exposed second sacrificial layers 1320 can be located at the same height.

[0092] It should be noted that if the second dielectric layer 1310 in a different stack is exposed after removing part of the initial second stack structure 1300', the exposed second dielectric layer 1310 may not be further removed, and the second contact structure 1600 ( Figure 13) may extend to the second gate layer 1330 ( closest to the second surface S2 ) on the plurality of second stepped steps 410 . Figure 13 , formed by replacing the second sacrificial layer 1320).

[0093] In the exemplary embodiment of the present application, the fourth portion 1300'-2 ( Figure 7 ) is formed in the initial second stacked structure 1300 ′ and extends to a portion of the initial channel structure 300 ( Figure 9 ); and removing the sacrificial material within the initial channel structure 300 via the second initial channel hole 510 to form a channel hole 520 ( Figure 10 ); and forming a channel structure 500 ( Figure 11 ).

[0094] For example, the channel hole 520 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 520 may have a cylindrical or pillar-like shape extending along the second direction Y in the initial second stacked structure 1300' and the initial first stacked structure 1100'.

[0095] The channel structure 500 includes a functional layer (not shown) extending along the second direction Y and a channel layer (not shown) located on a side of the functional layer away from the initial second stacked structure 1300' and the initial first stacked structure 1100'. For example, the functional layer may be formed on the sidewalls of the channel hole 520; and the channel layer extending along the second direction Y may be formed on a side of the functional layer away from the initial second stacked structure 1300' and the initial first stacked structure 1100'.

[0096] For example, the channel structure 500 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, a functional layer and a channel layer can be sequentially formed from the outside to the inside within the channel hole 520; a channel filling dielectric layer and a channel plug (not shown) can also be formed. It should be understood that the channel structure 500 can extend along the second direction Y to the substrate 200.

[0097] The functional layer may include a blocking layer (not shown) formed on the inner wall of the channel hole 520 to block the outflow of charges, a charge trapping layer (not shown) formed on the surface of the blocking layer to store charges during operation of the semiconductor structure, and a tunneling layer (not shown) formed on the surface of the charge trapping layer.

[0098] The barrier layer may include one or more layers, each of which may include one or more materials. The materials used for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The charge trapping layer may include one or more layers, each of which may include one or more materials. The materials used for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The tunneling layer may include one or more layers, each of which may include one or more materials. The materials used for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Exemplarily, the functional layer may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer may also have a structure different from the ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0099] The channel layer may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon. The material of the channel layer includes but is not limited to P-type doped polycrystalline silicon. Specifically, a filling semiconductor material may be used to fill the channel hole 520 to form a channel layer. The filling dielectric layer may include an oxidizing dielectric layer, such as silicon oxide. For example, during the filling process, a plurality of insulating gaps may be formed in the filling dielectric layer by controlling the channel filling process to reduce structural stress. The channel layer can be used to transport the required charges (electrons or holes). For example, a channel layer may be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0100] In addition, the channel structure 500 further includes a channel plug formed at one end of the channel layer away from the substrate 200 (which can be understood as the top of the channel structure 500). Specifically, the channel plug can be formed in the portion of the channel filling dielectric layer located at the top of the channel hole 520. The channel plug can be made of the same material as the channel layer, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer.

[0101] In the exemplary embodiment of the present application, Figure 11As shown, the first sacrificial layer 1120 can be replaced with a first gate layer 1130 to form a first stacked structure 1100. For example, replacing the first sacrificial layer 1120 with the first gate layer 1130 may include replacing the first sacrificial layer 1120 and the second sacrificial layer 1320 with a first gate layer 1130 and a second gate layer 1330, respectively, to form the first stacked structure 1100 and the second stacked structure 1300, respectively. In other words, the first gate layer 1130 and the second gate layer 1330 may be formed in the same process to form the first stacked structure 1100 and the second stacked structure 1300, respectively. The first stacked structure 1100 may include alternately stacked first dielectric layers 1110 and first gate layers 1130, and the second stacked structure 1300 may include alternately stacked second dielectric layers 1310 and second gate layers 1330.

[0102] Exemplarily, the material of the first gate layer 1130 and the second gate layer 1330 may be a conductive material, such as metal tungsten. Exemplarily, the first sacrificial layer 1120 and the second sacrificial layer 1320 may be replaced with the first gate layer 1130 and the second gate layer 1330, respectively, through a gate replacement process. Specifically, a gate gap (not shown) may be formed that passes through the initial second stacked structure 1300' and the initial first stacked structure 1100'; then, the first sacrificial layer 1120 and the second sacrificial layer 1320 may be removed through the gate gap, and the removed space may be filled with a conductive material to form the first gate layer 1130 and the second gate layer 1330. After the first gate layer 1130 and the second gate layer 1330 are formed, the gate gap may be filled to form a gate gap structure (not shown).

[0103] In the exemplary embodiment of the present application, Figure 12 As shown, a first contact structure 1500 can be formed that extends along the second direction Y to the first gate layer 1130 on the first stair step 110 that is closest to the first surface S1. By way of example, a plurality of first contact structures 1500 can be formed that extend along the second direction Y to the first gate layer 1130 on the plurality of first stair steps 110 (such as the first sub-step 111 and the plurality of second sub-steps 112, etc.) that are closest to the first surface S1. The first contact structure 1500 can penetrate the second substrate 400 along the second direction Y and extend to the first gate layer 1130 on the first stair step 110 that is closest to the first surface S1. The material of the first contact structure 1500 may include a conductive material such as a metal tungsten layer. The first contact structure 1500 can be used to achieve electrical connection with the first gate layer 1130, thereby drawing current out.

[0104] It should be understood that Figure 12The number of first contact structures 1500 shown in the figure, such as five, is merely an example and is not a specific limitation. The number of first contact structures 1500 can be adjusted according to the number of first gate layers 1130 and the number of first stair-steps 110. It should be noted that when the thickness H2 of the second sub-step 112 in the first stair-step 110 includes the thickness of multiple stacked layers, there may be first gate layers 1130 in some stacked layers that are not connected to the first contact structure 1500. Based on this, the present application can also form contact structures connected to other first gate layers (not shown).

[0105] In the exemplary embodiment of the present application, Figure 13 As shown, a second contact structure 1600 may be formed extending along the second direction Y to the second gate layer 1330 closest to the second surface S2 on the exposed second stair step 410. For example, during the process of forming the second contact structure 1600, an extraction structure 1510 may be formed extending along the second direction Y to the first contact structure 1500 to facilitate extraction of the first contact structure 1500.

[0106] It should be understood that the present application uses two initial stacked structures, such as the initial first stacked structure 1100' and the initial second stacked structure 1300', as examples for illustration only and not for specific limitation. For example, a third substrate (not shown) having a plurality of third stair steps may be formed on one side of the second surface S2, and an initial third stacked structure (not shown) may be formed covering the plurality of third stair steps and extending along the first direction X on one side of the third substrate. The second contact structure 1600 and the lead-out structure 1510 may penetrate the third substrate along the second direction Y and extend to the second gate layer 1330 and the first contact structure 1500, respectively.

[0107] In the present application, by arranging the first gate layers 1130 in multiple different stacks at the same height, the multiple first contact structures 1500 that are in contact with the multiple first gate layers 1130 are extended to the same height, thereby reducing the processing difficulty of the first contact structures 1500, reducing the risk of breakdown of the first gate layers 1130, and improving the feasibility of more stacked structures. Similarly, by arranging the second gate layers 1330 in multiple different stacks at the same height, the multiple second contact structures 1600 that are in contact with the multiple second gate layers 1330 are extended to the same height, thereby reducing the processing difficulty of the second contact structures 1600, reducing the risk of breakdown of the second gate layers 1330, and improving the feasibility of more stacked structures.

[0108] Figure 13 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0109] The semiconductor structure may include a first substrate 100 , a first stacked structure 1100 , and a first contact structure 1500 .

[0110] The first substrate 100 may include a plurality of first stepped steps 110. The first stacked structure 1100 may include alternating stacks of first dielectric layers 1110 and first gate layers 1130. The first stacked structure 1100 may cover the plurality of first stepped steps 110 and extend along a first direction X on one side of the first substrate 100. First surfaces S1 of the first stacked structure 1100, which are distal to the first substrate 100 along a stacking direction Z of the first stacked structure 1100, may be located at the same height. For example, the first surfaces S1 of the first stacked structure 1100 may be substantially flush along the first direction X. The first contact structure 1500 may extend along a second direction Y, opposite to the stacking direction Z, to the first gate layer 1130 on the plurality of first stepped steps 110, which is closest to the first surface S1. For example, the first direction X may intersect with the stacking direction Z.

[0111] By way of example, the material of the first substrate 100 may include, but is not limited to, insulating materials such as oxides. The plurality of first stair-steps 110 may include a first sub-step 111, a second sub-step 112, and a third sub-step 113. The first sub-step 111 and the third sub-step 113 may be located at opposite ends of the first substrate 100, respectively, and the plurality of second sub-steps 112 may be located between the first sub-step 111 and the third sub-step 113. By way of example, the thickness of the first sub-step 111, the second sub-step 112, and the third sub-step 113 along the stacking direction Z may be appropriately set based on actual process requirements. The requirements for the thickness of the first sub-step 111, the second sub-step 112, and the third sub-step 113 in this application are described in detail below.

[0112] For example, the semiconductor structure may further include a predetermined layer 1200 covering the first substrate 100 and extending along the first direction X on one side of the first substrate 100 , wherein the first stacked structure 1100 may be located on a surface of the predetermined layer 1200 .

[0113] For example, the semiconductor structure may further include a base 200 for supporting the first substrate 100 and the first stacked structure 1100, that is, the first substrate 100 and the first stacked structure 1100 may be located on the base 200. For example, the base 200 may be, for example, a polycrystalline silicon base, a single crystal silicon (Si) base, a single crystal germanium (Ge) base, a silicon germanium (GeSi) base, a silicon carbide (SiC) base, or a silicon-on-insulator (SOI) base, a germanium-on-insulator (GOI) base, or a base including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the base 200 may also be a multilayer structure, such as Si / SiGe. In other embodiments, the base 200 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0114] It should be understood that a first dielectric layer 1110 and a first gate layer 1130 may form a stack, and the first stack structure 1100 may include multiple stacks. The number and thickness of the first dielectric layer 1110 and the first gate layer 1130 are not limited to Figure 13 , without departing from the concept of the present application, those skilled in the art can set any number and thickness of the first dielectric layer 1110 and the first gate layer 1130 as needed. In addition, the thickness of the first gate layer 1130 can be greater than the thickness of the first dielectric layer 1110. The materials of the first dielectric layer 1110 and the first gate layer 1130 can be selected from suitable materials known in the art. For example, the material of the first dielectric layer 1110 may include an oxide such as silicon oxide, and the material of the first gate layer 1130 may include a conductive material such as metal tungsten. The material forming the preset layer 1200 may be different from the material forming the first dielectric layer 1110 and the first gate layer 1130. The material forming the preset layer 1200 may include a semiconductor material such as polysilicon.

[0115] For example, Figure 5As shown, the first sub-step 111 may be away from the first surface S1 along the stacking direction Z and closer to the portion of the first stacked structure 1100 extending along the first direction X. The thickness H1 of the first sub-step 111 may include the thickness of the predetermined layer 1200 and the thickness of at least one stacked layer. In one exemplary embodiment of the present application, the thickness H1 of the first sub-step 111 may include the thickness of the predetermined layer 1200 and the thickness of one stacked layer (i.e., one first dielectric layer 1110 and one first gate layer 1130). In other words, the thickness H1 of the first sub-step 111 may be the sum of the thicknesses of the predetermined layer 1200, one first dielectric layer 1110, and the first gate layer 1130. In another exemplary embodiment of the present application, the thickness H1 of the first sub-step 111 may include the thickness of the predetermined layer 1200 and the thicknesses of multiple stacked layers, such as two stacked layers (i.e., two first dielectric layers 1110 and two first gate layers 1130). In other words, the thickness H1 of the first sub-step 111 may be the sum of the thicknesses of the predetermined layer 1200 , the two first dielectric layers 1110 , and the first gate layer 1130 .

[0116] The thickness H2 of the second sub-step 112 may include the thickness of at least one stacked layer. In other words, the thickness H2 of the second sub-step 112 may be the sum of the thicknesses of at least one first dielectric layer 1110 and the first gate layer 1130. Furthermore, this application does not impose any specific restrictions on the thickness of the third sub-step 113, and the thickness of the third sub-step 113 may be appropriately set in actual processes.

[0117] It should be noted that, for the sake of clarity and simplicity in describing this application, the figures herein illustrate only the case where the thickness H1 of the first sub-step 111 includes the thickness of the predetermined layer 1200 and the thickness of one stack, and the thickness H2 of the second sub-step 112 includes the thickness of one stack. Furthermore, the number of second sub-steps 112 can be adjusted as needed, depending on the number of first gate layers 1130 in the first stacked structure 1100 and the number of stacked layers contained in each first stair-step 110.

[0118] For example, Figure 13 As shown, the portion of the predetermined layer 1200 that covers the highest point of the first substrate 100 may be located on the first surface S1. The first stacked structure 1100 may be located on the surface of the remaining portion of the predetermined layer 1200. The plurality of first contact structures 1500 may extend along the second direction Y to the first gate layer 1130 on the plurality of first steps 110 that is closest to the first surface S1.

[0119] For example, among the multiple different stacked layers of the first stacked structure 1100, Figure 13 The first gate layer 1130 in the five different stacks shown is located on the first surface S1. The plurality of first contact structures 1500 may extend to the plurality of different stacks located on the first surface S1, such as Figure 13 The first gate layer 1130 in the five different stacks shown. It should be understood that the first gate layer 1130 located on the first surface S1 described herein may refer to the portion of the first gate layer 1130 covering the top surface of the first step 110 being located on the first surface S1. The material of the first contact structure 1500 may include a conductive material such as a tungsten metal layer. The first contact structure 1500 may be used to establish an electrical connection with the first gate layer 1130, thereby conducting current.

[0120] It should be understood that Figure 13 The number of first contact structures 1500 shown in the figure, such as five, is only an example and is not a specific limitation. The number of first contact structures 1500 can be adjusted according to the number of first gate layers 1130 and the number of first stair steps 110. It should be noted that when the thickness H2 of the second sub-step 112 in the first stair step 110 includes the thickness of multiple stacked layers, there may be a portion of the stacked layers where the first gate layer 1130 is not connected to the first contact structure 1500. Based on this, the semiconductor structure provided in the present application may also include other contact structures (not shown) connected to the first gate layer.

[0121] In the present application, by rationally setting the relationship between the thicknesses of the plurality of first stair-steps 110, such as the first sub-step 111 and the second sub-step 112, the preset layer 1200, the first dielectric layer 1110, and the first gate layer 1130, it is advantageous to ensure that the first gate layers 1130 located in different stacks of the first stacked structure 1100 are located on the first surface S1. Furthermore, by arranging the first gate layers 1130 located in different stacks of the first stacked structure 1100 at the same height on the first surface S1, the present application facilitates ensuring that the first contact structures 1500 extending to the first gate layers 1130 in different stacks have substantially the same thickness, thereby facilitating reduced manufacturing difficulty of the first contact structures 1500, improved precision of the first contact structures 1500, and thus improved overall performance of the resulting semiconductor structure.

[0122] In an exemplary embodiment of the present application, the semiconductor structure may further include a second substrate 400, a second stacked structure 1300, and a second contact structure 1600. The second substrate 400 may be located on one side of the first surface S1 and include a plurality of second step steps 410, wherein the second step steps 410 and the first step steps 110 may be spaced apart along the first direction X. The second stacked structure 1300 may include second dielectric layers 1310 and second gate layers 1330 alternately stacked along a stacking direction Z. The second stacked structure 1300 may cover the plurality of second step steps 410 and extend along the first direction X on one side of the second substrate 400. For example, a second surface S2 of the second stacked structure 1300, distal from the second substrate 400 along the stacking direction Z, may be located at the same height. For example, the second surface S2 of the second stacked structure 1300 may be substantially flush along the first direction X. The second contact structure 1600 may extend along the second direction Y to the second gate layer 1330 closest to the second surface S2 on the plurality of second step steps 410.

[0123] For example, the second substrate 400 may include the same material as the first substrate 100 , such as, but not limited to, an insulating material such as oxide.

[0124] In an exemplary embodiment of the present application, the semiconductor structure may further include a buried layer 1400 located on the first surface S1 and the second step 410 , wherein the second stacked structure 1300 may be located on a surface of the buried layer 1400 .

[0125] It should be understood that a second dielectric layer 1310 and a second gate layer 1330 may be formed into a stack, and the second stack structure 1300 may include a plurality of stacks. The number and thickness of the second dielectric layer 1310 and the second gate layer 1330 are not limited to Figure 13 , without departing from the concept of the present application, those skilled in the art can set any number and thickness of the second dielectric layer 1310 and the second gate layer 1330 as needed. In addition, the thickness of the second gate layer 1330 can be greater than the thickness of the second dielectric layer 1310. The materials of the second dielectric layer 1310 and the second gate layer 1330 can be selected from suitable materials known in the art. For example, the material of the second dielectric layer 1310 can include an oxide such as silicon oxide, and the material of the second gate layer 1330 can include a conductive material such as metal tungsten. The material forming the buried layer 1400 can be different from the material forming the second dielectric layer 1310 and the second gate layer 1330. The material forming the buried layer 1400 can include a semiconductor material such as polysilicon.

[0126] For example, Figure 8As shown, the plurality of second stair-steps 410 may include a fourth sub-step 411, a fifth sub-step 412, and a sixth sub-step 413, wherein the fourth sub-step 411 and the sixth sub-step 413 may be located at two ends of the second substrate 400, respectively, and the plurality of fifth sub-steps 412 may be located between the fourth sub-step 411 and the sixth sub-step 413. For example, the thicknesses of the fourth sub-step 411, the fifth sub-step 412, and the sixth sub-step 413 along the stacking direction Z may be reasonably set according to actual process requirements.

[0127] For example, the thickness H3 of the fourth sub-step 411 may include the thickness of the buried layer 1400 and the thickness of at least one stacked layer. In one exemplary embodiment of the present application, the thickness H3 of the fourth sub-step 411 may include the thickness of the buried layer 1400 and the thickness of one stacked layer (i.e., one second dielectric layer 1310 and one second gate layer 1330). In other words, the thickness H3 of the fourth sub-step 411 may be the sum of the thicknesses of the buried layer 1400, one second dielectric layer 1310, and the second gate layer 1330. In another exemplary embodiment of the present application, the thickness H3 of the fourth sub-step 411 may include the thickness of the buried layer 1400 and the thickness of multiple stacked layers, such as two stacked layers (i.e., two second dielectric layers 1310 and two second gate layers 1330). In other words, the thickness H3 of the fourth sub-step 411 may be the sum of the thicknesses of the buried layer 1400, two second dielectric layers 1310, and the second gate layer 1330.

[0128] The thickness H4 of the fifth sub-step 412 may include the thickness of at least one stacked layer. In other words, the thickness H4 of the fifth sub-step 412 may be the sum of the thicknesses of at least one second dielectric layer 1310 and the second gate layer 1330. Furthermore, this application does not impose any specific restrictions on the thickness of the sixth sub-step 413; the thickness of the sixth sub-step 413 may be appropriately set in actual processes.

[0129] It should be noted that, for the sake of clarity and simplicity in describing this application, the figures herein illustrate only the case where the thickness H3 of the fourth sub-step 411 includes the thickness of the embedded layer 1400 and the thickness of one stack, and the thickness H4 of the fifth sub-step 412 includes the thickness of one stack. Furthermore, the number of fifth sub-steps 412 can be adjusted as needed, depending on the number of second gate layers 1330 in the second stacked structure 1300 and the number of stacked layers included in each second stair-step 410.

[0130] For example, Figure 13As shown, the portion of the buried layer 1400 that covers the highest point of the second substrate 400 may be located on the second surface S2. The second stacked structure 1300 may be located on the surface of the remaining portion of the buried layer 1400. The plurality of second contact structures 1600 may extend along the second direction Y to the second gate layer 1330 on the plurality of second stair steps 410 that is closest to the first surface S2.

[0131] For example, among the multiple different stacking layers of the second stacking structure 1300, Figure 13 The second gate layer 1330 in the five different stacks shown is located on the second surface S2. The plurality of second contact structures 1600 may extend to the plurality of different stacks located on the second surface S2, such as Figure 13 The second gate layer 1330 in five different stacks is shown. It should be understood that the second gate layer 1330 located on the second surface S2 described in this application may mean that the portion of the second gate layer 1330 covering the top surface of the second step 410 is located on the second surface S2.

[0132] In the present application, by rationally setting the relationship between the thicknesses of the plurality of second stair-steps 410, such as the fourth sub-step 411 and the fifth sub-step 412, the buried layer 1400, the second dielectric layer 1310, and the second sacrificial layer 1320, it is advantageous to ensure that the second gate layers 1330 located in different stacks in the second stacked structure 1300 are located on the second surface S2. In addition, by setting the remaining second gate layers 1330 located in different stacks in the second stacked structure 1300 at the same height on the second surface S2, the present application facilitates ensuring that the second contact structures 1600 extending to the second gate layers 1330 in different stacks have substantially the same thickness, thereby facilitating reduced manufacturing difficulty and improved precision of the second contact structures 1600, thereby improving the overall performance of the resulting semiconductor structure.

[0133] In an exemplary embodiment of the present application, the first contact structure 1500 may penetrate the second substrate 400 along the second direction Y and extend to the first gate layer 1130 closest to the first surface S1 on the first step 110. The semiconductor structure may further include an extraction structure 1510 extending along the second direction Y to the first contact structure 1500 to facilitate extraction of the first contact structure 1500.

[0134] It should be understood that the present application uses two stacked structures, such as the first stacked structure 1100 and the second stacked structure 1300, as examples for illustration only and not for specific limitation. For example, the semiconductor structure may further include a third substrate (not shown) located on one side of the second surface S2 and including a plurality of third stair steps, and a third stacked structure (not shown) covering the plurality of third stair steps and extending along the first direction X on one side of the third substrate. The second contact structure 1600 and the lead-out structure 1510 may penetrate the third substrate along the second direction Y and extend to the second gate layer 1330 and the first contact structure 1500, respectively.

[0135] In the present application, by arranging the first gate layers 1130 in multiple different stacks at the same height, the multiple first contact structures 1500 that are in contact with the multiple first gate layers 1130 are extended to the same height, thereby reducing the processing difficulty of the first contact structures 1500, reducing the risk of breakdown of the first gate layers 1130, and improving the feasibility of more stacked structures. Similarly, by arranging the second gate layers 1330 in multiple different stacks at the same height, the multiple second contact structures 1600 that are in contact with the multiple second gate layers 1330 are extended to the same height, thereby reducing the processing difficulty of the second contact structures 1600, reducing the risk of breakdown of the second gate layers 1330, and improving the feasibility of more stacked structures.

[0136] In the exemplary embodiment of the present application, the semiconductor structure may further include a channel structure 500 extending through the second stacked structure 1300 and the first stacked structure 1100 along the second direction Y. The channel structure 500 includes a functional layer (not shown) extending along the second direction Y and a channel layer (not shown) located on a side of the functional layer away from the second stacked structure 1300 and the first stacked structure 1100. It should be understood that the channel structure 500 may extend along the second direction Y to the substrate 200.

[0137] The functional layer may include a blocking layer (not shown) for blocking the outflow of charges, a charge trapping layer (not shown) formed on the surface of the blocking layer to store charges during operation of the semiconductor structure, and a tunneling layer (not shown) formed on the surface of the charge trapping layer.

[0138] The barrier layer may include one or more layers, each of which may include one or more materials. The materials used for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The charge trapping layer may include one or more layers, each of which may include one or more materials. The materials used for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The tunneling layer may include one or more layers, each of which may include one or more materials. The materials used for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Exemplarily, the functional layer may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer may also have a structure different from the ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0139] The channel layer may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon. The material of the channel layer includes but is not limited to P-type doped polycrystalline silicon. The filling dielectric layer may include an oxidizing dielectric layer, such as silicon oxide. Exemplarily, a plurality of insulating gaps may be present in the filling dielectric layer to reduce structural stress. The channel layer can be used to transport the required charges (electrons or holes). Exemplarily, the channel layer can be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0140] In addition, the channel structure 500 also includes a channel plug formed at one end of the channel layer away from the substrate 200 (which can be understood as the top of the channel structure 500). The channel plug can be made of the same material as the channel layer, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer.

[0141] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, related or similar contents will not be described in detail herein.

[0142] Although the exemplary structure and fabrication method of the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced, or added to the fabrication method of the semiconductor structure. In addition, the illustrated layers and their materials are merely exemplary.

[0143] Figure 14 2 is a schematic block diagram of a memory according to an exemplary embodiment of the present application. The memory 2000 may include a memory cell array 2100 and a peripheral circuit 2200 .

[0144] The memory cell array 2100 and the peripheral circuit 2200 may be separately formed on different substrates and then bonded to form the memory 2000 .

[0145] The peripheral circuit 2200 may be coupled to the memory cell array 2100. The peripheral circuit 2200 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 2100. For example, the peripheral circuit 2200 may include one or more of a page buffer, decoders (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor).

[0146] The memory cell array 2100 may include a semiconductor structure as described in any embodiment of the present application. For example, the memory cell array 2100 may include a plurality of memory cells, such as NAND memory cells. NAND memory cells are capable of maintaining a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the memory cell region. Each memory cell may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0147] Figure 15 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0148] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having the storage system 12 located therein. Figure 15 As shown, system 10 may include a host 18 and a storage system 12 having one or more memories, such as a three-dimensional memory 14, and a controller 17. Host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0149] The three-dimensional memory 14 may include a semiconductor structure as described in any of the embodiments herein. According to some embodiments, a controller 17 is coupled to the three-dimensional memory 14 and a host 18 and is configured to control the three-dimensional memory 14. The controller 17 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 17 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the controller 17 is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The controller 17 may be configured to control operations of the three-dimensional memory 14, such as read, erase, and program operations. The controller 17 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 17 is further configured to process error correction code (ECC) associated with data read from or written to the three-dimensional memory 14. The controller 17 may also perform any other appropriate functions, such as formatting the three-dimensional memory 14. The controller 17 may communicate with an external device (e.g., a host computer 18) according to a specific communication protocol. For example, the controller 17 may communicate with the external device via at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-Express, PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, and the like.

[0150] The controller 17 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of final electronic products. Figure 16AIn one example shown in FIG, the controller 17 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 15 The host 18 in the memory card connector 24 is coupled. Figure 16B In another example shown in FIG, the controller 17 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 15 In some embodiments, the SSD 26 has a storage capacity and / or an operating speed that is higher than that of the memory card 22.

[0151] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure comprising: a first substrate comprising a plurality of first steps; a first stacked structure comprising alternately stacked first dielectric layers and first gate layers, covering the first step and extending along a first direction on one side of the first substrate, wherein layers of the first stacked structure away from a first surface of the first substrate along a stacking direction of the first stacked structure are located at the same height, and the first direction intersects the stacking direction; as well as The first contact structure extends along a second direction opposite to the stacking direction to the first gate layer on the first step closest to the first surface.

2. The semiconductor structure according to claim 1, wherein The plurality of first contact structures extend along the second direction respectively to the first gate layer closest to the first surface on the plurality of first steps.

3. The semiconductor structure according to claim 2, wherein: The first gate layer in the plurality of different stacked layers of the first stacked structure is located on the first surface, The plurality of first contact structures respectively extend to the first gate layer in a plurality of different stacks located on the first surface.

4. The semiconductor structure according to any one of claims 1 to 3, wherein: The semiconductor structure further includes: a predetermined layer covering the first substrate and extending along the first direction on one side of the first substrate, The portion of the preset layer covering the highest point of the first substrate is located on the first surface, and the first stacked structure is located on the surface of the remaining portion of the preset layer, wherein the forming material of the preset layer is different from the forming material of the first dielectric layer and the first gate layer.

5. The semiconductor structure according to claim 4, wherein The semiconductor structure further comprises: a second substrate, located on one side of the first surface, comprising a plurality of second steps, wherein the second steps are spaced apart from the first steps along the first direction; a second stacked structure comprising second dielectric layers and second gate layers alternately stacked along the stacking direction, covering the second step and extending along the first direction on one side of the second substrate, wherein second surfaces of the second stacked structure away from the second substrate along the stacking direction are located at the same height; and The second contact structure extends along the second direction to the second gate layer on the second step closest to the second surface. The semiconductor structure according to claim 5 , wherein: The first contact structure penetrates the second substrate along the second direction and extends to the first gate layer on the first step closest to the first surface.

7. The semiconductor structure according to claim 5, wherein: The plurality of second contact structures extend along the second direction respectively to the second gate layer closest to the second surface on the plurality of second steps.

8. The semiconductor structure according to claim 7, wherein: The second gate layer in the plurality of different stacked layers of the second stacked structure is located on the second surface, The plurality of second contact structures respectively extend to the second gate layers in a plurality of different stacked layers located on the second surface.

9. The semiconductor structure according to claim 4, wherein: The materials of the first substrate and the first dielectric layer include oxide; The materials of the first gate layer and the first contact structure include metal; and The material of the preset layer includes polysilicon.

10. The semiconductor structure according to claim 4, wherein The plurality of first steps include: a first sub-step, a portion extending along the first direction, away from the first surface along the stacking direction and close to the first stacked structure along the first direction; and a plurality of second sub-steps, adjacent to the first sub-steps; Wherein, the thickness of the first sub-step includes the thickness of the preset layer and the thickness of at least one stacked layer; and The thickness of the second sub-step includes the thickness of at least one stacked layer.

11. A method of manufacturing a semiconductor structure, wherein: The method comprises: forming an initial first stacked structure covering a plurality of first stair steps of a first substrate and extending along a first direction on one side of the first substrate, wherein the initial first stacked structure comprises first dielectric layers and first sacrificial layers that are alternately stacked, and a portion of the initial first stacked structure covering the first stair steps and a portion of the initial first stacked structure extending along the first direction on one side of the first substrate have a height difference along a stacking direction of the initial first stacked structure, and the first direction intersects the stacking direction; removing a portion of the initial first stacked structure along a second direction opposite to the stacking direction, so that first surfaces of the remaining initial first stacked structure away from the first substrate along the stacking direction are located at the same height; replacing the first sacrificial layer with a first gate layer; and A first contact structure is formed extending along the second direction to the first gate layer on the first step closest to the first surface.

12. The method according to claim 11, wherein The semiconductor structure includes a plurality of first contact structures, Wherein, forming the first contact structure includes: A plurality of first contact structures are formed, each extending along the second direction to a portion of the first gate layer closest to the first surface on the plurality of first steps.

13. The method according to claim 12, wherein: Removing a portion of the initial first stacked structure, comprising: Part of the initial first stacked structure is removed along the second direction, so that the first surfaces of the remaining initial first stacked structures are located at the same height, and the first sacrificial layers located in different stacks in the remaining initial first stacked structure are exposed to the first surface.

14. The method according to any one of claims 11 to 13, wherein An initial first stacked structure is formed, which includes a plurality of first stair steps covering a first substrate and extending along a first direction on one side of the first substrate, comprising: forming a predetermined layer covering the first substrate and extending along the first direction on one side of the first substrate; and The initial first stacked structure is formed on the surface of the preset layer.

15. The method according to claim 14, wherein The portion of the preset layer that covers the highest point of the first substrate is located on the first surface. Removing a portion of the initial first stacked structure along the second direction, comprising: removing a portion of the initial first stacked structure along the second direction to expose a portion of the preset layer covering the highest point of the first substrate, and making the first surfaces of the remaining initial first stacked structure at the same height; The remaining first sacrificial layers in different stacked layers in the initial first stacked structure are exposed to the first surface.

16. The method according to claim 14, wherein Removing a portion of the initial first stacked structure along the second direction, comprising: removing a portion of the initial first stacked structure along the second direction to expose a portion of the predetermined layer covering the highest point of the first substrate, and making the first surfaces of the remaining initial first stacked structures located at the same height, wherein the first dielectric layers located in different stacks in the remaining initial first stacked structure are exposed; and The exposed first dielectric layer is removed to expose the first sacrificial layer located in a different stack, wherein the exposed first sacrificial layer is located on the first surface.

17. The method according to claim 14, wherein: The method further comprises: forming a second substrate having a plurality of second stepped steps on one side of the first surface, wherein the second stepped steps are spaced apart from the first stepped steps along the first direction; forming an initial second stacked structure covering the plurality of second stair-steps and extending along the first direction on one side of the second substrate, wherein the initial second stacked structure comprises second dielectric layers and second sacrificial layers alternately stacked along the stacking direction, and a portion of the initial second stacked structure covering the second stair-steps and a portion of the initial second stacked structure extending along the first direction on one side of the second substrate have a height difference along the stacking direction; and removing a portion of the initial second stacked structure along the second direction so that the second surfaces of the remaining initial second stacked structure away from the second substrate along the stacking direction are located at the same height; The step of replacing the first sacrificial layer with a first gate layer includes: The first sacrificial layer and the second sacrificial layer are replaced with the first gate layer and the second gate layer, respectively.

18. The method according to claim 17, wherein Forming a first contact structure of the first gate layer extending along the second direction to a portion of the first step closest to the first surface, comprising: A first contact structure is formed along the second direction, penetrating the second substrate and extending to the first gate layer on the first step closest to the first surface.

19. The method according to claim 17, wherein The method further comprises: A second contact structure is formed extending along the second direction to the second gate layer on the exposed second step closest to the second surface.

20. The method according to any one of claims 11 to 13, wherein The method further comprises: A portion of the initial first substrate is removed to form the first substrate having a plurality of the first step steps.

21. A memory, wherein: include: A memory cell array comprising the semiconductor structure according to any one of claims 1 to 10; as well as The peripheral circuit is coupled to the memory cell array.

22. A storage system, wherein: include: comprising the memory as claimed in claim 21; as well as The controller is coupled to the memory and is used to control the memory to store data.

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