Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a display panel including a plurality of first pixels in a first display area and a plurality of second pixels in a second display area and forming pixel groups, the pixel groups being spaced apart from each other with a transmission area therebetween, the touch sensing layer includes a plurality of electrodes on the display panel, where each of the plurality of electrodes includes a first conductive line having a mesh pattern, the first conductive line including a plurality of first openings respectively corresponding to at least one of the first pixels, and at least one of the plurality of electrodes includes a second conductive line having a mesh pattern, the second conductive line including a plurality of second openings respectively corresponding to at least one of the first pixels. The second conductive line includes a plurality of second openings respectively corresponding to at least one of the second pixels.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202011621160.X filed on December 30, 2020, and invention name “Display device and electronic device including a display device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0019080, filed on February 17, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Aspects of one or more example embodiments relate to a display device and an electronic device including the display device. Background Art

[0005] Recently, various uses of display devices have become more diverse. In addition, as display devices become thinner and lighter, their scope of use has gradually expanded.

[0006] Since display devices are used in various ways and for various applications, they have been designed to have various shapes and structures. Moreover, the functions that can be combined or associated with display devices are increasing.

[0007] The above information disclosed in this Background section is only for enhancement of background understanding and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0008] Aspects of one or more example embodiments relate to a display device and an electronic device including the display device, and, for example, to a display device having an expanded display area for displaying an image even in an area where electronic components are arranged and an electronic device including the display device.

[0009] As a method of increasing functionality that can be combined with or associated with a display device, one or more example embodiments may include a display device and an electronic device including the display device, the display device including a relatively expanded display area for displaying an image even in an area where electronic components are arranged. For example, one or more example embodiments may include a display device capable of acquiring information based on external input even in an area where electronic components are arranged, and an electronic device including the display device. However, the above technical features are examples, and the scope of the example embodiments according to the present disclosure is not limited thereto.

[0010] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented exemplary embodiments of the disclosure.

[0011] According to one or more example embodiments, a display device includes a display panel and a touch sensing layer, the display panel including a plurality of first pixels arranged in a first display area and a plurality of second pixels arranged in a second display area and forming pixel groups, the pixel groups being spaced apart from each other with a transmissive area located therebetween, the touch sensing layer including a plurality of electrodes arranged on the display panel, wherein each of the plurality of electrodes includes a first conductive line having a mesh pattern, the first conductive line including a plurality of first openings corresponding to at least one of the first pixels, respectively, and at least one of the plurality of electrodes includes a second conductive line having a mesh pattern, the second conductive line including a plurality of second openings corresponding to at least one of the second pixels, respectively, wherein one of the second conductive lines extends between adjacent pixel groups in a first direction or in a second direction intersecting the first direction.

[0012] According to some example embodiments, the first conductive line may be located between two adjacent first pixels among the first pixels, and the second conductive line may be located between two adjacent second pixels among the second pixels.

[0013] According to some example embodiments, the plurality of electrodes may include first electrodes arranged in a first direction and second electrodes arranged in a second direction intersecting the first direction.

[0014] According to some example embodiments, the display panel may further include at least one first wiring extending in a first direction and at least one second wiring extending in a second direction intersecting the first direction, and one of the second conductive lines may be arranged to at least partially overlap with the at least one first wiring or the at least one second wiring.

[0015] According to some example embodiments, the first wiring may include a data line, and the second wiring may include a scan line.

[0016] According to some example embodiments, a pixel group formed by a plurality of second pixels may include a first group of second pixels and a second group of second pixels spaced apart from each other with a transmissive region located therebetween, the second wires may include a first group of second wires located between at least two second pixels in the first group of second pixels and a second group of second wires located between at least two second pixels in the second group of second pixels, and one of the second wires may extend between the first group of second wires and the second group of second wires to connect the first group of second wires to the second group of second wires.

[0017] According to some example embodiments, the pixel group formed by a plurality of second pixels may further include a third group of second pixels and a fourth group of second pixels arranged in a first direction, the second wires may include a third group of second wires located between at least two second pixels in the third group of second pixels and a fourth group of second wires located between at least two second pixels in the fourth group of second pixels, and the first group of second pixels and the second group of second pixels may be arranged in a second direction different from the first direction.

[0018] According to some example embodiments, the touch sensing layer may further include a connection conductive line configured to electrically connect the third group of the second conductive lines to the fourth group of the second conductive lines.

[0019] According to some example embodiments, the display device may further include an insulating layer between the third group of second conductive lines and the connecting conductive lines and between the fourth group of second conductive lines and the connecting conductive lines, wherein the connecting conductive lines may be connected to the third group of second conductive lines and the fourth group of second conductive lines through contact holes of the insulating layer, respectively.

[0020] According to some example embodiments, the display panel may further include at least one first wiring extending in the first direction and at least one second wiring extending in the second direction, and the connection conductive line is arranged to at least partially overlap with the at least one first wiring.

[0021] According to some example embodiments, the display panel may further include a first wiring area corresponding to an area where the at least one first wiring is located, and the connection conductive line may be arranged to overlap the first wiring area.

[0022] According to some example embodiments, the display panel may further include a second wiring area corresponding to an area where the at least one second wiring is located, and one of the second conductive lines may be arranged to overlap the second wiring area.

[0023] According to some example embodiments, a width of the connection conductive line may be smaller than a width of the first wiring region.

[0024] According to some example embodiments, the first group of second pixels or the second group of second pixels may be arranged between the third group of second pixels and the fourth group of second pixels, and the connection wire may overlap with the first group of second pixels or the second group of second pixels.

[0025] According to some example embodiments, a width of the second conductive line may be greater than a width of the first conductive line.

[0026] According to some example embodiments, the number of second pixels per the same area may be smaller than the number of first pixels per the same area.

[0027] According to some example embodiments, the plurality of electrodes may each include a metal layer.

[0028] According to some example embodiments, the first conductive line and the second conductive line may include the same material.

[0029] According to some example embodiments, the connection conductive line may include the same material as the second conductive line.

[0030] According to one or more example embodiments, an electronic device includes a display device and an electronic component, the display device including a first display area and a second display area having different resolutions, the electronic component overlapping with a transmissive area included in the second display area, wherein the display device includes a display panel and a touch sensing layer, the display panel including a plurality of pixels, the plurality of pixels including a plurality of first pixels defining a first display area and a plurality of second pixels forming a pixel group and defining a second display area, the pixel groups being spaced apart from each other with the transmissive area located therebetween, the touch sensing layer including a plurality of electrodes arranged on the display panel, wherein the plurality of electrodes include a first conductive line having a mesh pattern, the first conductive line including a plurality of first openings respectively corresponding to at least one of the first pixels, at least one of the plurality of electrodes includes a second conductive line having a mesh pattern, the second conductive line including a plurality of second openings respectively corresponding to at least one of the second pixels, and one of the second conductive lines extending between adjacent pixel groups in a first direction or a second direction intersecting the first direction.

[0031] According to some example embodiments, the display panel may further include a pixel electrode, an intermediate layer arranged on the pixel electrode, a relative electrode arranged on the intermediate layer, and a pixel defining layer covering an edge of the pixel electrode, the first conductive line may be arranged to overlap with the pixel defining layer located in the first display area, and the second conductive line may be arranged to overlap with the pixel defining layer located in the second display area.

[0032] According to some example embodiments, the plurality of electrodes may include first electrodes arranged in a first direction and second electrodes arranged in a second direction intersecting the first direction.

[0033] According to some example embodiments, the display panel may further include at least one first wiring extending in a first direction and at least one second wiring extending in a second direction intersecting the first direction, and one of the second conductive lines is arranged to at least partially overlap with the at least one first wiring or the at least one second wiring.

[0034] According to some example embodiments, a pixel group formed by a plurality of second pixels may include a first group of second pixels and a second group of second pixels spaced apart from each other with a transmissive region located therebetween, the second wires may include a first group of second wires located between at least two second pixels in the first group of second pixels and a second group of second wires located between at least two second pixels in the second group of second pixels, and one of the second wires may extend between the first group of second wires and the second group of second wires to connect the first group of second wires to the second group of second wires.

[0035] According to some example embodiments, the pixel group formed by a plurality of second pixels may further include a third group of second pixels and a fourth group of second pixels arranged in a first direction, the second wires may include a third group of second wires located between at least two second pixels in the third group of second pixels and a fourth group of second wires located between at least two second pixels in the fourth group of second pixels, and the first group of second pixels and the second group of second pixels may be arranged in a second direction different from the first direction.

[0036] According to some example embodiments, the touch sensing layer may further include a connecting wire configured to electrically connect the third group of the second wires to the fourth group of the second wires.

[0037] According to some example embodiments, the touch sensing layer may further include an insulating layer between the third group of second conductive lines and the connecting conductive lines and between the fourth group of second conductive lines and the connecting conductive lines, and the connecting conductive lines may be connected to the third group of second conductive lines and the fourth group of second conductive lines through contact holes of the insulating layer, respectively.

[0038] According to some example embodiments, a width of the second conductive line may be greater than a width of the first conductive line.

[0039] According to some example embodiments, the electronic component may include an imaging device or a sensor.

[0040] These and / or other aspects will become more apparent and more readily understood from the following description of example embodiments, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other aspects, features and characteristics of certain example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0042] Figure 1 is a schematic perspective view of a display device according to some example embodiments;

[0043] Figure 2 is a schematic cross-sectional view of a portion of a display device according to some example embodiments;

[0044] Figure 3 is an equivalent circuit diagram of a pixel circuit included in a display device according to some example embodiments;

[0045] Figure 4 is a schematic plan view of a touch sensing layer included in a display device according to some example embodiments;

[0046] Figure 5 is a schematic cross-sectional view of a stacked structure of a touch sensing layer included in a display device according to some example embodiments;

[0047] Figure 6 is a schematic plan view of a first conductive layer of a touch sensing layer included in a display device according to some example embodiments;

[0048] Figure 7 is a schematic plan view of a second conductive layer of a touch sensing layer included in a display device according to some example embodiments;

[0049] Figure 8 is a schematic enlarged plan view of a display device according to some example embodiments;

[0050] Figure 9 is a schematic enlarged plan view of a display device according to some example embodiments, illustrating an arrangement of pixels, a transmissive region, a wiring region, and a touch sensing layer included in the display device;

[0051] Figure 10 is a schematic enlarged plan view of a display device according to some example embodiments, illustrating an arrangement of pixels, a transmissive region, a wiring region, and a touch sensing layer included in a display panel;

[0052] Figure 11 is a schematic cross-sectional view of a portion of a display device according to some example embodiments, illustrating an arrangement of a first conductive layer and a second conductive layer of a touch sensing layer;

[0053] Figure 12 is a schematic cross-sectional view of a portion of a display device according to some example embodiments, illustrating an arrangement of a first conductive layer, a second conductive layer, a first conductive line, and a second conductive line of a touch sensing layer;

[0054] Figure 13 is a schematic plan view of a touch sensing layer included in a display device according to some example embodiments; and

[0055] Figure 14 is a schematic cross-sectional view of a touch sensing layer included in a display device according to some example embodiments. DETAILED DESCRIPTION

[0056] Reference will now be made in more detail to various aspects of some example embodiments shown in the accompanying drawings, wherein the same reference numerals indicate the same elements throughout. In this respect, the present example embodiments may have different forms and should not be construed as being limited to the description set forth herein. Accordingly, the following description of various aspects of some example embodiments is provided solely with reference to the drawings to explain various aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0057] Hereinafter, the present exemplary embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and repeated description thereof will be omitted.

[0058] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another.

[0059] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0060] It will also be understood that the terms “comprises” and / or “comprising” as used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0061] It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present.

[0062] For the convenience of explanation, the size of the elements in the drawings may be enlarged or reduced. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0063] When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in a reverse order from the described order.

[0064] In this specification, "A and / or B" means A or B, or A and B. In addition, "at least one of A and B" means A or B, or A and B.

[0065] It will be understood that when a layer, region, or element is referred to as being “connected” to another layer, region, or element, it may be “directly connected” to the other layer, region, or element and / or may be “indirectly connected” to the other layer, region, or element with other layers, regions, or elements intervening. For example, it will be understood that when a layer, region, or element is referred to as being “electrically connected” to another layer, region, or element, it may be “directly electrically connected” to the other layer, region, or element, or may be “indirectly electrically connected” to the other layer, region, or element with other layers, regions, or elements intervening.

[0066] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0067] Figure 1 is a schematic perspective view of a display device 1 according to some example embodiments.

[0068] Reference Figure 1 The display device 1 includes a first display area DA1, a second display area DA2, and a surrounding area SA. The first display area DA1 and the second display area DA2 both emit light, and the surrounding area SA does not emit light. The second display area DA2 may be arranged adjacent to the first display area DA1, and the surrounding area SA may be arranged outside the first display area DA1.

[0069] According to some example embodiments, Figure 1 , a second display area DA2 is shown arranged inside the first display area DA1. However, according to some example embodiments, the number of second display areas DA2 may be two or more, and the shapes and sizes of the plurality of second display areas DA2 may be different from each other. The surrounding area SA may be a non-display area where no pixels are arranged. The first display area DA1 may be completely or partially surrounded by the surrounding area SA.

[0070] Despite Figure 1 , the second display area DA2 is shown as being substantially quadrilateral, but embodiments are not limited thereto. In a plan view (when viewed in a direction perpendicular to one surface of the substrate), the shape of each second display area DA2 may be variously modified, such as circular, elliptical, polygonal including a quadrilateral, star-shaped, and prismatic.

[0071] In addition, although Figure 1, the second display area DA2 is shown as being arranged on one side (upper right side) of the first display area DA1 having a quadrangular shape, but the embodiment is not limited thereto. According to some example embodiments, the second display area DA2 may be arranged on one side (e.g., upper left side or upper center) of the first display area DA1 having a quadrangular shape.

[0072] In addition, despite the Figure 1 , the second display area DA2 is shown to be completely surrounded by the first display area DA1, but the embodiment is not limited thereto. According to some example embodiments, the second display area DA2 may be partially surrounded by the first display area DA1, and a side of the second display area DA2 not surrounded by the first display area DA1 may be surrounded by the surrounding area SA.

[0073] Hereinafter, although the display device 1 according to some example embodiments is described as including an organic light-emitting display panel as an example, the display device 1 according to some example embodiments is not limited thereto. For example, according to some example embodiments, the display device 1 may include various other types of display devices or light-emitting components, such as an inorganic light-emitting display panel and a quantum dot light-emitting display panel. For example, the emission layer of the display element provided to the display panel 10 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

[0074] The display device 1 can provide a specific image by using light emitted from a plurality of pixels PX arranged in the first display area DA1 and the second display area DA2. A first pixel array in which the first pixels PX1 are two-dimensionally arranged may be located in the first display area DA1, and a second pixel array in which the second pixels PX2 are two-dimensionally arranged may be located in the second display area DA2.

[0075] The display device 1 may display a first image (or a main image) by using light emitted from the first pixels PX1 arranged in the first display area DA1, and may display a second image (or an auxiliary image) by using light emitted from the second pixels PX2 arranged in the second display area DA2. The first image and the second image may correspond to multiple parts of the same image, or may be independent images. According to some example embodiments, the resolution of the second image provided in the second display area DA2 may be lower than the resolution of the first image provided in the first display area DA1.

[0076] The display device 1 may include electronic components in the second display area DA2, and the second display area DA2 may include a transmissive area TA for driving of the electronic components.

[0077] Figure 2 is a schematic cross-sectional view of a portion of a display device 1 according to some example embodiments.

[0078] Reference Figure 2 , the display device 1 may include a display panel 10 and an electronic component 20 overlapping the display panel 10 .

[0079] The display panel 10 may include a substrate 100 , a display layer 200 on the substrate 100 , a thin film encapsulation layer 300 on the display layer 200 , a touch sensing layer 40 , an optical functional layer 50 , and a light blocking layer BML.

[0080] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer.

[0081] The display layer 200 may be arranged on a first surface (e.g., top surface) of the substrate 100, and the bottom protective film 175 may be arranged on a second surface (e.g., bottom surface) of the substrate 100 opposite to the first surface. The bottom protective film 175 may be attached to the second surface of the substrate 100. An adhesive layer may be arranged between the bottom protective film 175 and the substrate 100. Alternatively, the bottom protective film 175 may be formed directly on the second surface of the substrate 100. In this case, no adhesive layer may be arranged between the bottom protective film 175 and the substrate 100.

[0082] The bottom protective film 175 may support and protect the substrate 100. The bottom protective film 175 may include an opening 175OP corresponding to the second display area DA2. The bottom protective film 175 may improve the transmittance of the second display area DA2, for example, the transmittance of the transmissive area TA, by including the opening 175OP. The bottom protective film 175 may include polyethylene terephthalate (PET) or polyimide (PI).

[0083] The display layer 200 may include a circuit layer, a display element layer, and an insulating layer IL. The circuit layer includes a thin film transistor (TFT), and the display element layer includes an organic light-emitting diode (OLED) as a display element. The thin film transistor (TFT) and the organic light-emitting diode (OLED) electrically connected to the thin film transistor (TFT) may be arranged in each of the first display area DA1 and the second display area DA2. The second display area DA2 may include a transmissive area TA where the thin film transistor (TFT) and the organic light-emitting diode (OLED) are not arranged.

[0084] The transmission area TA is a region through which light output from and / or guided to the electronic component 20 can pass. The transmittance of the transmission area TA may be about 50% or more, about 60% or more, about 75% or more, about 80% or more, about 85% or more, or about 90% or more.

[0085] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to some example embodiments, the thin film encapsulation layer 300 may include first and second inorganic encapsulation layers 310 and 330 and an organic encapsulation layer 320 interposed therebetween.

[0086] The touch sensing layer 40 can obtain coordinate information based on external input (e.g., a touch event). The touch sensing layer 40 may include sensing electrodes and signal lines connected to the sensing electrodes. The touch sensing layer 40 may sense external input using mutual capacitance or self-capacitance.

[0087] The touch sensing layer 40 may be formed on the thin film encapsulation layer 300. Alternatively, the touch sensing layer 40 may be formed separately and then coupled to the thin film encapsulation layer 300 through an adhesive layer such as an optically clear adhesive (OCA). Figure 2 As shown in FIG, the touch sensing layer 40 may be formed directly on the thin film encapsulation layer 300. In this case, the adhesive layer may not be disposed between the touch sensing layer 40 and the thin film encapsulation layer 300.

[0088] The optical function layer 50 may be formed on the touch sensing layer 40. The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce reflectivity of light (external light) incident from the outside toward the display panel 10.

[0089] A light blocking layer BML may be disposed between the substrate 100 and the display layer 200. For example, the light blocking layer BML may be disposed between the thin film transistor TFT and the substrate 100.

[0090] The light-blocking layer BML may include an opening BML-OP corresponding to the transmissive area TA. The light-blocking layer BML may define the opening BML-OP and include a portion including a light-blocking material (e.g., metal or black ink, etc.) provided to the light-blocking layer BML. The portion of the light-blocking layer BML including the light-blocking material may be arranged to cover the first display area DA1 and a portion of the second display area DA2. The portion of the light-blocking layer BML covering the first display area DA1 and the portion of the light-blocking layer BML covering a portion of the second display area DA2 may be connected to each other as a whole. For example, the light-blocking layer BML may be arranged to correspond to the entire area of the first display area DA1 and the second display area DA2 of the display panel 10, excluding the transmissive area TA.

[0091] like Figure 2As shown in FIG, the light blocking layer BML may be disposed on the substrate 100. Alternatively, the light blocking layer BML may be disposed in a multi-layer structure of the substrate 100. For example, the light blocking layer BML may be disposed between a plurality of sub-layers constituting the substrate 100. The light blocking layer BML is not an essential element and may be omitted according to embodiments.

[0092] The electronic component 20 may be located in the second display area DA2. The electronic component 20 may include electronic components that use light or sound. For example, the electronic component may include a sensor that measures distance (such as a proximity sensor), a sensor that recognizes a part of the user's body (e.g., a fingerprint, iris, face, etc.), a small light that outputs light, or an image sensor that captures an image (e.g., a camera). Electronic components that use light may use light of various wavelength bands, including visible light, infrared light, and ultraviolet light. Electronic components that use sound may use ultrasonic waves or sounds of other frequency bands.

[0093] One or more electronic components 20 may be arranged in the second display area DA2. According to some example embodiments, the electronic component 20 may include a light emitter and a light receiver. The light emitter and the light receiver may be provided as one integrated structure, or a pair of light emitters and light receivers having physically separate structures may constitute one electronic component 20.

[0094] Figure 3 is an equivalent circuit diagram of a pixel circuit PC included in the display device 1 according to some example embodiments.

[0095] Reference Figure 3 The display panel 10 includes a pixel circuit PC, which includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cap. In addition, the display panel 10 may include an organic light emitting diode OLED as an emission element, which emits light by receiving a driving voltage from the pixel circuit PC.

[0096] The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor. Figure 3 As shown in , the thin film transistors may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7. According to some example embodiments, the pixel circuit PC may include additional components or fewer components, and the structure of the pixel circuit PC may vary without departing from the spirit and scope of the embodiments according to the present disclosure.

[0097] A gate electrode of the driving thin film transistor T1 is connected to an electrode of the storage capacitor Cap, one of a source electrode and a drain electrode of the driving thin film transistor T1 is connected to a driving voltage line PL via an operation control thin film transistor T5, and the other of the source electrode and the drain electrode of the driving thin film transistor T1 is electrically connected to a pixel electrode of the organic light emitting diode OLED via an emission control thin film transistor T6. The driving thin film transistor T1 is configured to receive a data signal Dm according to a switching operation of the switching thin film transistor T2 and to supply a driving current Id to the organic light emitting diode OLED.

[0098] A gate electrode of the switching thin film transistor T2 is connected to the first scan line SL, one of a source electrode and a drain electrode of the switching thin film transistor T2 is connected to the data line DL, and the other of the source electrode and the drain electrode of the switching thin film transistor T2 is connected to the driving thin film transistor T1 and is connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to a scan signal Sn transmitted through the first scan line SL and is configured to perform a switching operation to transmit a data signal Dm transmitted through the data line DL to the driving thin film transistor T1.

[0099] The gate electrode of the compensation thin film transistor T3 is connected to the first scan line SL, one of the source electrode and the drain electrode of the compensation thin film transistor T3 is connected to the driving thin film transistor T1 and is connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6, and the other of the source electrode and the drain electrode of the compensation thin film transistor T3 is connected to the electrode of the storage capacitor Cap, the first initialization thin film transistor T4, and the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the first scan line SL and is configured to cause the driving thin film transistor T1 to be diode-connected by electrically connecting the gate electrode of the driving thin film transistor T1 to one of the source electrode and the drain electrode of the driving thin film transistor T1 (e.g., the drain electrode).

[0100] A gate electrode of the first initialization thin film transistor T4 is connected to the second scan line SL-1, one of a source electrode and a drain electrode of the first initialization thin film transistor T4 is connected to the first initialization voltage line VL1, and the other of the source electrode and the drain electrode of the first initialization thin film transistor T4 is connected to an electrode of the storage capacitor Cap, the compensation thin film transistor T3, and the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to a previous scan signal Sn-1 transmitted through the second scan line SL-1, and is configured to perform an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1 by transmitting an initialization voltage Vint to the gate electrode of the driving thin film transistor T1.

[0101] A gate electrode of the operation control thin film transistor T5 is connected to the emission control line EL, one of the source electrode and the drain electrode of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the other of the source electrode and the drain electrode of the operation control thin film transistor T5 is connected to the driving thin film transistor T1 and the switching thin film transistor T2.

[0102] A gate electrode of the emission control thin film transistor T6 is connected to the emission control line EL, one of the source electrode and the drain electrode of the emission control thin film transistor T6 is connected to the driving thin film transistor T1 and the compensation thin film transistor T3, and the other of the source electrode and the drain electrode of the emission control thin film transistor T6 is electrically connected to the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0103] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL to allow the driving voltage ELVDD to be transmitted to the organic light emitting diode OLED, and thus, the driving current Id flows through the organic light emitting diode OLED.

[0104] The gate electrode of the second initialization thin film transistor T7 may be connected to the third scan line SL+1 of the pixels arranged in the next row of the corresponding pixels PX. In addition, one of the source electrode and the drain electrode of the second initialization thin film transistor T7 is connected to the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the other of the source electrode and the drain electrode of the second initialization thin film transistor T7 is connected to the second initialization voltage line VL2.

[0105] The first scan line SL may be electrically connected to the third scan line SL+1, and thus, the same scan signal Sn may be applied to the third scan line SL+1. Therefore, the second initialization thin film transistor T7 may be turned on in response to the scan signal Sn transmitted through the third scan line SL+1, and may perform an operation of initializing the pixel electrode of the organic light emitting diode OLED.

[0106] In another example, the first initialization thin film transistor T4 and the second initialization thin film transistor T7 may be simultaneously connected to the second scan line SL- 1 .

[0107] One electrode of the storage capacitor Cap is connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED can display an image by receiving the driving current Id from the driving thin film transistor T1 and emitting light.

[0108] Despite Figure 3FIG shows that the pixel circuit PC includes seven thin film transistors T1, T2, T3, T4, T5, T6, and T7 and one storage capacitor Cap, but the embodiments of the present disclosure are not limited thereto. The number of thin film transistors and the number of storage capacitors can be variously modified according to the design of the pixel circuit PC.

[0109] Figure 4 is a schematic plan view of a touch sensing layer 40 included in the display device 1 according to some example embodiments.

[0110] Reference Figure 4 , the touch sensing layer 40 may include a plurality of electrodes and signal lines. More specifically, the touch sensing layer 40 may include a plurality of electrodes and signal lines. The plurality of electrodes include a first sensing electrode 410, a first connecting electrode 411, a second sensing electrode 420, and a second connecting electrode 421. The signal lines include first signal lines 415-1, 415-2, 415-3, and 415-4 respectively connected to the first sensing electrode 410, and second signal lines 425-1, 425-2, 425-3, 425-4, and 425-5 respectively connected to the second sensing electrode 420.

[0111] First sensing electrodes 410 may be arranged in the y-direction, and second sensing electrodes 420 may be arranged in the x-direction intersecting the y-direction. First sensing electrodes 410 arranged in the y-direction may be connected to each other via first connection electrodes 411 between adjacent first sensing electrodes 410, forming first sensing lines 410C1, 410C2, 410C3, and 410C4. Second sensing electrodes 420 arranged in the x-direction may be connected to each other via second connection electrodes 421 between adjacent second sensing electrodes 420, forming second sensing lines 420R1, 420R2, 420R3, 420R4, and 420R5. First sensing lines 410C1 to 410C4 and second sensing lines 420R1 to 420R5 may intersect with each other. For example, first sensing lines 410C1 to 410C4 and second sensing lines 420R1 to 420R5 may be perpendicular to each other.

[0112] The first sensing lines 410C1 to 410C4 may be connected to the pads of the sensing signal pad unit 440 through the first signal lines 415-1 to 415-4 formed in the surrounding area SA. For example, each of the first signal lines 415-1 to 415-4 may have a dual routing structure in which the first signal lines 415-1 to 415-4 are respectively connected to the upper and lower sides of the first sensing lines 410C1 to 410C4. Each of the first signal lines 415-1 to 415-4 respectively connected to the upper and lower sides of the first sensing lines 410C1 to 410C4 may be connected to corresponding first pads 441C1 and 441C2.

[0113] The second sensing lines 420R1 to 420R5 may be connected to the pads of the sensing signal pad unit 440 through second signal lines 425-1 to 425-5 formed in the surrounding area SA. For example, each of the second signal lines 425-1 to 425-5 may be connected to a corresponding second pad 442R.

[0114] The ground line may be arranged in the surrounding area SA to prevent damage caused by static electricity introduced into the touch sensing layer 40 from the outside (eg, static electricity introduced into the surrounding area SA). Figure 4 A first ground line 461 extending along the left and upper sides of the surrounding area SA and a second ground line 462 extending along the right side of the surrounding area SA are shown. The first ground line 461 and the second ground line 462 may be spaced apart from each other by a certain interval. Figure 4 1 shows that the first ground line 461 and the second ground line 462 are spaced apart from each other in an area of the surrounding area SA adjacent to the upper right side of the display area DA. The first ground line 461 and the second ground line 462 may be connected to corresponding pads 446a and 446b, respectively. Each of the first ground line 461 and the second ground line 462 may have a voltage level of a constant voltage (e.g., zero voltage, a negative direct current (DC) voltage, or a positive DC voltage). The first ground line 461 and the second ground line 462 may have different levels of constant voltage or the same level of constant voltage.

[0115] Guard lines may be arranged around the group of first signal lines 415-1 to 415-4 and the group of second signal lines 425-1 to 425-5 to prevent interference between adjacent lines or wirings. Figure 4 As shown in FIG, the first protection line 451 may be located between the first ground line 461 and the group of the upper first signal lines 415-1 to 415-4. The second protection line 452 may be located between the second ground line 462 and the group of the second signal lines 425-1 to 425-5. The third protection line 453 may be located between the group of the upper first signal lines 415-1 to 415-4 and the group of the lower first signal lines 415-1 to 415-4, and the fourth protection line 454 may be located between the group of the lower first signal lines 415-1 to 415-4 and the group of the second signal lines 425-1 to 425-5. The first protection line 451, the second protection line 452, the third protection line 453, and the fourth protection line 454 may be connected to the corresponding pads 445a, 445b, 445c, and 445d, respectively. Each of the first, second, third, and fourth protection lines 451, 452, 453, and 454 may have a constant voltage level. For example, the first, second, third, and fourth protection lines 451, 452, 453, and 454 may have different levels of constant voltage or the same level of constant voltage.

[0116] although Figure 4 A dual routing structure is shown in which the first signal lines 415-1 to 415-4 are respectively connected to the upper and lower sides of the first sensing lines 410C1 to 410C4, but embodiments of the present disclosure are not limited thereto. According to some example embodiments, the first signal lines 415-1 to 415-4 may be connected only to the upper or lower sides of the first sensing lines 410C1 to 410C4.

[0117] Figure 5 is a schematic cross-sectional view of a stacked structure of a touch sensing layer 40 according to some example embodiments.

[0118] Reference Figure 5 The touch sensing layer 40 may include a first conductive layer 42 and a second conductive layer 44. A first insulating layer 41 may be disposed below the first conductive layer 42, a second insulating layer 43 may be disposed between the first conductive layer 42 and the second conductive layer 44, and a third insulating layer 45 may be disposed on the second conductive layer 44. Figure 4 Each of the described first sensing electrode 410 , first connection electrode 411 , second sensing electrode 420 , and second connection electrode 421 may be included in one of the first conductive layer 42 and the second conductive layer 44 .

[0119] The first conductive layer 42 and the second conductive layer 44 may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), mendelevium (Md), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In addition, the transparent conductive layer may include a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, graphene, etc.

[0120] Each of the first conductive layer 42 and the second conductive layer 44 may be a single layer or a multilayer. The first conductive layer 42 and the second conductive layer 44, each comprising a single layer, may include a single metal layer or a single transparent conductive layer, and the materials of the metal layer and the transparent conductive layer are as described above. One of the first conductive layer 42 and the second conductive layer 44 may include a single metal layer. The single metal layer may include a Mo layer or an alloy layer of MoMd.

[0121] One of the first conductive layer 42 and the second conductive layer 44 may include a multilayer metal layer. The multilayer metal layer may include, for example, three layers of Ti layer / Al layer / Ti layer, or two layers of Mo layer / Md layer. Alternatively, the multilayer metal layer may include a metal layer and a transparent conductive layer. The first conductive layer 42 and the second conductive layer 44 may have different stacking structures or the same stacking structure. For example, the first conductive layer 42 may include a metal layer, and the second conductive layer 44 may include a transparent conductive layer. Alternatively, the first conductive layer 42 and the second conductive layer 44 may include the same metal layer.

[0122] The materials of the first conductive layer 42 and the second conductive layer 44 and the sensing electrodes ( Figure 4 The arrangement of electrodes 410 and 420 can be determined based on sensing sensitivity. Resistance-capacitance (RC) delay can affect sensing sensitivity, and the resistance of each sensing electrode including a metal layer is smaller than that of a transparent conductive layer, thereby reducing the RC value. Consequently, the charging time of the capacitor defined between the sensing electrodes can be shortened. Compared to a metal layer, sensing electrodes including a transparent conductive layer can be invisible to the user and can increase the input area, thereby increasing capacitance.

[0123] Each of the first insulating layer 41, the second insulating layer 43, and the third insulating layer 45 may include an inorganic insulating material and / or an organic insulating material. The inorganic insulating material may include silicon oxide, silicon nitride, or silicon oxynitride, and the organic insulating material may include a polymer organic material.

[0124] Reference Figure 4 Some of the described first and second sensing electrodes 410 and 420 and first and second connection electrodes 411 and 421 may be disposed on the first conductive layer 42 , while others may be disposed on the second conductive layer 44 .

[0125] According to some example embodiments, the first conductive layer 42 may include a first connection electrode 411 (see Figure 4 ), and the second conductive layer 44 may include a first sensing electrode 410 and a second sensing electrode 420 (see Figure 4 ) and the second connecting electrode 421 (see Figure 4According to some example embodiments, the first conductive layer 42 may include the first and second sensing electrodes 410 and 420 and the second connection electrode 421, and the second conductive layer 44 may include the first connection electrode 411. According to some example embodiments, the first conductive layer 42 may include the first sensing electrode 410 and the first connection electrode 411, and the second conductive layer 44 may include the second sensing electrode 420 and the second connection electrode 421. In this case, the first sensing electrode 410 and the first connection electrode 411 may be provided on the same layer to be integrally connected to each other, and the second sensing electrode 420 and the second connection electrode 421 may also be provided on the same layer, and therefore, no contact hole may be provided in the insulating layer between the first conductive layer 42 and the second conductive layer 44.

[0126] Despite Figure 5 , the touch sensing layer 40 includes a first insulating layer 41, a first conductive layer 42, a second insulating layer 43, a second conductive layer 44, and a third insulating layer 45, but according to some example embodiments, the first insulating layer 41 under the first conductive layer 42 may be omitted.

[0127] Figure 6 is a schematic plan view of a first conductive layer 42 of a touch sensing layer 40 included in the display device 1 according to some example embodiments, and Figure 7 is a schematic plan view of a second conductive layer 44 of a touch sensing layer 40 included in the display device 1 according to some example embodiments. Figure 6 and Figure 7 The first conductive layer 42 and the second conductive layer 44 in the first display area DA1 of the touch sensing layer 40 are respectively shown.

[0128] Each of the first sensing electrode 410 and the second sensing electrode 420 and the first connection electrode 411 and the second connection electrode 421 may have a mesh (or grid) pattern. When the first sensing electrode 410 and the second sensing electrode 420 include a metal layer, the first sensing electrode 410 and the second sensing electrode 420 may have a mesh pattern. Figure 6 and Figure 7 , so as to prevent first sensing electrode 410 and second sensing electrode 420 from being visible to a user and / or so as to transmit light emitted from each pixel.

[0129] Reference Figure 6 The first conductive layer 42 of the touch sensing layer 40 may include a first connection electrode 411. The first connection electrode 411 may include a first conductive line CL1 having a mesh pattern and may include an opening 411OP surrounded by the first conductive line CL1. The opening 411OP may be arranged to overlap with the first pixel PX1 of the display panel 10.

[0130] The first connection electrodes 411 may electrically connect the first sensing electrodes 410 to each other, and the first sensing electrodes 410 are formed on a different layer from the first connection electrodes 411. The first connection electrodes 411 electrically connecting adjacent first sensing electrodes 410 may be formed on the second insulating layer 43 (see FIG. Figure 5 ) is connected to the first sensing electrode 410.

[0131] Reference Figure 7 The second conductive layer 44 of the touch sensing layer 40 may include a first sensing electrode 410, a second sensing electrode 420, and a second connection electrode 421. The first sensing electrode 410, the second sensing electrode 420, and the second connection electrode 421 may include a first conductive line CL1 having a mesh pattern, and may include openings 410OP, 420OP, and 421OP, respectively, surrounded by the first conductive line CL1. The openings 410OP, 420OP, and 421OP may be arranged to overlap with the first pixel PX1 of the display panel 10.

[0132] The second sensing electrodes 420 may be connected to each other through a second connection electrode 421 formed on the same layer as the second sensing electrodes 420. For example, the second sensing electrode 420 may include the same material as the second connection electrode 421 and may be integrally formed therewith.

[0133] The first sensing electrodes 410 may be electrically connected to each other through first connection electrodes 411 formed on a layer different from the first sensing electrodes 410. The first sensing electrodes 410 may be electrically connected to each other through first connection electrodes 411 formed on a layer different from the first sensing electrodes 410. Figure 5 ) is connected to the first sensing electrode 410.

[0134] Figure 8 is a schematic enlarged plan view of a display device 1 according to some example embodiments. Figure 8 The second display area DA2 of the display device 1 and the touch sensing layer 40 arranged in a portion of the first display area DA1 adjacent to the second display area DA2 are shown.

[0135] Reference Figure 8 A first pixel array in which a plurality of first pixels PX1 are two-dimensionally arranged in the x-direction and the y-direction different from the x-direction may be located in the first display area DA1. A second pixel array in which a plurality of second pixels PX2 are two-dimensionally arranged in the x-direction and the y-direction and spaced apart from each other with a transmissive area therebetween may be located in the second display area DA2.

[0136] The number of first pixels PX1 per the same area in the first display area DA1 may be greater than the number of second pixels PX2 per the same area in the second display area DA2. Accordingly, the resolution of the first image provided in the first display area DA1 may be higher than the resolution of the second image provided in the second display area DA2.

[0137] As reference Figure 6 and Figure 7 As described, a plurality of electrodes including the first and second conductive lines CL1 and CL2 having a mesh pattern may be arranged on the display panel 10 including the plurality of pixels PX.

[0138] At least one of the first sensing electrode 410, the second sensing electrode 420, the first connection electrode 411, and the second connection electrode 421 may at least partially overlap with the second display area DA2. Figure 8 4 shows that the first sensing electrode 410 , the second sensing electrode 420 , the first connection electrode 411 , and the second connection electrode 421 at least partially overlap with the second display area DA2 .

[0139] Reference Figure 8 The first sensing electrodes 410 arranged in the y direction and the second sensing electrodes 420 arranged in the x direction may be arranged across the boundary between the first display area DA1 and the second display area DA2. In addition, the first connection electrode 411 and the second connection electrode 421 may be arranged in the second display area DA2.

[0140] As a comparative example, the plurality of electrodes may not be arranged in the second display area DA2. In this case, coordinate information based on external input (e.g., a touch event) may not be obtained in the second display area DA2. In addition, sensing sensitivity may be degraded in the area of the first display area DA1 adjacent to the second display area DA2.

[0141] However, according to some example embodiments, since a plurality of electrodes are also arranged in the second display area DA2 in addition to the first display area DA1, coordinate information according to a touch event can be obtained in the second display area DA2. In addition, degradation of sensing sensitivity that may occur in an area of the first display area DA1 adjacent to the second display area DA2 can be prevented or minimized.

[0142] The second display area DA2 may be provided with a pixel circuit PC (see FIG. Figure 3 ) wiring WL.

[0143] In the following, reference will be made to Figure 9 and Figure 10The arrangement of pixels, transmissive regions, wiring regions, and touch sensing layers is described in more detail.

[0144] Figure 9 is a schematic enlarged plan view of a display panel 10 according to some example embodiments, illustrating an arrangement of pixels, a transmissive region, a wiring region, and a touch sensing layer included in the display panel 10 . Figure 9 Corresponds to Figure 8 of District IX.

[0145] Reference Figure 9 , the plurality of second pixels PX2 arranged in the second display area DA2 may be grouped in preset units to constitute a pixel group PG. Figure 9 , eight second pixels PX2 are defined as constituting one pixel group PG, but the embodiment of the present disclosure is not limited thereto. The number of second pixels PX2 constituting one pixel group PG may be modified according to the resolution of the second display area DA2.

[0146] Reference Figure 9 , a pixel group PG formed by a plurality of second pixels PX2 may include a first group of second pixels PX21 and a second group of second pixels PX22, and the first group of second pixels PX21 and the second group of second pixels PX22 may be spaced apart from each other with a transmission area TA located therebetween. The first group of second pixels PX21 and the second group of second pixels PX22 may be arranged two-dimensionally in the x-direction and the y-direction. The pixel groups PG and the transmission area TA are repeatedly arranged, thereby forming a second pixel array.

[0147] The second display area DA2 may be provided with pixel circuits PC electrically connected to the second pixels PX2 (see Figure 3 ) of a plurality of wirings WL. The wirings WL include at least one first wiring WL1 and at least one second wiring WL2 extending in directions intersecting each other. The first wiring WL1 may include a data line DL (see Figure 3 ) or driving voltage line PL (see Figure 3 ), and the second wiring WL2 may include scan lines SL-1, SL, and SL+1 (see Figure 3 ).

[0148] The first wiring WL1 may be arranged as a whole to extend in the y direction to connect the pixel circuits PC corresponding to the second pixels PX2 arranged in the same column. The second wiring WL2 may be arranged as a whole to extend in the x direction to connect the pixel circuits PC corresponding to the second pixels PX2 arranged in the same row. The x and y directions may be orthogonal to each other, or may be different directions that are not orthogonal to each other.

[0149] The transmission area TA may be defined as an area of the second display area DA2 excluding the pixel area PA where the second pixel PX2 and the pixel circuit PC corresponding to the second pixel PX2 are located and the wiring area WA where the wiring WL is located.

[0150] The wiring area WA may include a first wiring area WA1 and a second wiring area WA2. The first wiring area WA1 may include an area where at least one first wiring WL1 is located and an area between adjacent first wirings WL1. The second wiring area WA2 may include an area where at least one second wiring WL2 is located and an area between adjacent second wirings WL2. Figure 9 The pixel area PA is indicated by a dotted line, and the wiring area WA is indicated by a double-dashed line. The shape of the transmission area TA may be variously formed according to the arrangement and shape of the second pixel PX2 and the wiring WL, such as a polygon including a quadrangle, a circle, an ellipse, and a diamond.

[0151] Reference Figure 9 , touch sensing layer 40 (see Figure 4 ) may be disposed on the display panel 10, and the touch sensing layer 40 (see Figure 4 ) may include a plurality of electrodes, namely, a first sensing electrode 410 (see Figure 4 ), the second sensing electrode 420 (see Figure 4 ), the first connection electrode 411 (see Figure 4 ) and the second connecting electrode 421 (see Figure 4 ).

[0152] The electrode may include a first conductive line CL1 disposed on the first display area DA1 and a second conductive line CL2 disposed on the second display area DA2. The first conductive line CL1 and the second conductive line CL2 may include the same material and may be formed integrally with each other.

[0153] The first conductive line CL1 may include a mesh pattern having a plurality of first openings CL1-OP, each corresponding to at least one of the first pixels PX1 arranged in the first display area DA1. The second conductive line CL2 may include a mesh pattern having a plurality of second openings CL2-OP, each corresponding to at least one of the second pixels PX2 arranged in the second display area DA2. At least one conductive line CL2-C of the second conductive lines CL2 may extend between adjacent pixel groups PG in the y-direction or in the x-direction intersecting the y-direction. The first conductive line CL1 and the second conductive line CL2 may include a mesh pattern to prevent the first conductive line CL1 and the second conductive line CL2 from being visible to a user when the first conductive line CL1 and the second conductive line CL2 include metal, and / or to transmit light emitted from each pixel PX.

[0154] The first conductive line CL1 may be arranged between two adjacent first pixels PX1 among the first pixels PX1, and the second conductive line CL2 may be arranged between two adjacent second pixels PX2 among the second pixels PX2. The second conductive line CL2 may include a first group CL21 of second conductive lines arranged between at least two second pixels PX2 among the first group PX21 of second pixels, and a second group CL22 of second conductive lines arranged between at least two second pixels PX2 among the second group PX22 of second pixels.

[0155] For example, refer to Figure 9 At least one conductive line CL2-C among the second conductive lines CL2 may extend in the x-direction from the first group CL21 of second conductive lines to connect to the second group CL22 of second conductive lines adjacent to the first group CL21 of second conductive lines. Furthermore, at least one conductive line CL2-C among the second conductive lines CL2 may extend in the y-direction from the first group CL21 of second conductive lines to connect to the second group CL22 of second conductive lines adjacent to the first group CL21 of second conductive lines. In other words, at least one conductive line CL2-C among the second conductive lines CL2 may extend between the first group CL21 of second conductive lines and the second group CL22 of second conductive lines to connect the first group CL21 of second conductive lines to the second group CL22 of second conductive lines.

[0156] At least one conductive line CL2 -C of the second conductive lines CL2 may be integrally formed with the first group CL21 of second conductive lines and / or the second group CL22 of second conductive lines and may include the same material as each other.

[0157] To minimize the reduction in the area of the transmissive area TA, the second conductive lines CL2 may be arranged to overlap the pixel area PA and the wiring area WA. That is, the first group CL21 of the second conductive lines may overlap the area where the first group PX21 of the second pixel is located, and the second group CL22 of the second conductive lines may overlap the area where the second group PX22 of the second pixel is located. Furthermore, at least one conductive line CL2-C of the second conductive lines CL2, which connects the first group PX21 of the second pixel to the second group PX22 of the second pixel, may be arranged adjacent to the first wiring line WL1 or the second wiring line WL2. Consequently, at least a portion of the at least one conductive line CL2-C may overlap the first wiring line WL1 or the second wiring line WL2. At least one conductive line CL2-C of the second conductive lines CL2 may overlap the first wiring area WA1 or the second wiring area WA2.

[0158] Reference Figure 9 The width WD2 of the second conductive line CL2 may be greater than the width WD1 of the first conductive line CL1. RC delay may affect sensing sensitivity, and when the width of the conductive line CL included in the plurality of electrodes increases, the input area also increases, which may increase the capacitance of the conductive line CL, thereby improving sensing sensitivity.

[0159] Because the second display area DA2, unlike the first display area DA1, includes a transmissive area TA without second conductive lines CL2, the area of conductive lines CL arranged per equal area in the second display area DA2 can be smaller than that in the first display area DA1. Consequently, the sensing sensitivity in the second display area DA2 can be lower than that in the first display area DA1. To address this issue, the width WD2 of the second conductive lines CL2 arranged in the second display area DA2 can be greater than the width WD1 of the first conductive lines CL1 arranged in the first display area DA1. This can improve the sensing sensitivity in the second display area DA2.

[0160] Figure 10 is a schematic enlarged plan view of a display device 1 according to some example embodiments, illustrating an arrangement of pixels, a transmissive region, a wiring region, and a touch sensing layer included in a display panel 10 . Figure 10 Corresponds to Figure 8 The arrangement of the second pixel PX2, the transmission area TA and the wiring WL in the second display area DA2 is similar to the arrangement of the second pixel PX2, the transmission area TA and the wiring WL in the second display area DA2. Figure 9 The arrangements described are the same, and the following will mainly describe the differences between them.

[0161] Reference Figure 10 , the pixel group PG formed by the plurality of second pixels PX2 may include a first group PX21 of second pixels arranged in the x-direction and a second group PX22 of second pixels. In addition, the pixel group PG may include a third group PX23 of second pixels arranged in the y-direction different from the x-direction and a fourth group PX24 of second pixels.

[0162] For example, in Figure 10 , the first group of second pixels PX21 is arranged between the third group of second pixels PX23 and the fourth group of second pixels PX24. The second group of second pixels PX22 may be arranged adjacent to the first group of second pixels PX21 in the x-direction. The second group of second pixels PX22 may be arranged between the third group of second pixels PX23 and the fourth group of second pixels PX24. In this case, the first group of second pixels PX21 may be arranged adjacent to the second group of second pixels PX22 in the x-direction.

[0163] The second conductive lines CL2 may include a third group CL23 of second conductive lines located between at least two second pixels PX2 in the third group PX23 of second pixels. In addition, the second conductive lines CL2 may include a fourth group CL24 of second conductive lines located between at least two second pixels PX2 in the fourth group PX24 of second pixels.

[0164] The touch sensing layer 40 may include a connection wire CCL that can electrically connect the third group CL23 of the second wires to the fourth group CL24 of the second wires. Figure 10 The connection conductor CCL may extend from the third group CL23 of the second conductors in the y direction to connect to the fourth group CL24 of the second conductors. The connection conductor CCL may include the same material as the second conductor CL2. The connection conductor CCL may include a Figure 4 The first connecting electrode 411 is described.

[0165] The connection conductor CCL may be arranged adjacent to the first wiring WL1, and at least a portion of the connection conductor CCL may overlap with the first wiring WL1. The connection conductor CCL may be arranged to overlap with the first wiring area WA1. Furthermore, the width WD3 of the connection conductor CCL may be smaller than the width WD4 of the first wiring area WA1. Accordingly, a reduction in the area of the transmission area TA due to the connection conductor CCL may be prevented or minimized.

[0166] The connection conductor CCL may extend through the first group of second pixels PX21 or the second group of second pixels PX22, which is arranged between the third group of second pixels PX23 and the fourth group of second pixels PX24. The connection conductor CCL may overlap with the first group of second conductive lines CL21 or the second group of second conductive lines CL22. Accordingly, the connection conductor CCL may be prevented from overlapping with the second pixel PX2 and blocking light emitted from the second pixel PX2.

[0167] exist Figure 10 In the embodiment, at least one conductive line CL2-C of the second conductive lines CL2 that connects the first group CL21 of the second conductive lines to the second group CL22 of the second conductive lines may include a conductive line CL2-C having a first conductive line CL21 connected to the second group CL22 of the second conductive lines. Figure 4 In addition, a second conductive line CL2 connecting adjacent second sensing electrodes 420 may be included in the second connection electrode 421 .

[0168] An insulating layer may be disposed between the connecting wire CCL and the third group CL23 of the second wires and between the connecting wire CCL and the fourth group CL24 of the second wires. The connecting wire CCL may be connected to the third group CL23 of the second wires and the fourth group CL24 of the second wires through contact holes CNT of the insulating layer, respectively. The insulating layer may be a second insulating layer 43 (see Figure 5 ). In order to ensure a sufficient connection area, the contact hole CNT may be positioned to overlap with the third group CL23 of the second conductive lines and the fourth group CL24 of the second conductive lines.

[0169] Figure 11 is a schematic cross-sectional view of a display device according to some example embodiments, illustrating arrangements of a first conductive layer and a second conductive layer of a touch sensing layer 40 .

[0170] Reference Figure 11 The substrate 100 may be a transparent insulating substrate including a material such as glass and quartz and have a single-layer structure. According to some example embodiments, the substrate 100 may have a multi-layer structure including a base layer and an inorganic layer, the base layer including a polymer resin.

[0171] A buffer layer 111 may be disposed over the substrate 100. The buffer layer 111 may reduce or block penetration of foreign matter, moisture, or external air from below the substrate 100, and provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may have a single-layer structure or a multi-layer structure including the above materials.

[0172] The pixel circuit PC may be disposed on the buffer layer 111 and include a thin film transistor TFT and a storage capacitor Cap. The pixel circuit PC may be disposed in the first display area DA1 and the second display area DA2, respectively. The pixel circuit PC in the first display area DA1 and the pixel circuit PC in the second display area DA2 may have the same structure.

[0173] The light blocking layer BML may be disposed between the pixel circuit PC disposed in the second display area DA2 and the substrate 100. Figure 11 , the light blocking layer BML is shown to be disposed between the substrate 100 and the buffer layer 111, but the light blocking layer BML may be disposed between a plurality of sub-layers constituting the substrate 100. The light blocking layer BML may include a light blocking material, for example, metal, black ink, dye, or the like.

[0174] The light blocking layer BML can prevent light emitted from or directed toward the electronic component 20 from passing through the pixel circuit PC (see FIG. Figure 3 ) is diffracted by the narrow gaps between the wirings connected thereto, and light emitted from the electronic component 20 is prevented from being incident on the pixel circuit PC. Accordingly, the performance of the thin film transistor TFT can be improved. According to some example embodiments, the light blocking layer BML may be connected to at least one of the source electrode, the drain electrode, and the gate electrode of the thin film transistor and may be arranged in a floating state.

[0175] The thin film transistor TFT may include a semiconductor layer A1, a gate electrode G1, a source electrode S1, and a drain electrode D1. The gate electrode G1 overlaps the channel region of the semiconductor layer A1, and the source electrode S1 and the drain electrode D1 are connected to the source region and the drain region of the semiconductor layer A1, respectively. A gate insulating layer 112 is disposed between the semiconductor layer A1 and the gate electrode G1. A first interlayer insulating layer 113 and a second interlayer insulating layer 115 may be disposed between the gate electrode G1 and the source electrode S1 or between the gate electrode G1 and the drain electrode D1.

[0176] The storage capacitor Cap may overlap the thin film transistor TFT. The storage capacitor Cap may include a first capacitor plate CE1 and a second capacitor plate CE2 that overlap each other. According to some example embodiments, the gate electrode G1 of the thin film transistor TFT may include the first capacitor plate CE1 of the storage capacitor Cap. The first interlayer insulating layer 113 may be disposed between the first capacitor plate CE1 and the second capacitor plate CE2.

[0177] The semiconductor layer A1 may include polycrystalline silicon. According to some example embodiments, the semiconductor layer A1 may include amorphous silicon. According to some example embodiments, the semiconductor layer A1 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), Ti, and zinc (Zn). The semiconductor layer A1 may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with impurities.

[0178] The gate insulating layer 112 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may have a single-layer structure or a multi-layer structure including the above-mentioned materials.

[0179] The gate electrode G1 or the first capacitor plate CE1 may include a low-resistance conductive material including Mo, Al, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including the above materials.

[0180] The first interlayer insulating layer 113 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may have a single-layer structure or a multi-layer structure including the above materials.

[0181] The second capacitor plate CE2 may include Al, platinum (Pt), palladium (Pd), Ag, magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), Cr, calcium (Ca), Mo, Ti, tungsten (W) and / or Cu, and have a single-layer structure or a multi-layer structure including the above materials.

[0182] The second interlayer insulating layer 115 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may have a single-layer structure or a multi-layer structure including the above materials.

[0183] The source electrode S1 or the drain electrode D1 may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and / or Cu, and may have a single-layer structure or a multi-layer structure including the above materials. For example, the source electrode S1 or the drain electrode D1 may have a three-layer structure of Ti layer / Al layer / Ti layer.

[0184] The pixel circuit PC may be electrically connected to the pixel electrode 210, and the pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cap. Figure 11 As shown in FIG, the pixel circuit PC may be electrically connected to the pixel electrode 210 through the contact metal CM.

[0185] The contact metal CM may be disposed on the first planarization insulating layer 117 and connected to the pixel circuit PC through a contact hole formed in the first planarization insulating layer 117. The contact metal CM may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and / or Cu, and have a single-layer structure or a multi-layer structure including the above materials.

[0186] The first planarization insulating layer 117 may include an organic insulating material. The first planarization insulating layer 117 may include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, and hexamethyldisiloxane (HMDSO). The organic insulating material of the first planarization insulating layer 117 may include a photosensitive organic insulating material.

[0187] The second planarization insulating layer 118 is disposed on the contact metal CM. The second planarization insulating layer 118 may include an organic insulating material. The second planarization insulating layer 118 may include an organic insulating material such as acrylic, BCB, polyimide, and HMDSO. The organic insulating material of the second planarization insulating layer 118 may include a photosensitive organic insulating material.

[0188] The pixel electrode 210 may be disposed on the second planarization insulating layer 118. The pixel electrode 210 may be connected to the contact metal CM through a contact hole of the second planarization insulating layer 118.

[0189] The pixel electrode 210 may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. The pixel electrode 210 may include: a reflective layer containing the above materials and a transparent conductive layer located above and / or below the reflective layer. The transparent conductive layer may include ITO, IZO, ZnO, indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer stacked sequentially.

[0190] The pixel defining layer 119 may be disposed on the pixel electrode 210. The pixel defining layer 119 may cover an edge of the pixel electrode 210 and include an opening 119OP overlapping a central portion of the pixel electrode 210.

[0191] The pixel defining layer 119 can prevent arcing, etc., from occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the opposing electrode 230 located above the pixel electrode 210. The pixel defining layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin. The pixel defining layer 119 may be formed by a method such as spin coating.

[0192] The intermediate layer 220 is disposed on the pixel defining layer 119 to correspond to the pixel electrode 210. The intermediate layer 220 may include a polymer organic material or a low molecular weight organic material that emits light having a color (eg, a set or predetermined color).

[0193] The opposing electrode 230 is arranged on the intermediate layer 220. The opposing electrode 230 may include a conductive material having a relatively low work function. For example, the opposing electrode 230 may include a (semi-) transparent layer containing Ag, Mg, Al, Ni, Cr, lithium (Li), Ca, or an alloy thereof. Alternatively, the opposing electrode 230 may also include a layer containing ITO, IZO, ZnO, or In2O3 located above / below the (semi-) transparent layer containing the above materials. According to some example embodiments, the opposing electrode 230 may include Ag and Mg. The opposing electrode 230 may be formed as a whole to entirely cover the first display area DA1 and the second display area DA2 (see Figure 1 ).

[0194] The stacked structure in which the pixel electrode 210, the intermediate layer 220, and the opposing electrode 230 are stacked may constitute a light-emitting diode, for example, an organic light-emitting diode OLED. The organic light-emitting diode OLED may emit red light, green light, or blue light. The emission area of each organic light-emitting diode OLED corresponds to a pixel. For example, the first pixel PX1 corresponds to the emission area of the organic light-emitting diode OLED arranged in the first display area DA1, and the second pixel PX2 corresponds to the emission area of the organic light-emitting diode OLED arranged in the second display area DA2. Since the opening 119OP of the pixel defining layer 119 defines the size and / or width of the emission area, the size and / or width of the first pixel PX1 and the second pixel PX2 may depend on the opening 119OP of the pixel defining layer 119.

[0195] A capping layer 250 may be formed on the opposing electrode 230. The capping layer 250 may include lithium fluoride (LiF). Alternatively, the capping layer 250 may include an inorganic insulating material such as silicon nitride and / or an organic insulating material. According to some example embodiments, the capping layer 250 may be omitted.

[0196] The thin film encapsulation layer 300 may be disposed on the cover layer 250. The organic light emitting diode OLED may be covered by the thin film encapsulation layer 300. The thin film encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0197] Each of the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may include at least one inorganic insulating material. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may be formed by chemical vapor deposition.

[0198] Organic encapsulation layer 320 may include a polymer material. Polymer materials may include acrylic resins, epoxy resins, polyimide, and polyethylene. For example, organic encapsulation layer 320 may include an acrylic resin, such as polymethyl methacrylate, polyacrylic acid, etc. Organic encapsulation layer 320 may be formed by hardening a monomer or coating a polymer.

[0199] The touch sensing layer 40 may be disposed on the thin film encapsulation layer 300. The touch sensing layer 40 may include the Figure 5 The first insulating layer 41 , the first conductive layer 42 , the second insulating layer 43 , the second conductive layer 44 , and the third insulating layer 45 are sequentially stacked as described.

[0200] exist Figure 11 In the embodiment, the first conductive layer 42 may include a first connection electrode 411 (see Figure 10 ), and the first connection electrode 411 (see Figure 10 ) may include a connecting wire CCL. The connecting wire CCL may be arranged to overlap the pixel defining layer 119 located between adjacent second pixels PX2. In addition, the second conductive layer 44 may include a second sensing electrode 420 (see Figure 10 ), and may be the second conductive line CL2 included in the second sensing electrode 420. The second conductive line CL2 may be arranged to overlap with the pixel defining layer 119. Accordingly, the second conductive line CL2 may be arranged to overlap with the reference electrode 420. Figure 10 The first conductive line CL1 may be arranged to overlap the pixel defining layer 119 between the first pixels PX1 located in the first display area DA1. Accordingly, blocking of light emitted from the emission region of the organic light emitting diode OLED may be prevented or minimized.

[0201] Figure 12is a schematic cross-sectional view of a display device according to some example embodiments, illustrating the arrangement of a first conductive layer 42 and a second conductive layer 44 of a touch sensing layer 40 . Figure 12 It may correspond to a cross section of the display device taken along line BB′, a cross section of the display device taken along line CC′, and a cross section of the display device taken along line DD′.

[0202] Since the stacking structure of the display panel 10 and the touch sensing layer 40 is similar to that of the reference Figure 11 The stacking structures described are the same, so the following will mainly describe the differences between them, and some repeated descriptions of certain components may be omitted.

[0203] Reference Figure 12 In the transmission area TA in the cross section of the display device taken along line BB', the insulating layers on the substrate 100 may each include a hole formed in the transmission area TA. For example, the gate insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 115, the first planarization insulating layer 117, the second planarization insulating layer 118 and the pixel defining layer 119 may all be located in the transmission area TA and may respectively include a first hole H1, a second hole H2, a third hole H3, a fourth hole H4, a fifth hole H5 and a sixth hole H6 that overlap with each other. In addition, the relative electrode 230 may include a hole 230H in the transmission area TA. The light blocking layer BML does not exist in the transmission area TA. For example, the light blocking layer BML may include an opening BML-OP corresponding to the transmission area TA. The opening BML-OP of the light blocking layer BML may be defined by an edge BML-E of the light blocking layer BML. Thus, the transmittance of the transmission area TA can be improved. With reference to Figure 12 In the cross-section of the display device taken along line BB', the touch sensing layer 40 includes a second conductive layer 44 including a second conductive line CL2, which may be arranged on the second insulating layer 43. The second conductive line CL2 may overlap with the pixel defining layer 119, which covers the edge of the pixel electrode 210 located in the second display area DA2. Since the second conductive line CL2 is not arranged on the transmissive area TA, even if the second conductive line CL2 includes a metal layer, degradation of the transmittance in the transmissive area TA can be prevented. In addition, the second conductive line CL2 does not overlap with the second pixel PX2, and therefore, blocking of light emitted from the emission area of the organic light emitting diode OLED can be prevented or minimized.

[0204] The pixel circuit PC, the pixel electrode 210, and the second conductive line CL2 may not overlap with the opening BML-OP of the light-blocking layer BML and may be located in a region where the light-blocking layer BML is disposed. For example, an edge BML-E of the light-blocking layer BML may be located closer to the transmissive area TA than the pixel circuit PC, the pixel electrode 210, and the second conductive line CL2, and an edge of the second conductive line CL2 adjacent to the transmissive area TA may be located at least on the same line as the edge BML-E of the light-blocking layer BML.

[0205] Reference Figure 12 In the cross section of the display device taken along line CC', the second wiring WL2 may be arranged on the gate insulating layer 112. The area where the second wiring WL2 is arranged and the area between adjacent second wirings WL2 may be defined as a second wiring area WA2. The second wiring WL2 may include scan lines SL, SL-1, and SL+1 (see Figure 3 ) or emission control line EL (see Figure 3 ).

[0206] At least one of the second conductive lines CL2-C may be disposed on the second insulating layer 43. Furthermore, at least one of the second conductive lines CL2-C may be disposed so as to overlap with the second wiring area WA2. Accordingly, since at least one of the second conductive lines CL2-C is not disposed on the transmission area TA, degradation of light transmittance in the transmission area TA may be prevented.

[0207] Reference Figure 12 In the cross section of the display device taken along line DD', the first wiring WL1 may be arranged on the second interlayer insulating layer 115. The area where the first wiring WL1 is arranged and the area between adjacent first wirings WL1 may be defined as a first wiring area WA1. The first wiring WL1 may include a data line DL (see Figure 3 ) or driving voltage line PL (see Figure 3 ).

[0208] The connection conductor CCL may be disposed on the first insulating layer 41. In addition, the connection conductor CCL may be disposed to overlap the first wiring area WA1. Accordingly, since the connection conductor CCL is not disposed on the transmission area TA, deterioration of transmittance in the transmission area TA may be prevented.

[0209] The light blocking layer BML may be disposed on the substrate 100 to correspond to the first and second wiring areas WA1 and WA2 . The light blocking layer BML may prevent light incident on the display panel 10 from being diffracted while passing through narrow gaps between the wirings WL and accidentally incident on the electronic component 20 .

[0210] Figure 13is a schematic plan view of a touch sensing layer 40 ′ included in a display device according to some example embodiments.

[0211] Reference Figure 13 , the touch sensing layer 40' may include a plurality of sensing electrodes 400 and a plurality of signal lines 435. The sensing electrodes 400 may be arranged in the first display area DA1 and may have unique coordinate information.

[0212] For example, the sensing electrodes 400 may be arranged in a matrix. The sensing electrodes 400 may be arranged around the first display area DA1, and each of the sensing electrodes 400 may be connected to each of the signal lines 435. A portion of the signal lines 435 may be arranged in the first display area DA1, and a portion of the signal lines 435 may be arranged in the surrounding area SA. The sensing electrodes 400 may obtain coordinate information using self-capacitance. Each of the sensing electrodes 400 may have a mesh pattern.

[0213] Figure 14 1 is a schematic cross-sectional view of a touch sensing layer 40 ′ included in a display device according to some example embodiments, and is a cross-sectional view of the touch sensing layer 40 ′ taken along lines X1a-X1a′ and X1b-X1b′.

[0214] Reference Figure 14 The touch sensing layer 40′ may be disposed on the display panel 10 and may include a first insulating layer 41, a conductive layer CL including the sensing electrode 400 disposed on the first insulating layer 41, and a second insulating layer 43 covering the conductive layer CL. The conductive layer CL may include the sensing electrode 400 and the signal line 435. That is, the sensing electrode 400 and the signal line 435 may be formed together in the same process and may include the same material.

[0215] The conductive layer CL (e.g., the sensing electrode 400 and the signal line 435) may include Mo, Md, Ag, Ti, Cu, Al, and alloys thereof. The first insulating layer 41 and the second insulating layer 43 may include an inorganic insulating material and / or an organic insulating material. According to some example embodiments, the first insulating layer 41 may be omitted.

[0216] According to one or more embodiments described above, a display device and an electronic device including a display device can be realized, the display device having an expanded display area that can display an image even in an area where electronic components are arranged. In particular, a display device and an electronic device including a display device can be provided, the display device being able to obtain information based on external input even in an area where electronic components are arranged, and being able to prevent degradation of sensing sensitivity in a display area adjacent to an area where electronic components are arranged. However, the scope of the present disclosure is not limited by such effects.

[0217] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined in the appended claims and their equivalents.

Claims

1. A display device comprising: a substrate, the substrate comprising a first display area and a second display area, the second display area comprising a transmissive area, a first wiring extending in a first direction on the first display area; a plurality of first display elements, the plurality of first display elements being above the first wiring and arranged in the first display area; a plurality of second display elements, the plurality of second display elements being above the first wiring and arranged in the second display area; as well as a touch sensing layer disposed on the plurality of first display elements and the plurality of second display elements, Wherein, the touch sensing layer includes: a first conductive member including a plurality of first openings in the first display area; and a second conductive member including a plurality of second openings in the second display area, The 1-1th opening among the plurality of first openings and the 2-1st opening among the plurality of second openings are arranged on a first virtual line extending in the first direction.

2. The display device according to claim 1, wherein A 1-2 opening among the plurality of first openings and a 2-2 opening among the plurality of second openings are arranged on a second virtual line extending in the first direction, and the transmission area is arranged between the 2-1 opening and the 2-2 opening.

3. The display device according to claim 2, wherein: In a plan view, some of the plurality of first display elements are arranged between the first imaginary line and the second imaginary line in the first display area.

4. The display device according to claim 1, wherein At least a portion of the second conductive member is provided integrally with at least a portion of the first conductive member.

5. The display device according to claim 1, wherein Each of the plurality of first openings corresponds to one of the plurality of first display elements. The display device according to claim 1 , wherein: The first wiring includes a scan line.

7. The display device according to claim 1, further comprising: a circuit layer, the circuit layer being connected to the first wiring; as well as A light-blocking layer is arranged between the substrate and the circuit layer.

8. The display device according to claim 7, wherein: The light blocking layer includes an opening corresponding to the transmission area.

9. The display device according to claim 7, wherein: The circuit layer includes an insulating layer including a hole corresponding to the transmission area.

10. The display device according to claim 1, wherein The plurality of second openings are provided in a quadrangular shape.

11. An electronic device comprising: a display device comprising a first display area and a second display area, the second display area having a resolution different from a resolution of the first display area; as well as an electronic component, the electronic component overlapping the second display area, Wherein, the display device includes: substrate; a first wiring extending in a first direction on the first display area; a plurality of first display elements, the plurality of first display elements being arranged in the first display area; a plurality of second display elements, the plurality of second display elements being arranged in the second display area; and a touch sensing layer disposed on the plurality of first display elements and the plurality of second display elements, Wherein, the touch sensing layer includes: a first conductive member including a plurality of first openings in the first display area; and a second conductive member including a plurality of second openings in the second display area, The 1-1th opening among the plurality of first openings and the 2-1st opening among the plurality of second openings are arranged on a first virtual line extending in the first direction.

12. The electronic device according to claim 11, wherein: A 1-2 opening among the plurality of first openings and a 2-2 opening among the plurality of second openings are arranged on a second virtual line extending in the first direction, and the transmission area is arranged between the 2-1 opening and the 2-2 opening.

13. The electronic device according to claim 12, wherein: In a plan view, some of the plurality of first display elements are arranged between the first imaginary line and the second imaginary line in the first display area.

14. The electronic device according to claim 11, wherein At least a portion of the second conductive member is provided integrally with at least a portion of the first conductive member.

15. The electronic device according to claim 11, wherein Each of the plurality of first openings corresponds to one of the plurality of first display elements.

16. The electronic device according to claim 11, wherein The first wiring includes a scan line.

17. The electronic device according to claim 11, further comprising: a circuit layer, the circuit layer being connected to the first wiring; as well as A light-blocking layer is arranged between the substrate and the circuit layer.

18. The electronic device according to claim 17, wherein: The light blocking layer includes an opening corresponding to the transmission area.

19. The electronic device according to claim 17, wherein: The circuit layer includes an insulating layer including a hole corresponding to the transmission area.

20. The electronic device according to claim 11, wherein The plurality of second openings are provided in a quadrangular shape.

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