Display device

Abstract

The display device includes: a substrate including an emission area and a sensing area; a light emitting device on the substrate to correspond to the emission region; and a light receiving device on the substrate to correspond to the sensing region, in which the light emitting device includes a pixel electrode, an emission layer on the pixel electrode, and a counter electrode on the emission layer, and the light receiving device includes a sensing electrode, an active layer on the sensing electrode, and the counter electrode on the active layer, in which the active layer includes a first layer including an electron donor material and a second layer including an electron acceptor material on the first layer, and in which the electron acceptor material is larger than the electron donor material in a thickness direction of the substrate. The thickness of the first layer is at least the thickness of the second layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10-2024-0016915, filed with the Korean Intellectual Property Office on February 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of one or more embodiments relate to a display device, and more particularly, to a structure of a display device. Background Art

[0004] Generally, a display device operates by forming a light-emitting device such as an organic light-emitting diode and a thin-film transistor on a substrate and allowing the light-emitting device to emit light.

[0005] For example, each pixel of a display device may include a light-emitting device (such as an organic light-emitting diode) in which an intermediate layer including an emission layer is located between a pixel electrode and a counter electrode. The display device generally controls whether each pixel emits light or the degree of emission through a thin-film transistor electrically connected to the pixel electrode. Some of the layers included in the intermediate layer of the light-emitting device may be provided commonly in a plurality of light-emitting devices.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0007] Aspects of one or more embodiments include a display device capable of displaying relatively high-quality images and having relatively improved detection performance. However, the embodiments are examples and do not limit the scope of the embodiments according to the present disclosure.

[0008] Additional aspects will be set forth in part in the description that follows, and in part will be apparent from the description, or may be learned by practice of the presented embodiments.

[0009] According to one or more embodiments, a display device includes: a substrate including an emission region and a sensing region; a light-emitting device located on the substrate corresponding to the emission region; and a light-receiving device located on the substrate corresponding to the sensing region, wherein the light-emitting device includes a pixel electrode, an emission layer located on the pixel electrode, and a counter electrode located on the emission layer, and the light-receiving device includes a sensing electrode, an active layer located on the sensing electrode, and the counter electrode located on the active layer, wherein the active layer includes a first layer containing an electron donor material and a second layer located on the first layer and containing an electron acceptor material, and wherein, in the thickness direction of the substrate, the thickness of the first layer is at least the thickness of the second layer.

[0010] According to some embodiments, the first layer may include a p-type organic semiconductor, and the second layer may include an n-type organic semiconductor.

[0011] According to some embodiments, the thickness of the first layer may be inversely proportional to the absorbance of the first layer.

[0012] According to some embodiments, the thickness of the first layer may be in the range of about to about .

[0013] According to some embodiments, the absorbance of the first layer may be in the range of about 0.2 to about 0.6.

[0014] According to some embodiments, the thickness of the first layer may satisfy Equation 1, Equation 1

[0015] T = 120 / a,

[0016] where T is the thickness of the first layer and a is the absorbance of the first layer.

[0017] According to some embodiments, the display device may further include a common layer located between the pixel electrode and the emission layer and between the sensing electrode and the active layer, wherein the common layer includes at least one of a hole injection layer and a hole transport layer.

[0018] According to some embodiments, the light-emitting device may further include an optical auxiliary layer located between the common layer and the emission layer, wherein the bottom surface of the emission layer directly contacts the top surface of the optical auxiliary layer.

[0019] According to some embodiments, the optical auxiliary layer may be patterned to have different thicknesses for each light-emitting device.

[0020] According to some embodiments, the bottom surface of the active layer may directly contact the top surface of the common layer.

[0021] According to some embodiments, the pixel electrode and the sensing electrode may be reflective electrodes, and the counter electrode may be a semi-transmissive semi-reflective electrode or a transmissive electrode.

[0022] According to some embodiments, the light-emitting device may have a front resonance structure, and the light-receiving device may have a non-resonance structure in which resonance phenomena are eliminated / canceled (neutralized).

[0023] According to one or more embodiments, a display device includes: a substrate; a light-emitting device located on the substrate and including a pixel electrode, an emission layer located on the pixel electrode, and a counter electrode located on the emission layer; and a light-receiving device located on the substrate and including a sensing electrode, an active layer located on the sensing electrode, and the counter electrode located on the active layer, wherein the light-emitting device and the light-receiving device further include a common layer between the pixel electrode and the emission layer and between the sensing electrode and the active layer, and wherein the bottom surface of the active layer and the top surface of the common layer are in direct contact with each other.

[0024] According to some embodiments, the common layer may include at least one of a hole injection layer and a hole transport layer, and wherein the common layer is integrally formed over the entire surface of the substrate.

[0025] According to some embodiments, the light-emitting device may further include an optical assist layer between the common layer and the emission layer, and wherein the bottom surface of the emission layer directly contacts the optical assist layer.

[0026] According to some embodiments, the optical assist layer may be patterned only in the light-emitting device and may not be located in the light-receiving device.

[0027] According to some embodiments, the active layer may include a first layer including an electron donor material and a second layer located on the first layer and including an electron acceptor material, and wherein, in the thickness direction of the substrate, the thickness of the first layer is at least the thickness of the second layer.

[0028] According to some embodiments, the first layer may include a p-type organic semiconductor, and the second layer may include an n-type organic semiconductor.

[0029] According to some embodiments, the thickness of the first layer may be inversely proportional to the absorbance of the first layer.

[0030] According to some embodiments, the pixel electrode and the sensing electrode may be reflective electrodes, and the counter electrode may be a semi-transmissive semi-reflective electrode or a transmissive electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features, and characteristics of specific embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a plan view schematically showing a part of a display device according to some embodiments;

[0033] Figure 2 is a schematic cross-sectional view showing a display device according to some embodiments;

[0034] Figure 3 is an equivalent circuit diagram showing a pixel circuit electrically connected to a light-emitting device and a sensor circuit electrically connected to a light-receiving device of a display device according to some embodiments;

[0035] Figure 4 is a plan view schematically showing a part of a display device according to some embodiments;

[0036] Figure 5 is a cross-sectional view schematically showing a part of a display device according to some embodiments;

[0037] Figure 6 is a conceptual diagram schematically showing a part of a display device according to some embodiments; and

[0038] Figure 7 is a graph comparing the external quantum efficiency according to wavelength between a display device according to a comparative example and a display device according to some embodiments. DETAILED DESCRIPTION

[0039] Now, various aspects of some embodiments will be described in more detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments will only be described hereinafter by referring to the accompanying drawings to explain aspects of the present description. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or any combination of a, b, and / or c

[0040] Since the present disclosure allows for various modifications and many embodiments, specific embodiments will be shown in the drawings and described in the detailed description. The effects and features of the present disclosure and the methods for achieving them will be elucidated by referring to the embodiments described in more detail later with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described later and can be implemented in various forms.

[0041] Now, aspects of some embodiments will be referred to in more detail. Examples of the embodiments are shown in the drawings, and in the drawings, the same elements are denoted by the same reference numerals, and thus repeated descriptions thereof will be omitted.

[0042] Although terms such as "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0043] Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0044] It will also be understood that the terms "comprising" or "including" as used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0045] It will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, the layer, region, or component may be directly on the other layer, region, or component, or may be indirectly on the other layer, region, or component with an intervening layer, region, or component between the layer, region, or component and the other layer, region, or component.

[0046] For ease of explanation, the dimensions and thicknesses of components in the drawings may be exaggerated or reduced. For example, since the dimensions and thicknesses of components in the drawings are arbitrarily shown for ease of explanation, the present disclosure is not limited thereto.

[0047] When a specific embodiment can be implemented differently, the specific process sequence may be different from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or may be performed in a sequence opposite to the described sequence.

[0048] It will be understood that when a layer, region, or component is referred to as being "connected", the layer, region, or component may be directly connected, or may be indirectly connected with an intervening layer, region, or component between the layer, region, or component. For example, when a layer, region, or component is referred to as being "electrically connected", the layer, region, or component may be directly electrically connected, or may be indirectly electrically connected with an intervening layer, region, or component between the layer, region, or component.

[0049] Figure 1is a plan view schematically showing a part of a display device according to some embodiments.

[0050] Referring Figure 1 , the display device 1 may include a display area DA in which a plurality of pixels PX are located and a peripheral area PA located outside the display area DA (e.g., in the periphery of the display area DA or outside the occupied area of the display area DA). For example, the peripheral area PA may completely surround the display area DA. The substrate 100 included in the display device 1 (see Figure 5 ) may include the display area DA and the peripheral area PA. Although Figure 1 shows a single pixel PX, the embodiments according to the present disclosure are not limited thereto, and as will be appreciated by those of ordinary skill in the art, the display device 1 may include any suitable number of multiple rows and multiple columns of pixels PX according to the design and size of the display area DA.

[0051] Each pixel PX of the display device 1 is the smallest unit for displaying an image, and the display device 1 may display a desired image through the combination of a plurality of pixels PX. For example, each pixel PX may emit light of a specific color, and the display device 1 may display a desired image by using the light emitted from the pixel PX. For example, each pixel PX may emit red light, green light, or blue light. Each pixel PX may include a light-emitting device such as an organic light-emitting diode. The pixel PX may be connected to a pixel circuit including a thin-film transistor and a storage capacitor.

[0052] The display area DA may have any shape among polygon shapes including a quadrilateral shape as shown in Figure 1 . For example, the display area DA may have a rectangular shape in which the horizontal length (e.g., the length in the x-axis direction) is greater than the vertical length (e.g., the length in the y-axis direction), a rectangular shape in which the horizontal length is less than the vertical length, or a square shape. According to some embodiments, the display area DA, the peripheral area PA, and / or the display device 1 may have one or more rounded corners. Alternatively, the display area DA may have any shape among various shapes such as an oval shape or a circular shape.

[0053] The peripheral area PA may be a non-display area in which no pixel PX is located. A driver or the like for applying an electrical signal or power to the pixel PX may be located in the peripheral area PA. A plurality of pads to which various electronic devices or a printed circuit board may be electrically connected may be located in the peripheral area PA. The plurality of pads may be located in the peripheral area PA spaced apart from each other and may be electrically connected to the printed circuit board or the integrated circuit device respectively.

[0054] Figure 2 is a schematic cross-sectional view showing a display device according to some embodiments.

[0055] Reference Figure 2 , according to some embodiments, the display device 1 may further include an optical sensor in addition to a plurality of pixels PX (see Figure 1 ). Each of the plurality of pixels PX (see Figure 1 ) may include at least one of a first light-emitting device ED1, a second light-emitting device ED2, and a third light-emitting device ED3, and the optical sensor may include a first light-receiving device PD1. The first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 may emit lights of different colors. For example, the first light-emitting device ED1 may emit green light, the second light-emitting device ED2 may emit red light, and the third light-emitting device ED3 may emit blue light.

[0056] As Figure 2 shown, the display device 1 may have a function of sensing an object (e.g., a fingerprint of a finger F) covering the touch window CW. Since at least a part of the light reflected from the user's fingerprint among the lights emitted from at least one of the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 is re-incident on the first light-receiving device PD1, the first light-receiving device PD1 may detect the reflected light. For example, since the green light emitted from the first light-emitting device ED1 is reflected by the object covering the touch window CW and re-incident on the first light-receiving device PD1, the first light-receiving device PD1 may detect the re-incident green light.

[0057] Figure 3 is an equivalent circuit diagram showing a pixel circuit electrically connected to a light-emitting device and a sensor circuit electrically connected to a light-receiving device of a display device according to some embodiments.

[0058] Reference Figure 3 , the pixel PX (see Figure 1 ) may include a light-emitting device ED and a pixel circuit PC for controlling the amount of light emitted by the light-emitting device ED, and the optical sensor may include a light-receiving device PD and a sensor circuit PC' for controlling the amount of light received by the light-receiving device PD.

[0059] Each pixel circuit PC may be connected to a scan start line GIL, a scan control line GCL, a first scan write line GWL1, a second scan write line GWL2, an emission line EML, and a data line DL. In addition, each pixel circuit PC may be connected to a first driving voltage line VDDL to which a first driving voltage ELVDD is applied, a second driving voltage line VSSL to which a second driving voltage ELVSS is applied, a first initialization voltage line to which a first initialization voltage Vint1 is applied, and a second initialization voltage line to which a second initialization voltage Vint2 is applied.

[0060] Each sensor circuit PC’ can be connected to a first scan write line GWL1, a reset line RSTL, and a fingerprint detection line FRL. In addition, each sensor circuit PC’ can be connected to a second drive voltage line VSSL to which a second drive voltage ELVSS is applied, a reset voltage line to which a reset voltage Vrst is applied, and a first initialization voltage line to which a first initialization voltage Vint1 is applied.

[0061] Each pixel circuit PC can include a plurality of transistors and at least one capacitor, and can be connected to a light-emitting device ED. The plurality of transistors can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Among the plurality of transistors, the first transistor T1 can be a driving transistor, and each of the second transistor T2 to the seventh transistor T7 can be a transistor serving as a switching device that is turned on or off according to a scan signal applied to its gate electrode.

[0062] The first transistor T1 can include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 can be connected to the first electrode of the third transistor T3 and one electrode of the storage capacitor Cst, the first electrode of the first transistor T1 can be connected to the second electrode of the second transistor T2 and the second electrode of the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0063] The light-emitting device ED emits light according to a drive current. The amount of light emitted by the light-emitting device ED can be proportional to the drive current. The light-emitting device ED can be an organic light-emitting diode including a pixel electrode, a counter electrode, and an organic emission layer located between the pixel electrode and the counter electrode. Alternatively, the light-emitting device ED can be an inorganic light-emitting diode including an inorganic emission layer located between the pixel electrode and the counter electrode, or a quantum dot light-emitting diode including a quantum dot emission layer located between the pixel electrode and the counter electrode. In addition, the light-emitting device ED can be a micro light-emitting diode. The pixel electrode of the light-emitting device ED can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the counter electrode can be connected to the second drive voltage line VSSL.

[0064] The second transistor T2 can be turned on by a scan signal of the first scan write line GWL1 to connect the first electrode of the first transistor T1 to the data line DL. The gate electrode of the second transistor T2 can be connected to the first scan write line GWL1, the first electrode of the second transistor T2 can be connected to the data line DL, and the second electrode of the second transistor T2 can be connected to the first electrode of the first transistor T1.

[0065] The third transistor T3 can be turned on by the scanning signal of the scan control line GCL to connect the gate electrode and the second electrode of the first transistor T1. That is, because when the third transistor T3 is turned on, the gate electrode and the second electrode of the first transistor T1 are connected, the first transistor T1 can be driven as a diode. The gate electrode of the third transistor T3 can be connected to the scan control line GCL, the first electrode of the third transistor T3 can be connected to the gate electrode of the first transistor T1, and the second electrode of the third transistor T3 can be connected to the second electrode of the first transistor T1.

[0066] The fourth transistor T4 can be turned on by the scanning signal of the scan start line GIL to connect the gate electrode of the first transistor T1 to the second initialization voltage line. In this case, the gate electrode of the first transistor T1 can be discharged to the second initialization voltage Vint2 of the second initialization voltage line. The gate electrode of the fourth transistor T4 can be connected to the scan start line GIL, the first electrode of the fourth transistor T4 can be connected to the second initialization voltage line, and the second electrode of the fourth transistor T4 can be connected to the gate electrode of the first transistor T1.

[0067] The fifth transistor T5 can be turned on by the emission signal of the emission line EML to connect the first electrode of the first transistor T1 to the first driving voltage line VDDL. The gate electrode of the fifth transistor T5 can be connected to the emission line EML, the first electrode of the fifth transistor T5 can be connected to the first driving voltage line VDDL, and the second electrode of the fifth transistor T5 can be connected to the first electrode of the first transistor T1.

[0068] The sixth transistor T6 can be turned on by the emission signal of the emission line EML to connect the second electrode of the first transistor T1 to the pixel electrode of the light emitting device ED. The gate electrode of the sixth transistor T6 can be connected to the emission line EML, the first electrode of the sixth transistor T6 can be connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 can be connected to the pixel electrode of the light emitting device ED. When both the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current can be supplied to the light emitting device ED.

[0069] The seventh transistor T7 can be turned on by the scanning signal of the second scan writing line GWL2 to connect the first initialization voltage line to the pixel electrode of the light emitting device ED. In this case, the pixel electrode of the light emitting device ED can be discharged to the first initialization voltage Vint1. The gate electrode of the seventh transistor T7 can be connected to the second scan writing line GWL2, the first electrode of the seventh transistor T7 can be connected to the first initialization voltage line, and the second electrode of the seventh transistor T7 can be connected to the pixel electrode of the light emitting device ED.

[0070] The storage capacitor Cst may be formed between the gate electrode of the first transistor T1 and the first driving voltage line VDDL. One electrode of the storage capacitor Cst may be connected to the gate electrode of the first transistor T1, and the other electrode of the storage capacitor Cst may be connected to the first driving voltage line VDDL. Accordingly, the storage capacitor Cst may hold the potential difference between the gate electrode of the first transistor T1 and the first driving voltage line VDDL.

[0071] The boost capacitor C BOOST may be formed between the gate electrode of the second transistor T2 and the gate electrode of the first transistor T1. The boost capacitor C BOOST has one electrode connected to the first scan write line GWL1 which is connected to the gate electrode of the second transistor T2, and the other electrode of the boost capacitor C BOOST is connected to the gate electrode of the first transistor T1 and one electrode of the storage capacitor Cst. The boost capacitor C BOOST is a boosting capacitor, and when the signal of the first scan write line GWL1 is a voltage for turning off the second transistor T2, the voltage of the node may be increased to relatively reduce the voltage for displaying black (black voltage).

[0072] Each sensor circuit PC’ may include a plurality of transistors and may be connected to the light receiving device PD. The plurality of transistors may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. Among the plurality of transistors, the eighth transistor T8 may be a driving transistor, and the ninth transistor T9 and the tenth transistor T10 may be transistors serving as switching devices that are turned on or off according to a reset signal and a scan signal applied to their gate electrodes.

[0073] When the plurality of light emitting devices ED and the plurality of light receiving devices PD are arranged in one display device 1 (see Figure 1 ), when driving the light receiving device PD, the voltage wiring or signal wiring for driving the light emitting device ED may be shared. That is, since the additional arrangement of the voltage wiring or signal wiring for driving the plurality of light receiving devices PD in the display device 1 (see Figure 1 ) is minimized, the resolution of the display device 1 (see Figure 1 ) can be ensured, and the peripheral area PA (see Figure 1 ) can be minimized. For example, connected to the pixel PX (see Figure 1) The signal wiring of the gate electrode of the second transistor T2 can be shared with the signal wiring of the gate electrode of the tenth transistor T10 connected to the optical sensor. That is, the gate electrode of the second transistor T2 and the gate electrode of the tenth transistor T10 can be connected to the first scan write line GWL1. In another example, the second driving voltage line VSSL can be a common voltage wiring connected to the counter electrode of the light-emitting device ED and the counter electrode of the light-receiving device PD. In another example, the first initialization voltage line for applying the first initialization voltage Vint1 can be a common voltage wiring connected to the first electrode of the eighth transistor T8 and the first electrode of the seventh transistor T7 connected to the optical sensor.

[0074] Each of the plurality of light-receiving devices PD can be a light-receiving diode including a sensing electrode, a counter electrode, and a photoelectric conversion layer located between the sensing electrode and the counter electrode. Each light-receiving device PD can convert the light incident from the outside into an electrical signal. The light-receiving device PD can be a light-receiving diode or a phototransistor formed of a pn-type or pin-type inorganic material. Alternatively, the light-receiving device PD can be an organic light-receiving diode including an electron donor material for generating donor ions and an electron acceptor material for generating acceptor ions.

[0075] When the light-receiving device PD is exposed to external light, photo charges can be generated, and the generated photo charges can accumulate on the sensing electrode of the light-receiving device PD. In this case, the voltage of the node electrically connected to the sensing electrode can increase. When the light-receiving device PD and the fingerprint detection line FRL are connected according to the conduction of the eighth transistor T8 and the tenth transistor T10, a current can flow through the fingerprint detection line FRL in proportion to the voltage of the node where the charges are accumulated.

[0076] The eighth transistor T8 can be turned on by the voltage applied to the gate electrode of the eighth transistor T8 to connect the first initialization voltage line to the first electrode of the tenth transistor T10. In this case, the second electrode of the tenth transistor T10 can be discharged to the first initialization voltage Vint1. The gate electrode of the eighth transistor T8 can be connected to the node between the ninth transistor T9 and the light-receiving device PD, the first electrode of the eighth transistor T8 can be connected to the first initialization voltage line, and the second electrode of the eighth transistor T8 can be connected to the first electrode of the tenth transistor T10. The eighth transistor T8 can be a source follower amplifier that generates a source-drain current proportional to the amount of charge at the node input to the gate electrode of the eighth transistor T8. In some other embodiments, the first electrode of the eighth transistor T8 can be connected to the first driving voltage line VDDL or the second initialization voltage line.

[0077] The tenth transistor T10 can be turned on by a scan signal of the first scan write line GWL1 to connect the second electrode of the eighth transistor T8 to the fingerprint detection line FRL. The fingerprint detection line FRL can transmit a fingerprint detection signal to the readout circuit. The gate electrode of the tenth transistor T10 can be connected to the first scan write line GWL1, the first electrode of the tenth transistor T10 can be connected to the second electrode of the eighth transistor T8, and the second electrode of the tenth transistor T10 can be connected to the fingerprint detection line FRL.

[0078] The ninth transistor T9 can be turned on by a reset signal of the reset line RSTL to reset the node connected to the gate electrode of the eighth transistor T8 to the reset voltage Vrst. The gate electrode of the ninth transistor T9 can be connected to the reset line RSTL, the first electrode of the ninth transistor T9 can be connected to the reset voltage line, and the second electrode of the ninth transistor T9 can be connected to the node connecting the light receiving device PD to the eighth transistor T8. When the reset driver for outputting the reset signal of the reset line RSTL is omitted, the ninth transistor T9 can be turned on by a scan signal.

[0079] When the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 is a source electrode, the second electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be a drain electrode. Alternatively, when the first electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 is a drain electrode, the second electrode of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be a source electrode.

[0080] The active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may be p-type transistors. In this case, the active layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may be formed of polysilicon. In addition, each of the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be an n-type transistor including an active layer formed of an oxide semiconductor.

[0081] However, the embodiments are not limited thereto, and each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be a p-type transistor. In another example, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be formed as p-type transistors.

[0082] Although Figure 3 various components and connections between the components are shown, embodiments according to the present disclosure are not limited thereto, and some embodiments may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0083] Figure 4 is a plan view schematically showing a part of a display device according to some embodiments. For example, Figure 4 is schematically showing Figure 1 an enlarged plan view of part A of Figure 4 is a plan view on the bank layer 215.

[0084] Referring to Figure 4 the display device 1 (see Figure 1) may include a plurality of light-emitting devices and a plurality of light-receiving devices. The plurality of light-emitting devices may include a first light-emitting device ED1, a second light-emitting device ED2, and a third light-emitting device ED3, and the plurality of light-receiving devices may include a first light-receiving device PD1. The first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 may emit lights of different colors. For example, the first light-emitting device ED1 may emit green light, the second light-emitting device ED2 may emit red light, and the third light-emitting device ED3 may emit blue light. The red light may be light belonging to a wavelength band of 580 nm to 780 nm, the blue light may be light belonging to a wavelength band of 380 nm to 495 nm, and the green light may be light belonging to a wavelength band of 495 nm to 580 nm. The first light-receiving device PD1 may sense an object by detecting light emitted from the first light-emitting device ED1, the second light-emitting device ED2, and / or the third light-emitting device ED3 and reflected by the object.

[0085] Each light-emitting device may include a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode, and each light-receiving device may include a sensing electrode, a counter electrode, and an intermediate layer located between the sensing electrode and the counter electrode. Accordingly, the first light-emitting device ED1 may include a first pixel electrode 1210, the second light-emitting device ED2 may include a second pixel electrode 2210, the third light-emitting device ED3 may include a third pixel electrode 3210, and the first light-receiving device PD1 may include a first sensing electrode 4210. The first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 may be spaced apart from each other on a substrate 100 (see Figure 5 ). In the specification, "on a plane" means when observed in a direction perpendicular to the substrate 100. That is, "A and B are spaced apart from each other on a plane" means "when observed in a direction perpendicular to the substrate 100, A and B are spaced apart from each other".

[0086] In a cross-sectional view, a bank layer 215 may be located on the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210, and may cover edges of each of the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210. That is, the bank layer 215 may include a first opening OP1 through which a central portion of the first pixel electrode 1210 is exposed, a second opening OP2 through which a central portion of the second pixel electrode 2210 is exposed, a third opening OP3 through which a central portion of the third pixel electrode 3210 is exposed, and a fourth opening OP4 through which a central portion of the first sensing electrode 4210 is exposed.

[0087] According to some embodiments, multiple emission layers for emitting light may be respectively located in the first opening OP1, the second opening OP2, and the third opening OP3 of the bank layer 215, and multiple active layers for detecting light may be respectively located in the fourth opening OP4 of the bank layer 215. In a cross-sectional view, the counter electrode may be located on the emission layer and the active layer. As described above, the stacked structure of the pixel electrode, the emission layer, and the counter electrode may constitute a light-emitting device. In addition, as described above, the stacked structure of the sensing electrode, the active layer, and the counter electrode may constitute a light-receiving device. One opening of the bank layer 215 may correspond to one light-emitting device and may define an emission region. Alternatively, one opening of the bank layer 215 may correspond to one light-receiving device and may define a sensing region.

[0088] For example, an emission layer for emitting green light may be located in the first opening OP1 such that the first opening OP1 defines a first emission region EA1. Similarly, an emission layer for emitting red light may be located in the second opening OP2 such that the second opening OP2 defines a second emission region EA2. An emission layer for emitting blue light may be located in the third opening OP3 such that the third opening OP3 defines a third emission region EA3. An active layer for detecting light may be located in the fourth opening OP4 such that the fourth opening OP4 defines a first sensing region SA1.

[0089] Therefore, the size of the area of the first opening OP1 is the same as the size of the area of the first emission region EA1. The size of the area of the second opening OP2 is the same as the size of the area of the second emission region EA2, and the size of the area of the third opening OP3 is the same as the size of the area of the third emission region EA3. The size of the area of the fourth opening OP4 is the same as the size of the area of the first sensing region SA1.

[0090] When observed in a direction (z-axis direction) perpendicular to the substrate 100 (see Figure 5 ), each of the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4 may have a polygonal shape. In other words, when observed in a direction (z-axis direction) perpendicular to the substrate 100, each of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the first sensing region SA1 may have a polygonal shape. In Figure 4In [description], when observed in a direction perpendicular to the substrate 100 (z-axis direction), each of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the first sensing region SA1 has a quadrilateral shape, specifically, a quadrilateral shape with rounded corners. However, embodiments according to the present disclosure are not limited thereto. For example, when observed in a direction perpendicular to the substrate 100 (z-axis direction), each of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the first sensing region SA1 may have a circular shape or an elliptical shape.

[0091] Figure 5 is a cross-sectional view schematically showing a part of a display device according to some embodiments. For example, Figure 5 is along Figure 4 a schematic cross-sectional view taken along line I-I' of the display device. Figure 6 is a conceptual diagram schematically showing a part of a display device according to some embodiments. For example, Figure 6 is a cross-sectional view schematically showing a light-emitting device and a light-receiving device of a display device according to some embodiments.

[0092] As Figure 5 shown in [description], the display device 1 according to the present embodiment may include a substrate 100. The substrate 100 may include various flexible materials or bendable materials. For example, the substrate 100 may include glass or metal. In addition, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. However, various modifications may be made. For example, the substrate 100 may have a multilayer structure including two layers each including a polymer resin and a barrier layer including an inorganic material (e.g., silicon oxide, silicon nitride, or silicon oxynitride) and located between the two layers.

[0093] The first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3, the first light-receiving device PD1, the pixel circuit PC, and the sensor circuit PC' may be located on the substrate 100. The pixel circuit PC may be electrically connected to each of the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3, and the sensor circuit PC' may be electrically connected to the first light-receiving device PD1.

[0094] When each of the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 is connected to the pixel circuit PC, light emission can be controlled. In addition, when the first light-receiving device PD1 is electrically connected to the sensor circuit PC’, the light direction can be controlled. The pixel circuit PC may include a plurality of thin-film transistors TFTs and a storage capacitor Cst, and may have a structure substantially the same as the structure of the pixel circuit PC described in the reference Figure 3 . For ease of explanation, Figure 5 a thin-film transistor TFT is shown in Figure 3 , and the thin-film transistor TFT may correspond to the above-described first transistor T1 (see Figure 3 ). Similarly, the sensor circuit PC’ may include a plurality of thin-film transistors TFT’s, and may have a structure substantially the same as the structure of the sensor circuit PC’ described in the reference Figure 5 . For ease of explanation, Figure 3 a thin-film transistor TFT’ is shown in

[0095] . The thin-film transistor TFT’ may correspond to the above-described eighth transistor T8 (see

[0096] As shown in Figure 5 , the thin-film transistor TFT may include a semiconductor layer Act, and the semiconductor layer Act includes amorphous silicon, polycrystalline silicon, an organic semiconductor material, or an oxide semiconductor material. The thin-film transistor TFT may also include a gate electrode GE, a source electrode SE, and / or a drain electrode DE. The gate electrode GE may include any of various conductive materials and may have any of various layer structures. For example, the gate electrode GE may include a molybdenum (Mo) layer and an aluminum (Al) layer. Alternatively, the gate electrode GE may include a titanium nitride (TiN x ) layer, an Al layer, and / or a titanium (Ti) layer. Each of the source electrode SE and the drain electrode DE may also include any of various conductive materials and may have any of various layer structures. For example, each of the source electrode SE and the drain electrode DE may include a Ti layer, an Al layer, and / or a copper (Cu) layer.

[0097] To ensure insulation between the semiconductor layer Act and the gate electrode GE, a gate insulating layer 203 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be located between the semiconductor layer Act and the gate electrode GE. Although the gate insulating layer 203 has a shape corresponding to the entire surface of the substrate 100 and includes contact holes formed in a preset portion formed in Figure 5 , this disclosure is not limited thereto. For example, the gate insulating layer 203 may be patterned into the same shape as the shape of the gate electrode GE.

[0098] An interlayer insulating layer 205 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be located on the gate electrode GE. The interlayer insulating layer 205 may have a single-layer structure or a multi-layer structure including the above materials. Such an insulating layer including an inorganic material may be formed by using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0099] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2 that overlap each other, and the interlayer insulating layer 205 is between the first electrode CE1 and the second electrode CE2. The storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, although in Figure 5 the gate electrode GE of the thin film transistor TFT is the first electrode CE1 of the storage capacitor Cst, this disclosure is not limited thereto. For example, the storage capacitor Cst may not overlap with the thin film transistor TFT. The second electrode CE2 of the storage capacitor Cst may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the above materials.

[0100] A second interlayer insulating layer 207 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be located on the second electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 207 may have a single-layer structure or a multi-layer structure including the above materials.

[0101] The source electrode SE and the drain electrode DE may be located on the second interlayer insulating layer 207. Each of the source electrode SE and the drain electrode DE may include a material having excellent conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the above materials. For example, each of the source electrode SE and the drain electrode DE may have a multi-layer structure including Ti / Al / Ti. This disclosure is not limited thereto. For example, the thin film transistor TFT may include only one of the source electrode SE and the drain electrode DE, or may not include both the source electrode SE and the drain electrode DE.

[0102] The planarization layer 208 may be positioned to cover the thin film transistor TFT and the storage capacitor Cst. The planarization layer 208 may include an organic insulating material. For example, the planarization layer 208 may include a photoresist, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer (such as polyimide), an aryl ether polymer, an amide polymer, a fluorinated polymer, a parylene polymer, a polyvinyl alcohol polymer, or a mixture thereof. According to some embodiments, a third interlayer insulating layer may be further located under the planarization layer 208. The third interlayer insulating layer may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0103] The first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1 may be located on the planarization layer 208 and spaced apart from each other. The first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 may emit lights of different colors. For example, the first light emitting device ED1 may emit green light, the second light emitting device ED2 may emit red light, and the third light emitting device ED3 may emit blue light. The first light receiving device PD1 may detect the lights emitted from the first light emitting device ED1, the second light emitting device ED2, and the third light emitting device ED3 and reflected by an object.

[0104] The first light-emitting device ED1 may include a first pixel electrode 1210, a first intermediate layer 1220, and a counter electrode 230. The second light-emitting device ED2 may include a second pixel electrode 2210, a second intermediate layer 2220, and a counter electrode 230. The third light-emitting device ED3 may include a third pixel electrode 3210, a third intermediate layer 3220, and a counter electrode 230. The first light-receiving device PD1 may include a first sensing electrode 4210, a fourth intermediate layer 4220, and a counter electrode 230. That is, the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 provided in the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1, respectively, may be patterned and provided for each pixel. The counter electrode 230 of the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1 may be provided integrally across the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1. The first intermediate layer 1220, the second intermediate layer 2220, the third intermediate layer 3220, and the fourth intermediate layer 4220 may be located between the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 and the counter electrode 230, respectively.

[0105] The first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 may be located on the substrate 100 to be spaced apart from each other. The first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 may be reflective electrodes. For example, each of the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 includes a transmissive conductive layer formed of a transmissive conductive oxide such as ITO, In2O3, or IZO, and a reflective layer formed of a metal such as Al or Ag. For example, each of the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 may have a three-layer structure including ITO / Ag / ITO.

[0106] As Figure 5As shown, each of the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 may contact any one of the source electrode SE and the drain electrode DE to be electrically connected to the thin film transistor TFT. For example, each of the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 may contact any one of the source electrode SE and the drain electrode DE through a contact hole formed in the planarization layer 208. Similarly, the first sensing electrode 4210 may be electrically connected to the thin film transistor TFT' through a contact hole formed in the planarization layer 208.

[0107] The bank layer 215 may be located on the planarization layer 208. The bank layer 215 may have openings corresponding to each of the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1 (that is, openings through which the central portions of at least one pixel electrode (or sensing electrode) are exposed) to define emission regions and sensing regions. For example, the bank layer 215 may have a plurality of openings, such as the first opening OP1 (see Figure 4 ) through which the central portions of the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210 are respectively exposed, the second opening OP2 (see Figure 4 ), the third opening OP3 (see Figure 4 ), and the fourth opening OP4 (see Figure 4 ). In addition, the bank layer 215 may increase the distance between the pixel electrode and the counter electrode 230 or the distance between the sensing electrode and the counter electrode 230. Therefore, the occurrence of arcs or the like at the edges of the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210, or the edge of the first sensing electrode 4210 can be prevented or reduced. The bank layer 215 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0108] The counter electrode 230 may be located on the first pixel electrode 1210. The counter electrode 230 may be provided integrally over the first light emitting device ED1, the second light emitting device ED2, the third light emitting device ED3, and the first light receiving device PD1. Therefore, the counter electrode 230 may also be located on the second pixel electrode 2210, the third pixel electrode 3210, and the first sensing electrode 4210. The counter electrode 230 may be a semi-transmissive semi-reflective electrode or a transmissive electrode. For example, the counter electrode 230 may be a transmissive electrode including a transmissive conductive layer formed of ITO, In2O3, or IZO, or a semi-transmissive semi-reflective electrode including a semi-transmissive semi-reflective film containing a metal such as Al or Ag. For example, the counter electrode 230 may be a semi-transmissive semi-reflective film including at least one of magnesium (Mg) and silver.

[0109] Since the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 are reflective electrodes, and the counter electrode 230 is a semi-transmissive and semi-reflective electrode, each of the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 can have a front resonance structure. When light is repeatedly reflected between the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210, which are reflective electrodes, and the counter electrode 230, which is a semi-transmissive and semi-reflective electrode, light with a specific wavelength can be amplified by constructive interference, light with other wavelengths can be suppressed, and the amplified light can pass through the counter electrode 230, which is a semi-transmissive and semi-reflective electrode, and can be emitted to the outside. That is, through the front resonance structure, the front light emission efficiency of the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 can be relatively improved.

[0110] Since the first sensing electrode 4210 is a reflective electrode and the counter electrode 230 is a semi-transmissive and semi-reflective electrode, the first light-receiving device PD1 can also have a front resonance structure. However, the first light-receiving device PD1 can eliminate the resonance phenomenon through the active layer 4223 described later. The front resonance structure of the first light-receiving device PD1 will be described in more detail later.

[0111] Referring to Figure 5 and Figure 6 , the intermediate layer can be located between the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210, and the first sensing electrode 4210 and the counter electrode 230. The intermediate layer can include a first intermediate layer 1220, a second intermediate layer 2220, a third intermediate layer 3220, and a fourth intermediate layer 4220. The first intermediate layer 1220 can be located between the first pixel electrode 1210 and the counter electrode 230. The second intermediate layer 2220 can be located between the second pixel electrode 2210 and the counter electrode 230, and the third intermediate layer 3220 can be located between the third pixel electrode 3210 and the counter electrode 230. The fourth intermediate layer 4220 can be located between the first sensing electrode 4210 and the counter electrode 230.

[0112] The first intermediate layer 1220 may include a first common layer 221, a second common layer 222, a first emission layer 1223, a buffer layer 224, a third common layer 225, and a fourth common layer 226. The second intermediate layer 2220 may include a first common layer 221, a second common layer 222, a second emission layer 2223, a buffer layer 224, a third common layer 225, and a fourth common layer 226. The third intermediate layer 3220 may include a first common layer 221, a second common layer 222, a third emission layer 3223, a buffer layer 224, a third common layer 225, and a fourth common layer 226. The fourth intermediate layer 4220 may include a first common layer 221, a second common layer 222, a first active layer 4223, a buffer layer 224, a third common layer 225, and a fourth common layer 226.

[0113] In this case, the first common layer 221, the second common layer 222, the buffer layer 224, the third common layer 225, and the fourth common layer 226 may be provided integrally throughout the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3, as well as the first light-receiving device PD1. That is, the first common layer 221, the second common layer 222, the buffer layer 224, the third common layer 225, and the fourth common layer 226 may be formed over the entire surface of the substrate 100. The emission layers 223 and the first active layer 4223 may be patterned and provided separately for each light-emitting device and light-receiving device.

[0114] According to some embodiments, the first light-emitting device ED1 may emit green light, the second light-emitting device ED2 may emit red light, and the third light-emitting device ED3 may emit blue light. To achieve such light emission, the first emission layer 1223 may emit green light, the second emission layer 2223 may emit red light, and the third emission layer 3223 may emit blue light. The first light-receiving device PD1 may detect light emitted from the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 and reflected by an object. To achieve such light detection, the first active layer 4223 may have a wide detectable light wavelength range and may absorb light in the visible wavelength band and the near-infrared wavelength band. This is due to the resonance cancellation phenomenon of the first light-receiving device PD1, and the non-resonant structure of the first light-receiving device PD1 will be described later.

[0115] The first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 may include an organic material containing a fluorescent material or a phosphorescent material that emits green light, red light, blue light, or white light. The first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 may be an organic emission layer including a low molecular weight organic material or a high molecular weight organic material. For example, the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 are organic emission layers and may include copper phthalocyanine, tris(8-hydroxyquinoline)aluminum, poly(p-phenylene vinylene) (PPV) materials, or polyfluorene materials.

[0116] According to some embodiments, the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 may include a host material and a dopant material. The dopant material is a material for emitting light of a specific color and may include a luminescent material. The luminescent material may include at least one of a phosphorescent dopant, a fluorescent dopant, and a quantum dot. The host material is the main material of the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 and helps the dopant material to emit light.

[0117] The first active layer 4223 may receive light from the outside to generate excitons, and then may separate the generated excitons into holes and electrons. When a positive (+) potential is applied to the first sensing electrode 4210 and a negative (-) potential is applied to the counter electrode 230, the holes separated in the first active layer 4223 may move toward the counter electrode 230, and the electrons separated in the first active layer 4223 may move toward the first sensing electrode 4210. Therefore, a photocurrent may be formed in the direction from the first sensing electrode 4210 to the counter electrode 230. When a bias voltage is applied between the first sensing electrode 4210 and the counter electrode 230, a dark current may flow through the first light receiving device PD1. The first light receiving device PD1 may detect the amount of light according to the ratio of the photocurrent to the dark current.

[0118] The first active layer 4223 may include a p-type organic semiconductor and an n-type organic semiconductor. According to some embodiments, the first active layer 4223 may include a first layer 4223a containing an electron donor material and a second layer 4223b containing an electron acceptor material. That is, the first active layer 4223 may have a bilayer structure in which the first layer 4223a and the second layer 4223b located on the first layer 4223a are stacked. In this case, the first layer 4223a may include a p-type organic semiconductor, and the second layer 4223b may include an n-type organic semiconductor. The p-type organic semiconductor may be used as an electron donor, and the n-type organic semiconductor may be used as an electron acceptor. The first layer 4223a including the p-type organic semiconductor and the second layer 4223b including the n-type organic semiconductor may form a pn junction. Due to the photoinduced charge separation occurring at the interface between these layers, excitons can be effectively separated into holes and electrons.

[0119] The p-type organic semiconductor included in the first layer 4223a may be a compound that serves as an electron donor for supplying electrons. According to some embodiments, the first layer 4223a may include at least one of boron subphthalocyanine chloride (SubPc) and boron sub-2,3-naphthalocyanine chloride (SubNc). When the first layer 4223a includes SubPc or SubNc, light in a wide wavelength band can be absorbed. However, the p-type organic semiconductor is not limited thereto, and the p-type organic semiconductor may be an organic compound capable of supplying electrons. Examples of the p-type organic semiconductor include, but are not limited to, triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysiloxane compounds, thiophene compounds, phthalocyanine compounds, naphthalocyanine compounds, cyanine compounds, merocyanine compounds, oxacyanine compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, fused aromatic carbocyclic compounds (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, or fluoranthene derivatives), and metal complexes having a nitrogen-containing heterocyclic compound as a ligand.

[0120] The n-type organic semiconductor included in the second layer 4223b may be a compound that serves as an electron acceptor for accepting electrons. According to some embodiments, the second layer 4223b may include at least one of perylene tetracarboxylic dianhydride (PTCDA), 1,4,5,8-naphthalenetetracarboxylic dianhydride (NTCDA), 3,4,9,10-perylenetetracarboxylic diimide (PTCDI), naphthalenetetracarboxylic diimide (NTCDI), C60 fullerene, and C70 fullerene. However, the n-type organic semiconductor is not limited thereto, and the n-type organic semiconductor may be an organic compound capable of accepting electrons. Examples of the n-type organic semiconductor may include, but are not limited to, fullerenes, fullerene derivatives, fused aromatic carbocyclic compounds (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, or fluoranthene derivatives), 5-membered to 7-membered heterocyclic compounds containing a nitrogen atom, an oxygen atom, or a sulfur atom (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzoazepine, or tribenzoazepine), polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silicon-based compounds, and metal complexes having a nitrogen-containing heterocyclic compound as a ligand.

[0121] Each of the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3 may further include an optical assist layer 223o to adjust the optical length for the microcavity. The optical assist layer 223o may be located between the hole transport region and the emission layer 223 described later. For example, the optical assist layer 223o may be located between the second common layer 222 and the emission layer 223. That is, the bottom surface of the emission layer 223 may directly contact the top surface of the corresponding optical assist layer 223o.

[0122] The optical assist layer 223o may be patterned and provided for each light-emitting device. For example, the optical assist layer 223o may include a first optical assist layer 1223o in the first light-emitting device ED1, a second optical assist layer 2223o in the second light-emitting device ED2, and a third optical assist layer 3223o in the third light-emitting device ED3. The optical assist layer 223o may increase the light emission efficiency (e.g., the front light emission efficiency) through the front resonance structure by compensating the resonance distance according to the wavelength of the light emitted from the emission layer 223. Therefore, the optical assist layer 223o may have a thickness proportional to the wavelength of the light emitted from the light-emitting device. For example, the second optical assist layer 2223o of the second light-emitting device ED2 for emitting red light having a wavelength of 580 nm to 780 nm may have to The first optical auxiliary layer 1223o of the first light-emitting device ED1 for emitting green light with a wavelength of 495 nm to 580 nm may have a thickness of to The third optical auxiliary layer 3223o of the third light-emitting device ED3 for emitting blue light with a wavelength of 380 nm to 495 nm may have a thickness of to The thickness of

[0123] Since the optical auxiliary layer 223o is located between the hole transport region and the emission layer 223, the optical auxiliary layer 223o may include materials of a hole transport layer (HTL). For example, the optical auxiliary layer 223o may be formed of the same material as that of the second common layer 222 described later. For example, the optical auxiliary layer 223o may include carbazole derivatives (such as N-phenylcarbazole or polyvinylcarbazole), fluorene derivatives, N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (TPD), triphenylamine derivatives (such as 4,4',4''-tris(N-carbazolyl)triphenylamine (TCTA), N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), 4,4'-cyclohexylidenebis[N,N'-bis(4-methylphenyl)aniline] (TAPC), 4,4'-bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl (HMTPD)), 9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole (CzSi), 9-phenyl-9H-3,9'-bicarbazole (CCP), 1,3-bis(N-carbazolyl)benzene (mCP) or 1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene (mDCP).

[0124] In contrast, the first light-receiving device PD1 may not include the optical auxiliary layer 223o for adjusting the optical distance. That is, different from the first light-emitting device ED1, the second light-emitting device ED2, and the third light-emitting device ED3, the optical auxiliary layer 223o may not be located between the first sensing electrode 4210 and the first active layer 4223. In other words, the bottom surface of the first active layer 4223 may directly contact the top surface of the second common layer 222. This can achieve a high-resolution image in the display device 1.

[0125] As a comparative example, in order for the first light receiving device PD1 to absorb green light, the optical auxiliary layer in the first light receiving device PD1 may be deposited simultaneously with the first optical auxiliary layer 1223o of the first light emitting device ED1 for emitting green light. However, when high-resolution images need to be realized, it may be difficult to fabricate a mask that can deposit the first optical auxiliary layer 1223o and the optical auxiliary layer for the first light receiving device PD1 simultaneously. In addition, when depositing the first optical auxiliary layer 1223o and the optical auxiliary layer for the first light receiving device PD1, additional processes and devices may be required, which may be disadvantageous in terms of productivity. Therefore, in the display device 1 according to some embodiments, in order to ensure productivity and realize high-resolution images, the optical auxiliary layer 223o may not be located in the first light receiving device PD1.

[0126] However, when the first light receiving device PD1 does not include the optical auxiliary layer 223o, the optical distance for the pre-resonance of the first light receiving device PD1 may not be adjusted. To solve this problem, the display device 1 according to some embodiments may eliminate the resonance phenomenon in the first light receiving device PD1 by using the first layer 4223a included in the first active layer 4223, and may increase the light absorption efficiency of the first active layer 4223 itself.

[0127] As described above, the first layer 4223a may include an electron donor material, that is, a p-type organic semiconductor material. The p-type organic semiconductor material included in the first layer 4223a may be a material with high absorbance. Therefore, when the thickness of the first layer 4223a increases, the light absorption efficiency of the first active layer 4223 itself may be relatively improved. In addition, when the first layer 4223a is formed thick and the optical auxiliary layer is not positioned in the first light receiving device PD1, the light reflected between the first sensing electrode 4210 and the counter electrode 230 may be absorbed into the first layer 4223a, thereby eliminating the resonance phenomenon. Therefore, while existing light receiving devices absorb light of a single color in a narrow wavelength band by using the pre-resonance phenomenon, the first light receiving device PD1 may absorb light in a wider wavelength band by using the light absorption characteristics of the first layer 4223a.

[0128] Since the thickness of the first layer 4223a increases, in the thickness direction of the substrate 100, the thickness of the first layer 4223a may be at least the thickness of the second layer 4223b. According to some embodiments, the thickness of the first layer 4223a may be to The thickness of the second layer 4223b may be to When the first layer 4223a has When the thickness is equal to or greater than a certain value, the first layer 4223a can eliminate the pre-resonance in the first light receiving device PD1, and can increase the wavelength band of light that can be absorbed by the first light receiving device PD1 by using the unique spectrum of the light absorption material included in the first layer 4223a.

[0129] However, the thickness of the first layer 4223a can vary according to the absorbance of the electron donor material included in the first layer 4223a. The thickness of the first layer 4223a can be inversely proportional to the absorbance of the first layer 4223a. According to some embodiments, the absorbance of the first layer 4223a can be 0.2 to 0.6.

[0130] For example, the thickness of the first layer 4223a can satisfy Equation 1.

[0131] Equation 1

[0132] T = 120 / a

[0133] In Equation 1, T is the thickness of the first layer 4223a, and a can be the absorbance of the material included in the first layer 4223a. For example, when the absorbance of the material included in the first layer 4223a is 0.2, the first layer 4223a can have a thickness of at least . Alternatively, when the absorbance of the material included in the first layer 4223a is 0.6, the first layer 4223a can have a thickness of at least .

[0134] As a result, since the first layer 4223a is formed to have a thickness equal to or greater than the minimum thickness corresponding to the absorbance of the first layer 4223a, the resonance phenomenon of the first light receiving device PD1 is eliminated, and the first active layer 4223 can absorb light in a wider wavelength band. Therefore, the light absorption efficiency and sensing sensitivity of the first light receiving device PD1 can be relatively improved. In particular, the display device 1 can read various information from the user according to the wavelength band of the light absorbed by the first light receiving device PD1. For example, when the light absorbed by the first light receiving device PD1 has a short wavelength, only the surface level information about the user's fingerprint can be read, but when the light absorbed by the first light receiving device PD1 has a long wavelength, the information in the user's blood vessels can also be read. Therefore, because the display device 1 according to the embodiment can eliminate the resonance phenomenon by increasing the thickness of the first layer 4223a and can absorb light in a wide wavelength band, various information can be read from the user, thereby increasing the usability.

[0135] However, the structure of the first active layer 4223 is not limited to the stacked structure described above. In some other embodiments, the first active layer 4223 may be a mixed layer in which an electron donor material and an electron acceptor material are mixed. In this case, the first active layer 4223 may be formed by co-depositing a p-type organic semiconductor and an n-type organic semiconductor. Even when the first active layer 4223 is a mixed layer, the first active layer 4223 may have a thickness equal to or greater than the minimum thickness capable of eliminating the resonance phenomenon.

[0136] The first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1 may further include a charge-assist layer that promotes the movement of holes and electrons. The first common layer 221, the second common layer 222, the buffer layer 224, the third common layer 225, and the fourth common layer 226 may be included in the charge-assist layer. The first common layer 221 and the second common layer 222 may be located between the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 and the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223, and may be located between the first sensing electrode 4210 and the first active layer 4223. The buffer layer 224, the third common layer 225, and the fourth common layer 226 may be located between the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 and the counter electrode 230, and may be located between the first active layer 4223 and the counter electrode 230. That is, the first common layer 221, the second common layer 222, the third common layer 225, the fourth common layer 226, and the buffer layer 224 may be provided integrally throughout the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1.

[0137] According to some embodiments, a hole transport region may be defined between the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 and the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 and between the first sensing electrode 4210 and the first active layer 4223. In addition, an electron transport region may be defined between the first emission layer 1223, the second emission layer 2223, and the third emission layer 3223 and the counter electrode 230 and between the first active layer 4223 and the counter electrode 230.

[0138] The hole transport region may promote the movement of holes and may have a single-layer structure or a multi-layer structure. The hole transport region may include at least one of a hole injection layer (HIL), a hole transport layer, and an electron blocking layer (EBL). According to some embodiments, the first common layer 221 located in the hole transport region may be a hole injection layer (HIL), and the second common layer 222 may be a hole transport layer (HTL).

[0139] The thickness of the hole transport region can be about to about For example, about to about When the hole transport region includes a hole injection layer, a hole transport layer, or a combination thereof, the thickness of the hole injection layer (HIL) can be about to about For example, about to about And the thickness of the hole transport layer (HTL) can be about to about For example, about to about When the thicknesses of the hole injection layer (HIL) and the hole transport layer (HTL) satisfy the above ranges, satisfactory hole transport characteristics can be obtained without significantly increasing the driving voltage.

[0140] The first common layer 221 and the second common layer 222 include at least one selected from m-MTDATA, TDATA, 2-TNATA, NPB (NPD), β-NPB, TPD, spiro-TPD, spiro-NPB, methylated-NPB, TAPC, HMTPD, 4,4',4”-tris(N-carbazolyl)triphenylamine (TCTA), polyaniline / dodecylbenzenesulfonic acid (Pani / DBSA), polyaniline / camphorsulfonic acid (Pani / CSA), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonic acid) (PEDOT / PSS), and polyaniline / poly(4-styrenesulfonic acid) (Pani / PSS).

[0141] The electron transport region facilitates the movement of electrons and can have a single-layer structure or a multi-layer structure. The electron transport region can include at least one of an electron injection layer (EIL), an electron transport layer (ETL), and a hole blocking layer (HBL). According to some embodiments, the third common layer 225 located in the electron transport region can be an electron transport layer (ETL), and the fourth common layer 226 can be an electron injection layer (EIL).

[0142] The thickness of the electron transport region can be about to about For example, about to about When the electron transport region includes a buffer layer, an electron transport layer, an electron injection layer, or a combination thereof, the thicknesses of the buffer layer, the electron transport layer, and the electron injection layer can be independent of each other. For example, the thickness of the electron injection layer can be about to about For example, about to about and the thickness of the electron transport layer can be about to about For example, about to about When the thickness of the buffer layer, the thickness of the electron transport layer, the thickness of the electron injection layer, and / or the thickness of the electron transport region satisfy the above ranges, satisfactory electron transport characteristics can be obtained without significantly increasing the driving voltage.

[0143] The buffer layer 224 can include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the third common layer 225 and the fourth common layer 226 can include at least one compound selected from 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (Bphen), Alq3, BAlq, 3-(biphenyl-4-yl)-5-(4-tert-butylphenyl)-4-phenyl-4H-1,2,4-triazole (TAZ), and NTAZ.

[0144] The cover layer 240 can be located on the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1 having the above structure. That is, the cover layer 240 can be located on the counter electrode 230 and can be integrally formed over the entire surface of the substrate 100. The cover layer 240 can inhibit the penetration of impurities such as water or oxygen into the display device 1, thereby relatively improving the reliability of the display device 1.

[0145] The cover layer 240 can be an organic cover layer including an organic material, an inorganic cover layer including an inorganic material, or an organic-inorganic composite cover layer including an organic material and an inorganic material. The cover layer 240 can include a carbocyclic compound, a heterocyclic compound, a compound containing an amine group, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or any combination thereof. The carbocyclic compound, the heterocyclic compound, and the compound containing an amine group can optionally be substituted with a substituent including O, N, S, Se, Si, F, Cl, Br, I, or any combination thereof.

[0146] According to some embodiments, the encapsulation portion can be located on the cover layer 240. The encapsulation portion can be located on the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1 to protect the first light-emitting device ED1, the second light-emitting device ED2, the third light-emitting device ED3, and the first light-receiving device PD1 from the effects of moisture or oxygen. The encapsulation portion can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation portion can include an inorganic film and an organic film, and the inorganic film includes silicon nitride (SiN x ), silicon oxide (SiOx ) indium tin oxide, indium zinc oxide, or any combination thereof, and the organic film includes polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid), epoxy resin (e.g., aliphatic glycidyl ether (AGE)), or any combination thereof.

[0147] Figure 7 is a graph comparing the external quantum efficiency according to wavelength between the display device according to the comparative example and the display device according to some embodiments.

[0148] Figure 7 is a graph showing the results obtained after measuring the external quantum efficiency (EQE) according to the wavelength absorbed by the light receiving device of the display device and comparing the comparative example with the embodiment. Figure 7 For the graph, the horizontal axis represents the wavelength (nm) absorbed by the light receiving device, and the vertical axis represents the EQE (%) of the light receiving device. Figure 7 (a) to (c) thereof show the evaluation results of Comparative Example 1 to Comparative Example 3, and Figure 7 (d) to (g) thereof show the evaluation results of Example 1 to Example 4.

[0149] In the display device of Comparative Example 1, the light receiving device includes an optical auxiliary layer, and the first layer of the active layer has a thickness of, and the second layer of the active layer has a thickness of. In the display device of Comparative Example 2, the light receiving device does not include an optical auxiliary layer, and the first layer of the active layer has a thickness of, and the second layer of the active layer has a thickness of. In the display device of Comparative Example 3, the light receiving device does not include an optical auxiliary layer, and the first layer of the active layer has a thickness of, and the second layer of the active layer has a thickness of.

[0150] In the display device of Example 1, the light receiving device does not include an optical auxiliary layer, and the first layer of the active layer has a thickness of, and the second layer of the active layer has a thickness of. In the display device of Example 2, the light receiving device does not include an optical auxiliary layer, and the first layer of the active layer has a thickness of, and the second layer of the active layer has a thickness of. In the display device of Example 3, the light receiving device does not include an optical auxiliary layer, and the first layer of the active layer has a thickness of, and the second layer of the active layer has The thickness. In the display device of Example 4, the light receiving device does not include an optical auxiliary layer, and the first layer of the active layer has a thickness, and the second layer of the active layer has a thickness.

[0151] Referring to Figure 7 , it is found that the light receiving devices of Examples 1 to 4 and the light receiving device of Comparative Example 1 have an absorption center wavelength of approximately 530 nm ± 50 nm. That is, it is found that the light receiving devices of Examples 1 to 4 and the light receiving device of Comparative Example 1 can detect green light. On the other hand, it is found that the light receiving device of Comparative Example 2 has an absorption center wavelength of 480 nm ± 50 nm, and the light receiving device of Comparative Example 3 has an absorption center wavelength of 450 nm ± 50 nm. That is, it is found that the light receiving devices of Comparative Example 2 and Comparative Example 3 can mainly detect light with a short wavelength, such as blue light.

[0152] Therefore, it is found that when the light receiving device does not include an optical auxiliary layer and the thickness of the first layer of the active layer is insufficient, the light that can be mainly detected by the light receiving device moves to light with a short wavelength. As described above, when the light receiving device absorbs light with a short wavelength, there may be limitations in the information that can be read from the user, or the object may not be accurately recognized. For example, referring to Figure 7 , the display device of Comparative Example 2 has an EQE of 33% for light with a wavelength of 530 nm, and the display device of Comparative Example 3 has an EQE of 13% for light with a wavelength of 530 nm. That is, simply removing the optical auxiliary layer from the light receiving device to increase the resolution of Display Device 1 (see Figure 5 ) may relatively reduce the sensing sensitivity.

[0153] However, in order to achieve a high-resolution product, it may be inevitable to remove the optical auxiliary layer from the light receiving device. To solve this problem, by increasing the thickness of the layers of the active layer, even though the optical auxiliary layer is not positioned, the display device according to the embodiment can also have a high EQE.

[0154] For example, referring to Figure 7, the display device of Example 1 has an EQE of 50% for light with a wavelength of 530 nm, and the display device of Example 2 has an EQE of 73% for light with a wavelength of 530 nm. The display device of Example 3 has an EQE of 90% for light with a wavelength of 530 nm, and the display device of Example 4 has an EQE of 100% for light with a wavelength of 530 nm. That is, it was found that even without positioning the optical auxiliary layer, the display devices of Examples 1 to 4 have high absorption efficiency and high EQE for light with a wavelength of 530 nm. In particular, it was found that the EQE increases as the thickness of the first layer of the active layer increases, which may mean that the sensing sensitivity of the light receiving device increases as the thickness of the first layer of the active layer increases.

[0155] In addition, it was found that in the display devices of Examples 1 to 4, since the first layer of the active layer has a specific thickness or greater thickness, the resonance phenomenon of the light receiving device can be eliminated, and light in a wide wavelength band can be absorbed by using the light absorption characteristics of the material of the first layer. For example, it was found that the display devices of Examples 1 to 4 have a high EQE in the wavelength band of 530 nm and can absorb all light in the wavelength band of 440 nm to 560 nm with high efficiency. In other words, the display devices of Examples 1 to 4 can detect light in a wide wavelength band, and thus, compared with the case where the display device of Comparative Example 1 detects light in a narrow wavelength band, can have excellent sensing sensitivity.

[0156] In summary, in a display device according to some embodiments, when the light receiving device does not include an optical auxiliary layer and the first layer of the active layer has a sufficient thickness, high-resolution images can be achieved and the sensing sensitivity can be relatively improved.

[0157] As described above, in a display device according to some embodiments, the light receiving device can absorb light in a wide wavelength band, thereby relatively improving the sensing sensitivity. The above effects are only examples, and the scope of the present disclosure is not limited by these effects.

[0158] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of the features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: a substrate including an emitting region and a sensing region; a light emitting device on the substrate corresponding to the emission area; and a light receiving device on the substrate corresponding to the sensing area, The light emitting device includes a pixel electrode, an emission layer on the pixel electrode, and a counter electrode on the emission layer, and The light receiving device includes a sensing electrode, an active layer on the sensing electrode, and the counter electrode on the active layer. wherein the active layer comprises a first layer comprising an electron donor material and a second layer on the first layer and comprising an electron acceptor material, Wherein, in the thickness direction of the substrate, the thickness of the first layer is at least the thickness of the second layer.

2. The display device according to claim 1, wherein The first layer includes a p-type organic semiconductor, and The second layer includes an n-type organic semiconductor.

3. The display device according to claim 1, wherein The thickness of the first layer is inversely proportional to the absorbance of the first layer.

4. The display device according to claim 3, wherein The thickness of the first layer is to within the range.

5. The display device according to claim 3, wherein The absorbance of the first layer is in the range of 0.2 to 0.

6. The display device according to claim 3 , wherein: The thickness of the first layer satisfies Equation 1, Equation 1 T=120 / a, wherein T is the thickness of the first layer, and a is the absorbance of the first layer.

7. The display device according to claim 1, wherein The display device further includes a common layer between the pixel electrode and the emission layer and between the sensing electrode and the active layer, The common layer includes at least one of a hole injection layer and a hole transport layer.

8. The display device according to claim 7, wherein The light emitting device further includes an optical auxiliary layer between the common layer and the emission layer, Wherein, the bottom surface of the emission layer directly contacts the top surface of the optical auxiliary layer.

9. The display device according to claim 8, wherein The optical auxiliary layer is patterned to have a different thickness for each light emitting device.

10. The display device according to claim 7, wherein A bottom surface of the active layer directly contacts a top surface of the common layer.

11. The display device according to claim 1, wherein The pixel electrode and the sensing electrode are reflective electrodes, and The counter electrode is a semi-transmissive and semi-reflective electrode or a transmissive electrode.

12. The display device according to claim 11, wherein The light emitting device has a front resonance structure, and The light receiving device has a non-resonant structure in which a resonance phenomenon is eliminated.

13. A display device, wherein: The display device comprises: substrate; a light emitting device on the substrate and comprising a pixel electrode, an emission layer on the pixel electrode, and a counter electrode on the emission layer; and a light receiving device on the substrate and including a sensing electrode, an active layer on the sensing electrode, and the counter electrode on the active layer, The light emitting device and the light receiving device further include a common layer between the pixel electrode and the emission layer and between the sensing electrode and the active layer. Wherein, a bottom surface of the active layer and a top surface of the common layer are in direct contact with each other.

14. The display device according to claim 13, wherein The common layer includes at least one of a hole injection layer and a hole transport layer, The common layer is integrally formed over the entire surface of the substrate.

15. The display device according to claim 13, wherein The light emitting device further includes an optical auxiliary layer between the common layer and the emission layer, Wherein, the bottom surface of the emission layer directly contacts the optical auxiliary layer.

16. The display device according to claim 15, wherein The optical auxiliary layer is patterned only in the light emitting device and is not located in the light receiving device.

17. The display device according to claim 13, wherein The active layer comprises a first layer comprising an electron donor material and a second layer on the first layer and comprising an electron acceptor material, Wherein, in the thickness direction of the substrate, the thickness of the first layer is at least the thickness of the second layer.

18. The display device according to claim 17, wherein The first layer includes a p-type organic semiconductor, and The second layer includes an n-type organic semiconductor.

19. The display device according to claim 17, wherein The thickness of the first layer is inversely proportional to the absorbance of the first layer.

20. The display device according to claim 13, wherein The pixel electrode and the sensing electrode are reflective electrodes, and the counter electrode is a semi-transmissive and semi-reflective electrode or a transmissive electrode.

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