Display device

Abstract

The present disclosure provides a display device including: a substrate including a display area allowing an image to be displayed and a non-display area outside the display area; a first protective layer over the substrate; a second protective layer disposed on the first protective layer and having a first opening; a plurality of first electrodes disposed on the second protective layer; and a wall pattern disposed on the first protective layer and located at a boundary or inside of the first opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0017381 filed on February 5, 2024, in the Korean Intellectual Property Office, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to electronic devices having displays, and more particularly, to display devices. Background Art

[0004] With the development of the information-oriented society, various demands for display devices (which can be referred to as displays) for displaying images have increased. As such displays, liquid crystal displays (LCDs), inorganic light-emitting displays, organic light-emitting diode (OLED) displays, quantum dot (QD) displays, etc. have been developed and are increasingly used.

[0005] Among these displays, organic light-emitting diode (OLED) displays have self-luminous properties and can offer advantages such as wider viewing angles and higher contrast ratios compared to liquid crystal displays (LCDs). OLED displays can be packaged into thinner and lighter packages without the need for backlights and consume less power. Furthermore, OLED displays can be driven at low DC voltages, have fast response times, and are particularly cost-effective to manufacture. Summary of the Invention

[0006] One or more aspects of the present disclosure may provide a display device capable of minimizing leakage current.

[0007] One or more aspects of the present disclosure may provide a display device capable of solving a problem in which a deposition material does not have a uniform thickness according to relative positions of a deposition source and a unit display panel during a deposition process.

[0008] One or more aspects of the present disclosure may provide a display device capable of preventing one or more sub-pixels that are not driven for image display among a plurality of sub-pixels having a common intermediate layer and a cathode layer from emitting light due to lateral leakage current (in this document, the term "lateral leakage current" may refer to leakage current flowing along a boundary or portion of an opening formed in a sub-pixel).

[0009] One or more aspects of the present disclosure may provide a display device capable of improving color gamut and display quality in low grayscale by preventing one or more unintended sub-pixels from emitting light.

[0010] The problems or issues to be solved herein are not limited to the above description, and other problems or issues to be solved will become apparent to those skilled in the art from the following description.

[0011] According to one or more example embodiments of the present disclosure, a display device may be provided, comprising: a substrate including a display area allowing an image to be displayed and a non-display area outside the display area; a first protective layer over the substrate; a second protective layer disposed on the first protective layer and having a first opening; a plurality of first electrodes disposed on the second protective layer; and a wall pattern disposed on the first protective layer and located at a boundary or inside the first opening.

[0012] According to one or more aspects of the present disclosure, a display device can be provided that sets a wall pattern in consideration of the relative positions of a deposition source and a display panel so that a light-emitting layer or a cathode layer can be deposited in a display panel with a uniform thickness during a deposition process regardless of the position.

[0013] According to one or more aspects of the present disclosure, a display device can be provided, which, by setting a wall pattern, can prevent oxygen from penetrating into a light-emitting element (or one or more elements included in the light-emitting element) and shrinking of the light-emitting element due to a reduction in the thickness of a deposited light-emitting layer or a cathode layer or a disconnection of the light-emitting layer or the cathode layer.

[0014] According to one or more aspects of the present disclosure, a display device can be provided, which is configured with a structure in which an opening is formed in a portion of a protective layer in a region between adjacent sub-pixels, and a wall pattern is provided at a boundary or inside the opening of the protective layer, and which provides the following advantages: lateral leakage current is reduced by enabling current flowing through a common intermediate layer to be discharged through the wall pattern when a ground voltage is applied to the wall pattern.

[0015] According to one or more aspects of the present disclosure, a display device can be provided that is capable of improving color gamut by minimizing unintended light emission of one or more light-emitting elements by reducing lateral leakage current, and improving display quality by minimizing display artifacts such as brightness differences, color differences, etc., which may be visible when displaying images with low grayscale.

[0016] Additional features and aspects will be set forth in part in the following description, and in part will become apparent from the description, or may be learned by practicing the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and obtained by structures particularly pointed out in the written description, its claims, and the accompanying drawings, or may be inferred therefrom.

[0017] Other systems, methods, features, and advantages will be or will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims. Nothing in this section should be taken as a limitation on those claims.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The configuration of an example display device according to aspects of the present disclosure is schematically illustrated.

[0020] Figure 2 Example configurations of display panels according to aspects of the present disclosure are shown.

[0021] Figure 3 is a plan view schematically illustrating an example deposition process for forming a light emitting element according to aspects of the present disclosure.

[0022] Figure 4 is an example cross-sectional view illustrating a result of a deposition process performed on a substrate according to aspects of the present disclosure.

[0023] Figure 5 is an example cross-sectional view illustrating lateral leakage current originating from a common intermediate layer according to aspects of the present disclosure.

[0024] Figure 6 An example in which a lateral leakage current is discharged through a wall pattern in a display device according to aspects of the present disclosure is shown.

[0025] 7A to 7D Example cross-sections of display panels including corresponding wall patterns according to aspects of the present disclosure are shown.

[0026] Figures 8A to 8D Example cross-sections of display panels including corresponding wall patterns according to aspects of the present disclosure are shown.

[0027] Figure 9 is an example plan view illustrating that a display area is divided into sub-areas at different positions in a display panel according to aspects of the present disclosure.

[0028] Figure 10A is a cross-sectional view illustrating example positions of wall patterns provided in a display area in Case 1 in a display panel according to aspects of the present disclosure.

[0029] Figure 10B is a cross-sectional view illustrating example positions of wall patterns provided in a display area in Case 2 in a display panel according to aspects of the present disclosure.

[0030] Figure 10C is a cross-sectional view illustrating example positions of wall patterns provided in a display area in Case 3 in a display panel according to aspects of the present disclosure.

[0031] Figures 11A to 11C Example wall patterns disposed between sub-pixels in a display panel according to aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to the embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, unless otherwise stated, the structures, embodiments, implementations, methods, and operations described herein are not limited to one or more specific examples set forth herein and may be modified as known in the art. Throughout the text, similar reference numerals refer to similar elements unless otherwise stated. The names of the various elements used in the following description are selected solely for the convenience of writing the specification and may therefore differ from those used in actual products. The advantages and features of the present disclosure and their implementation methods will be illustrated by the following example embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure may be sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, where a detailed description of a related known function or configuration may unnecessarily obscure various aspects of the present disclosure, such a detailed description of such known function or configuration may be omitted. The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the various exemplary embodiments of the present disclosure are given as examples only. Therefore, the present disclosure is not limited to the illustrations in the drawings. Where the terms "comprising," "having," "including," "containing," "consisting of," "composed of," or the like are used, one or more other elements may be added unless a term such as "only" is used. Unless the context clearly indicates otherwise, an element described in the singular is intended to include a plurality of elements, and vice versa.

[0033] Although the terms "first," "second," "A," "B," "(a)," "(b)," etc., may be used herein to describe various elements, these elements should not be understood as limited by these terms because they are not used to define a particular order or priority. These terms are only used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of this disclosure.

[0034] When referring to a first element being “connected or coupled to,” “contacting or overlapping,” etc. a second element, it should be understood that not only the first element may be “directly connected or coupled to,” or “directly contacting or overlapping,” but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled to,” “contacting or overlapping,” etc., with each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to,” “contacting or overlapping,” etc., with each other.

[0035] When describing a positional relationship, for example, when using terms such as "on," "above," "below," "above," "below," "next to," or "near" to describe the positional relationship between two components, one or more other components may be located between the two components unless more restrictive terms such as "immediately," "directly," or "immediately adjacent" are used. For example, when an element or layer is disposed "on" another element or layer, a third element or layer may be interposed therebetween. Furthermore, terms such as "left," "right," "top," "bottom," "downward," "upward," "upper," and "lower" refer to an arbitrary reference system.

[0036] Furthermore, when referring to any dimensions, relative sizes, etc., it should be understood that the numerical values or corresponding information (e.g., levels, ranges, etc.) of the elements or features include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can."

[0037] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 The configuration of an example display device 100 according to aspects of the present disclosure is schematically illustrated.

[0039] Reference Figure 1In one or more example embodiments, a display device 100 may include a display panel 110 including a display area A / A in which a plurality of sub-pixels SP are disposed and a non-display area N / A outside the display area A / A. The display device 100 may include a gate driving circuit 120, a data driving circuit 130, a controller 140, and the like for driving several types of signal lines disposed in the display panel 110.

[0040] A plurality of gate lines GL and a plurality of data lines DL may be disposed in the display panel 110 , and a corresponding one of the plurality of sub-pixels SP may be disposed in each region in which the gate line GL and the data line DL intersect each other.

[0041] The gate driving circuit 120 may be controlled by the controller 140 and may control a driving timing of a plurality of sub-pixels SP by sequentially outputting scan signals to a plurality of gate lines GL provided in the display panel 110 .

[0042] The gate driver circuit 120 may include one or more gate driver integrated circuits GDIC. The gate driver circuit 120 may be located and / or electrically connected to, but not limited to, one side or one portion (e.g., the left edge or the right edge) of the display panel 110. In one or more aspects, depending on the driving scheme, panel design scheme, etc., the gate driver circuit 120 may be located and / or electrically connected to, but not limited to, two sides or two portions (e.g., the left edge and the right edge) of the display panel 110 or at least two of the four sides or four portions (e.g., the top edge, the bottom edge, the left edge, and the right edge) of the display panel 110.

[0043] Each gate driver integrated circuit GDIC can be connected to a pad, such as a bonding pad, of the display panel 110 by a tape automated bonding (TAB) technique or a chip on glass (COG) technique, or can be directly disposed in the display panel 110 by a gate in panel (GIP) technique. In one or more aspects, the one or more gate driver integrated circuits GDIC can be integrated into a circuit system or circuit block of the display panel 110. In one or more aspects, each gate driver integrated circuit GDIC can be mounted on a film connected to the display panel 110 by a chip on film (COF) technique.

[0044] The data driving circuit 130 may receive image data from the controller 140 and convert the received image data into analog data voltages. The data driving circuit 130 may output data voltages to the data lines DL according to the timing when the scan signals transmitted through the gate lines GL are applied, thereby enabling the sub-pixels SP to emit light at a brightness corresponding to the image data.

[0045] The data driving circuit 130 may include one or more source driver integrated circuits SDIC.

[0046] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0047] Each source driver integrated circuit SDIC can be connected to a pad of the display panel 110, such as a bonding pad, by tape automated bonding (TAB) technology or chip on glass (COG) technology, or directly provided in the display panel 110. In one or more aspects, one or more source driver integrated circuits SDIC can be integrated into a circuit system or circuit block of the display panel 110. In one or more aspects, each source driver integrated circuit SDIC can be implemented by chip on film (COF) technology. In this implementation, each source driver integrated circuit SDIC can be mounted on a film connected to the display panel 110 and electrically connected to the display panel 110 through a line on the film.

[0048] The controller 140 may provide several control signals to the gate driving circuit 120 and the data driving circuit 130 and control operations of the gate driving circuit 120 and the data driving circuit 130 .

[0049] The controller 140 may be mounted on a printed circuit board (PCB), a flexible printed circuit (FPC), or the like, and electrically connected to the gate driving circuit 120 and the data driving circuit 130 through the printed circuit board (PCB), the flexible printed circuit (FPC), or the like.

[0050] The controller 140 can enable the gate driving circuit 120 to output a scanning signal according to the timing processed in each frame, convert image data input from an external source such as an external device, a network, a host system, etc. into a data signal form used in the data driving circuit 130, and then output the converted image data to the data driving circuit 130.

[0051] In addition to image data, the controller 140 may also receive several types of timing signals from other devices or systems (eg, the host system 150 ), including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, and the like.

[0052] The controller 140 may generate several types of control signals using several types of timing signals received from other devices or systems, and output the generated signals to the gate driving circuit 120 and the data driving circuit 130 .

[0053] In one or more aspects, to control the gate driving circuit 120 , the controller 140 may output several types of gate control signals GCS, including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like.

[0054] The gate start pulse GSP can be used to control the operation start timing of one or more gate driver integrated circuits GDIC included in the gate driver circuit 120. The gate shift clock GSC can be a clock signal generally input to the one or more gate driver integrated circuits GDIC and used to control the shift timing of the scan signal. The gate output enable signal GOE can be used to indicate the timing information of the one or more gate driver integrated circuits GDIC.

[0055] In one or more aspects, to control the data driving circuit 130 , the controller 140 may output several types of data control signals DCS, including a source start pulse SSP, a source sampling clock SSC, a source output enable (SOE) signal, and the like.

[0056] The source start pulse SSP can be used to control the data sampling start timing of one or more source driver integrated circuits SDIC included in the data driving circuit 130. The source sampling clock SSC can be a clock signal used to control the sampling timing of data in each source driver integrated circuit SDIC. The source output enable signal SOE can be used to control the output timing of the data driving circuit 130.

[0057] The display device 100 may further include a power management integrated circuit for providing several types of voltages or currents to the display panel 110 , the gate driving circuit 120 , the data driving circuit 130 , etc., or for controlling several types of voltages or currents to be provided.

[0058] Each sub-pixel SP may be defined by an intersection of one or more gate lines GL and one or more data lines DL. Depending on the type of the display device, a liquid crystal or a light emitting element may be provided in each sub-pixel SP.

[0059] Figure 2 An example configuration of the display panel 110 according to aspects of the present disclosure is shown.

[0060] Reference Figure 2 In one or more example embodiments, the display panel 110 may include a substrate SUB on which a plurality of sub-pixels SP are disposed and an encapsulation layer 200 over the substrate SUB. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation stack.

[0061] Reference Figure 2In an example where the display device 100 is a self-luminous display device, each of the plurality of sub-pixels SP provided on the substrate SUB may include a light emitting element ED and a sub-pixel circuit SPC for driving the light emitting element ED.

[0062] Reference Figure 2 The sub-pixel circuit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light-emitting element ED. The sub-pixel circuit SPC may drive the light-emitting element ED by supplying a driving current to the light-emitting element ED at a predetermined timing. The light-emitting element ED may emit light by being driven by the driving current.

[0063] The plurality of pixel driving transistors may include a driving transistor DRT for driving the light emitting element ED and a scanning transistor SCT configured to be turned on or off according to a scanning signal SC.

[0064] The driving transistor DRT may supply a driving current to the light emitting element ED.

[0065] The scan transistor SCT may be configured to control an electrical state of a corresponding node (eg, the second node N2 ) in the sub-pixel circuit SPC, or control a state or operation of the drive transistor DRT.

[0066] The at least one capacitor may include a storage capacitor Cst configured to maintain a constant voltage during a display frame or during a certain period of the display frame.

[0067] In order to drive the one or more sub-pixels SP, at least one data signal VDATA as an image signal and at least one scan signal SC as a gate signal may be applied to the one or more sub-pixels SP. In addition, in order to drive the one or more sub-pixels SP, a common driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the one or more sub-pixels SP.

[0068] Each light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[0069] In an example where the light-emitting element ED is an organic light-emitting element such as an organic light-emitting diode (OLED), the intermediate layer EL may include a light-emitting layer EML and a common intermediate layer EL_COM. The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 may be disposed between the pixel electrode PE and the light-emitting layer EML and may include at least one layer (e.g., an organic layer). The second common intermediate layer COM2 may be disposed between the light-emitting layer EML and the common electrode CE and may include at least one layer (e.g., an organic layer).

[0070] In one or more aspects, the light emitting layer EML may be provided in each of the plurality of sub-pixels SP, or commonly provided in all or some of the plurality of sub-pixels SP. The common intermediate layer EL_COM may be commonly provided in all or some of the plurality of sub-pixels SP.

[0071] The light emitting layer EML may be disposed in each light emitting region, and the common intermediate layer EL_COM may be commonly disposed on the plurality of light emitting regions and the non-light emitting region.

[0072] The pixel electrode PE may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode commonly provided in all or some of the plurality of sub-pixels SP.

[0073] For example, the pixel electrode PE may be an anode and the common electrode CE may be a cathode. In another example, the pixel electrode PE may be a cathode and the common electrode CE may be an anode. Hereinafter, a discussion is provided based on an example in which the pixel electrode PE is an anode and the common electrode CE is a cathode.

[0074] In one or more aspects, the first common intermediate layer COM1 of the common intermediate layer EL_COM may include a hole injection layer HIL, a hole transport layer HTL, etc. The second common intermediate layer COM2 of the common intermediate layer EL_COM may include an electron transport layer ETL, an electron injection layer EIL, etc.

[0075] The hole injection layer can inject holes from the pixel electrode PE into the hole transport layer, and the hole transport layer can transport holes to the emission layer EML. The electron injection layer can inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport electrons to the emission layer EML.

[0076] In one or more aspects, the common electrode CE may be electrically connected to a second common drive voltage line VSSL. A second common drive voltage VSS, which is a type of common drive voltage, may be applied to the common electrode CE via the second common drive voltage line VSSL. The pixel electrode PE may be electrically connected directly or indirectly (via another transistor) to the first node N1 of the corresponding drive transistor DRT of each sub-pixel SP. Herein, the second common drive voltage VSS may also be referred to as a base voltage VSS, and the second common drive voltage line VSSL may be referred to as a base voltage line VSSL.

[0077] Each light-emitting element ED may be configured by overlapping corresponding portions of the corresponding pixel electrode PE, the corresponding light-emitting layer EML in the intermediate layer EL, and the common electrode CE. A corresponding light-emitting region may be formed by each light-emitting element ED. For example, the corresponding light-emitting region of each light-emitting element ED may be configured by an area in which corresponding portions of the corresponding pixel electrode PE, the corresponding light-emitting layer EML in the intermediate layer EL, and the common electrode CE overlap with each other.

[0078] In one or more aspects, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic material-based light-emitting diode (LED), or a quantum dot (QD) light-emitting element. In an example where the light-emitting element ED is an organic light-emitting diode (OLED), the intermediate layer EL included in the light-emitting element ED may be a layer including an organic material.

[0079] The driving transistor DRT may be a transistor configured to supply a driving current to the light emitting element ED. The driving transistor DRT may be connected between the first common driving voltage line VDDL and the light emitting element ED.

[0080] The driving transistor DRT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light emitting element ED, the data signal VDATA may be applied to the second node N2, and the first common driving voltage VDD transmitted through the first common driving voltage line VDDL may be applied to the third node N3.

[0081] In the driving transistor DRT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation only, a discussion may be provided based on an example in which the first node, the second node, and the third node (N1, N2, and N3) of the driving transistor DRT are the source node, the gate node, and the drain node, respectively. However, example embodiments of the present disclosure are not limited thereto.

[0082] Included in Figure 2The scan transistor SCT in the illustrated sub-pixel circuit SPC may be a switching transistor for allowing the data signal VDATA, which is an image signal, to be supplied to the second node N2, which is a gate node of the driving transistor DRT.

[0083] The scan transistor SCT can be turned on or off by a scan signal SC, which is a gate signal carried by a scan signal line SCL, which serves as a gate line GL. The scan transistor SCT can control the electrical connection between the second node N2 of the drive transistor DRT and the data line DL. The drain electrode or source electrode of the scan transistor SCT can be electrically connected to the data line DL. The source electrode or drain electrode of the scan transistor SCT can be electrically connected to the second node N2 of the drive transistor DRT. The gate electrode of the scan transistor SCT can be electrically connected to the scan signal line SCL.

[0084] The storage capacitor Cst may be electrically connected between a first node N1 and a second node N2 of the driving transistor DRT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DRT; and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DRT.

[0085] In one or more aspects, the storage capacitor Cst may be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor such as a parasitic capacitor (e.g., Cgs or Cgd) that may be formed between the first node N1 and the second node N2 of the driving transistor DRT.

[0086] Each of the driving transistor DRT and the scanning transistor SCT may be an n-type transistor or a p-type transistor.

[0087] The display panel 110 may have a top emission structure or a bottom emission structure.

[0088] In an example where the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light-emitting element ED in a vertical direction. In this configuration, the area or size of the corresponding light-emitting region may be increased, and the corresponding aperture ratio may be increased.

[0089] In an example where the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting element ED in a vertical direction.

[0090] like Figure 2As shown, the sub-pixel circuit SPC may include two transistors (2T: DT and ST) and a capacitor (1C: Cst) (which may be referred to as a "2T1C structure"), and in some implementations, may also include one or more transistors, or may also include one or more capacitors.

[0091] The type and number of gate signals supplied to the subpixel SP and / or the type and number of gate lines connected to the subpixel SP may vary according to the structure of the corresponding subpixel circuit SPC. The type and number of common driving voltages may vary according to the structure of the corresponding subpixel circuit SPC.

[0092] Since the circuit elements included in each sub-pixel SP (particularly, the light-emitting element ED implemented using an organic light-emitting diode including an organic material) are susceptible to external moisture or oxygen, an encapsulation layer 200 may be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into such circuit elements. The encapsulation layer 200 may be provided in various shapes or configurations to prevent the light-emitting element ED from contacting moisture or oxygen.

[0093] In one or more aspects, the display device 100 may be configured to have an extremely narrow bezel structure in which the non-display area NDA of the display panel 110 is configured to have a very small size.

[0094] Figure 6 is an example cross-sectional view of a display device 100 according to aspects of the present disclosure.

[0095] Reference Figure 6 In one or more example embodiments, the display device 100 may include a substrate SUB, a signal line SL, an interlayer insulating layer ILD, a first protective layer OC1, a second protective layer OC2, a first electrode PE, an intermediate layer EL, a second electrode CE, and a wall pattern WP.

[0096] The substrate SUB may include, for example, an insulating material such as glass, plastic, crystal, etc., but example embodiments of the present disclosure are not limited thereto. In an example where the substrate SUB includes an organic polymer, the organic polymer may be, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, polyethersulfone, etc. The substrate SUB or the material included in the substrate SUB may be selected in consideration of mechanical strength, thermal stability, transparency, surface smoothness, ease of handling, waterproofness, etc.

[0097] The substrate SUB may include a display area that allows an image to be displayed so that a user can recognize the image, and a non-display area corresponding to a remaining area other than the display area. A plurality of light-emitting elements such as organic light-emitting diodes may be provided in the display area, and one or more pads configured to transmit one or more electrical signals from a power source (not shown) or a signal generator (not shown) to the display area may be provided in the non-display area.

[0098] Thin film transistors (not shown) directly or electrically connected to the various signal lines SL may be provided in the display region of the substrate SUB. At least one of the thin film transistors may be electrically connected to a corresponding organic light emitting element ED.

[0099] The thin film transistor may include a driving thin film transistor for controlling the organic light emitting element ED and a switching thin film transistor for switching the driving thin film transistor.

[0100] Each thin film transistor may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor layer may include a semiconductor material and serve as an active layer of the thin film transistor. The semiconductor layer may include an inorganic semiconductor material or an organic semiconductor material.

[0101] The gate insulating layer may be disposed on the semiconductor layer, may cover the semiconductor layer, and may include at least one of an organic insulating material and an inorganic insulating material.

[0102] The gate electrode may be disposed on the gate insulating layer and configured to cover a region corresponding to a channel region of the semiconductor layer.

[0103] The source electrode and the drain electrode may be disposed on the interlayer insulating layer ILD on the gate insulating layer. The drain electrode may contact the drain region of the semiconductor layer through a contact hole formed in the gate insulating layer and the interlayer insulating layer ILD, and the source electrode may contact the source region of the semiconductor layer through a contact hole formed in the gate insulating layer and the interlayer insulating layer ILD.

[0104] A first protective layer OC1 and a second protective layer OC2 may be provided on the source electrode, the drain electrode, and the interlayer insulating layer ILD. The first protective layer OC1 may serve as a protective layer for protecting the thin film transistor and may also serve as a planarization layer for flattening the top of the thin film transistor. The second protective layer OC2 may be used to extract light or determine the path of light.

[0105] The second protective layer OC2 may include a first opening H1 , and at least a portion of the first protective layer OC1 may be exposed through the first opening H1 .

[0106] The organic light emitting element ED may be disposed on at least a portion of the second protective layer OC2 , and may include a first electrode ( PE1 and PE2 ), an intermediate layer EL disposed on the first electrode ( PE1 and PE2 ), and a second electrode CE disposed on the intermediate layer EL.

[0107] The first electrodes (PE1 and PE2) may be pixel electrodes or anodes. The first electrodes (PE1 and PE2) may be transmissive electrodes, semi-transmissive electrodes, or reflective electrodes. The first electrodes (PE1 and PE2) may include a conductive compound containing a metal, a metal alloy, or a metal oxide. The first electrodes (PE1 and PE2) may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). The first electrodes (PE1 and PE2) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). In one or more aspects, the first electrode (PE1 and PE2) may have a structure configured with multiple layers, the multiple layers including: a reflective layer or a semi-transmissive layer comprising one or more of the aforementioned materials; and a transparent conductive layer comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0108] The second electrode CE may be a common electrode or a cathode. The second electrode CE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The second electrode CE may include a conductive compound containing a metal, a metal alloy, or a metal oxide. The second electrode CE may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). The second electrode CE may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). In one or more aspects, the second electrode CE may have a structure configured with multiple layers, the multiple layers including: a reflective layer or a semi-transmissive layer including one or more of the aforementioned materials; and a transparent conductive layer including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0109] The first electrodes (PE1 and PE2) may be reflective electrodes, and the second electrode CE may be a semi-transmissive electrode or a transmissive electrode.

[0110] Reference Figure 6The wall pattern WP may be disposed on the first protective layer OC1 and may be located at the boundary or inside the first opening H1 formed in the second protective layer OC2. For example, the base voltage applied to the second electrode CE may be applied to the wall pattern WP1. In one or more aspects, the wall pattern WP1 may be a ground pattern. Figure 6 and Figure 7A It is shown that the wall pattern WP1 is provided at the side or boundary of the first opening H1, but example embodiments of the present disclosure are not limited thereto. For example, the wall pattern WP may be provided at a position such as Figures 7B to 7D . Thus, in one embodiment, the light-emitting element of the first sub-pixel may be disposed on a portion of the second protective layer OC2, and the light-emitting element of the second sub-pixel may be disposed on another portion of the second protective layer. The wall pattern WP may be disposed on the first protective layer OC1, and at least a portion of the wall pattern WP may be covered by the second protective layer OC2, or may be disposed on a portion of the first protective layer OC1.

[0111] In one or more aspects, the display device may include a top-emission organic light emitting element ED. However, example embodiments of the present disclosure are not limited thereto. For example, the display device may include a bottom-emission organic light emitting element ED.

[0112] Figure 3 is a plan view schematically illustrating an example of a deposition process for forming a light emitting element according to aspects of the present disclosure.

[0113] Reference Figure 3 , a plurality of panel areas may be defined in the base substrate 1. For example, a plurality of display panels P (hereinafter, each display panel P may be Figure 1 and Figure 2 The display panel 110) can be arranged on the base substrate 1. Figure 3 Panel areas corresponding to six display panels P are illustrated, but example embodiments of the present disclosure are not limited thereto.

[0114] After performing a deposition process to form the light emitting element ED in each of the plurality of display panels P, a scribing process may be performed to separate the plurality of display panels P from each other.

[0115] A plurality of sub-pixels (eg, each of the plurality of sub-pixels may be Figure 2 The sub-pixel SP) can be set in each of the plurality of display panels P.

[0116] A corresponding display area may be defined in each of the plurality of panel regions. Thus, a plurality of sub-pixels SP may be provided in each display area. For example, the plurality of sub-pixels SP may be configured with gate lines, data lines, thin film transistors, pixel electrodes, and the like.

[0117] Reference Figure 3 , the display panel can be formed using a deposition device. The deposition device may include a deposition chamber (not shown), a deposition source S disposed inside the deposition chamber, and a mask assembly (not shown) disposed inside the deposition chamber. The mask assembly can support the base substrate 1. As a deposition condition, the deposition chamber can be configured to operate in a vacuum. The deposition source S can evaporate a deposition material, such as an inorganic material in the form of a vapor.

[0118] although Figure 3 Not shown in FIG, the deposition equipment may further include a fixture or a robotic arm for holding the mask assembly. In one or more aspects, the deposition equipment may further include additional machinery for implementing an in-line system.

[0119] For example, an insulating layer may be formed in a display panel using deposition equipment. For example, a conductive layer or a semiconductor layer may be formed in a display panel and then patterned using deposition equipment. The formation of conductive layers and semiconductor layers according to example embodiments of the present disclosure is not limited thereto.

[0120] In one or more aspects, another deposition apparatus can be used to form a light-emitting layer on the display panel. The deposition apparatus for forming such a light-emitting layer can include a mask assembly including a mask. Multiple openings can be defined in each mask, and these openings can be uniformly arranged. Multiple types of masks with different opening patterns can be used to form different types of light-emitting layers.

[0121] After the light emitting element is formed in each display panel on the base substrate 1 , the base substrate 1 may be cut into individual display panels using a cutting wheel or the like, thereby obtaining separate display panels.

[0122] Figure 4 is a cross-sectional view illustrating an example in which a deposition layer (or deposition material) does not have a uniform thickness depending on relative positions of a deposition source and a display panel when a deposition process is performed to form a light emitting element on a base substrate according to aspects of the present disclosure.

[0123] Reference Figure 4 , it can be seen that the thickness of the deposited material is non-uniform according to the position of the deposited material, that is, the deposited material is formed non-uniformly.

[0124] Therefore, when the deposition material is deposited in the form of deposition vapor to form a light-emitting layer or a cathode layer by using a deposition source S, the thickness of the deposition material may be uneven depending on the relative positions of the deposition source S and the light-emitting layer or cathode layer deposited in the display panel P.

[0125] For example, when the display panel P is located in a vertical direction facing the deposition source S, since the deposition vapor is sprayed relatively uniformly on the layer to be deposited (e.g., the light emitting layer or the cathode layer), the deposition material can be formed to have a uniform thickness regardless of the position.

[0126] In the case where the display panel P is located diagonally relative to the deposition source S instead of facing the deposition source S perpendicularly, since elements previously formed in the display panel P may serve as obstacles to the injection of deposition vapor, the thickness of the deposition material may be uneven depending on the position, or the deposition material may be disconnected.

[0127] Reference Figure 3 and Figure 4 As described above, due to the relative positions of the deposition source S and the display panel P or the position of the layer to be deposited in the display panel P, a region where the thickness of the resulting deposition material is less than that of the normal deposition material may be defined as a risk region RA.

[0128] For example, in such a risk region RA, since the deposition thickness of the electrode layer (eg, cathode) is reduced or disconnected, oxygen or moisture may penetrate into the reduced portion or the disconnected portion, and the corresponding light emitting element ED may shrink.

[0129] In another example, in the risk region RA, due to the reduced deposition thickness or disconnection of the cathode layer, the lateral leakage current LLC may flow through the intermediate layer EL below the cathode layer, as shown in FIG. Figure 5 shown.

[0130] In yet another example, when the inclined surface of the bank has a large height or forms a large angle with the flat portion of the bank, the deposition thickness of the cathode disposed on the bank may be reduced or disconnected.

[0131] For example, since the amount of current flowing through the green subpixel is relatively greater than the amount of current flowing through the blue or red subpixels, the green subpixel may emit light due to lateral leakage current even when it is not intended to emit light.

[0132] To address these issues, in one or more example embodiments, Figure 6As shown, considering the relative positions of the deposition source S and each display panel P, a corresponding wall pattern WP may be provided on the first protection layer OC1 in each display panel P. Thus, the deposition thickness of the intermediate layer EL or cathode layer CE formed in each display panel during the deposition process may be uniformly formed regardless of the position.

[0133] In addition, refer to Figure 6 Since the lateral current leaking through the intermediate layer EL is discharged through the wall pattern WP, which may be a ground pattern, the leakage current flowing along the intermediate layer EL of a corresponding sub-pixel can be prevented from flowing into another adjacent sub-pixel. To achieve these results, the wall pattern WP may include metal or a metal pattern.

[0134] In the following, referring to FIG. 7 to FIG. Figure 9 Formation of the wall pattern WP is described in detail.

[0135] 7A to 7D and Figures 8A to 8D Example cross-sections of display panels according to aspects of the present disclosure are shown.

[0136] Figure 9 1 and 2 are example plan views illustrating that the wall pattern WP is disposed at different positions in the display panel according to aspects of the present disclosure.

[0137] Reference 7A to 8D In one or more example embodiments, the display panel P may include a substrate SUB, a first protective layer OC1 on the substrate SUB, a second protective layer OC2 disposed on the first protective layer OC1 and having a first opening, a plurality of first electrodes (PE1 and PE2) disposed on the second protective layer OC2, and a wall pattern WP1 disposed on the first protective layer OC1 and disposed at a boundary or inside the first opening. The display panel P may further include an intermediate layer EL covering the plurality of first electrodes (PE1 and PE2), the second protective layer OC2, a portion of the first protective layer OC1 exposed by the first opening, and a second electrode CE disposed on the intermediate layer EL. Previously, reference has been made to Figure 6 The fabrication methods and materials for each layer are described.

[0138] For example, the display panel P may be provided with the wall pattern WP disposed in a position determined according to relative positions of the deposition source S and the display panel P.

[0139] In one or more aspects, the first wall pattern WP1 , the second wall pattern WP2 , the third wall pattern WP3 and / or the fourth wall pattern WP4 , which may be disposed at different positions and / or have different configurations, may be provided in the display panel P. This will be described in detail below.

[0140] like Figure 7AAs shown, in one or more aspects, the display panel P may include a first wall pattern WP1 located in a portion of a first boundary of the first opening H1.

[0141] For example, the first wall pattern WP1 may be disposed in a portion of the first boundary of the first opening H1 adjacent to the first light emitting area EA1 and on the first protective layer OC1. Figure 7A At least a portion of the first wall pattern WP1 may be covered by the second protective layer OC2 or the intermediate layer EL. In one embodiment, the first sub-pixel may be disposed on the left side of the second sub-pixel, and a portion of the second protective layer OC2 covers at least a portion of the wall pattern WP.

[0142] like Figure 7B As shown, in one or more aspects, the display panel P may include a second wall pattern WP2 located in a portion of a second boundary opposite to the first boundary of the first opening H1.

[0143] For example, the second wall pattern WP2 may be disposed in a portion of the second boundary of the first opening H1 adjacent to the second light emitting area EA2 and on the first protective layer OC1. Figure 7B At least a portion of the second wall pattern WP2 may be covered by the second protective layer OC2 or the intermediate layer EL. In one embodiment, the second sub-pixel may be disposed to the right of the first sub-pixel, and another portion of the second protective layer OC2 may cover at least a portion of the wall pattern WP.

[0144] like Figure 7C As shown, in one or more aspects, the display panel P may include a third wall pattern WP3 disposed in respective portions of the first and second boundaries of the first opening H1 and disposed on the first protection layer OC1.

[0145] For example, the third wall pattern WP3 may be respectively provided in a portion of the first boundary of the first opening H1 adjacent to the first light emitting area EA1 and a portion of the second boundary of the first opening H1 adjacent to the second light emitting area EA2. Figure 7C In one embodiment, a portion of the second protection layer OC2 covers at least a portion of the wall pattern WP, and another portion of the second protection layer OC2 covers at least a portion of the second wall pattern WP.

[0146] Therefore, the third wall pattern WP3 may be a configuration including both the first wall pattern WP1 and the second wall pattern WP2 .

[0147] like Figure 7D As shown, in one or more aspects, the display panel P may include a fourth wall pattern WP4 located inside the first opening H1.

[0148] For example, the fourth wall pattern WP4 may be disposed at the center of the first opening H1 and disposed on the first protection layer OC1. Figure 7D The fourth wall pattern WP4 may be covered by the intermediate layer EL. The fourth wall pattern WP4 may be provided on a portion of the first protection layer OC1 between a portion and another portion of the second protection layer OC2.

[0149] Figures 8A to 8D FIG2 shows an example cross section of a display panel including corresponding wall patterns according to various aspects of the present disclosure. In addition to further providing a bank BNK on at least a portion of the second protective layer OC2 and at least corresponding portions of the first electrodes (PE1 and PE2), Figures 8A to 8D The structure can be 7A to 7D The structures are the same or substantially the same.

[0150] like Figure 8A As shown, in one or more aspects, the display panel P may include a first wall pattern WP1 located in a portion of a first boundary of the first opening H1.

[0151] For example, the first wall pattern WP1 may be disposed in a portion of the first boundary of the first opening H1 adjacent to the first light emitting area EA1 and on the first protective layer OC1. Figure 8A At least a portion of the first wall pattern WP1 may be covered by the second protection layer OC2 or the intermediate layer EL.

[0152] like Figure 8B As shown, in one or more aspects, the display panel P may include a second wall pattern WP2 located in a portion of a second boundary opposite to the first boundary of the first opening H1.

[0153] For example, the second wall pattern WP2 may be disposed in a portion of the second boundary of the first opening H1 adjacent to the second light emitting area EA1 and on the first protective layer OC1. Figure 8B At least a portion of the second wall pattern WP2 may be covered by the second protection layer OC2 or the intermediate layer EL.

[0154] like Figure 8C As shown, in one or more aspects, the display panel P may include a third wall pattern WP3 disposed in respective portions of the first and second boundaries of the first opening H1 and disposed on the first protection layer OC1.

[0155] For example, the third wall pattern WP3 may be respectively provided in a portion of the first boundary of the first opening H1 adjacent to the first light emitting area EA1 and a portion of the second boundary of the first opening H1 adjacent to the second light emitting area EA2. Figure 8C As shown in the cross-sectional view.

[0156] Therefore, the third wall pattern WP3 may be a configuration including both the first wall pattern WP1 and the second wall pattern WP2 .

[0157] like Figure 8D As shown, in one or more aspects, the display panel P may include a fourth wall pattern WP4 located inside the first opening H1.

[0158] For example, the fourth wall pattern WP4 may be disposed at the center of the first opening H1 and disposed on the first protection layer OC1. Figure 8D The fourth wall pattern WP4 may be covered by the intermediate layer EL.

[0159] Figure 9 is an example plan view illustrating that a display area is divided into sub-areas at different positions in a display panel according to aspects of the present disclosure.

[0160] In case 1, the display panel 110 can be divided into: a first area A, which is located on a first side of a central data line among multiple data lines located in a central area of the display panel (or display area); a second area B, which is located on a second side of the central data line opposite to the first side; and a third area C, which is between the first area A and the second area B.

[0161] Figure 10A is a cross-sectional view illustrating example positions of wall patterns provided in a display area in Case 1 in a display panel according to aspects of the present disclosure.

[0162] Reference Figure 10A , in which the display panel 110 is divided as follows: a first area A, which is located on a first side of a central data line among a plurality of data lines located in a central area of the display panel (or display area); a second area B, which is located on a second side of the central data line opposite to the first side; and a third area C, which is between the first area A and the second area B. In an example, the wall pattern may be set as follows: when the first opening H1 is located in the first area A, the display panel 110 may include a first wall pattern WP1; when the first opening H1 is located in the second area B, the display panel 110 may include a second wall pattern WP2; and when the first opening H1 is located in the third area C, the display panel 110 may include a third wall pattern WP3 or a fourth wall pattern WP4.

[0163] Return to reference Figure 9In case 2, the display area of the display panel 110 can be divided into: two areas located side by side on a first side of a central data line located in the central area of the display panel (or display area) among a plurality of data lines, and two areas located side by side on a second side of the central data line opposite to the first side.

[0164] For example, Case 2 can be considered as a structure in which, compared with Case 1, when the third area C in Case 1 is divided into two halves relative to the center data line, a first area A and a second area B located on the right and left sides of the center data line are further set in the third area C.

[0165] Therefore, in case 2, the display panel 110 may be divided into a first region A, a second region B, another first region A, and another second region B from the left in the horizontal direction.

[0166] Figure 10B is a cross-sectional view illustrating example positions of wall patterns provided in a display area in Case 2 in a display panel according to aspects of the present disclosure.

[0167] Reference Figure 10B In an example in which the display panel 110 is divided into a left first area A, a left second area B, a right first area A, and a right second area B from the left in the horizontal direction, the wall pattern may be arranged as follows: when the first opening H1 is located in the left first area A or the right first area A, the display panel 110 may include a first wall pattern WP1; and when the first opening H1 is located in the left second area B and the right second area B, the display panel 110 may include a second wall pattern WP2.

[0168] Return to reference Figure 9 In case 3, the display panel 110 can be divided into: a first area A, which is located on a first side of a central data line among a plurality of data lines located in a central area of the display panel (or display area); and a second area B, which is located on a second side of the central data line opposite to the first side.

[0169] Figure 10C is a cross-sectional view illustrating example positions of wall patterns provided in a display area in Case 3 in a display panel according to aspects of the present disclosure.

[0170] Reference Figure 10CIn an example in which the display panel 110 is divided into: a first area A located on a first side of a central data line among a plurality of data lines located in a central area of the display panel (or display area); and a second area B located on a second side of the central data line opposite to the first side, the wall pattern may be set as follows: when the first opening H1 is located in the first area A, the display panel 110 may include a first wall pattern WP1; and when the first opening H1 is located in the second area B, the display panel 110 may include a second wall pattern WP2.

[0171] To enable these examples, as described above, the display device 100 may include a plurality of data lines extending in a column direction of the display panel 110 , and the wall pattern WP may extend in the column direction.

[0172] Figures 11A to 11C Example wall patterns disposed between sub-pixels in a display panel according to aspects of the present disclosure are shown.

[0173] Reference Figure 11A In one or more example embodiments, a wall pattern may be provided in each first opening H1 located between three or four sub-pixels included in a pixel. For example, each of the three or four sub-pixels may emit light of a different color. In one or more aspects, each of the four sub-pixels may emit red light, white light, blue light, and green light, and each of the three sub-pixels may emit red light, blue light, and green light. In the example where a corresponding wall pattern WP is provided in each first opening H1 between the sub-pixels, lateral leakage current can be prevented with a high probability.

[0174] However, in these examples, there may be disadvantages in that the overall aperture ratio of the display panel may be reduced and a design margin may be insufficient.

[0175] In order to solve these problems, such as Figure 11B As shown, at least one wall pattern WP may be provided only in at least one first opening H1 located at at least one side of each green sub-pixel.

[0176] Therefore, considering that the amount of current flowing through the green subpixel is relatively greater than that flowing through the blue or red subpixel, at least one wall pattern WP may be provided only in the at least one first opening H1 located at at least one side of each green subpixel.

[0177] For example, red, green, and blue subpixels may be arranged in this order, and according to this arrangement, a plurality of red, green, and blue subpixels may be arranged in a predefined direction of the display panel 110 .

[0178] Reference Figure 11CEven in an example where three sub-pixels are included in one pixel, at least one wall pattern WP may be provided only in at least one first opening H1 located at at least one side of each green sub-pixel.

[0179] Reference Figure 11C , when the distance between the green sub-pixel and the red sub-pixel is the first distance L1, the distance between the green sub-pixel and the blue sub-pixel is the second distance L2, and the distance between the red sub-pixel and the blue sub-pixel is the third distance L3, the third distance L3 can be smaller than the first distance L1 and the second distance L2.

[0180] As in these implementations, by providing the wall pattern only in the first opening H1 located on one side of the sub-pixel having the highest probability of lateral leakage current among the sub-pixels, reduction in aperture ratio can be minimized and sufficient design margin can be ensured.

[0181] Therefore, the wall pattern can be provided only in the first opening H1 located on one side of the green sub-pixel, and the distances between the sub-pixels of the remaining colors can be set to be smaller than the distance between the green sub-pixel and the adjacent sub-pixel. The first opening H1 containing the wall pattern is located between the green sub-pixel and the adjacent sub-pixel. Thus, the design margin can be reduced.

[0182] The above-mentioned exemplary embodiments will be briefly described as follows.

[0183] According to an example embodiment of the present disclosure, a display device may be provided, comprising: a substrate including a display area allowing an image to be displayed and a non-display area outside the display area; a first protective layer over the substrate; a second protective layer disposed on the first protective layer and having a first opening; a plurality of first electrodes disposed on the second protective layer; and a wall pattern disposed on the first protective layer and located at a boundary or inside the first opening.

[0184] In one or more aspects, the wall pattern may include at least one of the following: a first wall pattern located at a portion of a first boundary of the first opening, a second wall pattern located at a portion of a second boundary opposite to the first boundary of the first opening, a third wall pattern located at corresponding portions of the first boundary and the second boundary of the first opening, and a fourth wall pattern located inside the first opening.

[0185] In one or more aspects, the display area may include: a first area located on a first side of a central data line located in a central area of the display area among a plurality of data lines; and a second area located on a second side of the central data line opposite to the first side, and when the first opening is located in the first area, the wall pattern may include a first wall pattern.

[0186] In one or more aspects, the display area may include: a first area located on a first side of a central data line located in a central area of the display area among a plurality of data lines; and a second area located on a second side of the central data line opposite to the first side, and when the first opening is located in the second area, the wall pattern may include a second wall pattern.

[0187] In one or more aspects, the display area may include: a first area located on a first side of a central data line located in a central area of the display area among a plurality of data lines; a second area located on a second side of the central data line opposite to the first side; and a third area between the first area and the second area, and when the first opening is located in the third area, the wall pattern may include a third wall pattern or a fourth wall pattern.

[0188] In one or more aspects, the display device may further include a common intermediate layer on the plurality of first electrodes and a second electrode on the common intermediate layer, and the common intermediate layer may be configured to extend to the plurality of first electrodes and the wall pattern on the second protective layer.

[0189] For example, leakage current originating from the common intermediate layer may flow through the wall pattern.

[0190] In one or more aspects, the wall pattern may be a ground pattern.

[0191] In one or more aspects, the display device may further include a common intermediate layer on the plurality of first electrodes and a second electrode on the common intermediate layer, and the basic voltage applied to the second electrode may be applied to the wall pattern.

[0192] In one or more aspects, the display device may further include a plurality of data lines extending in a column direction, and the wall pattern may extend in the column direction.

[0193] In one or more aspects, the display area may include a plurality of sub-pixels, and the wall pattern may be disposed between two adjacent sub-pixels of the plurality of sub-pixels.

[0194] In one or more aspects, the display area may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the wall pattern may be provided on at least one side of one of the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

[0195] In one or more aspects, the wall pattern may be provided on at least one side of a green sub-pixel among the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

[0196] In one or more aspects, the leakage current originating from the green sub-pixel can have a larger current amount than the leakage current originating from each of the red sub-pixel and the blue sub-pixel.

[0197] In one or more aspects, the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in this order, and when the distance between the green sub-pixel and the red sub-pixel is a first distance, the distance between the green sub-pixel and the blue sub-pixel is a second distance, and the distance between the red sub-pixel and the blue sub-pixel is a third distance, the third distance may be smaller than the first distance and the second distance.

[0198] In one or more aspects, the display device may further include: a bank covering at least a portion of each of the plurality of first electrodes.

[0199] In one or more aspects, the bank overlaps at least a portion of the wall pattern.

[0200] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first protective layer on the substrate; a second protective layer on the first protective layer, the second protective layer including a portion and another portion, wherein at least a portion of the first protective layer is exposed between the portion and the other portion of the second protective layer; a first sub-pixel and a second sub-pixel on the substrate, wherein a light-emitting element of the first sub-pixel is disposed on a portion of the second protective layer, and a light-emitting element of the second sub-pixel is disposed on another portion of the second protective layer; and a wall pattern disposed on the first protective layer, wherein at least a portion of the wall pattern is covered by the second protective layer or disposed on the exposed portion of the first protective layer.

[0201] The first sub-pixel is disposed on a left side of the second sub-pixel, and a portion of the second protection layer covers at least a portion of the wall pattern.

[0202] The second sub-pixel is disposed on the right side of the first sub-pixel, and another portion of the second protection layer covers at least a portion of the wall pattern.

[0203] The display device may further include a second wall pattern, wherein a portion of the second protective layer covers at least a portion of the wall pattern, and another portion of the second protective layer covers at least a portion of the second wall pattern.

[0204] The display device may further include: a third subpixel and a fourth subpixel on the substrate and a second wall pattern disposed on the first protective layer, wherein the first subpixel and the second subpixel are in a first region of the substrate, wherein the first subpixel is disposed on the left side of the second subpixel, and the wall pattern is closer to the first subpixel than to the second subpixel, and wherein the third subpixel and the fourth subpixel are in a second region of the substrate, wherein the fourth subpixel is disposed on the right side of the third subpixel, and the second wall pattern is closer to the fourth subpixel than to the third subpixel.

[0205] The display device may further include: a fifth subpixel and a sixth subpixel on the substrate, and a third wall pattern disposed on the first protective layer, wherein the fifth subpixel and the sixth subpixel are in a third region of the substrate between the first region and the second region.

[0206] The display device may further include a third sub-pixel on the substrate, wherein at least one of the first sub-pixel and the second sub-pixel emits green light, and wherein no wall pattern is disposed between the second sub-pixel and the third sub-pixel.

[0207] The display device may further include a bank covering at least a portion of the first electrode of the light emitting element of the first sub-pixel.

[0208] The light emitting element of the first sub-pixel may include a first portion of the light emitting layer, and the light emitting element of the second sub-pixel may include a second portion of the light emitting layer, and wherein the light emitting layer is disposed on the wall pattern.

[0209] The above description has been presented to enable any person skilled in the art to implement and use the present invention, and is provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art without departing from the spirit and scope of the present disclosure, and the general principles defined herein may be applied to other embodiments and applications. Although exemplary embodiments have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications and applications are possible without departing from the essential features of the present disclosure. For example, various modifications may be made to specific components of the exemplary embodiments. The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown, but should be given the widest scope consistent with the claims. The scope of protection of the present disclosure should be interpreted according to the claims, and all technical concepts within the scope of the claims should be interpreted as included within the scope of the present disclosure.

Claims

1. A display device comprising: a substrate comprising a display area for displaying an image and a non-display area outside the display area; a first protective layer on the substrate; a second protective layer disposed on the first protective layer and having a first opening; a plurality of first electrodes disposed on the second protective layer; as well as A wall pattern is provided on the first protection layer and is located at a boundary or inside of the first opening.

2. The display device according to claim 1, wherein The wall pattern includes at least one of the following: a first wall pattern located at a portion of a first boundary of the first opening, a second wall pattern located at a portion of a second boundary opposite to the first boundary of the first opening, a third wall pattern located at corresponding portions of the first boundary and the second boundary of the first opening, and a fourth wall pattern located inside the first opening.

3. The display device according to claim 2, wherein: The display area includes: a first area located on a first side of a central data line located in a central area of the display area among a plurality of data lines; and a second area located on a second side of the central data line opposite to the first side, and Wherein, when the first opening is located in the first region, the wall pattern includes the first wall pattern.

4. The display device according to claim 2, wherein The display area includes: a first area located on a first side of a central data line located in a central area of the display area among a plurality of data lines; and a second area located on a second side of the central data line opposite to the first side, and Wherein, when the first opening is located in the second region, the wall pattern includes the second wall pattern.

5. The display device according to claim 2, wherein The display area includes: a first area located on a first side of a central data line located in a central area of the display area among a plurality of data lines; a second area located on a second side of the central data line opposite to the first side; and a third area between the first area and the second area, and Wherein, when the first opening is located in the third region, the wall pattern includes the third wall pattern or the fourth wall pattern.

6. The display device according to claim 1, further comprising: a common intermediate layer on the plurality of first electrodes; as well as a second electrode on the common intermediate layer, The common intermediate layer is configured to extend to the plurality of first electrodes and the wall patterns on the second protective layer.

7. The display device according to claim 6, wherein: A leakage current originating from the common intermediate layer flows through the wall pattern.

8. The display device according to claim 1, wherein The wall pattern is a ground pattern.

9. The display device according to claim 1, further comprising: a common intermediate layer on the plurality of first electrodes; as well as a second electrode on the common intermediate layer, The basic voltage applied to the second electrode is applied to the wall pattern.

10. The display device according to claim 1, further comprising: A plurality of data lines extending in the column direction, Wherein, the wall pattern extends in the column direction.

11. The display device according to claim 1, wherein The display area includes a plurality of sub-pixels, and the wall pattern is disposed between two adjacent sub-pixels among the plurality of sub-pixels.

12. The display device according to claim 1, wherein The display area includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the wall pattern is provided on at least one side of one of the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

13. The display device according to claim 12, wherein: The wall pattern is provided on at least one side of the green sub-pixel among the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

14. The display device according to claim 12, wherein: A leakage current originating from the green sub-pixel has a current amount greater than a leakage current originating from each of the red sub-pixel and the blue sub-pixel.

15. The display device according to claim 12, wherein: The red sub-pixel, the green sub-pixel, and the blue sub-pixel are arranged in this order, and when the distance between the green sub-pixel and the red sub-pixel is a first distance, the distance between the green sub-pixel and the blue sub-pixel is a second distance, and the distance between the red sub-pixel and the blue sub-pixel is a third distance, the third distance is smaller than the first distance and the second distance.

16. The display device according to claim 1, further comprising: A bank covers at least a portion of each of the plurality of first electrodes.

17. The display device according to claim 16, wherein: The bank overlaps at least a portion of the wall pattern.

18. A display device comprising: substrate; a first protective layer on the substrate; a second protective layer on the first protective layer, the second protective layer comprising a portion and another portion, wherein at least a portion of the first protective layer is exposed between the portion and the another portion of the second protective layer; a first sub-pixel and a second sub-pixel on the substrate, wherein the light emitting element of the first sub-pixel is disposed on the portion of the second protective layer, and the light emitting element of the second sub-pixel is disposed on the other portion of the second protective layer; and A wall pattern is provided on the first protective layer, wherein at least a portion of the wall pattern is covered by the second protective layer or is provided on an exposed portion of the first protective layer.

19. The display device according to claim 18, wherein The first sub-pixel is disposed on a left side of the second sub-pixel, and the portion of the second protection layer covers at least a portion of the wall pattern.

20. The display device according to claim 18, wherein The second sub-pixel is disposed on the right side of the first sub-pixel, and the other portion of the second protection layer covers at least a portion of the wall pattern.

21. The display device according to claim 18, further comprising a second wall pattern, wherein The portion of the second protective layer covers at least a portion of the wall pattern, and the other portion of the second protective layer covers at least a portion of the second wall pattern.

22. The display device according to claim 18, further comprising: a third sub-pixel and a fourth sub-pixel on the substrate and a second wall pattern provided on the first protective layer, wherein the first sub-pixel and the second sub-pixel are in a first region of the substrate, wherein the first sub-pixel is disposed on the left side of the second sub-pixel, and the wall pattern is closer to the first sub-pixel than the second sub-pixel, and The third subpixel and the fourth subpixel are in the second region of the substrate, the fourth subpixel is disposed on the right side of the third subpixel, and the second wall pattern is closer to the fourth subpixel than the third subpixel.

23. The display device according to claim 18, further comprising a third sub-pixel on the substrate, wherein: At least one of the first sub-pixel and the second sub-pixel emits green light, and wherein no wall pattern is provided between the second sub-pixel and the third sub-pixel.

24. The display device according to claim 18, further comprising: A bank covers at least a portion of the first electrode of the light-emitting element of the first sub-pixel.

25. The display device according to claim 18, wherein The light emitting element of the first sub-pixel includes a first portion of a light emitting layer, and the light emitting element of the second sub-pixel includes a second portion of the light emitting layer, and wherein the light emitting layer is disposed on the wall pattern.

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