Display device, display panel thereof and preparation method of display panel

Abstract

The invention relates to the technical field of display, in particular to a display device, a display panel of the display device and a preparation method of the display panel. The display device comprises a substrate, a display layer and a first packaging layer, wherein the display layer is arranged on the substrate; the first packaging layer is located on one side, far away from the substrate, of the display layer; the first packaging layer at least comprises an aluminum oxide layer; in the first packaging layer, the aluminum oxide layer is arranged far away from the display layer. According to the display panel, the water vapor blocking capability of the display panel can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display device and a display panel thereof, and a method for manufacturing the display panel. Background Art

[0002] In the related art, an OLED (Organic Light-Emitting Diode) display panel is usually packaged in a three-layer structure: a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer.

[0003] As the application scope of OLED displays expands, such as in-vehicle displays, the requirements for the life of the displays are becoming increasingly higher, and similarly, higher requirements are also being placed on the water vapor transmission rate (WVTR) performance of the encapsulation layer.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and provide a display device and a display panel thereof, and a method for manufacturing a display panel, which can improve the ability of the display panel to block water vapor and improve the packaging performance, thereby better protecting the display panel PNL from water vapor erosion and extending its service life and stability.

[0006] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0007] substrate;

[0008] A display layer is provided on the base substrate;

[0009] The first encapsulation layer is located on a side of the display layer away from the base substrate; the first encapsulation layer at least includes an aluminum oxide layer; in the first encapsulation layer, the aluminum oxide layer is arranged away from the display layer.

[0010] In one embodiment of the present disclosure, the first encapsulation layer further includes a transition layer, and the transition layer is a mixed layer of aluminum oxide and aluminum;

[0011] The transition layer is located between the aluminum oxide layer and the display layer.

[0012] In one embodiment of the present disclosure, the first encapsulation layer further includes an aluminum layer, and the aluminum layer is located between the transition layer and the display layer.

[0013] In one embodiment of the present disclosure, the display layer comprises a driving layer and a pixel layer sequentially stacked on the base substrate;

[0014] The pixel layer comprises a pixel electrode layer, a pixel definition layer, a light-emitting function layer and a common electrode layer sequentially stacked on the driving layer;

[0015] The pixel layer further includes an electrode protection layer located between the first encapsulation layer and the common electrode layer.

[0016] In one embodiment of the present disclosure, the orthographic projection of the electrode protection layer on the base substrate is larger than the orthographic projection of the common electrode layer on the base substrate, and the orthographic projection of the common electrode layer on the base substrate is within the orthographic projection of the electrode protection layer on the base substrate.

[0017] In one embodiment of the present disclosure, the display layer has at least one insulating layer;

[0018] A partial area of at least one of the insulating layers is not covered by the first encapsulation layer;

[0019] The roughness of the surface of the insulating layer not covered by the first encapsulation layer on the side away from the base substrate is greater than the roughness of the surface of the insulating layer covered by the first encapsulation layer on the side away from the base substrate.

[0020] In one embodiment of the present disclosure, the display panel further includes a second encapsulation layer; the second encapsulation layer includes an organic encapsulation layer and a second inorganic encapsulation layer sequentially stacked on the first encapsulation layer;

[0021] The orthographic projection of the second inorganic encapsulation layer on the base substrate is larger than the orthographic projection of the first encapsulation layer on the base substrate, and the orthographic projection of the first encapsulation layer on the base substrate is located within the orthographic projection of the second inorganic encapsulation layer on the base substrate.

[0022] In one embodiment of the present disclosure, the display panel further includes a second encapsulation layer; the second encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the first encapsulation layer;

[0023] The orthographic projection of the first inorganic encapsulation layer on the base substrate is larger than the orthographic projection of the first encapsulation layer on the base substrate, and the orthographic projection of the first encapsulation layer on the base substrate is located within the orthographic projection of the first inorganic encapsulation layer on the base substrate.

[0024] In one embodiment of the present disclosure, the display panel has a display area and a non-display area;

[0025] In the non-display area, the display layer has at least one blocking dam;

[0026] The first encapsulation layer completely covers at least one of the barrier dams close to the display area.

[0027] According to another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0028] According to another aspect of the present disclosure, a method for preparing the display panel is provided, comprising:

[0029] preparing the display layer on the base substrate;

[0030] Prepare an aluminum metal structure on the side of the display layer away from the base substrate to form a first panel;

[0031] The first panel is placed in a chemical vapor deposition device, and an aluminum metal structure is bombarded with oxygen plasma to oxidize at least one side of the aluminum metal structure away from the display layer into an aluminum oxide layer, thereby forming the first encapsulation layer and obtaining the display panel.

[0032] In one embodiment of the present disclosure, the display layer comprises a driving layer and a pixel layer sequentially stacked on the base substrate;

[0033] The pixel layer comprises a pixel electrode layer, a pixel definition layer, a light-emitting function layer, a common electrode layer and an electrode protection layer stacked in sequence on the driving layer; the common electrode layer is prepared by evaporation;

[0034] The aluminum metal structure is prepared by the same evaporation method as the common electrode layer.

[0035] In one embodiment of the present disclosure, the display panel further includes a second encapsulation layer located on a side of the first encapsulation layer away from the display layer;

[0036] After forming the first encapsulation layer, the method further includes:

[0037] A second encapsulation layer is prepared on a side of the first encapsulation layer away from the display layer, and the display panel is obtained.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0040] Figure 1 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0041] Figure 2 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0042] Figure 3 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0043] Figure 4 Schematic diagram of the structure of the first packaging layer in one embodiment of the present disclosure.

[0044] Figure 5 FIG. 1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0046] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0047] The terms "a", "an", "the", "said", and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", etc. are used only as labels and are not intended to limit the quantity of their objects.

[0048] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0049] In an embodiment of the present disclosure, a thin film transistor (TFT) includes an active layer, a gate insulating layer and a gate that are stacked. The active layer is located in the semiconductor layer, and the active layer includes a channel region and a source and a drain located on both sides of the channel region. The channel region maintains semiconductor properties, and the source and the drain are both conductive. In an embodiment of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "drain" and the "source" can be interchanged. In an embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0050] The present disclosure provides a display device, which can be applied to fields such as vehicle-mounted displays, etc. The display device includes a display panel PNL.

[0051] In one embodiment of the present disclosure, the display panel PNL may be an OLED (Organic Light-Emitting Diode, organic light-emitting diode, referred to as OLED) display panel. Figure 1 The display panel PNL includes a display area AA and a non-display area BB located outside the display area AA. The non-display area BB can be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA. The display area AA can be used to emit light to display images, while the non-display area BB does not emit light.

[0052] In this example, see Figure 2 The display panel PNL includes a display layer having a plurality of insulating layers.

[0053] In this example, the display layer includes a driver backplane DBP and a pixel layer PIXL, which are stacked in sequence. The driver backplane DBP may include a stacked base substrate SBT and a driver layer DRL, with the pixel layer PIXL disposed on the side of the driver layer DRL facing away from the base substrate SBT. In this example, the pixel layer PIXL is provided with light-emitting elements LD for display, and the driver layer DRL is provided with pixel circuits PDC that drive each light-emitting element LD to emit light.

[0054] In one embodiment of the present disclosure, the material of the substrate SBT may be an organic material, such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. Of course, the substrate SBT may also be other materials not shown.

[0055] Optionally, in the drive layer (DRL), any pixel circuit may include a thin film transistor (TFT) and a storage capacitor. Furthermore, the thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0056] It is understandable that, among the transistors in the pixel circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0057] In one embodiment of the present disclosure, see Figure 2 and Figure 3 The driving layer DRL may include a semiconductor layer SCL stacked between the substrate SBT and the pixel layer PIXL, a first insulating layer (the first insulating layer is a gate insulating layer GI), a gate layer GT, a second insulating layer (the second insulating layer is an interlayer dielectric layer ILD), a source-drain metal layer SD, and a third insulating layer (the third insulating layer is a planarization layer PLN), etc. Each thin film transistor and storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source-drain metal layer SD. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Furthermore, the semiconductor layer SCL can be used to form the channel region of the transistor, as well as the first and second electrodes located on both sides of the channel region. If necessary, it can also be formed by conductorization to form partial wiring or conductive structure. The gate layer GT can be used to form one or more gate layer wirings such as scan wiring, reset control wiring, and light-emitting control wiring, and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plates of the storage capacitor. The source-drain metal layer SD can be used to form source-drain metal layer wirings such as data wiring and driving power supply voltage wiring, and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may also include an inorganic buffer layer BUF located between the semiconductor layer SCL and the substrate SBT. As needed, any of the above-mentioned semiconductor layer SCL, gate layer GT, source-drain metal layer SD and other film layers may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0058] As an example, the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked sequentially on the surface of the substrate SBT, and the thin film transistor formed in this way is a top-gate thin film transistor. In other examples, the driving layer may include an inorganic buffer layer, a gate layer, a gate insulating layer, a semiconductor layer, a source / drain metal layer, and a planarization layer stacked sequentially on the surface of the substrate SBT, and the thin film transistor formed in this way is a bottom-gate thin film transistor. In other examples, the driving layer may also have a dual-gate thin film transistor, etc.

[0059] It is understandable that the above example of the driving backplane DBP is only one possible manner of the driving backplane DBP in the embodiment of the present disclosure. In other embodiments of the present disclosure, the driving backplane DBP may also have other structures.

[0060] In one embodiment of the present disclosure, see Figure 2 and Figure 3 The light emitting element LD in the pixel layer PIXL is a thin film light emitting element, which may include two stacked electrodes and a light emitting functional layer EFL sandwiched between the two electrodes. Figure 3 The pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML, which are sequentially stacked on the side of the planarization layer PLN facing away from the substrate SBT. The pixel electrode layer PEL includes multiple pixel electrodes. The portion of the light-emitting functional layer EFL connected to the pixel electrodes serves as the light-emitting functional unit of the light-emitting element LD. The common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional units of each light-emitting element LD.

[0061] In this example, see Figure 3 The pixel layer PIXL may further include a fourth insulating layer (the fourth insulating layer is a pixel definition layer PDL) located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional unit), thereby defining the light-emitting area and light-emitting area of the light-emitting element LD. The light-emitting functional layer EFL at least covers the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting functional layer EFL. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The portion of the light-emitting functional layer EFL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrode, the common electrode layer COML, and the light-emitting functional unit form the light-emitting element LD. One of the pixel electrode and the common electrode layer COML serves as an anode of the light emitting element LD, and the other serves as a cathode of the light emitting element LD.

[0062] In an example, the pixel electrode may serve as an anode of the light emitting element LD, and the common electrode layer COML may serve as a cathode of the light emitting element LD.

[0063] In some embodiments of the present disclosure, the types of the light-emitting elements LD are different, and the materials and film layers of the light-emitting functional units are different.

[0064] In this example, the light-emitting functional layer (EFL) may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material.

[0065] In one embodiment of the present disclosure, see Figure 5 The pixel layer PIXL may further have a support column PS, which is disposed on the pixel definition layer PDL (between the common electrode layer COML and the support column PS, for example only, and does not mean that the thickness of the common electrode layer COML at the support column PS is thinner).

[0066] In one embodiment of the present disclosure, see Figure 2 and Figure 3 , the display panel PNL also includes a second encapsulation layer FZ2 located above the display layer. It can be understood that the second encapsulation layer FZ2 is located on the side of the pixel layer PIXL away from the driving layer DRL. In one example, the second encapsulation layer FZ2 can be a thin film encapsulation layer TFE. In this example, the second encapsulation layer FZ2 includes an inorganic encapsulation layer and an organic encapsulation layer that are alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PIXL, which may cause aging of the material in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the non-display area BB. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area AA and the edge of the inorganic encapsulation layer. For example, see Figure 3 The second encapsulation layer FZ2 includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT. Of course, in other embodiments of the present disclosure, the display panel PNL can also use other methods to encapsulate and protect the pixel layer PIXL.

[0067] In one embodiment of the present disclosure, the materials of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 can be SiON or SiN or SiO x .

[0068] In one embodiment of the present disclosure, in the non-display area BB, the display layer further comprises at least one barrier dam DAM. The barrier dam DAM is disposed on the pixel definition layer PDL (in this example, the barrier dam DAM is disposed on the same layer as the support pillars PS). A second encapsulation layer FZ2 is located on the side of the barrier dam DAM away from the base substrate SBT. At least a portion of the orthographic projection of the barrier dam DAM on the base substrate SBT is located within the orthographic projection of the second encapsulation layer FZ2 on the base substrate SBT, and the second encapsulation layer FZ2 at least partially covers the barrier dam DAM. The barrier dam DAM cooperates with the second encapsulation layer FZ2 to further block the intrusion of external moisture and oxygen, thereby extending the service life of the display panel PNL. In one example, there is one barrier dam DAM, which can be annular in shape. The barrier dam DAM is disposed on the side of the pixel definition layer PDL away from the base substrate SBT, and the barrier dam DAM is disposed around the display area AA. In another example, there are at least two barrier dams DAM, for example, two, three, five, or the like. The barrier dams DAM are sequentially arranged in a direction away from the display area AA, and gaps are provided between the barrier dams DAM.

[0069] Of course, in other embodiments, the blocking dam DAM can also be formed by stacking film layers such as the pixel definition layer PDL and the support pillar PS. In one example, there may be a gap between the blocking dam DAM and the pixel definition layer PDL, which exposes insulating layers such as the planarization layer PLN located under the pixel definition layer PDL.

[0070] In related technologies, OLED display panels are usually encapsulated using the aforementioned second encapsulation layer, which is prepared using chemical vapor deposition (CVD) equipment. In applications, the water-oxygen barrier efficiency (WVTR) of the inorganic encapsulation layer is generally used to evaluate the encapsulation capability of the display panel. The MOCON / Technolox equipment commonly used in the industry for evaluation is generally used. The WVTR of SiON / SiN (inorganic material / inorganic encapsulation layer) is generally in the range of 1*10 -3 g*m 2 / day~5*10 -4 g*m 2 / day.

[0071] As the application scope of OLED displays expands, such as in-vehicle displays, the requirements for display life are becoming increasingly higher, and the WVTR performance of the packaging function is also subject to higher requirements.

[0072] In order to further improve the packaging effect of the display panel PNL and reduce the water and oxygen barrier efficiency, in this disclosure, see Figure 3-Figure 5 , add aluminum oxide layer ALOC for double packaging. The water and oxygen barrier efficiency (WVTR) of aluminum oxide layer ALOC can reach 5*10-5 g*m 2 / day, which improves the ability of the display panel PNL to block water vapor, thereby better protecting the display panel PNL from water vapor erosion and extending its service life and stability.

[0073] In one embodiment of the present disclosure, see Figure 3-Figure 5 A first encapsulation layer FZ1 is provided between the display layer and the second encapsulation layer FZ2. It is understood that the first encapsulation layer FZ1 is located between the pixel layer PIXL and the second encapsulation layer FZ2. It is understood that the first encapsulation layer FZ1 is located between the common electrode layer COML and the second encapsulation layer FZ2.

[0074] In one example, see Figure 3-Figure 5 The first encapsulation layer FZ1 is an aluminum oxide layer ALOC (it can be understood that the material of the aluminum oxide layer ALOC is aluminum oxide Al2O3). In the present disclosure, the aluminum oxide layer ALOC is provided between the common electrode layer COML and the second encapsulation layer FZ2 (the first inorganic encapsulation layer CVD1). The water and oxygen barrier efficiency (WVTR) of the aluminum oxide layer ALOC can reach 5*10 -5 g*m 2 / day, thereby greatly improving the ability of the display panel PNL to block water vapor and improving the packaging performance, so as to better protect the display panel PNL from water vapor erosion and extend its service life and stability.

[0075] The present disclosure also provides a method for preparing a display panel PNL. The method provided in the present disclosure does not require the use of atomic layer deposition equipment (ALD) to prepare the first encapsulation layer FZ1. Instead, the first encapsulation layer FZ1 is prepared through existing evaporation equipment and chemical vapor deposition equipment (CVD), thereby improving the film formation rate (the film formation rate of the atomic layer deposition equipment (ALD) is relatively low), which can meet the utilization rate requirements of the production line without increasing costs too much.

[0076] Specifically, the preparation method includes:

[0077] The driving layer DRL and the pixel layer PIXL are sequentially prepared on the substrate SBT, wherein the common electrode layer COML is prepared by evaporation;

[0078] An aluminum metal structure is prepared on the side of the pixel layer PIXL away from the substrate SBT to form a first panel; wherein the aluminum metal structure is deposited in the same manner as the common electrode layer COML;

[0079] The first panel is sent to a chemical vapor deposition device (CVD) through a vacuum transmission device; in the chemical vapor deposition device (CVD), oxygen (O2) is used as a raw material, and the chemical vapor deposition device (CVD) ionizes the oxygen (O2) into O plasma, and bombards the surface of the aluminum metal structure with the O plasma (oxygen plasma) until the aluminum metal structure is completely oxidized through an oxidation reaction to form a dense aluminum oxide layer, thereby forming a first encapsulation layer FZ1.

[0080] This disclosure provides a method for achieving the encapsulation of the first encapsulation layer (aluminum oxide layer (Al2O3)) using existing evaporation equipment and chemical vapor deposition equipment. This method can improve product packaging reliability and extend service life. This method solves the problem that existing chemical vapor deposition equipment cannot achieve aluminum oxide layer (Al2O3) encapsulation.

[0081] In the present disclosure, since the aluminum oxide layer (Al2O3) is completed in a chemical vapor deposition device, in order to further improve its packaging performance, the same device can also be used to continue the packaging process of the second packaging layer FZ2 (first inorganic packaging layer CVD1 (chemical vapor deposition process), organic packaging layer IJP (inkjet printing process) and second inorganic packaging layer CVD2 (chemical vapor deposition process)), that is, the second packaging layer FZ2 is prepared on the side of the first packaging layer FZ1 away from the base substrate SBT to obtain the display panel PNL.

[0082] Of course, in other examples, the display panel PNL may further include other film layers not shown on the side of the second encapsulation layer FZ2 away from the base substrate SBT.

[0083] Of course, in this example, see Figure 3 and Figure 5 The pixel layer PIXL may also include an electrode protection layer CPL. The electrode protection layer CPL is located between the common electrode layer COML and the first encapsulation layer FZ1 (aluminum oxide layer ALOC). The electrode protection layer CPL is used to protect the common electrode layer COML and reduce the adverse electrical effects caused by contact between the common electrode layer COML and aluminum (Al). In other words, the provision of the electrode protection layer CPL can ensure the display performance and electrical performance of the display panel PNL.

[0084] In this example, see Figure 5The orthographic projection of the electrode protection layer CPL on the base substrate SBT is larger than the orthographic projection of the common electrode layer COML on the base substrate SBT, and the orthographic projection of the common electrode layer COML on the base substrate SBT is located within the orthographic projection of the electrode protection layer CPL on the base substrate SBT (that is, the electrode protection layer CPL completely covers the common electrode layer COML (the electrode protection layer CPL covers the surface of the common electrode layer COML away from the base substrate SBT side and covers the edge of the common electrode layer COML)). In this way, the adverse electrical effects caused by the contact between the common electrode layer COML and aluminum (Al) can be avoided. In other words, the provision of the electrode protection layer CPL can ensure the display performance and electrical performance of the display panel PNL.

[0085] In another example, see Figure 3-Figure 5 The first encapsulation layer FZ1 has a two-layer structure, including an aluminum oxide layer ALOC (Al2O3) and a transition layer GDC. The transition layer GDC is a mixed layer of aluminum oxide (Al2O3) and aluminum (Al). In other words, the material of the transition layer GDC is a mixture of aluminum oxide (Al2O3) and aluminum (Al). The aluminum oxide layer ALOC is arranged near the second encapsulation layer FZ2, and the transition layer GDC is located between the aluminum oxide layer ALOC and the common electrode layer COML.

[0086] In this example, see Figure 3 and Figure 5 The pixel layer PIXL also includes an electrode protection layer (CPL). The electrode protection layer (CPL) is located between the common electrode layer (COML) and the transition layer (GDC). The electrode protection layer (CPL) protects the common electrode layer (COML) and reduces the electrical effects of contact between the common electrode layer (COML) and aluminum (Al). In other words, the electrode protection layer (CPL) ensures the display and electrical performance of the display panel (PNL).

[0087] In this example, see Figure 3 and Figure 5 The orthographic projection of the electrode protection layer CPL on the base substrate SBT is larger than the orthographic projection of the common electrode layer COML on the base substrate SBT, and the orthographic projection of the common electrode layer COML on the base substrate SBT is located within the orthographic projection of the electrode protection layer CPL on the base substrate SBT (that is, the electrode protection layer CPL completely covers the common electrode layer COML (the electrode protection layer CPL covers the surface of the common electrode layer COML away from the base substrate SBT side and covers the edge of the common electrode layer COML)). In this way, the adverse electrical effects caused by the contact between the common electrode layer COML and aluminum (Al) can be avoided. In other words, the provision of the electrode protection layer CPL can ensure the display performance and electrical performance of the display panel PNL.

[0088] In another example, see Figure 3 、 Figure 4 and Figure 5 The first encapsulation layer FZ1 has a three-layer structure, including an aluminum oxide layer ALOC (Al2O3), a transition layer GDC, and an aluminum layer ALC. The transition layer GDC is a mixed layer of aluminum oxide (Al2O3) and aluminum (Al), and the aluminum layer ALC is made of aluminum. The aluminum oxide layer ALOC is located adjacent to the second encapsulation layer FZ2, and the aluminum layer ALC is located adjacent to the common electrode layer COML. In other words, the first encapsulation layer FZ1 includes the aluminum layer ALC, transition layer GDC, and aluminum oxide layer ALOC (Al2O3), stacked sequentially on the common electrode layer COML in a direction away from the substrate SBT.

[0089] In this example, see Figure 3 and Figure 5 The pixel layer PIXL also includes an electrode protection layer CPL. The electrode protection layer CPL is located between the common electrode layer COML and the aluminum layer ALC. The electrode protection layer CPL is used to protect the common electrode layer COML and reduce the adverse electrical effects caused by contact between the common electrode layer COML and aluminum (Al). In other words, the provision of the electrode protection layer CPL can ensure the display performance and electrical performance of the display panel PNL.

[0090] In this example, the display panel PNL includes a base substrate SBT, a driving layer DRL, a pixel layer PIXL, a first encapsulation layer FZ1 and a second encapsulation layer FZ2, wherein the first encapsulation layer FZ1 is a multi-layer structure. In other words, the first encapsulation layer FZ1 includes at least an aluminum oxide layer ALOC and a transition layer GDC; it can be understood that the first encapsulation layer FZ1 is an aluminum oxide layer ALOC and a transition layer GDC, or the first encapsulation layer FZ1 is an aluminum oxide layer ALOC, a transition layer GDC and an aluminum layer ALC.

[0091] The preparation method comprises:

[0092] A driving layer DRL and a pixel layer PIXL are sequentially formed on a substrate SBT, wherein a common electrode layer COML is formed by evaporation, and an electrode protection layer CPL is formed by evaporation on a side of the common electrode layer COML away from the substrate SBT;

[0093] An aluminum metal structure is prepared on the side of the electrode protection layer CPL away from the substrate SBT to form a first panel; wherein the aluminum metal structure is deposited in the same manner as the common electrode layer COML;

[0094] The first panel is transported to a chemical vapor deposition (CVD) device via a vacuum transport device. In the CVD device, oxygen (O2) is used as a raw material. The CVD device ionizes the oxygen (O2) into O plasma, and bombards the surface of the aluminum metal structure with the O plasma until at least the surface of the aluminum metal structure away from the substrate SBT is oxidized into aluminum oxide through an oxidation reaction, thereby forming a first encapsulation layer FZ1.

[0095] A second encapsulation layer FZ2 is formed on a side of the first encapsulation layer FZ1 away from the substrate SBT to obtain a display panel PNL.

[0096] Of course, in other examples, the display panel PNL may further include other film layers not shown on the side of the second encapsulation layer FZ2 away from the base substrate SBT.

[0097] In this example, see Figure 3 and Figure 5 The orthographic projection of the electrode protection layer CPL on the base substrate SBT is larger than the orthographic projection of the common electrode layer COML on the base substrate SBT, and the orthographic projection of the common electrode layer COML on the base substrate SBT is located within the orthographic projection of the electrode protection layer CPL on the base substrate SBT. This can avoid the adverse electrical effects caused by contact between the common electrode layer COML and aluminum (Al). In other words, the provision of the electrode protection layer CPL can ensure the display performance and electrical performance of the display panel PNL.

[0098] In one embodiment of the present disclosure, the orthographic projection of the first inorganic encapsulation layer CVD1 on the substrate SBT is larger than the orthographic projection of the first encapsulation layer FZ1 on the substrate SBT, and the orthographic projection of the first encapsulation layer FZ1 on the substrate SBT is located within the orthographic projection of the first inorganic encapsulation layer CVD1 on the substrate SBT. Since the aluminum oxide layer ALOC (Al2O3) is formed by oxidation, the adhesion of the underlying aluminum (Al) to the underlying film layer (pixel definition layer PDL) is lower than the adhesion of inorganic film layers such as the first inorganic encapsulation layer CVD1 to the underlying film layer. Therefore, the present disclosure stipulates that the orthographic projection of the first encapsulation layer FZ1 on the substrate SBT is located within the orthographic projection of the first inorganic encapsulation layer CVD1 on the substrate SBT, so that the boundary of the first encapsulation layer FZ1 should be covered by the first inorganic encapsulation layer CVD1. This can prevent the first encapsulation layer FZ1 from falling off due to external forces, or external static electricity from being transmitted to the display area AA through the underlying Al, resulting in poor display.

[0099] In one embodiment of the present disclosure, when the barrier dam DAM and the support pillar PS are provided on the same layer, the orthographic projection of the pixel definition layer PDL on the base substrate SBT is larger than the orthographic projection of the first encapsulation layer FZ1 on the base substrate SBT; furthermore, the surface roughness of the pixel definition layer PDL not covered by the first encapsulation layer FZ1 on the side away from the base substrate SBT is greater than the surface roughness of the pixel definition layer PDL covered by the first encapsulation layer FZ1 on the side away from the base substrate SBT. This is because oxygen plasma is used to treat the surface of the aluminum metal structure in a chemical vapor deposition (CVD) device. Since oxygen plasma has a certain etching effect on organic / inorganic film layers such as the planarization layer PLN, the roughness of the film layer below the area not covered by the aluminum metal structure increases.

[0100] In another embodiment, the barrier dam DAM may also be formed by stacking a pixel definition layer PDL and support pillars PS, and a gap may be provided between the barrier dam DAM and the pixel definition layer PDL, exposing the planarization layer PLN located below the pixel definition layer PDL. In this case, the roughness of the surface of the pixel definition layer PDL and the planarization layer PLN not covered by the first encapsulation layer FZ1 on the side facing away from the base substrate SBT is greater than the roughness of the corresponding surface of the pixel definition layer PDL and the planarization layer PLN covered by the first encapsulation layer FZ1 on the side facing away from the base substrate SBT.

[0101] Of course, in other embodiments, the gap may expose other insulating layers.

[0102] In one embodiment of the present disclosure, the first encapsulation layer FZ1 at least completely covers the first barrier dam DAM. In this way, the first encapsulation layer FZ1, the barrier dam DAM and the second encapsulation layer FZ2 form a triple protection, further improving the encapsulation effect of the display panel PNL.

[0103] In another embodiment of the present disclosure, the second encapsulation layer FZ2 may also include an organic encapsulation layer IJP and a second inorganic encapsulation layer CVD2 sequentially stacked on the first encapsulation layer FZ1. It is understood that an aluminum oxide layer ALOC is provided between the common electrode layer COML and the second encapsulation layer FZ2 (organic encapsulation layer IJP).

[0104] In this example, the orthographic projection of the second inorganic encapsulation layer CVD2 on the substrate SBT is larger than the orthographic projection of the first encapsulation layer FZ1 on the substrate SBT, and the orthographic projection of the first encapsulation layer FZ1 on the substrate SBT is located within the orthographic projection of the second inorganic encapsulation layer CVD2 on the substrate SBT. Since the aluminum oxide layer ALOC (Al2O3) is formed by oxidation, the adhesion between the underlying aluminum (Al) and the underlying film layer (pixel definition layer PDL) is lower than the adhesion between the second inorganic encapsulation layer CVD2 and the underlying film layer. Therefore, the present disclosure stipulates that the orthographic projection of the first encapsulation layer FZ1 on the substrate SBT is located within the orthographic projection of the second inorganic encapsulation layer CVD2 on the substrate SBT, so that the boundary of the first encapsulation layer FZ1 should be covered by the second inorganic encapsulation layer CVD2. This can prevent external forces from causing the first encapsulation layer FZ1 to fall off, or external static electricity from being transmitted to the display area AA through the underlying Al, resulting in poor display.

[0105] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; A display layer is provided on the base substrate; The first encapsulation layer is located on a side of the display layer away from the base substrate; the first encapsulation layer at least includes an aluminum oxide layer; in the first encapsulation layer, the aluminum oxide layer is arranged away from the display layer.

2. The display panel according to claim 1, wherein: The first encapsulation layer further includes a transition layer, which is a mixed layer of aluminum oxide and aluminum; The transition layer is located between the aluminum oxide layer and the display layer.

3. The display panel according to claim 2, wherein: The first encapsulation layer further includes an aluminum layer, and the aluminum layer is located between the transition layer and the display layer.

4. The display panel according to any one of claims 1 to 3, wherein: The display layer comprises a driving layer and a pixel layer sequentially stacked on the base substrate; The pixel layer comprises a pixel electrode layer, a pixel definition layer, a light-emitting function layer and a common electrode layer sequentially stacked on the driving layer; The pixel layer further includes an electrode protection layer located between the first encapsulation layer and the common electrode layer.

5. The display panel according to claim 4, wherein: The orthographic projection of the electrode protection layer on the base substrate is larger than the orthographic projection of the common electrode layer on the base substrate, and the orthographic projection of the common electrode layer on the base substrate is located within the orthographic projection of the electrode protection layer on the base substrate.

6. The display panel according to claim 1, wherein: The display layer has at least one insulating layer; A partial area of at least one of the insulating layers is not covered by the first encapsulation layer; The roughness of the surface of the insulating layer not covered by the first encapsulation layer on the side away from the base substrate is greater than the roughness of the surface of the insulating layer covered by the first encapsulation layer on the side away from the base substrate.

7. The display panel according to claim 1, wherein: The display panel further includes a second encapsulation layer; the second encapsulation layer includes an organic encapsulation layer and a second inorganic encapsulation layer sequentially stacked on the first encapsulation layer; The orthographic projection of the second inorganic encapsulation layer on the base substrate is larger than the orthographic projection of the first encapsulation layer on the base substrate, and the orthographic projection of the first encapsulation layer on the base substrate is located within the orthographic projection of the second inorganic encapsulation layer on the base substrate.

8. The display panel according to claim 1, wherein: The display panel further includes a second encapsulation layer; the second encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the first encapsulation layer; The orthographic projection of the first inorganic encapsulation layer on the base substrate is larger than the orthographic projection of the first encapsulation layer on the base substrate, and the orthographic projection of the first encapsulation layer on the base substrate is located within the orthographic projection of the first inorganic encapsulation layer on the base substrate.

9. The display panel according to claim 1, wherein: The display panel has a display area and a non-display area; In the non-display area, the display layer has at least one blocking dam; The first encapsulation layer completely covers at least one of the barrier dams close to the display area.

10. A display device, characterized in that: A display panel according to any one of claims 1 to 9.

11. A method for preparing a display panel according to any one of claims 1 to 9, characterized in that: include: preparing the display layer on the base substrate; Prepare an aluminum metal structure on the side of the display layer away from the base substrate to form a first panel; The first panel is placed in a chemical vapor deposition device, and an aluminum metal structure is bombarded with oxygen plasma to oxidize at least one side of the aluminum metal structure away from the display layer into an aluminum oxide layer, thereby forming the first encapsulation layer and obtaining the display panel.

12. The method for manufacturing a display panel according to claim 11, wherein: The display layer comprises a driving layer and a pixel layer sequentially stacked on the base substrate; The pixel layer comprises a pixel electrode layer, a pixel definition layer, a light-emitting function layer, a common electrode layer and an electrode protection layer stacked in sequence on the driving layer; the common electrode layer is prepared by evaporation; The aluminum metal structure is prepared by the same evaporation method as the common electrode layer.

13. The method for manufacturing a display panel according to claim 11, wherein: The display panel further includes a second encapsulation layer located on a side of the first encapsulation layer away from the display layer; After forming the first encapsulation layer, the method further includes: A second encapsulation layer is prepared on a side of the first encapsulation layer away from the display layer, and the display panel is obtained.

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