MEMS packaging structure and electronic equipment

Abstract

The invention discloses an MEMS (Micro Electro Mechanical System) packaging structure and electronic equipment. The MEMS packaging structure comprises a substrate, a cover body, an MEMS chip and an ASIC (Application Specific Integrated Circuit) chip, an opening structure is arranged on the substrate; the cover body is arranged on the first surface of the substrate, and an accommodating cavity is formed between the cover body and the substrate; the MEMS chip is positioned in the accommodating cavity and is arranged on the first surface of the substrate; the ASIC chip is embedded in the substrate, the ASIC chip is provided with a first bonding pad, and the first bonding pad is arranged opposite to the opening structure so as to be electrically connected to the MEMS chip through routing of the opening structure. When the MEMS packaging structure provided by the invention is used for a microphone product, the device performance can be improved.

Description

Technical Field

[0001] The present application belongs to the field of MEMS structure technology, and specifically relates to a packaging structure and an electronic device. Background Art

[0002] Existing MEMS (Micro-Electro-Mechanical Systems) packaging structures typically mount a MEMS chip and an ASIC (Application-Specific Integrated Circuit) chip side by side on a PCB, then solder a housing to the PCB. This packaging approach results in a larger product, and since both chips fit into the same space, heat generated by the ASIC chip can affect the performance of the MEMS chip, leading to reduced product performance.

[0003] To solve the above problem, there is a solution in the prior art to embed the ASIC chip inside the substrate. Although this can solve the above problem, the high impedance pins of the ASIC chip will cause parasitic capacitance and leakage problems, thereby reducing product performance. Summary of the Invention

[0004] The present application aims to provide a MEMS packaging structure and an electronic device to at least solve one of the problems of the background technology.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] According to a first aspect of the present application, a MEMS packaging structure is provided, comprising:

[0007] A substrate, wherein a first surface of the substrate is provided with an open hole structure;

[0008] a cover body, the cover body being buckled onto the first surface and forming a receiving cavity between the cover body and the substrate;

[0009] A MEMS chip is located in the accommodating cavity and is disposed on the first surface of the substrate;

[0010] An ASIC chip is embedded in the substrate and has a first pad. The first pad is exposed on the first surface through the opening structure so as to be electrically connected to the MEMS chip through a wiring of the opening structure.

[0011] Optionally, there are multiple first pads, one opening structure is provided, and the multiple first pads are electrically connected to the MEMS chip through one opening structure wiring; or,

[0012] The opening structures are provided in a plurality corresponding to the number of the first pads, and the plurality of first pads are electrically connected to the MEMS chip through the plurality of opening structure wirings in a one-to-one correspondence.

[0013] Optionally, in the thickness direction of the substrate, the opening structure includes a first opening and a second opening that are connected to each other, a plurality of first pads are provided, the number of the first openings is the same as the number of the first pads, and the projection of each first opening in the thickness direction of the substrate falls within the second opening;

[0014] Among them, multiple first bonding pads are electrically connected to the MEMS chip through gold wires respectively, and each gold wire passes through each first opening one by one and passes through the second opening together, so that each first bonding pad is electrically connected to the MEMS chip.

[0015] Optionally, in the thickness direction of the substrate, the projection of the first pad on the substrate completely falls inside the open hole structure, and is at a distance of 30 μm to 100 μm from the edge of the open hole structure.

[0016] Optionally, in a thickness direction of the substrate, a projection of the ASIC chip on the substrate and a projection of the MEMS chip on the substrate at least partially overlap.

[0017] Optionally, the substrate includes a conductive structure, wherein a first end of the conductive structure is located inside the substrate, and a second end of the conductive structure extends from the inside of the substrate to a second surface of the substrate to form an exposed external pad area, and the second surface is located on the opposite side of the first surface;

[0018] The ASIC chip further has a second pad electrically connected to the first end of the conductive structure, and the outer pad area is used for electrically connecting to an external circuit.

[0019] Optionally, the substrate further includes an insulating area and a metal area surrounding the insulating area, the conductive structure and the ASIC chip are both located in the insulating area, and the metal area is grounded.

[0020] Optionally, the second pad is located on a side of the ASIC chip facing the first surface, and the conductive structure extends from a side of the ASIC chip close to the first surface, around the ASIC chip, to a side away from the first surface.

[0021] Optionally, a plurality of the second pads are provided, the number of the conductive structures is the same as the number of the second pads, and each of the second pads is electrically connected to the second surface through each of the conductive structures in a one-to-one correspondence.

[0022] According to a second aspect of the present application, an electronic device is provided, comprising: the MEMS packaging structure described in the first aspect.

[0023] In an embodiment of the present application, an opening structure is provided on the first surface of the substrate, and the ASIC chip is embedded in the interior of the substrate, so that the first pad of the ASIC chip can be exposed on the first surface of the substrate, and then the first pad and the MEMS chip are electrically connected by routing directly through the opening structure, thereby realizing electrical connection between the ASIC chip and the MEMS chip.

[0024] Embedding the ASIC chip within the substrate prevents the heat generated by the chip from affecting the performance of the MEMS chip, while also saving space in the housing cavity, improving the performance of the MEMS chip and reducing the size of the package structure. Furthermore, this application allows the first pad to be routed through the opening structure to connect directly to the MEMS chip, avoiding the parasitic capacitance and leakage problems caused by the high-impedance pins of the ASIC chip, thereby improving the product's SNR and acoustic performance.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0027] Figure 1 This is a top view of the MEMS packaging structure provided in this application (without the cover).

[0028] Figure 2 The MEMS packaging structure provided by this application is Figure 1 Cross-sectional view at GG in the middle;

[0029] Figure 3 yes Figure 2 A partial enlarged view of point A in the middle;

[0030] Figure 4 The MEMS packaging structure provided by this application is Figure 3 Cross-sectional view of the section at BB;

[0031] Figure 5 The MEMS packaging structure provided by this application is Figure 3 Cross-sectional view of the section at CC;

[0032] Figure 6 The MEMS packaging structure provided by this application is Figure 3 Cross-sectional view of the section at DD;

[0033] Figure 7 yes Figure 6 Schematic diagram of the connection between the ASIC chip and the conductive structure;

[0034] Figure 8 The MEMS packaging structure provided by this application is Figure 3 Cross-sectional view of the section at EE;

[0035] Figure 9 The MEMS packaging structure provided by this application is Figure 3 Cross-sectional view of the section at FF;

[0036] Figure 10 It is a schematic structural diagram of the second surface of the substrate provided in this application.

[0037] Reference numerals:

[0038] 1. Substrate; 11. Opening structure; 111. First opening; 112. Second opening; 12. Conductive structure; 13. Metal area; 14. External pad area; 15. Insulation area; 16. First surface; 17. Second surface; 18. Ground pad; 2. Cover; 21. Accommodating cavity; 3. MEMS chip; 4. ASIC chip; 41. First pad; 42. Second pad; 421. VDD trace; 422. DATA trace; 423. CLK trace; 424. L / R trace; 5. Gold wire. DETAILED DESCRIPTION

[0039] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of protection of the present application.

[0040] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly refer to one or more of the features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more. Furthermore, "and / or" in the specification and claims refers to at least one of the connected entities, and the character " / " generally indicates an "or" relationship between the connected entities.

[0041] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0042] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0043] The following combination Figures 1-10 A MEMS packaging structure and an electronic device according to embodiments of the present application are described.

[0044] like Figures 1 to 10 As shown, according to the first aspect of the present application, a MEMS packaging structure is provided, including: a substrate 1, a cover body 2, a MEMS chip 3 and an ASIC chip 4; the first surface 16 of the substrate 1 is provided with an opening structure 11; the cover body 2 is buckled onto the first surface 16, and forms a receiving cavity 21 between the cover body 2 and the substrate 1; the MEMS chip 3 is located in the receiving cavity 21 and is provided on the first surface 16 of the substrate 1; the ASIC chip 4 is embedded in the interior of the substrate 1 and has a first solder pad 41, and the first solder pad 41 is exposed to the first surface 16 through the opening structure 11, so as to be electrically connected to the MEMS chip 3 through the routing of the opening structure 11.

[0045] Specifically, in this embodiment, by embedding the ASIC chip 4 within the substrate 1, compared to placing it directly on the first surface 16 of the substrate 1, the space occupied by the housing cavity 21 is reduced. When the MEMS packaging structure is applied to a microphone product, the housing cavity 21 serves as the product's back cavity, which can increase the back cavity and improve the product's SNR (Signal-to-Noise Ratio). Furthermore, the heat generated by the ASIC chip 4 is prevented from interfering with the MEMS chip 3, further improving the product's SNR. A higher SNR for a microphone product results in clearer and purer sound, stronger anti-interference capabilities, and superior recording quality, particularly in noisy environments.

[0046] It can be understood that when the ASIC chip 4 is embedded in the interior of the substrate 1, Figure 2 , which can be in the thickness direction of the substrate 1 ( Figure 2 The ASIC chip 4 is arranged overlapping or intersecting with the MEMS chip 3 in the X direction (in the X direction) of the substrate 1. Compared to placing the ASIC chip 4 directly on the first surface 16 of the substrate 1, it does not need to be placed side by side with the MEMS, which facilitates the miniaturization of the MEMS packaging structure. Furthermore, when the MEMS packaging structure is used in a microphone product, embedding the ASIC chip 4 within the substrate 1 can enhance the product's anti-RF (radio frequency interference) capabilities.

[0047] Furthermore, in this embodiment, the substrate 1 is provided with an opening structure 11 connected to the first surface 16. When the ASIC chip 4 is embedded in the interior of the substrate 1, the first pad 41 can be exposed to the first surface 16 of the substrate 1 through the opening structure 11. Figures 1 to 3 , that is, the first pad 41 is arranged opposite to the opening structure 11 and can be directly in contact with the outside, so that the MEMS chip 3 can be directly electrically connected to the first pad 41 through routing, for example, the first pad 41 and the MEMS chip 3 are connected by a gold wire 5 to achieve electrical connection with the ASIC chip 4.

[0048] Compared to placing the ASIC chip 4 inside the substrate 1, the above-described method of directly connecting the ASIC chip 4 and the MEMS chip 3 by routing wires through the opening structure 11 avoids the generation of parasitic capacitance in high-impedance situations and leakage problems, thereby improving the safety and reliability of the MEMS packaging structure and ensuring the acoustic performance of the product. Furthermore, it saves the process and material costs of making the pads on the substrate 1, reducing the production cost of the MEMS packaging structure.

[0049] For example, Figure 1 As shown, in one embodiment, the ASIC chip 4 has three pads (first pad 41) of Vmic, Vin and Vsub for connecting to the MEMS chip 3, wherein the Vmic and Vin pads are both high-impedance pins. When the ASIC chip 4 is embedded in the substrate 1, if it is connected to the MEMS chip 3 through the pads on the first surface 16 of the substrate 1, parasitic capacitance will be generated, which will cause the SNR of the MEMS packaging structure to be correspondingly reduced when used for a microphone.

[0050] In this application, an opening structure 11 is provided on the first surface 16 of the substrate 1, allowing the three pads (Vmic, Vin, and Vsub) of the ASIC chip 4 to be directly electrically connected to the MEMS chip 3 via gold wires 5. This avoids the generation of parasitic capacitance and leakage problems, thereby improving the acoustic performance and safety of the product. Furthermore, this approach eliminates the cost of RDL (Re-distribution Layer) required to provide pads on the substrate 1, reducing production costs.

[0051] It can be understood that in the above embodiment, the first solder pad 41 exposed on the first surface 16 of the substrate 1 means that it can be directly connected to the outside, and does not mean that the first solder pad 41 needs to protrude from the first surface 16 of the substrate 1 or be flush with the first surface 16. Optionally, the surface of the first solder pad 41 is generally lower than the first surface 16 of the substrate 1 so that the opening structure 11 can protect the first solder pad 41.

[0052] Alternatively, as Figures 1 to 2 As shown, there are multiple first solder pads 41, and one opening structure 11 is provided. The multiple first solder pads 41 are electrically connected to the MEMS chip 3 through one opening structure 11; or, the opening structure 11 is provided with multiple first solder pads 41 corresponding to the number of first solder pads 41, and the multiple first solder pads 41 are electrically connected to the MEMS chip 3 through multiple opening structures 11 respectively.

[0053] Specifically, in this embodiment, three first pads 41 are typically provided when connecting the ASIC chip 4 to the MEMS chip 3, namely, the three pins Vmic, Vin, and Vsub. In practical applications, only one opening structure 11 may be provided, and the gold wires 5 electrically connecting the multiple first pads 41 to the MEMS chip 3 all pass through the same opening structure 11. This simplifies the processing steps of the substrate 1, reducing process requirements and production costs.

[0054] In another embodiment, multiple opening structures 11 can be provided to correspond to the number of first pads 41. For example, three opening structures 11 can be provided to correspond to the three pins Vmic, Vin, and Vsub. The gold wires 5 connecting the three pins to the MEMS chip 3 are each electrically connected through one of the opening structures 11. This opening arrangement can further reduce the transfer of heat generated by the ASIC into the accommodation cavity 21, thereby preventing excessive impact on the performance of the MEMS chip 3. In addition, the increased coverage of the ASIC chip 4 further enhances the product's anti-RF capabilities.

[0055] In the above embodiments, the number and form of the opening structure 11 can be adaptively designed based on the specific needs of the product and cost control, and are not limited here. In addition, the shape of the opening structure 11 can be circular, square, or other shapes, and its size can completely cover the first pad 41. This application does not impose any restrictions on this.

[0056] Alternatively, as Figures 2 to 3 As shown, in the thickness direction of the substrate 1, the opening structure 11 includes a first opening 111 and a second opening 112 that are connected, and a plurality of first pads 41 are provided. The number of first openings 111 is the same as the number of first pads 41, and the projection of each first opening 111 in the thickness direction of the substrate 1 falls within the second opening 112; wherein, the plurality of first pads 41 are electrically connected to the MEMS chip 3 through gold wires 5 respectively, and each gold wire 5 passes through each first opening 111 one by one, and passes through the second opening 112 together, so that each first pad 41 is electrically connected to the MEMS chip 3.

[0057] Specifically, in this embodiment, the opening structure 11 is configured as a first opening 111 and a second opening 112 that are connected. The first opening 111 is located inside the substrate 1, and the second opening 112 connects the first opening 111 to the first surface 16 of the substrate 1. This allows the gold wires 5 connected to each first pad 41 to first pass through one of the first openings 111, then pass through the first surface 16 of the substrate 1 through the second opening 112 and connect to the MEMS chip 3. The provision of the first opening 111 can prevent the gold wires 5 from interfering with other wires or conductive structures 12 inside the substrate 1, while the provision of the second opening 112 facilitates the extraction of the gold wires 5 to the substrate 1 and connection to the MEMS chip 3.

[0058] In some embodiments, the substrate 1 and the ASIC chip 4 are manufactured integrally. That is, during the production process of the substrate 1, the ASIC chip 4 is simultaneously embedded within the substrate 1. The substrate 1 is manufactured layer by layer, making the arrangement of the first opening 111 more convenient. After the substrate 1 is produced, it is only necessary to open the second opening 112 on the first surface 16 of the substrate 1 at a position corresponding to the first opening 111. All first openings 111 need to fall within the interior of the second opening 112 and be spaced a certain distance from the edge of the second opening 112 to facilitate subsequent connection between the gold wire 5 and the first pad 41 and the MEMS chip 3.

[0059] Alternatively, as Figure 1 、 Figure 3 and Figure 4 As shown, in the thickness direction of the substrate 1 , the projection of the first pad 41 on the substrate 1 completely falls inside the open hole structure 11 , and the distance from the edge of the open hole structure 11 is 30 μm to 100 μm.

[0060] Specifically, in this embodiment, the first pad 41 is completely embedded in the inner side of the opening structure 11, that is, the first pad 41 is completely exposed within the opening structure 11, making it easier to connect the gold wire 5 to the first pad 41 and the MEMS chip 3. At the same time, a certain gap is left between the first pad 41 and the edge of the opening structure 11 to avoid interference or wear between the gold wire 5 and the opening structure 11, thereby improving the reliability of the connection.

[0061] The distance between the edge of the first pad 41 and the edge of the opening structure 11 can generally be set to 30 μm to 100 μm, such as 40 μm, 50 μm, 80 μm, etc. A distance that is too large will cause the opening structure 11 to be too large, so that the heat generated by the ASIC will still affect the performance of the MEMS chip 3 and the embedding effect of the ASIC chip 4 within the substrate 1. On the other hand, a distance that is too small will make it difficult to connect the gold wire 5. Setting the distance within 30 μm to 100 μm can ensure the embedding effect while taking into account the convenience of assembly.

[0062] Alternatively, as Figure 2 As shown, in the thickness direction of the substrate 1 , the projection of the ASIC chip 4 on the substrate 1 and the projection of the MEMS chip 3 on the substrate 1 at least partially overlap.

[0063] Specifically, in this embodiment, ASIC chip 4 is embedded within substrate 1, allowing it to overlap or intersect with MEMS chip 3 in the thickness direction of substrate 1. This reduces the size of the entire package structure and facilitates product miniaturization. In practical applications, first pads 41 of ASIC chip 4 can be reserved outside of MEMS chip 3, allowing first pads 41 to escape through opening structure 11 onto first surface 16 for electrical connection to MEMS chip 3 via routing.

[0064] Alternatively, as Figures 2 to 10 As shown, the substrate 1 includes a conductive structure 12, a first end of the conductive structure 12 is located inside the substrate 1, and a second end extends from the inside of the substrate 1 to the second surface 17 of the substrate 1 and forms an exposed external pad area 14, and the second surface 17 is located on the opposite side of the first surface 16; the ASIC chip 4 also has a second pad 42, which is electrically connected to the first end of the conductive structure 12, and the external pad area 14 is used to electrically connect to an external circuit.

[0065] Specifically, in this embodiment, the electrical connection between the ASIC chip 4 and the substrate 1 is achieved through the conductive structure 12 inside the substrate 1, so that the ASIC chip 4 does not need to lead the second solder pad 42 to the first surface 16 of the substrate 1, and the first surface 16 of the substrate 1 does not need to reserve a connection position or setting position for the second solder pad 42, further reducing the size of the substrate 1.

[0066] Furthermore, the first end of the conductive structure 12 is located inside the substrate 1, and the second end extends from the interior of the substrate 1 to the second surface 17 of the substrate 1 to form an external pad area 14. This allows the ASIC chip 4 to be electrically connected to the first end of the conductive structure 12, thereby achieving electrical connection to an external circuit via the external pad, simplifying the connection between the ASIC chip 4 and the substrate 1. The conductive structure 12 can be a conductive member such as gold wire and can be fabricated and laid during the production process of the substrate 1.

[0067] Alternatively, as Figures 5 and 6 As shown, the substrate 1 further includes an insulating region 15 and a metal region 13 surrounding the insulating region 15 . The conductive structure 12 and the ASIC chip 4 are both located in the insulating region 15 , and the metal region 13 is grounded.

[0068] Specifically, in this embodiment, substrate 1 includes an insulating region 15 within and a metal region 13 outside of insulating region 15. Metal region 13 is grounded via a ground pad 18 on second surface 17 of substrate 1. This allows metal region 13 to form a metal shield for ASIC chip 4 located within insulating region 15, preventing interference from signals from various antennas and other devices outside substrate 1. This further enhances the anti-RF capabilities of the MEMS package structure when used in a microphone, improving the product's acoustic performance. Furthermore, conductive structure 12 is also located within insulating region 15, facilitating its placement.

[0069] Alternatively, as Figures 2 to 3 As shown, the second pad 42 is located on the side of the ASIC chip 4 facing the first surface 16 , and the conductive structure 12 extends from the side of the ASIC chip 4 close to the first surface 16 , around the ASIC chip 4 , and to the side away from the first surface 16 .

[0070] Specifically, in this embodiment, the first pad 41 and the second pad 42 on the ASIC chip 4 are both located on the side close to the first surface 16 of the substrate 1. The first pad 41 is located on the side close to the first surface 16 of the substrate 1 to facilitate its exposure to the first surface 16 through the opening structure 11 and connection with the MEMS chip 3, while the second pad 42 needs to be connected to the first end of the conductive structure 12, and then connected to the external pad area 14 through the conductive structure 12.

[0071] In actual connection, the first end of the conductive structure 12 is connected to the first pad 41, and it itself needs to be routed from the upper side of the ASIC chip 4 to the lower side of the ASIC chip 4, that is, the side of the ASIC chip 4 away from the first surface 16. Compared with the second pad 42 being routed to the first surface 16 of the substrate 1 and then to the second surface 17, this simplifies the connection between the ASIC chip 4 and the substrate 1 and reduces the size of the package structure.

[0072] Alternatively, as Figures 5 to 10 As shown, a plurality of second pads 42 are provided, and the number of the conductive structures 12 is the same as the number of the second pads 42 . Each second pad 42 is electrically connected to the second surface 17 through each conductive structure 12 in a one-to-one correspondence.

[0073] Specifically, in practical applications, the connection between the ASIC chip 4 and the external circuit usually requires multiple second pads 42 to achieve specific functions. Figures 5 to 9 As shown, the ASIC chip 4 is provided with four second pads 42, which are respectively led from the inside of the substrate 1 to the second surface 17 of the substrate 1 through the VDD trace 421, the DATA trace 422, the CLK trace 423 and the L / R trace 424 (conductive structure 12), forming the external pad area 14. The connection of each of the above traces needs to be connected to a second pad 42 and then approach the first surface 16 of the substrate 1, and then bypass the ASIC chip 4 and extend in the direction close to the second surface 17 of the substrate 1, and finally lead to the four external pad areas 14. That is, according to Figure 6-Figure 5 - Figure 6-Figure 8 - Figure 9-10 The sequence extends to the outer pad area 14.

[0074] According to a second aspect of the present application, an electronic device is provided, comprising: the MEMS packaging structure of the first aspect.

[0075] Specifically, in this embodiment, the MEMS packaging structure is used in microphone products or combination sensors (such as a pressure and microphone combination). The ASIC chip 4 based on the packaging structure is embedded in the interior of the substrate 1 and is directly connected to the MEMS chip 3 through wiring, thereby improving the acoustic performance and anti-RF capability of the microphone. At the same time, it can also reduce its size and avoid the problems of parasitic capacitance and leakage. When these products are used in electronic devices, the acoustic performance and reliability of the acoustic function of the product can be improved. Among them, the electronic device can be a smartphone, tablet computer, etc., which is not limited in this application.

[0076] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0077] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A MEMS packaging structure, characterized in that: include: A substrate, wherein a first surface of the substrate is provided with an open hole structure; a cover body, the cover body being buckled onto the first surface and forming a receiving cavity between the cover body and the substrate; A MEMS chip is located in the accommodating cavity and is disposed on the first surface of the substrate; An ASIC chip is embedded in the substrate and has a first pad. The first pad is exposed on the first surface through the opening structure so as to be electrically connected to the MEMS chip through a wiring of the opening structure.

2. The MEMS packaging structure according to claim 1, wherein: There are multiple first pads, one opening structure, and all of the multiple first pads are electrically connected to the MEMS chip through one opening structure wiring; or The opening structures are provided in a plurality corresponding to the number of the first pads, and the plurality of first pads are electrically connected to the MEMS chip through the plurality of opening structure wirings in a one-to-one correspondence.

3. The MEMS packaging structure according to claim 1, wherein: In the thickness direction of the substrate, the opening structure includes a first opening and a second opening that are connected. A plurality of first pads are provided. The number of the first openings is the same as the number of the first pads, and the projection of each first opening in the thickness direction of the substrate falls within the second opening. Among them, multiple first bonding pads are electrically connected to the MEMS chip through gold wires respectively, and each of the gold wires passes through each of the first openings one by one and passes through the second opening together, so that each of the first bonding pads is electrically connected to the MEMS chip.

4. The MEMS packaging structure according to claim 1, wherein: In the thickness direction of the substrate, the projection of the first pad on the substrate completely falls inside the open hole structure, and the distance from the edge of the open hole structure is 30 μm to 100 μm.

5. The MEMS packaging structure according to claim 1, wherein: In a thickness direction of the substrate, a projection of the ASIC chip on the substrate at least partially overlaps with a projection of the MEMS chip on the substrate.

6. The MEMS packaging structure according to claim 1, wherein: The substrate includes a conductive structure, wherein a first end of the conductive structure is located inside the substrate, and a second end of the conductive structure extends from the inside of the substrate to a second surface of the substrate to form an exposed external pad area, and the second surface is located on the opposite side of the first surface; The ASIC chip further has a second pad electrically connected to the first end of the conductive structure, and the outer pad area is used for electrically connecting to an external circuit.

7. The MEMS packaging structure according to claim 6, characterized in that: The substrate further includes an insulating area and a metal area surrounding the insulating area. The conductive structure and the ASIC chip are both located in the insulating area, and the metal area is grounded.

8. The MEMS packaging structure according to claim 6, wherein: The second pad is located on a side of the ASIC chip facing the first surface. The conductive structure extends from a side of the ASIC chip close to the first surface, around the ASIC chip, and to a side away from the first surface.

9. The MEMS packaging structure according to claim 6, wherein: There are a plurality of second pads, the number of the conductive structures is the same as the number of the second pads, and each of the second pads is electrically connected to the second surface through each of the conductive structures in a one-to-one correspondence.

10. An electronic device, characterized in that: include: The MEMS packaging structure according to any one of claims 1 to 9.

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