Matrix switch test method, equipment, medium and product

Abstract

The invention discloses a matrix switch test method, equipment, a medium and a product, and relates to the technical field of circuit assembly testing, and the key points of the technical scheme are as follows: extracting primitives contained in a to-be-tested matrix switch, drawing a link diagram of the to-be-tested matrix switch according to the primitives, and configuring program control information for each primitive in the link diagram; generating at least one signal transmission link according to the connection relationship among the primitives in the link diagram, and generating a control instruction according to the program control information configured by each primitive in each signal transmission link; wherein the control instruction comprises a fixed start bit, a control panel type number, an interface number, a state field and a checksum; and establishing synchronization between the to-be-tested matrix switch and the vector network analyzer according to a preset communication protocol, issuing a control instruction to a signal transmission link of the to-be-tested matrix switch according to a pre-configured test parameter to execute a test, and outputting a test result by the vector network analyzer.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit component testing, and more particularly to a test method, equipment, medium and product for a matrix switch. Background Art

[0002] In the field of electronic testing, matrix switches are core components for signal routing, and their performance testing (such as insertion loss, isolation, and standing wave ratio) is crucial to the reliability of communication systems and radar equipment. Traditional matrix switch testing relies on manual operation, requiring manual drawing of link diagrams, configuration of component parameters (such as control board interfaces and pin status), and issuance of control commands one by one. This process is cumbersome and prone to test errors due to human oversight.

[0003] As matrix switches become more complex (e.g., multi-channel RF switches and mixed-mode control requirements), the inefficiency and poor compatibility of manual testing become increasingly prominent. Existing testing methods lack automated link generation mechanisms, making it difficult to quickly match control protocols for different hardware types (e.g., TTL boards, high-voltage boards, and RF switches). Furthermore, test result management is fragmented, making it impossible to efficiently trace historical data or export it for analysis. This severely restricts the efficiency of matrix switch R&D and production testing. Summary of the Invention

[0004] The purpose of the present invention is to provide a method, device, medium and product for testing a matrix switch, which solve the problems of insufficient testing efficiency and reliability in existing methods for testing matrix switches.

[0005] The above technical objectives of the present invention are achieved through the following technical solutions: A first aspect of the present invention provides a method for testing a matrix switch, the method comprising: Extracting the graphic elements contained in the matrix switch to be tested, drawing a link diagram of the matrix switch to be tested based on the graphic elements, and configuring program control information for each graphic element in the link diagram; Generate at least one signal transmission link based on the connection relationship between each graphic element in the link diagram, and generate a control instruction based on the program control information configured for each graphic element in each signal transmission link; wherein the control instruction includes a fixed start bit, a control board type number, an interface number, a status field, and a checksum; The matrix switch to be tested is synchronized with the vector network analyzer according to the preset communication protocol, and control instructions are sent to the signal transmission link of the matrix switch to be tested according to the pre-configured test parameters to perform the test, and the vector network analyzer outputs the test results.

[0006] In one implementation, the method further includes configuring a communication control board for the link map, and allocating communication protocol parameters to the communication control board.

[0007] In one implementation, at least one signal transmission link is generated according to the connection relationship between the graph elements in the link graph, specifically: Configure basic information for the primitives; Analyze the input and output terminals based on the basic information of the graphics element; Filter the graphic elements containing program-controlled information in the path from the input end to the output end, and generate signal transmission links according to the signal flow order.

[0008] In one implementation, the basic information includes the name of the graphic element, the input end, the output end, the display direction of the internal interface of the graphic element, the description information of the graphic element, the foreground color of the graphic element, and the background color of the graphic element.

[0009] In one implementation, the program control information includes the control board type, interface number, pin status and mixed mode configuration; wherein, the mixed mode configuration is used for one-to-many control of the matrix switch to be tested. When the mixed mode is enabled, the status fields of multiple interfaces of the control instruction are bitwise ORed into a single field and mapped to the interface status of the control instruction.

[0010] In one implementation, the control instruction is a hexadecimal instruction.

[0011] In one implementation, the checksum of the control instruction is the result of an exclusive OR operation from the second bit to the last bit.

[0012] A second aspect of the present invention provides a test device for a matrix switch, comprising a memory and a processor; a memory for storing a computer program, wherein the computer program includes program instructions; The processor is configured to execute the program instructions so as to enable the testing device to perform the steps of a matrix switch testing method provided in the first aspect of the present invention.

[0013] A third aspect of the present invention provides a computer program product comprising program instructions, which, when executed by a test device, causes the test device to execute the steps of a matrix switch testing method provided in the first aspect of the present invention.

[0014] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a computer program. When the computer program is executed by one or more processors, the computer program implements a matrix switch testing method as provided in the first aspect of the present invention.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. Through automated link generation, command configuration, and test result management, manual intervention is reduced, test rework caused by manual configuration errors is reduced, and overall test efficiency and reliability are improved.

[0016] 2. The present invention automatically screens the graphics elements that need to be controlled according to whether the graphics elements have program-controlled information, and generates signal transmission links according to the signal flow direction, without the need to manually define them one by one, greatly reducing the amount of manual operation.

[0017] 3. The control instructions use hexadecimal characters, including a fixed start bit, control board type / number / interface, status and checksum. It is compatible with various hardware protocols such as TTL and high-voltage boards to ensure accurate instruction parsing and avoid communication errors caused by protocol differences. The checksum mechanism and fixed start bit design effectively prevent data transmission errors and reduce the risk of malfunction of the matrix switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 A method for testing a matrix switch is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0020] It should be noted that the terms "include" or "may include" used in various embodiments of the present application indicate the presence of the claimed function, operation or element, and do not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present application, the terms "include", "have" and their cognates are only intended to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0021] It should be understood that terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0022] Please refer to Figure 1 , Figure 1 A test method for a matrix switch provided by an embodiment of the present invention is as follows: Figure 1 As shown, the method includes: S101 , extracting graphic elements included in the matrix switch to be tested, drawing a link diagram of the matrix switch to be tested based on the graphic elements, and configuring program control information for each graphic element in the link diagram.

[0023] In this embodiment, the matrix switches to be tested include DPDT switches, SPDT switches, SP4T switches, SP6T switches, power dividers, etc. This is common knowledge in the field of electronic testing, and this embodiment does not provide a detailed description of their working principles.

[0024] Graphic primitives represent the various switch types included in a matrix switch. For example, a DPDT switch can be analogized as having two independent "contact groups" within the switch (like two blades, each capable of operating two circuit paths). Each "blade" (contact group) has two possible connection positions. For example, if the circuit is originally in one connection state, operating the switch will cause each contact group to switch to the other connection state.

[0025] Therefore, by extracting the graphic elements contained in the matrix switch to be tested, and then according to the connection relationship between these graphic elements, a link diagram of the matrix switch to be tested can be drawn. The link diagram represents multiple signal transmission links formed by multiple switches connected in sequence.

[0026] Secondly, program control information is configured for each element in the link diagram. It should be noted that this program control information covers the control board type, interface, pin, and mixed mode. The pin can be configured to 0 to disconnect the link. The mixed mode configuration is used for a one-to-two RF switch and can merge multiple interface control information. These flexible program control configuration functions can meet the complex testing requirements of different switch matrices, improve the flexibility and adaptability of the test, and enable the test method to cover more types of switch matrix test scenarios. For example, in a one-to-two RF switch, if two paths need to be disconnected simultaneously, this can be achieved through pin 0 configuration, avoiding physical disassembly or manual intervention.

[0027] Among them, the hybrid mode configuration is used for one-to-many control of the matrix switch to be tested. When the hybrid mode is enabled, the status fields of multiple interfaces of the control instruction are merged into a single field by bitwise OR operation and mapped to the interface status of the control instruction. It should be noted here that one-to-many control is generally for one-to-many control of RF switches. For example, a signal transmission link contains two one-to-two RF switches, and it is necessary to control pin 3 of interface 1 and pin 5 of interface 2 at the same time. Then, after enabling the hybrid mode, the two pin states such as "01" and "10" are bitwise ORed to generate the merged control board interface status field "11". The corresponding control instruction is "0F 02 01 03 11 0A", and the instruction realizes the control of multiple pins through a single interface.

[0028] S102, generating at least one signal transmission link according to the connection relationship between each graphic element in the link diagram, and generating a control instruction according to the program control information configured for each graphic element in each signal transmission link; wherein the control instruction includes a fixed start bit, a control board type number, an interface number, a status field and a checksum.

[0029] In this embodiment, at least one signal transmission link is generated, specifically: basic information is configured for the graphic element; the input end and the output end are parsed according to the basic information of the graphic element; the graphic element containing the program control information in the path from the input end to the output end is filtered, and the signal transmission link is generated in the order of signal flow.

[0030] Specifically, the basic information includes the name of the primitive, the input end, the output end, the display direction of the primitive's internal interface, the primitive's description information, the primitive's foreground color, and the primitive's background color.

[0031] It should be understood that this embodiment uses basic primitive information to help operators more clearly and accurately identify and distinguish different primitives, facilitate understanding of the functions and roles of primitives in the link, facilitate the drawing of complex link diagrams, and enhance the readability and maintainability of link diagrams. During the link diagram drawing process, operators can use this basic information to quickly locate the required primitives.

[0032] The fixed start bit of the control command is the predefined hexadecimal character "0F". The checksum field is generated by bit-by-bit XOR operation, which ensures the integrity of the control command transmission.

[0033] Control instructions are defined for each control board and expressed using hexadecimal characters. These characters include a fixed start bit, the control board type number, and other components. This standardized instruction definition ensures the accuracy and consistency of control instructions during testing, making communication between the test platform and the physical switch matrix more stable and reliable. Instructions corresponding to different control boards can be accurately identified and executed, avoiding test errors caused by incorrect instructions. The use of hexadecimal characters to represent control instructions is compatible with various hardware protocols (such as TTL and high-voltage boards), and the unified instruction format simplifies parsing logic. A fixed start bit and checksum ensure reliable instruction transmission, preventing malfunctions caused by data errors.

[0034] In one embodiment, a control instruction such as "0F 02 01 01 01 05" is generated according to the link, where the first bit 0F represents a fixed start bit, the second bit 02 represents the control board type, the third bit 01 represents the control board number, the fourth bit 01 represents the control board interface number, the fifth bit 01 represents the control board interface status, and 05 represents the checksum from the second bit to the last bit.

[0035] S103, establishing synchronization between the matrix switch to be tested and the vector network analyzer according to a preset communication protocol, issuing control instructions to the signal transmission link of the matrix switch to be tested according to pre-configured test parameters to perform testing, and the vector network analyzer outputs the test results.

[0036] In this embodiment, the communication protocol supports TCP / IP, GPIB and USB protocols, and can also automatically adapt the communication protocol according to the type of the matrix switch to be tested.

[0037] Preconfigured test parameters refer to the vector network analysis measurement parameters such as the start frequency, end frequency, frequency bandwidth, measurement S parameters, and marker points.

[0038] The testing process is: (1) Draw a link diagram and configure program control parameters; (2) Generate links and control instructions based on the drawn data; (3) Configure vector network analyzer test parameters; (4) Configure the vector network analyzer and matrix switch connection parameters in the device management function module and connect them; (5) In the indicator test module, select the indicator to be tested and check whether to save the test data; (6) Execute indicator test and automatically save test results according to selection.

[0039] In some embodiments, the method further includes: configuring a communication control board for the link map, and allocating communication protocol parameters to the communication control board.

[0040] Specifically, the communication control board allows users to modify parameters. For example, when designing a link diagram, testers only need to focus on the connection between the RF switch and the control board in the matrix switch under test. The communication control board (such as the Ethernet interface module) will be automatically configured for the entire link diagram and assigned default communication protocol parameters (such as the IP address and verification method). For example, when a tester draws a link including a TTL board, a high-voltage board, and an RF switch, the communication board can be set up by default at the link starting point. Testers do not need to manually configure it and can directly enter the link connection and testing phase. This simplifies personnel operations, avoids human errors, and improves the efficiency of link diagram drawing.

[0041] An embodiment of the present invention also provides a test device for a matrix switch. The test device includes a processor, a memory, a communication interface, and at least one communication bus for connecting the processor, the memory, and the communication interface. The memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (PROM), or a compact disc read-only memory (CD-ROM), and is used to store relevant instructions and data.

[0042] The communication interface is used to receive and send data. The processor can be one or more CPUs. When the processor is a CPU, the CPU can be a single-core CPU or a multi-core CPU. The processor in the test equipment is used to read one or more programs stored in the memory and perform the following operations: extract the graphics elements contained in the matrix switch to be tested, draw a link diagram of the matrix switch to be tested based on the graphics elements, and configure program control information for each graphics element in the link diagram; generate at least one signal transmission link based on the connection relationship between the graphics elements in the link diagram, and generate control instructions based on the program control information configured for each graphics element in each signal transmission link; wherein the control instructions include a fixed start bit, a control board type number, an interface number, a status field and a checksum; establish synchronization between the matrix switch to be tested and the vector network analyzer according to a preset communication protocol, send control instructions to the signal transmission link of the matrix switch to be tested according to the pre-configured test parameters to perform the test, and the vector network analyzer outputs the test results.

[0043] It should be noted that the specific implementation of each operation can be as described above. Figure 1 The corresponding description of the method embodiment shown is that the testing device can be used to execute a matrix switch testing method of the above method embodiment of the present application, which will not be described in detail here.

[0044] An embodiment of the present invention further provides a computer-readable storage medium, which is a memory device in a computer device and is used to store programs and data. It should be understood that the computer-readable storage medium herein may include both built-in storage media in the computer device and, of course, extended storage media supported by the computer device. The computer-readable storage medium provides storage space, which stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for being loaded and executed by a processor. These instructions may be one or more computer programs (including program code). It should be noted that the computer-readable storage medium herein may be a high-speed RAM memory or a non-volatile memory, such as at least one disk drive. The processor may load and execute the one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the matrix switch testing method described in the above embodiment. Those skilled in the art will appreciate that the embodiments of the present invention may be provided as a method, system, or computer program product. Therefore, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0045] Embodiments of the present invention also provide a computer program product including program instructions. The computer program product may be software or a program product including program instructions that can be executed on a computing device or stored on any usable medium. When the computer program product is executed on at least one test device, the at least one test device executes a method for testing a matrix switch.

[0046] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for testing a matrix switch, characterized in that: Methods include: Extracting the graphic elements contained in the matrix switch to be tested, drawing a link diagram of the matrix switch to be tested based on the graphic elements, and configuring program control information for each graphic element in the link diagram; Generate at least one signal transmission link based on the connection relationship between each graphic element in the link diagram, and generate a control instruction based on the program control information configured for each graphic element in each signal transmission link; wherein the control instruction includes a fixed start bit, a control board type number, an interface number, a status field, and a checksum; The matrix switch to be tested is synchronized with the vector network analyzer according to the preset communication protocol, and control instructions are sent to the signal transmission link of the matrix switch to be tested according to the pre-configured test parameters to perform the test, and the vector network analyzer outputs the test results.

2. A matrix switch testing method according to claim 1, characterized in that: The method further includes configuring a communication control board for the link map and allocating communication protocol parameters to the communication control board.

3. The matrix switch testing method according to claim 1, wherein: At least one signal transmission link is generated based on the connection relationship between the various elements in the link graph, specifically: Configure basic information for the primitives; Analyze the input and output terminals based on the basic information of the graphics element; Filter the graphic elements containing program-controlled information in the path from the input end to the output end, and generate signal transmission links according to the signal flow order.

4. A matrix switch testing method according to claim 3, characterized in that: The basic information includes the name of the graphic element, the input end, the output end, the display direction of the internal interface of the graphic element, the description information of the graphic element, the foreground color of the graphic element and the background color of the graphic element.

5. The method for testing a matrix switch according to claim 1, wherein: The program control information includes the control board type, interface number, pin status and mixed mode configuration; wherein, the mixed mode configuration is used for one-to-many control of the matrix switch to be tested. When the mixed mode is enabled, the status fields of multiple interfaces of the control instruction are bitwise ORed into a single field and mapped to the interface status of the control instruction.

6. The matrix switch testing method according to claim 1, wherein: The control instruction is a hexadecimal instruction.

7. A matrix switch testing method according to claim 6, characterized in that: The checksum of the control instruction is the result of an exclusive OR operation from the second bit to the last bit.

8. A test device for a matrix switch, characterized in that: including memory and processor; a memory for storing a computer program, wherein the computer program includes program instructions; The processor is configured to execute the program instructions so as to enable the testing device to perform the steps of the matrix switch testing method according to any one of claims 1 to 7.

9. A computer program product comprising program instructions, characterized in that When the program instructions are executed by the testing device, the testing device executes the steps of the matrix switch testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a computer program, and when the computer program is executed by one or more processors, the computer program implements the matrix switch testing method according to any one of claims 1 to 7.

Images