A signal processing device for detecting defects in an external thermal insulation composite system

Abstract

The application discloses an external wall external thermal insulation layer defect detection signal processing device, and relates to computer and data processing technology, which comprises a sampling and preprocessing board, wherein FPGA is used as a main controller, the FPGA controls a DDS chip to generate baseband waveform output through SPI and I / O_UPDATA signal lines, the FPGA controls a receiving and transmitting module to generate transmitting and receiving radio frequency signals through a parallel bus interface, the FPGA controls communication with an upper computer, the FPGA controls parameter configuration of an ADC chip through SPI, controls an ADC circuit to collect intermediate frequency signals input by the receiving module, and the FPGA is also used for realizing digital down-conversion and other signal processing functions; and the upper computer realizes phase correlation accumulation, direct current bias removal, band pass filtering and other signal processing functions. The application adopts FPGA to realize logic interface control functions and inverse Fourier transform algorithm, ensures that the device is small in size and low in power consumption, realizes part of signal processing algorithms on a general upper computer, and greatly reduces programming difficulty and device cost.

Description

Technical Field

[0001] This application relates to the fields of computer and data processing technology, and in particular to a signal processing device for detecting defects in the external insulation layer of an exterior wall. Background Technology

[0002] When detecting internal defects in the external insulation layer of building exterior walls, to accurately detect these defects, the maximum longitudinal distance resolution of the detection device is often designed to be at the centimeter level, and the maximum detection distance is typically set to around 0.5 meters. Correspondingly, the electromagnetic wave transmission signal frequency sweep range is designed to be above ten gigahertz. Due to environmental limitations, the device is generally used at close range, typically only a few tens of centimeters from the exterior wall. The short operating distance and large transmission signal bandwidth of the device result in strong clutter in the echo signal and a weak target signal, making direct identification of internal defects difficult. Therefore, efficient signal processing methods and devices for suppressing clutter and extracting weak targets are needed.

[0003] To achieve high longitudinal range resolution, external wall insulation layer defect detection devices typically transmit broadband stepped frequency sweep signals, then synthesize a large-bandwidth signal at the receiving end using the stepped frequency method. The principle of improving range resolution by transmitting stepped frequency signals was proposed as early as the 1960s. The stepped frequency synthesis method has advantages such as low requirements for the instantaneous bandwidth of the RF channel, narrow intermediate frequency bandwidth, small sampling rate, large synthesis bandwidth, and high receiver sensitivity. With the development of digital signal processing technology, the stepped frequency synthesis method is more widely used in radar detection. Currently, the stepped frequency synthesis method in radar detection is mainly implemented using digital domain inverse Fourier transform algorithms. Due to the different working environments, usage methods, and target characteristics of conventional radar detection, the clutter suppression methods and weak target extraction methods mainly rely on algorithms such as frequency domain filtering, moving target indication, and Doppler detection.

[0004] Currently, there is a lack of effective signal processing methods and devices for detecting defects inside the external insulation layer of exterior walls, in order to ensure the accuracy and effectiveness of defect detection. Summary of the Invention

[0005] This application provides a signal processing device for detecting defects in the external insulation layer of an exterior wall. It uses an FPGA to implement the logic interface control function and the inverse Fourier transform algorithm, ensuring that the device is miniaturized and has low power consumption. Some signal processing algorithms are implemented on a general-purpose host computer, which greatly reduces programming difficulty and equipment cost.

[0006] This application provides a signal processing device for detecting defects in the external insulation layer of an exterior wall, comprising: a sampling and preprocessing board and a host computer, wherein:

[0007] The sampling and preprocessing board is implemented using an FPGA as the main controller. The FPGA controls the DDS chip to generate baseband waveform output through SPI and I / O_UPDATA signal lines. The FPGA controls the receiving and transmitting module to generate transmitting and receiving radio frequency signals through a parallel bus interface. The FPGA controls communication with the host computer. The FPGA configures the parameters of the ADC chip through SPI and controls the ADC circuit to acquire the intermediate frequency signal input from the receiving module. It receives the serially acquired digital baseband signal from the ADC chip. The FPGA is also used to implement some signal processing functions such as digital down-conversion and Fourier transform.

[0008] The host computer implements some signal processing functions such as coherent accumulation, DC bias removal, bandpass filtering, background noise elimination, multiple wave elimination, and gain adjustment.

[0009] The embodiments of this application use FPGA to implement logic interface control functions and inverse Fourier transform algorithms, ensuring that the device is miniaturized and has low power consumption. Some signal processing algorithms are implemented on a general-purpose host computer, which greatly reduces programming difficulty and equipment cost.

[0010] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0012] Figure 1 This is a schematic diagram of the architecture of the external wall insulation layer defect detection signal processing device according to an embodiment of this application;

[0013] Figure 2 This is a schematic diagram of the FPGA and DDS interface of the external wall insulation layer defect detection signal processing device according to an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of the FPGA and receiving / transmitting module interface of the external wall insulation layer defect detection signal processing device according to an embodiment of this application;

[0015] Figure 4 This is a schematic diagram of the FPGA and ADC interface of the external wall insulation layer defect detection signal processing device according to an embodiment of this application;

[0016] Figure 5A schematic diagram of the logic flow for generating transmit pulse 1 using the FPGA in this embodiment of the application;

[0017] Figure 6 This is the normal operating timing of the external wall insulation layer defect detection signal processing device according to an embodiment of this application;

[0018] Figure 7 This is a schematic diagram of the signal processing module operation of the external wall insulation layer defect detection signal processing device according to an embodiment of this application. Detailed Implementation

[0019] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0020] This application provides a signal processing device for detecting defects in the external insulation layer of an exterior wall, such as... Figure 1 As shown, it includes: a sampling and preprocessing board and a host computer, wherein:

[0021] like Figure 2-4 As shown, the sampling and preprocessing board mainly implements some signal processing, logic, and interface control functions. The FPGA serves as the main controller of the sampling and preprocessing board. The FPGA controls the DDS chip to generate baseband waveform output via SPI (serial bus) and I / O_UPDATA (input / output update) signal lines. The FPGA controls the transmit and receive modules to generate transmit and receive RF signals via a parallel bus interface. The FPGA controls the Ethernet circuit to achieve Ethernet communication with the host general-purpose computer. The FPGA configures the parameters of the high-speed ADC chip via SPI, controls the ADC circuit to acquire the intermediate frequency signal input from the receiving module, and receives the serially acquired digital baseband signal from the ADC chip's JESD204B protocol interface. The FPGA logic also implements some signal processing functions such as digital down-conversion and Fourier transform.

[0022] like Figure 1 As shown, the sampling and preprocessing board, depending on the required functions, can be divided into a main control module, a data acquisition module, a baseband waveform generation module, an Ethernet interface module, a signal processing module, an interface with internal storage module 1, and an interface with internal storage module 2, etc.

[0023] The main control module primarily implements interface control and timing control functions for the receiving and transmitting modules. FPGA internal storage module 1 buffers the commands and data received and transmitted by the main control module. FPGA internal storage module 2 buffers intermediate results from data acquisition and signal processing.

[0024] The host computer implements some signal processing functions such as coherent accumulation, DC bias removal, bandpass filtering, background clutter elimination, multiple wave elimination, and gain adjustment. It can also extract defects in the external insulation layer and eliminate background clutter. In a specific example, the host computer can be a general-purpose host computer.

[0025] In this specific example, the host general-purpose computer communicates with the main control module via Gigabit Ethernet. The specific details of the communication protocol between the host general-purpose computer and the FPGA are shown in Tables 1 and 2.

[0026] Table 1 Control commands transmitted from the host computer

[0027]

[0028] Table 2. Response data packets uploaded from the sampling and preprocessing board.

[0029]

[0030]

[0031] The external wall insulation layer defect detection device of this application includes two modes: self-test mode and normal mode. These two modes represent the timing control functions primarily implemented by the FPGA. Figure 5 As shown, the main control module implements Figure 5 The control logic process generates transmit pulse 1, which is the main control timing pulse signal of the device. The main control module provides the accumulation cycle counter and control logic, the sub-pulse counter and control logic within each cycle, and the sub-pulse counter and control logic with control words such as the predetermined number of accumulation cycles M, the number of sub-pulses per cycle N, and the sub-pulse length count value cnt, respectively, based on the device waveform parameters. Here, cnt is calculated according to the following formula:

[0032]

[0033] The driving clock is the clock input for each of the aforementioned control logic modules. The sub-pulse counter and control logic inside the FPGA start counting when external trigger pulse 2 is valid. When the sub-pulse counter value is less than the sub-pulse length count value, and the sub-pulse counter value in each cycle is less than the predetermined number of sub-pulses per cycle, the sub-pulse counter value continuously increases by 1 under the driving clock. When the sub-pulse counter value equals the sub-pulse length count value, and the sub-pulse counter value in each cycle is less than the predetermined number of sub-pulses per cycle, the sub-pulse counter value is reset to zero and counting restarts. Simultaneously, the sub-pulse counter value increments by 1 in each cycle. This process is repeated until the sub-pulse counter value in each cycle equals the predetermined number of sub-pulses per cycle.

[0034] When the sub-pulse counter equals the predetermined number of sub-pulses per cycle, the accumulated cycle counter value is incremented by 1, and the sub-pulse counter and sub-pulse counter count values ​​are reset to zero and start counting again. When the accumulated cycle counter equals the predetermined number of accumulated cycles, the accumulated cycle counter, sub-pulse counter and sub-pulse counter count values ​​are reset to zero and operation stops, waiting for the next external trigger pulse.

[0035] According to the above logic, under the triggering of an external trigger pulse, a transmission pulse that satisfies the device waveform parameters is generated.

[0036] After the system boots up, the default operating mode is normal mode. In some embodiments, under normal operating mode, such as Figure 6 As shown, at any time t0, the host computer sends a control command to the sampling and preprocessing board. In a specific example, the control command is sent by the host general-purpose computer to the FPGA main control module via the Ethernet interface module at any time t0.

[0037] The main control module of the sampling and preprocessing board receives an external trigger pulse 2 at measurement point i at time t1. The main control module sends the device waveform parameters to the receiving and transmitting module and the baseband waveform generation module according to the cached control command. Then, at times t2, t4, t8 and t10, it generates a transmission pulse 1 that satisfies the device waveform parameters.

[0038] After transmitting the first transmission pulse, the echo pulse returns to the receiving module at times t2, t4, t8, and t10.

[0039] The data acquisition module of the sampling and preprocessing board receives and acquires echo pulses at times t3, t5, t9, and t11 based on a time delay Δt. In a specific example, the time delay Δt is determined by the processing delay of the receiving channel, etc.

[0040] The received echo signal is sampled to obtain the corresponding discrete signal sequence S(0)~S(9), and the discrete signal is sent to the signal processing module of the sampling and preprocessing board.

[0041] In the signal processing module, the discrete signal sequence S(0)~S(9) is processed according to Equation 2 and Figure 7 After performing digital downconversion and filtering operations, the processed data is then cached, for example, in internal storage module 2.

[0042]

[0043] In the formula, f s f is the sampling frequency of the data acquisition module. i S'(n) is the intermediate frequency of the digital oscillator, and S′(n) is the discrete sampling sequence after digital down-conversion.

[0044] In some embodiments, such as Figure 6 As shown, it also includes:

[0045] At times t12 and t13, after the data acquisition module has completed acquiring the echo pulses for each accumulation cycle, the signal processing module generates the read address value according to formula (3) based on the device range, satisfying:

[0046]

[0047] Among them, f s ε is the sampling frequency of the data acquisition module. r is the relative permittivity of the single-layer medium, c is the speed of light in vacuum, int() represents the integer operation, and L is the device range;

[0048] The signal processing module selects the sample point S(j, k) corresponding to the digital sequence of each echo subpulse processed in the internal storage (internal storage module 2) of the cached data according to the address value, where j represents the processed data corresponding to the j-th (1≤j≤N) subpulse in each accumulation cycle at the current measurement point, and k represents the index value of the sample point in the processed digital sequence selected according to the device range.

[0049] The S(j,k) corresponding to each accumulation cycle of the current measurement point i is sent to the FFT transform module in the signal processing module for inverse Fourier transform to obtain the sequence A(l).

[0050]

[0051] In the formula, N is the number of sub-pulses per cycle, and l is the index of the time-domain discrete point of the corresponding inverse Fourier transform result.

[0052] At times t6 and t14, the main control module sends the processed sequence A(l) to the host computer from the Ethernet interface module according to the specified response data packet format, such as the response data packet format uploaded by the sampling and preprocessing board provided in Table 2, and waits for the subsequent data processing operations to be completed.

[0053] In some embodiments, the peak point index l0 of sequence A(l) is extracted for each accumulation period, and the corresponding target distance R is obtained as follows:

[0054]

[0055] In the formula, N is the number of sub-pulses per cycle, l0 is the peak index of the corresponding inverse Fourier transform result, and Δf is the frequency increment set by the device waveform parameters.

[0056] In some embodiments, the method further includes, in self-test mode, connecting the output of the transmitting module to the input of the receiving module via a coaxial cable and an attenuator according to formula (6), and controlling the device to detect an ideal point target with a simulated echo delay of τ, and verifying the target processing display results on the host computer. The delay τ and the length L1 of the coaxial cable 1 satisfy the following relationship:

[0057]

[0058] In the formula, L1 is the total length, ε r1 Let be the relative permittivity of coaxial conductor 1.

[0059] The host computer mainly consists of a coherent accumulation module, a DC bias removal module, a bandpass filter module, a background clutter elimination module, and a gain adjustment module to extract defects in the external wall insulation layer and eliminate background clutter. In some embodiments, the host computer is used to process the inverse Fourier transform sequence A of each accumulation period corresponding to each measurement point. m (l) Perform summation to improve the signal-to-noise ratio of the processed sequence A′(1):

[0060]

[0061] In the formula, m is the index value of the accumulation period at the measuring point;

[0062] Remove the initial DC component, DC bias, or low-frequency components from signal A′(l):

[0063]

[0064] Where A′(l) is the one-dimensional data of each measurement point after passing through the coherent accumulation module, B(l) is the one-dimensional data after passing through the DC bias removal module, and N is the number of data samples of the sequence A′(l).

[0065] In some embodiments, the method further includes using a host computer to suppress low-frequency energy clutter and additional high-frequency noise generated by the interaction between the antenna and the external wall surface through a bandpass filtering module. The bandpass filtering is performed on the one-dimensional data at each measurement point to obtain the filtered sequence c(l), which satisfies:

[0066] C(ω)=B(ω)H(ω) (9)

[0067] Where H(ω) is the bandpass filter characteristic function, B(ω) is the frequency domain sequence corresponding to sequence B(l), and C(ω) is the frequency domain sequence corresponding to sequence c(l).

[0068] In some embodiments, the system further includes a background clutter elimination module using a host computer. After the device completes a measurement along the measurement line, the one-dimensional sequence c(l) obtained at each measurement point is first combined into a two-dimensional data matrix r(l,i), and then the mean value of the sequence at each measurement point is subtracted from the data matrix r(l,i) to eliminate background clutter.

[0069]

[0070] The data matrix r(l,i) consists of the sequence c(l) at each successive measuring point on the measuring line, where I is the total number of measuring points on the measuring line.

[0071] In some embodiments, the method further includes using the gain adjustment module of the host computer to calculate the column vector f(l) by taking the maximum absolute value of each row of data in the two-dimensional data matrix r′(l,i) to eliminate background clutter:

[0072] f(l)=max (abs(r′(l,i)),1) (11)

[0073] In the formula, absr′ takes the absolute value of each row of data in matrix r′(l,i);

[0074] Find the extreme envelope g(l) of f(l), and adjust r′(l,i) to obtain the gain-adjusted data matrix z(l,i):

[0075]

[0076] Where w is the gain adjustment constant, which can be specified.

[0077] After the above operations, the target features in the data matrix z(l,i) become more prominent, which is beneficial for identifying internal defects in the external wall insulation layer.

[0078] This application utilizes an FPGA-based sampling and preprocessing board and a host general-purpose computer to implement a signal processing method and device for detecting defects in external wall insulation layers. The FPGA primarily implements signal processing, timing logic, and interface control functions. The timing logic functions mainly implement two operating timing sequences: self-test mode and normal mode. The interface control functions implement the main control module, data acquisition module, baseband waveform generation module, Ethernet interface module, signal processing module, and interfaces with internal storage module 1 and internal storage module 2. The signal processing function is mainly undertaken by the signal processing module, which implements operations such as step-frequency signal synthesis based on the inverse Fourier transform algorithm and digital down-conversion. The host general-purpose computer functions mainly consist of a coherent accumulation module, a DC bias removal module, a bandpass filter module, a background clutter elimination module, and a gain adjustment module. These modules enable the extraction of defects in the external wall insulation layer and the elimination of background clutter, making the target features more prominent.

[0079] This application enables effective suppression of strong clutter and effective extraction of weak defect targets. The method and apparatus use an FPGA chip as the main processor, implementing some signal processing, timing logic, and interface control functions. Implementing the inverse Fourier transform algorithm on an FPGA offers advantages such as high computational efficiency and high real-time performance. Using an FPGA as the hardware implementation platform ensures the device's advantages of miniaturization, low power consumption, fast algorithm computation speed, and low design cost. Furthermore, employing a general-purpose computer to implement signal processing algorithms for coherent accumulation, DC bias removal, bandpass filtering, background clutter elimination, and gain adjustment significantly reduces programming difficulty and equipment cost.

[0080] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0081] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0082] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0083] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A signal processing device for detecting defects in external wall insulation layers, characterized in that, include: The sampling and preprocessing board and the host computer, wherein: The sampling and preprocessing board is implemented using an FPGA as the main controller. The FPGA controls the DDS chip to generate baseband waveform output through SPI and I / O_UPDATA signal lines. The FPGA controls the receiving and transmitting module to generate transmitting and receiving radio frequency signals through a parallel bus interface. The FPGA controls communication with the host computer. The FPGA configures the parameters of the ADC chip through SPI and controls the ADC circuit to acquire the intermediate frequency signal input from the receiving module. The FPGA receives the serially acquired digital baseband signal from the ADC chip. The FPGA is also used to implement some signal processing functions such as digital down-conversion and Fourier transform. The host computer implements some signal processing functions such as coherent accumulation, DC bias removal, bandpass filtering, background noise elimination, multiple wave elimination, and gain adjustment. In normal operating mode, at any time t0, the host computer sends a control command to the sampling and preprocessing board. The main control module of the sampling and preprocessing board receives an external trigger pulse at measurement point i at time t1. The main control module sends the device waveform parameters to the receiving and transmitting module and the baseband waveform generation module according to the cached control command. Then, it generates a transmission pulse that satisfies the device waveform parameters at times t2, t4, t8, and t10. After the transmission pulse is transmitted, the echo pulse returns to the receiving module at times t2, t4, t8, and t10. At times t12 and t13, after the data acquisition module has completed acquiring the echo pulses for each accumulation cycle, the signal processing module generates a read address value based on the device range, satisfying the following: in, The sampling frequency of the data acquisition module. Let be the relative permittivity of the monolayer medium, and c be the speed of light in vacuum. () indicates the rounding operation, and L is the device range; The signal processing module selects the sample point S(j, k) corresponding to the digital sequence of each echo subpulse processed in the internal storage of the cached data according to the address value, where j represents the processed data corresponding to the j-th (1≤j≤N) subpulse in each accumulation cycle at the current measurement point, and k represents the index value of the sample point in the processed digital sequence selected according to the device range. The S(j,k) corresponding to each accumulation cycle of the current measurement point i is sent to the FFT transformation module in the signal processing module for inverse Fourier transform to obtain the sequence A(j,k). l ), and at times t6 and t14, the main control module will process the sequence A( l The response data packet is sent to the host computer according to the specified format. Extract sequence A for each accumulation cycle. l Peak point index The target distance R is obtained as follows: In the formula, N is the number of sub-pulses per cycle. This corresponds to the peak point index of the inverse Fourier transform result. The frequency increment set for the device waveform parameters; Using the host computer, the inverse Fourier transform sequence for each accumulation period corresponding to each measurement point is obtained. Summation and accumulation are performed to improve the efficiency of the processed sequence. Signal-to-noise ratio: In the formula, m is the index value of the accumulation period at the measuring point; Remove signal The initial DC component, DC bias, or low-frequency component of the signal: in, This represents the one-dimensional data for each measurement point after passing through the coherent accumulation module. The data is a one-dimensional sequence after being processed by the DC bias removal module, where N is the sequence number. Number of data samples.

2. The signal processing device for detecting defects in the external insulation layer of a wall as described in claim 1, characterized in that, The data acquisition module of the sampling and preprocessing board receives and acquires echo pulses at times t3, t5, t9, and t11 based on a time delay Δt. The received echo signal is sampled to obtain the corresponding discrete signal, and the discrete signal is sent to the signal processing module of the sampling and preprocessing board. In the signal processing module, the discrete signal is digitally down-converted and filtered before the processed data is buffered.

3. The signal processing device for detecting defects in the external insulation layer of a wall as described in claim 1, characterized in that, This also includes using a host computer to suppress low-frequency energy clutter and additional high-frequency noise generated by the interaction between the antenna and the external wall surface through a bandpass filter module. The bandpass filtering of the one-dimensional data at each measurement point satisfies the following: in, The characteristic function of the bandpass filter, For sequence The corresponding frequency domain sequence, For sequence The corresponding frequency domain sequence.

4. The signal processing device for detecting defects in the external insulation layer of a wall as described in claim 3, characterized in that, This also includes using a host computer. After the equipment completes one measurement along the measurement line, the one-dimensional sequence obtained at each measurement point is first processed. Composition of two-dimensional data matrix Then the data matrix Background clutter is eliminated by subtracting the mean of the sequence at each measurement point.

5. The signal processing device for detecting defects in the external insulation layer of a wall as described in claim 4, characterized in that, It also includes using a host computer to process the two-dimensional data matrix for removing background clutter. The column vector is calculated by finding the maximum absolute value of each row of data. : In the formula, For matrix Take the absolute value of each row of data; right Find the extreme value envelope ,right The data matrix after gain adjustment is obtained by adjustment. : in, This is the gain adjustment constant.

6. The signal processing device for detecting defects in the external insulation layer of an exterior wall as described in claim 1, characterized in that, It also includes connecting the output of the transmitting module to the input of the receiving module via coaxial cable and attenuator in self-test mode, controlling the device to detect an ideal point target with simulated echo delay of τ, and verifying the target processing display results on the host computer.

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