Doppler flicker interference generation method based on FPGA

Abstract

The present invention belongs to the field of radar electronic countermeasures technology and discloses a method for generating Doppler flicker interference based on an FPGA. The method comprises: a host computer transmits system parameters and Doppler flicker interference strategy parameters to the FPGA; a signal transmission and acquisition module of the FPGA receives radar radio frequency signals, processes them, obtains radar baseband signals, and stores them; a control unit extracts the radar baseband signals based on the system parameters and generates alternating Doppler frequency control words based on strategy parameters; the extracted radar baseband signals or their synchronization information and the frequency control words are fed into a multi-channel parallel DDS unit to generate Doppler flicker interference baseband signals; the interference baseband signals are processed by the signal transmission and acquisition module and then transmitted to form interference radio frequency signals. Implemented using an FPGA, the present invention can flexibly and efficiently generate Doppler flicker interference, effectively deceiving radar velocity tracking, and has the advantages of fast response speed, high flexibility, and good interference effect.

Description

Technical Field

[0001] The invention belongs to the technical field of radar electronic countermeasures, and in particular relates to a Doppler flicker interference generation method based on a field programmable gate array (FPGA). Background Art

[0002] In modern radar electronic warfare environments, radar systems face a variety of complex electromagnetic threats. The increasing complexity of radar transmission signals and the continuous improvement of radar anti-interference technology have posed new challenges to radar jamming systems: how to rationally utilize limited jamming resources to effectively jam new radar systems.

[0003] Doppler flicker jamming is a common radar jamming method. Its principle is to alternately generate two or more jamming signals with slight frequency differences at a specific period T within the tracking bandwidth of the radar velocity tracking circuit.

[0004] For example, the interference signal a +Δ 1. a +Δ 2. Two different interference frequencies appear. This alternating interference signal will cause the radar speed tracking gate to swing on these interference frequencies, making it impossible for the radar system to accurately and stably capture the target's true speed, thereby achieving the purpose of deceiving or suppressing the radar.

[0005] During the development of radar jamming systems, the system needs to be able to generate Doppler flicker interference. Similarly, in order to test the performance of newly developed radar receivers, the corresponding radar jammers also need to be able to generate Doppler flicker interference.

[0006] However, existing technologies lack efficient, flexible, and easy-to-implement Doppler scintillation jamming generation technology, especially in terms of fast response generation based on hardware platforms, and cannot fully meet the requirements of modern electronic countermeasure systems.

[0007] Traditional jamming generation methods may rely on dedicated chips or complex analog circuits, which are costly, less flexible, and difficult to adapt to rapidly changing battlefield environments and radar systems. Summary of the Invention

[0008] The present invention aims to overcome the shortcomings of existing technologies by providing an FPGA-based Doppler flicker interference generation method. This method leverages the parallel processing capabilities and reconfigurability of FPGAs to build digital circuits within the FPGA and directly generate Doppler flicker interference using hardware circuits. This approach aims to address the lack of efficient and flexible Doppler flicker interference generation technologies in existing technologies.

[0009] To achieve the above object, the present invention adopts the following technical solutions:

[0010] The Doppler flicker interference generation method based on FPGA includes the following steps:

[0011] Step S1: The host computer sends system parameters and Doppler flicker interference strategy parameters to the FPGA. The system parameters are used to control signal detection and processing, while the Doppler flicker interference strategy parameters are used to define the frequency characteristics and switching period of the interference signal.

[0012] Step S2: The signal transmission and acquisition module inside the FPGA receives the external input radar RF signal, digitizes and baseband processes the radar RF signal to obtain a radar baseband signal, and sends the radar baseband signal to the signal storage unit inside the FPGA for storage.

[0013] Step S3: The control unit inside the FPGA extracts the radar baseband signal from the signal storage unit according to the system parameters, and generates an alternating Doppler frequency control word according to the Doppler flicker interference strategy parameter control.

[0014] Step S4: The extracted radar baseband signal and the alternating Doppler frequency control word are fed into a multi-channel parallel direct digital synthesizer (DDS) unit within the FPGA. The multi-channel parallel DDS unit generates multi-channel parallel Doppler flicker interference baseband signals based on the input radar baseband signal characteristics and the Doppler frequency control word.

[0015] Step S5: sending the multi-channel parallel Doppler flicker interference baseband signals to the signal transmission and acquisition module inside the FPGA, performing up-conversion and digital-to-analog conversion processing, and finally transmitting them to form interference radio frequency signals.

[0016] Furthermore, the system parameters include a signal detection threshold, a processing start flag, a system reset flag, and a radar signal distance parameter.

[0017] Furthermore, the Doppler flicker interference strategy parameters include at least two different Doppler flicker frequency values. For example, these frequency values ​​include Doppler flicker frequency Corresponding quantization frequency control word , and Doppler scintillation frequency Corresponding quantization frequency control word , and a Doppler scintillation cycle T Among them, any Doppler flicker frequency To its corresponding quantization frequency control word The conversion is quantified by the following formula:

[0018] (1)

[0019] Where, is the quantized Doppler flicker frequency control word, It is the Doppler flashing frequency set by the host computer. is the number of parallel paths of the multi-path parallel DDS unit, is the operating clock frequency of the FPGA, is the number of quantized bits of the frequency control word, for example You can take 32.

[0020] Furthermore, the Doppler frequency control unit inside the FPGA is configured to control the Doppler frequency according to the Doppler flicker period in the Doppler flicker interference strategy parameter. T Whenever the count reaches the preset period value, the Doppler frequency control unit switches the currently output Doppler frequency control word , for example in and At the same time, the counter is reset and starts counting again.

[0021] Furthermore, the continuous wave signal generated by the multi-channel parallel DDS unit can be expressed in a discrete form as follows:

[0022] (2)

[0023] Where, It is The sampling point value generated by the path in the nth parallel processing cycle, where The value range is 0, 1, 2, ..., -1. It is the reference frequency parameter corresponding to the currently effective Doppler flicker frequency. is the operating clock frequency of the FPGA, is the initial phase of the signal, is the number of parallel paths. The specific form of each signal is as follows:

[0024] (3)

[0025] Furthermore, the initial phase required for each DDS in the multi-channel parallel DDS unit is It can be calculated and loaded using the following formula:

[0026] (4)

[0027] Where, is the number of quantization bits of the phase accumulator, for example It can be set to 32. The meanings of other parameters are the same as those in formula (2).

[0028] Furthermore, in step S2, the signal transmission and acquisition module performs analog-to-digital conversion (ADC) and digital down-conversion (DDC) processing on the received radar radio frequency signal to obtain a radar baseband signal.

[0029] Furthermore, in step S5, the signal transmission and acquisition module performs digital up-conversion (DUC) and digital-to-analog conversion (DAC) processing on the multi-channel parallel Doppler flicker interference baseband signals, and outputs interference radio frequency signals.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. The Doppler flicker interference signal of the present invention exhibits target characteristics in the frequency domain, with two or more frequencies flickering alternately. This characteristic effectively causes the radar velocity tracking gate to swing back and forth at these interference frequencies, making it impossible to accurately and stably capture the true target velocity, thereby increasing the difficulty of the radar in distinguishing true from false targets.

[0032] 2. The present invention generates multiple parallel Doppler flicker jamming signals by designing multiple parallel DDS modules. This design can support effective Doppler flicker jamming of wideband radar signals, and its bandwidth capability can reach The FPGA operating clock frequency is increased by several times, which increases the applicable scope of interference.

[0033] 3. The present invention is fully implemented based on FPGA hardware. Through segmented processing and parallel execution of internal logic circuits, the critical path is optimized, the system processing delay is effectively reduced, and the real-time response capability of interference is improved.

[0034] 4. The present invention uses a host computer to flexibly configure parameters such as Doppler scintillation frequency and scintillation period. This configuration can simulate complex and variable Doppler scintillation target scenarios, significantly increasing the flexibility and diversity of interference, thereby posing a more severe challenge to the radar's detection and tracking capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0036] Figure 1 This is a block diagram of the interference signal generation principle according to an embodiment of the present invention;

[0037] Figure 2 Schematic diagram of the principle of generating multi-channel parallel interference signals according to an embodiment of the present invention;

[0038] Figure 3 This is an IQ analysis diagram of a Doppler flicker interference spectrum analyzer according to an embodiment of the present invention;

[0039] Figure 4 FIG. 1 is a timing diagram of Doppler flicker interference generation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following, in conjunction with specific embodiments, describes in detail the specific steps and operating procedures of a two-stage potential diffusion system for high-fidelity virtual try-on of the present invention, so that ordinary technicians in the relevant technical field can implement the present invention. Through the following specific embodiments, technicians can fully understand and implement the technical solutions of the present invention.

[0041] The present invention provides a Doppler flicker interference generation method based on FPGA. In a specific embodiment of the method, the signal transmission and acquisition module is responsible for performing analog-to-digital conversion (ADC) and digital down-conversion (DDC) processing on the received radar radio frequency signal, and outputting the radar baseband signal to the signal storage unit. In this embodiment, a four-way parallel DDS structure can be used, that is, a parallel path number =4, to generate four parallel Doppler flicker interference signals. These signals are then output to the signal transmission and acquisition module for digital up-conversion (DUC) and digital-to-analog conversion (DAC) processing, and finally output the interference RF signal.

[0042] In a specific embodiment of the present invention, the signal transmission and acquisition module can use the XCZU47DR chip from the Zynq UltraScale+ RFSoC series from XILINX, which integrates high-performance ADCs and DACs. The signal processing module can use the XCVU9P chip from the Virtex UltraScale+ series, which is connected to an external DDR4 module as a signal storage unit.

[0043] The specific implementation method of the present invention comprises the following steps:

[0044] Step S1: The host computer sends system parameters and Doppler flicker interference strategy parameters to registers or memories in the FPGA through a control interface such as PCIe or Ethernet.

[0045] The system parameters include a signal detection threshold, a processing start flag, a system reset flag, a radar signal distance parameter, and a receiving gain parameter, among which the radar signal distance parameter is used to control the starting position or delay of baseband signal extraction.

[0046] The Doppler flicker interference strategy parameters include at least two Doppler flicker frequency values, such as the Doppler flicker frequency Corresponding quantization frequency control word , and Doppler scintillation frequency Corresponding quantization frequency control word , and the Doppler flicker period T. The quantitative calculation of the Doppler flicker frequency can be calculated using the following formula (5), which is the specific form of the above formula (1) when the number of parallel paths A is equal to 4 and the number of quantization bits N is equal to 32:

[0047] (5)

[0048] In the formula is the quantized Doppler flicker frequency control word, It is the Doppler flash frequency set by the host computer, such as 200kHz or 2MHz. is the operating clock frequency of the FPGA, is the number of quantization bits of the frequency control word.

[0049] Step S2: After receiving the external radar RF signal, the signal transmission and acquisition module, such as the XCZU47DR, performs ADC and DDC processing on it to generate a digitized radar baseband signal. An FPGA, such as the XCVU9P, detects in real time whether the radar baseband signal power exceeds the signal detection threshold. When a valid signal is detected and a processing start flag is received, the signal storage unit, such as DDR4, stores the detected radar baseband signal in DDR based on the start flag and the signal detection threshold. Simultaneously, the FPGA's internal logic generates a signal detection flag and sends this flag to the raw signal extraction control unit.

[0050] Step S3: The original signal extraction control unit and the Doppler frequency control unit work together. The original signal extraction control unit extracts the radar baseband signal from the signal storage unit DDR after receiving the signal detection flag according to the distance parameter sent by the host computer, after a certain delay to simulate distance deception. The Doppler frequency control unit counts according to the flicker period T in the Doppler flicker interference strategy parameter. Whenever the count value of the internal counter reaches the value corresponding to T, the unit will switch the frequency control word output to the DDS unit. , for example in and After the switch is completed, the counter is cleared and restarts counting for the next cycle.

[0051] Step S4: The extracted radar baseband signal, or its features such as synchronization information, can be used to generate interference waveforms directly in some implementations. Instead of using the baseband signal as DDS input, it can be used as a basis for DDS parameter adjustment or synchronization signal and sent to the four-way parallel DDS unit. The DDS unit generates interference waveforms directly in some implementations. ,Right now or , and the preset initial phase, generate four parallel Doppler scintillation interference baseband signals.

[0052] The discrete expression of the continuous wave signal generated by the four-way parallel module of DDS is shown in formula (6), which is the above formula (2) in the parallel path number. The specific form when it is equal to 4:

[0053] (6)

[0054] In the formula It is the reference frequency parameter corresponding to the currently selected Doppler flicker frequency. is the FPGA operating clock frequency, is the initial phase, The values ​​are 0, 1, 2, and 3.

[0055] The specific form of each signal is shown in formula (7), which is the above formula (3) in the parallel path The specific form when it is equal to 4:

[0056] (7)

[0057] The frequency control word required for each DDS ,Right now The quantized value of is provided by the Doppler frequency control unit. The calculation and loading of is shown in formula (8), which is the above formula (4) in the parallel path number Equal to 4, the number of phase quantization bits M The specific form when it is equal to 32:

[0058] (8)

[0059] Step S5: The generated four-way parallel Doppler scintillation interference baseband signal is fed into a signal transmission and acquisition module, such as the XCZU47DR. Within this module, the interference baseband signal undergoes digital up-conversion (DUC) and digital-to-analog conversion (DAC) to form the final interference RF signal, which is then transmitted through the antenna.

[0060] See also Figure 1 , which is a block diagram of the interference signal generation principle of an embodiment of the present invention. The host computer calculates the parameters and sends them to the signal processing module in the FPGA. The signal processing module contains a parameter analysis unit, an original signal extraction control unit, a Doppler frequency control unit, and a multi-channel parallel DDS unit. The radar RF signal is converted into a radar baseband signal after passing through the ADC and DDC and stored in the signal storage unit. The original signal extraction control unit extracts the signal from the signal storage unit, and the Doppler frequency control unit controls the frequency switching. The two work together on the multi-channel parallel DDS to generate an interference baseband signal. The interference baseband signal is transmitted as an interference RF signal after passing through the DUC and DAC.

[0061] See also Figure 2 , is a schematic diagram of the principle of generating multi-path parallel interference signals according to an embodiment of the present invention. The input radar original signal or its synchronization information and the frequency control word K generated by the Doppler frequency control unit f And the initial phase calculated for each channel , , ,..., ( -1) Common input to Each DDS independently generates a digital signal, which is then combined or selected to form the final Doppler flicker interference baseband signal. The figure illustrates the generation of Doppler flicker interference signals for channels 1, 2, 3, 4, and 5.

[0062] See also Figure 4 , is a timing diagram of Doppler flicker interference generation in an embodiment of the present invention. When the start flag is valid, the system starts processing radar pulses. The Doppler flicker frequency is in period T. equal and equal The frequency of the FM signal, that is, the baseband interference signal output by the DDS, changes accordingly, and the final interference signal also reflects this alternating frequency change.

[0063] In a specific application scenario, assuming that the radar signal is a dot frequency signal, the difference in the selected Doppler flicker frequency is large, for example, one is 200kHz corresponding to , the other is 2MHz corresponding The Doppler flicker period T is set to 100us. The RF center frequency is assumed to be 1.8GHz. The IQ analysis diagram of the generated Doppler flicker interference signal on the spectrum analyzer is as follows: Figure 3 As shown. Figure 3 The upper half of the spectrum shows that the signal energy is primarily concentrated near two frequencies, which appear alternately. The lower half of the IQvs time plot shows how the signal envelope and phase change over time, reflecting the frequency switching. For example, the signal alternates between 1.8 GHz plus 200 kHz to equal 1.8002 GHz and 1.8 GHz plus 2 MHz to equal 1.802 GHz, or between ±200 kHz and ±2 MHz relative to the baseband, with an interval of 100 μs.

[0064] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these specific embodiments are merely illustrative, and that those skilled in the art may omit, substitute, and modify the details of the methods and systems described above without departing from the principles and spirit of the present invention. For example, combining the above method steps to perform substantially the same functions in substantially the same manner to achieve substantially the same results falls within the scope of the present invention. Accordingly, the scope of the present invention is limited solely by the appended claims.

Claims

1. A Doppler flicker interference generation method based on FPGA, characterized in that: The following steps are involved: Step S1: The host computer sends system parameters and Doppler flicker interference strategy parameters to the FPGA; Step S2: The signal transmission and acquisition module within the FPGA receives the external input radar radio frequency signal, processes the radar radio frequency signal to obtain a radar baseband signal, and sends the radar baseband signal to the signal storage unit within the FPGA; Step S3: The control unit inside the FPGA extracts the radar baseband signal from the signal storage unit according to the system parameter control, and generates an alternating Doppler frequency control word according to the Doppler flicker interference strategy parameter control; The Doppler flicker interference strategy parameters include quantized frequency control words corresponding to at least two different Doppler flicker frequency values. and , and a Doppler scintillation period T; Among them, any Doppler flash frequency To its corresponding quantization frequency control word The conversion is quantified by the following formula: （1） Where, is the quantized Doppler flicker frequency control word, It is the Doppler flashing frequency set by the host computer. is the number of parallel paths of the multi-path parallel DDS unit, is the operating clock frequency of the FPGA, is the number of quantization bits of the frequency control word; Step S4: sending the extracted radar baseband signal or its synchronization information and the alternating Doppler frequency control word together into a multi-channel parallel direct digital frequency synthesizer DDS unit inside the FPGA to generate a multi-channel parallel Doppler flicker interference baseband signal; Step S5: sending the multi-path parallel Doppler flicker interference baseband signals to the signal transmission and acquisition module inside the FPGA for processing, and transmitting to form interference radio frequency signals.

2. The FPGA-based Doppler flicker interference generation method according to claim 1, wherein: The system parameters include a signal detection threshold, a processing start flag, a system reset flag, and a radar signal distance parameter.

3. The FPGA-based Doppler flicker interference generation method according to claim 1, wherein: The Doppler frequency control unit inside the FPGA performs timing counting according to the Doppler flashing period T; whenever the count reaches a preset period value, the Doppler frequency control unit switches the currently output Doppler frequency control word ,exist and The counters are switched alternately to assign values ​​to the multi-channel parallel DDS units; at the same time, the counters are reset to zero and restart counting.

4. The FPGA-based Doppler flicker interference generation method according to claim 1, wherein: The continuous wave signal generated by the multi-channel parallel DDS unit is The road is The sample point values ​​generated by the parallel processing cycle The discretized form of is: Where, It is the reference frequency parameter corresponding to the currently effective Doppler flicker frequency. is the operating clock frequency of the FPGA, is the initial phase of the signal, is the number of parallel paths, is the parallel channel index, with values ​​of 0, 1, ..., -1.

5. The FPGA-based Doppler flicker interference generation method according to claim 4, characterized in that: The initial phase required for each DDS in the multi-channel parallel DDS unit Calculated and loaded using the following formula: Where, is the number of quantization bits of the phase accumulator.

6. The FPGA-based Doppler flicker interference generation method according to claim 1, wherein: In step S2, the signal transmission and acquisition module performs analog-to-digital conversion (ADC) and digital down conversion (DDC) processing on the received radar radio frequency signal to obtain the radar baseband signal.

7. The FPGA-based Doppler flicker interference generation method according to claim 1, wherein: In step S5, the signal transmission and acquisition module performs digital up-conversion (DUC) and digital-to-analog conversion (DAC) processing on the multi-path parallel Doppler flicker interference baseband signals, and outputs the interference radio frequency signals.

8. The FPGA-based Doppler flicker interference generation method according to any one of claims 1 to 7, characterized in that: The methods are all implemented through single or multiple field programmable gate array (FPGA) chip hardware logic.

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