Semiconductor optical element and method for manufacturing semiconductor optical element

Abstract

The invention provides a semiconductor optical element and a manufacturing method of the semiconductor optical element, which can improve heat dissipation performance. This semiconductor optical element is provided with: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor, having an optical gain, and having a mesa, the silicon layer having a waveguide, recessed portions provided on both sides of the waveguide, and a first slat portion connected to the waveguide, the recessed portions being a portion recessed from a surface of the waveguide and a surface of the first slat portion, and the first slat portion being provided on both sides of the waveguide. The semiconductor element is bonded to the first lath portion, and the mesa is located above the first lath portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor optical element and a method for manufacturing the semiconductor optical element. Background Art

[0002] A hybrid semiconductor optical element can be formed by bonding a semiconductor element made of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) with a waveguide formed thereon (e.g., Non-Patent Document 1). After bonding, the semiconductor element is etched, etc., allowing light to migrate between the silicon waveguide and the semiconductor element.

[0003] Prior art literature Non-patent literature Non-Patent Document 1: Alexander W. Fang, et al. “Electrically pumped hybrid AlGaInAs-silicon evanescent laser” OPTICS EXPRESS Vol. 14, No. 20, pp. 9203-9210 (2 October 2006) Non-patent document 2: Javad Rahimi, et al. “Demonstration of a High-EfficiencyShort-Cavity III-V-on-Si C-Band DFB Laser Diode” IEEE JOURNAL OF SELECTEDTOPICS IN QUANTUM ELECTRONICS,Vol.28,No.3,820406 (May / June 2022) Summary of the Invention Problems to be solved by the invention Semiconductor elements bonded to a substrate are active elements and generate heat when driven. Grooves (slots) are provided on both sides of the waveguide in the substrate. The interior of the grooves is filled with air or a dielectric. The grooves have lower heat dissipation than areas outside the grooves in the substrate. This raises the risk of performance degradation due to temperature increases. Therefore, the present invention aims to provide a semiconductor optical element and a method for manufacturing a semiconductor optical element that improves heat dissipation.

[0004] Means used to solve problems The semiconductor optical element according to the present invention comprises: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor, having optical gain, and having a mesa. The silicon layer has a waveguide, a recessed portion, and a first slab portion. The recessed portion is a portion recessed relative to the surface of the waveguide and the first slab portion and is provided on both sides of the waveguide. The first slab portion is connected to the waveguide, and the semiconductor element is bonded to the first slab portion. The mesa is located above the first slab portion.

[0005] Effects of the Invention According to the present invention, a semiconductor optical element capable of improving heat dissipation performance and a method for manufacturing the semiconductor optical element can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a plan view illustrating a semiconductor optical element according to a first embodiment.

[0007] FIG. 2A is an enlarged top view of the vicinity of the migration structure.

[0008] FIG. 2B is a top view illustrating an example of a substrate.

[0009] FIG3A is a cross-sectional view illustrating an example of a semiconductor optical element.

[0010] FIG3B is a cross-sectional view illustrating an example of a semiconductor optical element.

[0011] FIG4A is a cross-sectional view illustrating an example of a semiconductor optical element.

[0012] FIG4B is a cross-sectional view illustrating an example of a semiconductor optical element.

[0013] Figure 5 is a cross-sectional view illustrating a semiconductor optical element.

[0014] FIG. 6 is a diagram illustrating light output by way of example.

[0015] FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor optical element.

[0016] FIG8 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor optical element.

[0017] FIG9 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor optical element.

[0018] FIG10 is a cross-sectional view illustrating a semiconductor optical element according to the second embodiment.

[0019] Description of Reference Numerals 10, 12: substrate; 11: insulating film; 14: buried oxide layer; 16: silicon layer; 20: waveguide; 21, 31, 34, 38: cone; 24: recess; 36, 37: portion; 27: platform; 28, 32: slab portion; 30: semiconductor element; 33: protrusion; 35: table; 39: virtual table; 40, 44: cladding layer; 42: active layer; 46: contact layer; 48, 49: electrode; 100, 200: semiconductor optical element; 101, 102: migration structure; 103: ring resonator; 104: loop mirror. DETAILED DESCRIPTION

[0020] [Description of Embodiments of the Invention] First, the contents of the embodiments of the present invention will be listed and described.

[0021] One embodiment of the present invention is (1) a semiconductor optical element, wherein the semiconductor optical element comprises: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor, having optical gain, and having a mesa, wherein the silicon layer has a waveguide, a recess, and a first slab portion, wherein the recess is a portion recessed from the surface of the waveguide and the first slab portion and is provided on both sides of the waveguide, the first slab portion is connected to the waveguide, the semiconductor element is bonded to the first slab portion, and the mesa is located above the first slab portion. Since the semiconductor element is bonded to the first slab portion, heat dissipation is improved. Heat generated by the semiconductor element is released through the first slab portion. By suppressing temperature rise, deterioration of the characteristics of the semiconductor optical element is suppressed. The mode shape of light is controlled by the mesa of the semiconductor element. Light loss can be suppressed.

[0022] (2) In the above (1), the first slat portion may extend directly below the mesa and within a range of 3 μm or more from the end of the mesa. Heat is generated in the mesa. Since the first slat portion is located directly below the mesa and within a range of 3 μm or more from the end of the mesa, heat dissipation is enhanced. The mode shape of light propagating through the first slat portion is maintained, and light loss can be suppressed.

[0023] (3) In the above (1) or (2), the semiconductor element may include a second strip portion, the second strip portion being bonded to the first strip portion, and the mesa being located above the second strip portion. Since the first strip portion and the second strip portion are bonded, the contact area increases, thereby improving heat dissipation and bonding strength.

[0024] (4) Alternatively, in accordance with (3), the semiconductor element may include a first semiconductor layer, an active layer, and a second semiconductor layer, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in order from the side closest to the substrate, the first semiconductor layer having a first conductivity type, the second semiconductor layer having a second conductivity type, the mesa including the second semiconductor layer, and the second slat portion including the first semiconductor layer and the active layer. Current flows through the mesa, injecting carriers into the active layer, thereby generating light. Heat is generated by the current flowing through the mesa. Since the first slat portion is located below the mesa, heat dissipation is high, thereby suppressing temperature increases.

[0025] (5) Alternatively, in the above (4), the semiconductor optical element may include: a first electrode separated from the mesa and electrically connected to the first semiconductor layer; and a second electrode provided above the mesa and electrically connected to the second semiconductor layer, wherein the first strip portion extends from below the mesa to below the second electrode. Current flows between the first electrode and the second electrode. The first strip portion is located below the current path. Heat dissipation is enhanced, enabling efficient heat dissipation.

[0026] (6) In any one of (3) to (5) above, the semiconductor element may include a protrusion that protrudes from the second slat portion to above the waveguide. This can improve the coupling efficiency between the semiconductor element and the substrate and suppress light loss.

[0027] (7) In any one of (1) to (6) above, the semiconductor element may include a virtual mesa, and two virtual mesas may be located on both sides of the mesa. This can suppress the concentration of stress on the mesa.

[0028] (8) In any one of (1) to (7) above, the semiconductor element may be in contact with the silicon layer. This can improve heat dissipation.

[0029] (9) A method for manufacturing a semiconductor optical element, wherein the method comprises: a step of bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain to a silicon layer of a substrate; and a step of forming a mesa on the semiconductor element after bonding, wherein the silicon layer has a waveguide, a recess, and a slab portion, wherein the recess is a portion recessed from the surface of the waveguide and the slab portion and is provided on both sides of the waveguide, and the slab portion is connected to the waveguide. In the bonding step, the semiconductor element is bonded to the slab portion, and the mesa is located above the slab portion. Since the semiconductor element is bonded to the slab portion, heat dissipation is improved. Heat generated by the semiconductor element is released through the slab portion. By suppressing temperature rise, deterioration of the characteristics of the semiconductor optical element is suppressed. The mode shape of light is controlled by the mesa of the semiconductor element. Light loss can be suppressed.

[0030] [Details of the embodiments of the present invention] Specific examples of semiconductor optical devices and methods for manufacturing semiconductor optical devices according to embodiments of the present invention are described below with reference to the accompanying drawings. It should be noted that the present invention is not limited to these examples, but is intended to encompass all modifications within the meaning and scope of the claims, which are equivalent to the claims.

[0031] <First embodiment> (Semiconductor Optical Components) Figure 1 is a top view illustrating a semiconductor optical element 100 according to the first embodiment. Semiconductor optical element 100 is a hybrid-type wavelength-tunable laser element comprising a substrate 10, a semiconductor element 30, an electrode 48 (second electrode), and an electrode 49 (first electrode). Semiconductor element 30 provides optical gain and is bonded to one surface of substrate 10. The Z-axis is the normal to the top surface of substrate 10. The X-axis is parallel to the waveguide. The Y-axis is orthogonal to the X- and Z-axis directions.

[0032] The semiconductor optical element 100 includes a transition structure 101, a transition structure 102, two ring resonators 103, and two loop mirrors 104. In the X-axis direction, the loop mirrors 104, the ring resonators 103, the transition structure 102, the semiconductor element 30, the transition structure 101, the ring resonators 103, and the loop mirrors 104 are arranged in this order. These components form a laser resonator.

[0033] The ring resonator 103 and the loop mirror 104 are provided on the substrate 10 . The migration structure 101 and the migration structure 102 are portions for migrating light between the substrate 10 and the semiconductor element 30 , and are formed by the substrate 10 and the semiconductor element 30 .

[0034] FIG2A is an enlarged top view of the vicinity of the migration structure 101. FIG2B is an example top view of the substrate 10, with the semiconductor element 30 removed from FIG2A. Figure 5 3A to 3B are cross-sectional views illustrating the semiconductor optical element 100, and illustrate cross sections along line A1, line A2, line A3, line A4 of FIG. 2A and line L of FIG. 1 . Figure 5 The dotted line in FIG. 4 shows the light distribution by way of example.

[0035] As shown in Figure 3A to Figure 5 As shown, substrate 10 is an SOI (Silicon on Insulator) substrate and includes a substrate 12, a buried oxide layer 14, and a silicon (Si) layer 16 stacked sequentially in the Z-axis direction. Substrate 12 is formed, for example, of Si. Buried oxide layer 14 is formed, for example, of silicon oxide (SiO2). The thickness of buried oxide layer 14 is, for example, 3 μm. The thickness of silicon layer 16 is, for example, 220 nm. The upper surface of substrate 10 and the surface of semiconductor element 30 are covered by insulating film 11. Insulating film 11 is formed, for example, of SiO2 with a thickness of 1 μm. The refractive index of silicon layer 16 is 3.45. The refractive index of buried oxide layer 14 and insulating film 11 is lower than that of silicon layer 16, at 1.45. Functional components such as waveguides are provided in silicon layer 16 in substrate 10.

[0036] As shown in Figures 1, 2A, and 2B, substrate 10 includes a waveguide 20, a recess 24, a platform 27, and a slat portion 28 (a first slat portion). As shown in Figure 1, waveguide 20 is connected to both ends of slat portion 28 in the X-axis direction. Slat portion 28 extends from migration structure 101 to migration structure 102.

[0037] As shown in FIG2B , waveguide 20 is parallel to the X-axis. Waveguide 20 has a tapered portion 21. The width of tapered portion 21 increases as it approaches slat portion 28 and decreases as it moves away from slat portion 28. The width W1 at the tip of waveguide 20 shown in FIG2B is, for example, 420 nm.

[0038] In the Y-axis direction, a recess 24 and a terrace 27 are provided in this order on both sides of the waveguide 20. That is, the recess 24 is arranged next to the waveguide 20. The terrace 27 is arranged on the opposite side of the recess 24 from the waveguide 20. The recess 24 extends along the waveguide 20 and has a tapered shape corresponding to the tapered portion 21 of the waveguide 20.

[0039] As shown in Figures 3A to 4B, the waveguide 20 and terrace 27 are portions of the silicon layer 16 that protrude further in the Z-axis direction (upward) than the recess 24. The surface of the waveguide 20 is located at the same height as the surface of the terrace 27. The recess 24 is recessed relative to the surfaces of the waveguide 20 and terrace 27. The silicon layer 16 forms the bottom surface of the recess 24. The thickness of the silicon layer 16 in the recess is, for example, 30 nm. The recess 24 can extend to the middle of the silicon layer 16 in the Z-axis direction, or it can penetrate the silicon layer 16 and extend to the buried oxide layer 14. The insulating film 11 is embedded in the recess 24.

[0040] As shown in FIG2B , the slat portion 28 has a greater width than the waveguide 20 in the Y-axis direction and is connected to the platforms 27 on both sides of the waveguide 20. That is, no recess is provided between the slat portion 28 and the platform 27. Figure 5 As shown, the strip portion 28 is a plate-shaped portion. The surface of the strip portion 28 is located at the same height as the surface of the platform 27. The strip portion 28 is formed integrally with the platform 27, extends parallel to the XY plane, and forms the surface of the silicon layer 16.

[0041] As shown in FIG1 , semiconductor device 30 includes a strip portion 32 (second strip portion), two protrusions 33, and a mesa 35. Protrusions 33, strip portion 32, and protrusion 33 are arranged in this order in the X-axis direction. Strip portion 32 and mesa 35 extend from one migration structure 101 to the other migration structure 102.

[0042] As shown in FIG2A , the strip portion 32 is joined to the strip portion 28 of the substrate 10. The lower surface of the strip portion 32 contacts the upper surface of the strip portion 28. The strip portion 32 is plate-shaped and has a width greater than that of the protrusion 33 and the terrace 35. The strip portion 32 has a rectangular planar shape. When viewed from above, the strip portion 32 does not protrude further than the strip portion 28. The strip portion 28 extends from the position where it overlaps with the strip portion 32 to the outside of the strip portion 32.

[0043] The protrusion 33 extends parallel to the X-axis, protruding from the slat portion 32 above the waveguide 20 and positioned above the tapered portion 21 of the waveguide 20. The protrusion 33 includes a tapered portion 34. In the example of FIG2A , the entire protrusion 33 is tapered portion 34. The width of the tapered portion 34 increases as it approaches the slat portion 32 and decreases as it moves away from the slat portion 32. The protrusion 33 is wider than the mesa 35. The width of the protrusion 33 at the portion where it connects to the slat portion 32 is, for example, 5.7 μm.

[0044] As shown in FIG2A , the mesa 35 extends parallel to the X-axis, from a position overlapping the waveguide 20 to a position overlapping the slat portion 28. The mesa 35 is located above the slat portion 28, the slat portion 32, and the protrusion 33. The mesa 35 includes a portion 36 and a portion 37. The portion 36 protrudes outward from the slat portion 32 in the X-axis direction and is located above the protrusion 33 and the waveguide 20. The portion 37 is located above the slat portion 32.

[0045] Portion 36 of mesa 35 has a tapered portion 38 (third tapered portion). Tapered portion 38 is located above protrusion 33. The width of tapered portion 38 increases as it approaches stripe portion 32 and decreases as it moves away from stripe portion 32. The width of the tip of mesa 35 is, for example, 400 nm.

[0046] The protrusion 33 and the mesa 35 do not protrude outward from the waveguide 20 in a plan view, but are located inside the waveguide 20. The waveguide 20 protrudes from below the protrusion 33 and the mesa 35 to the outside of the protrusion 33.

[0047] The tapered portion 31 of the semiconductor element 30 protrudes from the strip portion 32 in the X-axis direction, is located on both sides of the mesa 35 in the Y-axis direction, and is located between the strip portion 32 and the tapered portion 38 of the mesa 35 in the X-axis direction. The width of the portion of the tapered portion 31 connected to the strip portion 32 is, for example, 3 μm.

[0048] As shown in Figure 3B to Figure 5 As shown, semiconductor element 30 includes a cladding layer 40 (first semiconductor layer), an active layer 42, a cladding layer 44, and a contact layer 46 (both layers constitute the second semiconductor layer). As shown in Figures 3B and 4A, protrusion 33 of semiconductor element 30 is formed by cladding layer 40. As shown in Figure 4A, tapered portion 31 is formed by active layer 42.

[0049] The mesa 35 includes an active layer 42, a cladding layer 44, and a contact layer 46. As shown in FIG4A and FIG4B, a portion 36 of the mesa 35 includes the active layer 42, the cladding layer 44, and the contact layer 46, and has a deep ridge structure. Figure 5 As shown, portion 37 of mesa 35 does not include active layer 42 but includes cladding layer 44 and contact layer 46, and has a shallow ridge structure. Width W of portion 37 of mesa 35 is, for example, not less than 1 μm and not more than 3 μm.

[0050] like Figure 5 As shown, semiconductor device 30 has two virtual mesas 39. These two virtual mesas 39 are located on either side of mesa 35 in the Y-axis direction and are separated from mesa 35. Virtual mesas 39 include a cladding layer 44 and a contact layer 46. The height of virtual mesas 39 is equal to the height of mesa 35. The length of virtual mesas 39 in the X-axis direction is, for example, equal to the length of portion 37 of mesa 35.

[0051] like Figure 5 As shown, the slat portion 32 includes a cladding layer 40 and an active layer 42. The slat portion 28 of the silicon layer 16 is provided below the slat portion 32. The slat portion 28 is provided at least directly below the mesa 35 and within a range of a distance D1 or more from both ends of the mesa 35 in the Y-axis direction. D1 can be, for example, 3 μm or 5 μm. Figure 5 In the example shown in FIG. 2 , the strip portion 32 is provided directly below the portion 37 of the mesa 35 in the Z-axis direction, between the mesa 35 and the two virtual mesas 39, below the virtual mesas 39, and outside the virtual mesas 39. In other words, the strip portion 32 extends from below the portion 37 of the mesa 35 to outside the two virtual mesas 39. The strip portion 28 may also extend to the end of the semiconductor optical element 100 in the Y-axis direction.

[0052] The cladding layer 40 is located between the active layer 42 and the silicon layer 16 of the substrate 10, and extends outward in the Y-axis direction from the active layer 42. The cladding layer 40 is in contact with the silicon layer 16. The strip portion 28 may also extend from directly below the mesa 35 to outside the virtual mesa 39.

[0053] The insulating film 11 covers the substrate 10, the strip portion 32, the protrusion 33, the mesa 35, and the virtual mesa 39. Figure 5 As shown, the insulating film 11 has an opening above the mesa 35. The electrode 48 is a p-type electrode provided on the surface of the insulating film 11 and the upper surface of the mesa 35. The electrode 48 is in contact with the surface of the contact layer 46 at the opening of the insulating film 11 and is electrically connected to the contact layer 46.

[0054] Electrode 48 extends from the top surface of mesa 35 to a dummy mesa 39, covers the top surface and side surfaces of dummy mesa 39, and extends to the outside of strip portion 32. An insulating film 11 is provided between electrode 48, dummy mesa 39, and strip portion 32. Electrode 48 is electrically connected to contact layer 46 of mesa 35, but is not connected to contact layer 46 of dummy mesa 39 or cladding layer 40.

[0055] The insulating film 11 also has an opening at a position separated from the mesa 35 and the virtual mesa 39. The electrode 49 is an n-type electrode and is electrically connected to the cladding layer 40 via the opening. The electrode 49 is located above the strip portion 32 and the strip portion 28.

[0056] The cladding layer 40 is formed, for example, of n-type (first conductivity type) indium phosphide (n-InP). The thickness of the cladding layer 40 is, for example, 400 nm. The active layer 42 has a quantum well structure (MQW: Multiple Quantum Well) and includes barrier layers and well layers. Multiple barrier layers and multiple well layers are alternately stacked. The barrier layers and well layers are formed, for example, of i-type gallium indium arsenide phosphide (GaInAsP). The thickness of the active layer 42 is, for example, 200 nm. Guide layers may be provided between the active layer 42 and the cladding layer 40, and between the active layer 42 and the cladding layer 44. The cladding layer 44 is formed, for example, of p-type (second conductivity type) indium phosphide (p-InP). The thickness of the cladding layer 44 is, for example, 2 μm. The contact layer 46 is formed, for example, of p-type gallium indium arsenide (p-GaInAs). The semiconductor layers of the semiconductor element 30 may also be formed of Group III-V compound semiconductors other than those described above.

[0057] Electrodes 48 and 49 are formed of metal. Electrode 48 is formed, for example, of a stack of titanium (Ti), platinum (Pt), and gold (Au) stacked from the side closest to mesa 35. Electrode 49 is formed, for example, of an alloy of gold, germanium, and nickel (AuGeNi).

[0058] The migration structure 102 has the same configuration as the migration structure 101 . The strip portion 28 of the silicon layer 16 and the strip portion 32 of the semiconductor element 30 extend from the migration structure 101 to the migration structure 102 .

[0059] A voltage is applied to the semiconductor element 30 using electrodes 48 and 49, injecting carriers into the active layer 42. The active layer 42 has optical gain, and light is generated by the carrier injection. The wavelength of the light is, for example, 1.55 μm. The semiconductor element 30 and the substrate 10 are subjected to evanescent light coupling. The light generated by the semiconductor element 30 is transferred to the waveguide 20 in the transition structures 101 and 102. The light resonates in the ring resonator 103 and is reflected by the loop mirror 104. The reflected light propagates toward the semiconductor element 30 and is transferred from the waveguide 20 to the semiconductor element 30 in the transition structures 101 and 102. The light undergoes laser oscillation through repeated reflection.

[0060] The diameter of one of the two ring resonators 103 is different from the diameter of the other ring resonator. The oscillation wavelength is determined by the Vernier effect of the two ring resonators 103. The transmittance of one of the two loop mirrors 104 is higher than the transmittance of the other loop mirror. A portion of the laser light passes through the loop mirror 104 and is emitted outside the semiconductor optical element 100.

[0061] In Figures 3A to Figure 5In the figure, the shape of light is schematically illustrated by a dotted closed curve. The light mode is defined by the waveguide 20 and the mesa 35. As shown in FIG3A , light is concentrated in the waveguide 20 just before the tapered portion 21. In the migration structure 101, light is transferred from the waveguide 20 to the semiconductor element 30. Since the protrusion 33 and the mesa 35 of the semiconductor element 30 have a tapered shape, the light is gradually transferred and the light mode is smoothly converted. Figure 5 As shown, silicon layer 16 has slat portions 28. Mesas 35 are located above slat portions 28. Light is confined near mesas 35 of semiconductor element 30, making it difficult to spread. While light propagates through semiconductor element 30, the converted light mode is maintained, thus minimizing light loss.

[0062] When voltage is applied to the semiconductor element 30, current flows between the electrode 48 and the electrode 49. The current flows through the contact layer 46, the cladding layer 44, the active layer 42, and the cladding layer 40 of the semiconductor element 30. Heat is generated by the flow of current. Figure 5 As shown, a strip portion 28 of silicon layer 16 is provided below the portion between electrode 48 and electrode 49. In other words, in the portion below the current path, the silicon layer 16 is provided with strip portions 28, rather than cavities such as grooves. Silicon has a lower thermal resistance than air. The presence of strip portions 28 enhances heat dissipation. Silicon layer 16 functions as a heat dissipation path. Heat generated when operating semiconductor optical element 100 is dissipated from silicon layer 16, suppressing degradation of characteristics due to temperature increases.

[0063] Figure 6 is a graph illustrating light output. The horizontal axis represents the current flowing through semiconductor element 30. The vertical axis represents the light output emitted from the semiconductor optical element. The solid line represents the light output measurement results for the first embodiment. The dotted line represents the measurement results for the comparative example. In the comparative example, the waveguide and recess of silicon layer 16 extend from the outside of semiconductor element 30 to the bottom of semiconductor element 30. The waveguide width is 1 μm. The wavelength of light is 1.55 μm.

[0064] 6 , as the current increases, the light output also increases. When the current is 100 mA or more, the light output of the first embodiment is higher than that of the comparative example when compared at the same current.

[0065] In the comparative example, the concave portion of the silicon layer 16 is also provided below the semiconductor element 30. The concave portion is filled with air. The heat dissipation of the concave portion is low, and the heat generated by the semiconductor element 30 is difficult to be released. Since the temperature easily rises, the characteristics deteriorate. Figure 5 As shown, the light output is difficult to increase.

[0066] In the first embodiment, a slat portion 28 is provided below the semiconductor element 30 instead of a recess. Due to the high heat dissipation, heat is easily released and the temperature is unlikely to rise. This can suppress the degradation of characteristics caused by temperature rise. The greater the current, the greater the heat generation, so high heat dissipation is required. Figure 5 As shown, the higher the current, the greater the difference in light output between the first embodiment and the comparative example. The light output of the first embodiment is about 1.3 times that of the comparative example.

[0067] (Manufacturing Method) 7 to 9 are cross-sectional views illustrating a method for manufacturing the semiconductor optical element 100, and Figure 5 The cross section of the corresponding position.

[0068] In the steps preceding FIG. 7 , silicon layer 16 of substrate 10 is dry-etched, for example. The portion exposed by the mask (not shown) is etched, forming recesses 24. The portion covered by the mask (not shown) is not etched. Waveguide 20, terraces 27, and slats 28 are formed.

[0069] On an InP substrate, different from the SOI substrate (substrate 10), a contact layer 46, a cladding layer 44, an active layer 42, and a cladding layer 40 are epitaxially grown in this order by methods such as metal organic chemical vapor deposition (MOCVD). This InP substrate is diced to form a semiconductor element 30. Immediately after dicing, the semiconductor element 30 is a rectangular parallelepiped and lacks the slat portion 32, the protrusion 33, or the mesa 35.

[0070] As shown in Figure 7, a semiconductor element 30 is bonded to the upper surface of substrate 10. Plasma is irradiated onto one surface of silicon layer 16 and the surface of cladding layer 40 surrounding semiconductor element 30 to activate these surfaces. The surface of cladding layer 40 is brought into contact with the surface of silicon layer 16, thereby bonding semiconductor element 30 to silicon layer 16. For example, semiconductor element 30 covers the upper surface of silicon layer 16 and is positioned above waveguide 20, recess 24, terrace 27, and slat 28. After bonding, wet etching is performed to remove the InP substrate. The semiconductor layer remains from contact layer 46 to cladding layer 40.

[0071] As shown in FIG8 , a mesa 35 and a virtual mesa 39 are formed on the semiconductor element 30. The mesa 35 and the virtual mesa 39 are located above the slat portion 28. Specifically, a mask (not shown) is placed on the upper surface of the contact layer 46. The contact layer 46 and the cladding layer 44 are etched in the portion not covered by the mask. The mesa 35 and the virtual mesa 39 are formed in the portion covered by the mask. For example, the contact layer 46 and the cladding layer 44 can be removed by wet etching using a hydrochloric acid-based etchant. Alternatively, dry etching can be performed up to the middle of the contact layer 46 and the cladding layer 44, and the remaining portion can be wet-etched. The active layer 42 and the cladding layer 40 remain in the etched portion and are located below the mesa 35 and the virtual mesa 39, forming the slat portion 32.

[0072] As shown in Fig. 9 , the active layer 42 and the cladding layer 40 are etched, so that a portion of the cladding layer 40 is exposed from the active layer 42. The protrusion 33 shown in Fig. 2B and the like are also formed.

[0073] By plasma CVD method (PECVD, Plasma Enhanced Chamical Vapor Deposition), etc., as shown in Figure 3A to Figure 5 Insulating film 11 is formed in this manner. Openings are formed in the portion of insulating film 11 above mesas 35, and openings are also formed above cladding layer 40. Electrodes 48 and 49 are formed in the openings by vacuum deposition or the like. The semiconductor optical element 100 is formed through the above steps.

[0074] According to the first embodiment, the silicon layer 16 of the substrate 10 includes the waveguide 20, the recess 24, and the slat portion 28. Since the semiconductor element 30 is bonded to the slat portion 28, heat dissipation is enhanced. Heat generated by the semiconductor element 30 is dissipated through the slat portion 28. By suppressing temperature increases, degradation of the characteristics of the semiconductor optical element 100 is suppressed. For example, as shown in FIG6 , high optical output can be achieved.

[0075] The mesa 35 of the semiconductor element 30 is located above the slat portion 28. Light is distributed near the mesa 35, and the mode shape is controlled by the mesa 35. The light mode is distributed throughout the lower portion of the mesa 35, the slat portion 32, and the slat portion 28. The slat portion 28 is located directly below the mesa 35 and within a range of a distance D1 or greater from the end of the mesa 35. Distance D1 is 3 μm or greater. By setting distance D1 to 3 μm or greater, the mode of light entering from the waveguide 20 is stably maintained near the mesa 35. For example, single-mode light can be propagated through the mesa 35, the slat portion 32, and the slat portion 28, thereby suppressing light loss.

[0076] Semiconductor element 30 is bonded to strip portion 28. Compared to bonding above recess 24, the contact area between semiconductor element 30 and silicon layer 16 increases, resulting in higher bonding strength. This improves the mechanical strength of semiconductor optical element 100. The etchant used in wet etching is blocked by strip portion 28, suppressing etching of semiconductor element 30 from the bonding interface. This can prevent damage to semiconductor element 30.

[0077] When voltage is applied, current flows through the mesa 35, generating heat. The slat portion 28 of the silicon layer 16 is provided at least directly below the mesa 35 and within a range of a distance D1 or greater from the end of the mesa 35. Distance D1 is, for example, 1 μm or greater, 3 μm or greater, or 5 μm or greater. The slat portion 28 may also be provided within a range wider than the width of the slat portion 32 in the Y-axis direction. The slat portion 28 functions as a heat dissipation path, dissipating heat generated by the mesa 35. This improves heat dissipation. Heat diffuses along the XY directions in the slat portion 28 and the slat portion 32. A small recess may be provided in a portion of the slat portion 28 below the slat portion 32, without dividing the heat dissipation path, when viewed from above. Dividing the heat dissipation path means that the recess passes through the slat portion 28 located below the slat portion 32 when viewed from above. Even when a small recess that does not divide the heat dissipation path is provided, it is preferable not to provide the small recess directly below the mesa 35 or within a range of a distance D1 (eg, D1 is 3 μm) from the end of the mesa 35 to suppress light loss.

[0078] like Figure 5 As shown, the strip portion 28 may extend from below the table 35 to the outside of the electrode 49. Current flows between the electrode 48 and the electrode 49 provided on the table 35. Heat is generated in the current path. The strip portion 28 is provided at a position overlapping the current path. This improves heat dissipation, enabling efficient heat dissipation.

[0079] No resin or the like is provided between the semiconductor element 30 and the silicon layer 16, and the semiconductor element 30 is in contact with the silicon layer 16. Heat is easily transferred from the semiconductor element 30 to the silicon layer 16, and heat dissipation is enhanced.

[0080] In Figure 1 and Figure 5 In the example shown, recess 24 is not provided at the position overlapping semiconductor element 30, but strip portion 28 is provided. This improves heat dissipation. Strip portion 28 contacts the entire lower surface of semiconductor element 30. This increases the contact area between semiconductor element 30 and silicon layer 16, improving bonding strength.

[0081] Semiconductor element 30 includes a strip portion 32. Strip portion 32 of semiconductor element 30 is bonded to strip portion 28 of silicon layer 16. Bonding the strip portions increases the contact area, improving heat dissipation and bonding strength. A mesa 35 is located above strip portion 32. The mesa 35 enables control of the light pattern, thus minimizing light loss.

[0082] Semiconductor element 30 includes a cladding layer 40, an active layer 42, a cladding layer 44, and a contact layer 46. The slat portion 32 includes the cladding layer 40 and the active layer 42. Portion 37 of mesa 35 includes the cladding layer 44 and the contact layer 46. The stacking of the n-type cladding layer 40, the i-type active layer 42, the p-type cladding layer 44, and the contact layer 46 forms a pin (positive-intrinsic-negative) junction on mesa 35. Injecting carriers into the active layer 42 generates light. When current flows through mesa 35, heat is generated. Because the slat portion 28 is located below mesa 35, heat dissipation is enhanced, suppressing temperature increases.

[0083] Semiconductor element 30 has a protrusion 33. Protrusion 33 is located above waveguide 20. This improves the coupling efficiency between semiconductor element 30 and substrate 10 and allows for smooth light migration. Portion 37 of mesa 35, located above slat portion 32, includes cladding layer 44 and contact layer 46. Light is confined near mesa 35, thus minimizing light loss.

[0084] As shown in FIG2A , the waveguide 20 protrudes outside the protrusion 33 and the mesa 35. The protrusion 33 and the mesa 35 do not protrude but are located inward of the waveguide 20. This prevents etching of the semiconductor element 30 from the bonding interface. The mesa 35 is located inward of the protrusion 33. Etching facilitates the production of the protrusion 33 and the mesa 35. After forming the mesa 35, the protrusion 33 can be formed below the mesa 35.

[0085] Waveguide 20 has a tapered portion 21. Protrusion 33 has a tapered portion 34. Mesa 35 has a tapered portion 38. Tapered portion 34 of protrusion 33 joins tapered portion 21 of waveguide 20. Tapered portion 38 of mesa 35 is located above tapered portion 34 of protrusion 33. The multi-stage tapered structure improves the coupling efficiency between semiconductor element 30 and substrate 10.

[0086] The two virtual terraces 39 are located on both sides of the terrace 35. This can suppress the concentration of stress on the terrace 35 during the manufacturing process, etc. The mechanical strength is improved, and breakage can be suppressed.

[0087] The insulating film 11 covers the silicon layer 16 of the substrate 10 and the semiconductor element 30. Since the insulating film 11 functions as a cladding layer, it is possible to suppress light loss.

[0088] The semiconductor optical element 100 shown in Fig. 1 is a wavelength tunable laser element. The semiconductor optical element 100 may be an optical device different from the wavelength tunable laser element.

[0089] <Second embodiment> FIG10 is a cross-sectional view showing an example of a semiconductor optical element 200 according to the second embodiment. Figure 5 The description of the same configuration as that of the first embodiment will be omitted.

[0090] As shown in FIG10 , semiconductor element 30 of semiconductor optical element 200 does not have a virtual mesa, but rather has a mesa 35. Slat portion 32 extends from below mesa 35 to the outside of mesa 35. Insulating film 11 covers the side surfaces of mesa 35 and the top and side surfaces of slat portion 32. Electrode 48 is provided on the top surface of mesa 35 and also extends to the top surfaces of slat portion 32 and slat portion 28.

[0091] According to the second embodiment, the semiconductor element 30 is bonded to the slat portion 28, resulting in high heat dissipation. Heat generated by the semiconductor element 30 is dissipated through the slat portion 28. This suppresses temperature rise, thereby minimizing degradation of characteristics. The mesa 35 of the semiconductor element 30 is located above the slat portion 28. Light is distributed near the mesa 35, and the mode shape is controlled by the mesa 35, thereby minimizing light loss.

[0092] While the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A semiconductor optical element, wherein: The semiconductor optical element comprises: a substrate having a silicon layer; and A semiconductor element formed of a III-V compound semiconductor, having optical gain and having a mesa, The silicon layer has a waveguide, a recess, and a first slab portion, The recessed portion is a portion recessed from the surface of the waveguide and the first slat portion and is provided on both sides of the waveguide. The first slat portion is connected to the waveguide, The semiconductor element is bonded to the first strip portion, The table top is located above the first slat portion.

2. The semiconductor optical element according to claim 1, wherein The first strip portion extends directly below the mesa and within a range of 3 μm or more from an end portion of the mesa.

3. The semiconductor optical element according to claim 1 or 2, wherein The semiconductor element has a second strip portion, the second strip portion is engaged with the first strip portion, The table top is located above the second slat portion. The semiconductor optical element according to claim 3 , wherein: The semiconductor element comprises a first semiconductor layer, an active layer and a second semiconductor layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked in order from the side closest to the substrate, The first semiconductor layer has a first conductivity type, The second semiconductor layer has a second conductivity type, The mesa comprises the second semiconductor layer, The second slab portion includes the first semiconductor layer and the active layer. The semiconductor optical element according to claim 4 , wherein The semiconductor optical element comprises: a first electrode, separated from the mesa and electrically connected to the first semiconductor layer; as well as a second electrode, disposed above the mesa and electrically connected to the second semiconductor layer; The first strip portion extends from below the mesa to below the second electrode. The semiconductor optical element according to claim 3 , wherein: The semiconductor element has a protrusion, The protrusion protrudes from the second strip portion to above the waveguide.

7. The semiconductor optical element according to claim 1 or 2, wherein The semiconductor element has a virtual mesa, The two virtual table surfaces are located on both sides of the table surface.

8. The semiconductor optical element according to claim 1 or 2, wherein The semiconductor element is in contact with the silicon layer.

9. A method for manufacturing a semiconductor optical element, wherein: The method for manufacturing the semiconductor optical element comprises: A step of bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain to the silicon layer of the substrate; as well as In the process of forming a mesa in the semiconductor element after bonding, The silicon layer has a waveguide, a recessed portion, and a slat portion, The recessed portion is a portion recessed from the surface of the waveguide and the slat portion and is provided on both sides of the waveguide. The slat portion is connected to the waveguide, In the bonding step, the semiconductor element is bonded to the strip portion. The table top is located above the slat portion.

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