Display panel

Abstract

According to the display panel, a first data line part and a second data line part of a data line are each provided with one side and the other side which are oppositely arranged in the second direction, and a first routing part of a touch routing line is overlapped with one side of the first data line part and is spaced from the other side of the first data line part; a second routing part of the touch routing is overlapped with the other side of the second data line part and is spaced from one side of the second data line part, so that the first routing part and the second routing part respectively form an asymmetric complementary overlapping structure with the first data line part and the second data line part, and when the touch routing is subjected to alignment offset, the first data line part and the second data line part are mutually overlapped; the change amount of the overlapping area between the first wiring part and the corresponding first data line part and the change amount of the overlapping area between the second wiring part and the corresponding second data line part are counteracted reversely, so that the overlapping area between the touch control wiring and the data line wiring is almost unchanged before and after the alignment offset of the touch control wiring relative to the data line; therefore, RC load fluctuation caused by alignment offset of the touch wires and the data lines is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] With the rapid development of display technology, in-cell display panels with integrated touch functions have become the mainstream technology direction due to their advantages such as lightness, thinness, and high integration. In in-cell products, the touch line (TP line) needs to share the limited pixel layout space with the display data line (data line). In order to take into account the panel aperture ratio, the existing technology usually adopts an overlapping design of TP line and data line, for example, making the TP line partially or completely overlap with the data line in the vertical projection direction. However, this overlapping structure will cause a large coupling capacitance to form between the TP line and the data line, significantly increasing the RC load (RC loading) of the touch signal transmission path. When the RC load is too large, the delay and distortion of the touch signal will be aggravated, which will cause the display of the display panel to be abnormal during touch operation (such as screen flickering, drive failure, etc.), seriously affecting the user experience.

[0003] In addition, in the display panel manufacturing process, the alignment accuracy of the TP line and the data line is limited by the shift margin of the photolithography process. In actual products, the overlapping area of the two may fluctuate due to alignment shift. The fluctuation of the overlapping area of the TP line and the data line directly changes the coupling capacitance between the TP line and the data line, causing the RC load of the touch signal path to be non-uniformly distributed. This fluctuation of the RC load will lead to a decrease in the signal response consistency of the touch function, which is specifically manifested in regional differences in touch sensitivity, coordinate positioning drift and other problems. Especially in high-resolution or large-size panels, the miniaturization of line width and line spacing further amplifies the impact of alignment shift, making the RC load fluctuation problem more prominent.

[0004] Conventional technology often mitigates capacitive coupling between TP lines and data lines by increasing the spacing between them or introducing a shielding layer. However, these approaches sacrifice panel aperture ratio or increase process complexity (e.g., requiring additional mask passes). Another approach is to optimize TP line material properties to reduce capacitance per unit length, but this approach struggles to fundamentally eliminate the RC load fluctuation caused by misalignment. Therefore, how to suppress RC load fluctuations caused by misalignment between TP lines and data lines while maintaining stable touch signal transmission, while maintaining a high aperture ratio and low process cost, remains a pressing technical challenge in this field. Summary of the Invention

[0005] The present application provides a display panel to alleviate the technical problem of large RC load fluctuation caused by the misalignment between touch lines and data lines in existing panels.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] An embodiment of the present application provides a display panel, comprising:

[0008] A touch wiring, comprising a first wiring portion and a second wiring portion arranged along a first direction; and

[0009] a data line comprising a first data line portion and a second data line portion arranged along the first direction, wherein the first data line portion and the second data line portion each have one side and another side oppositely arranged along a second direction, wherein the second direction intersects the first direction;

[0010] The first routing portion overlaps with the one side of the first data line portion and is spaced from the other side of the first data line portion; the second routing portion overlaps with the other side of the second data line portion and is spaced from the one side of the second data line portion.

[0011] In the display panel provided in an embodiment of the present application, the touch wiring further includes a first connecting portion connecting the first wiring portion and the second wiring portion, and the data line further includes a second connecting portion connecting the first data line portion and the second data line portion, and the shape of the second connecting portion is different from that of the first connecting portion.

[0012] In the display panel provided by the embodiment of the present application, the first data line portion and the second data line portion are axially symmetric about a center line of the second connecting portion; and the first routing portion and the second routing portion are asymmetrically arranged.

[0013] In the display panel provided by the embodiment of the present application, in the second direction, the width of the first wiring portion extending beyond the first data line portion is equal to the width of the second wiring portion extending beyond the second data line portion.

[0014] In the display panel provided in the embodiment of the present application, the width of the first routing portion exceeding the first data line portion is equal to the overlapping width of the first routing portion and the first data line portion; the width of the second routing portion exceeding the second data line portion is equal to the overlapping width of the second routing portion and the second data line portion.

[0015] In the display panel provided in the embodiment of the present application, the overlapping area between the first routing portion and the first data line portion is a first area, the overlapping area between the second routing portion and the second data line portion is a second area, and the sum of the first area and the second area is 1 / 3 to 2 / 3 of the sum of the areas of the first routing portion and the second routing portion.

[0016] In the display panel provided in the embodiment of the present application, the vertical orthographic projection of the first wiring portion is located within the vertical orthographic projection of the first data line portion, and the vertical orthographic projection of the second wiring portion is located outside the vertical orthographic projection of the second data line portion.

[0017] In the display panel provided in the embodiment of the present application, the length of the first wiring portion is equal to the length of the second wiring portion.

[0018] The display panel provided in the embodiment of the present application further includes:

[0019] a plurality of scan lines arranged at intervals along the first direction, wherein the plurality of scan lines are insulated from and cross the plurality of data lines to define a plurality of sub-pixels, each of the sub-pixels comprising a transistor and a pixel electrode connected to the transistor;

[0020] Two adjacent first connection parts are a first type first connection part and a second type first connection part, and two adjacent second connection parts are a first type second connection part and a second type second connection part. The first type first connection part is arranged corresponding to the first type second connection part, and the second type first connection part corresponds to the second type second connection part. The first type second connection part is located between two adjacent sub-pixels, and the second type second connection part is located at the intersection of the data line and the scan line.

[0021] The display panel provided in the embodiment of the present application includes:

[0022] a first substrate;

[0023] a first conductive layer, disposed on one side of the first substrate, wherein the first conductive layer is provided with the scanning line;

[0024] a second conductive layer, disposed on a side of the first conductive layer away from the first substrate, the second conductive layer being formed with the data line and the drain of the transistor;

[0025] a third conductive layer, disposed on a side of the second conductive layer away from the first substrate, the touch trace being formed on the third conductive layer;

[0026] a first transparent conductive layer, disposed on a side of the third conductive layer away from the first substrate, wherein the first transparent conductive layer is formed with a common electrode and a touch electrode, and the touch electrode is connected to the touch trace;

[0027] The second transparent conductive layer is provided on a side of the first transparent conductive layer away from the first substrate. The pixel electrode is formed on the second transparent conductive layer, and the pixel electrode is connected to the drain electrode.

[0028] The beneficial effects of the present application are as follows: in the display panel provided by the present application, the first data line portion and the second data line portion of the data line each have one side and the other side arranged opposite to each other along the second direction; the first routing portion of the touch routing overlaps with one side of the first data line portion and is spaced from the other side of the first data line portion; the second routing portion of the touch routing overlaps with the other side of the second data line portion and is spaced from one side of the second data line portion, so that the first routing portion and the second routing portion form an asymmetric complementary overlapping structure with the first data line portion and the second data line portion respectively; the overlap amount of the first routing portion and the first data line portion is equal to the overlap amount of the second routing portion. The overlap between the routing portion and the second data line portion is complementary, so that when the touch routing portion is offset, the changes in the overlapping areas of the first routing portion, the second routing portion, and the corresponding first data line portion and the second data line portion are inversely offset, thereby achieving self-compensation of the total overlapping area. In this way, the overlapping area between the touch routing portion and the data line portion remains almost unchanged before and after the touch routing portion is offset relative to the data line, thereby reducing the RC load fluctuation caused by the offset between the touch routing portion and the data line, thereby improving the technical problem of large RC load fluctuation caused by the offset between the touch routing portion and the data line in existing panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 The following is a schematic diagram of a planar structure of a display panel.

[0031] Figure 2 for Figure 1 Schematic diagram of the planar structure of the touch wiring of the display panel with a left deviation.

[0032] Figure 3 for Figure 1 Schematic diagram of the planar structure of the touch line of the display panel is right-biased.

[0033] Figure 4A schematic diagram of a planar structure of a display panel provided in an embodiment of the present application.

[0034] Figure 5 for Figure 4 Detailed planar structure diagram of a sub-pixel in .

[0035] Figure 6 for Figure 5 Detailed structural diagram of M in the middle.

[0036] Figure 7 for Figure 5 Detailed structural diagram at N in the figure.

[0037] Figure 8 A schematic diagram of a partial film layer structure of a display panel provided in an embodiment of the present application.

[0038] Figure 9 A schematic diagram comparing RC load fluctuations provided in an embodiment of the present application.

[0039] Figure 10 A schematic diagram of another planar structure of a sub-pixel provided in an embodiment of the present application.

[0040] Figure 11 This is another schematic diagram of a planar structure of a sub-pixel provided in an embodiment of the present application.

[0041] Reference numerals:

[0042] 100. Display panel;

[0043] 10. Third conductive layer; touch trace, TP; 11. First trace portion; 12. Second trace portion; 13. First connection portion;

[0044] 20. Second conductive layer; Data, data line; Dr, drain; 21. First data line portion; 22. Second data line portion; 23. Second connecting portion;

[0045] 30. First conductive layer; Gate, scan line;

[0046] 40. a first substrate;

[0047] 50. First transparent conductive layer; 51. Common electrode; Sensor, touch electrode;

[0048] 60. Second transparent conductive layer; 61. Pixel electrode;

[0049] 70. Second substrate; 71. Light shielding layer; 72. Color filter layer; 73. Flat layer;

[0050] 80. Support column;

[0051] TFT, transistor; As, active layer; Y, first direction; X, second direction. DETAILED DESCRIPTION

[0052] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0053] Reference Figures 1 to 3 , Figure 1 The following is a schematic diagram of a planar structure of a display panel. Figure 2 for Figure 1 Schematic diagram of the planar structure of the touch line of the display panel on the left side. Figure 3 for Figure 1 A schematic diagram of the touch line structure of the display panel with the touch line offset to the right. In in-cell products, the touch line (TP line) needs to share the limited pixel layout space with the display data line (data line). To take into account the panel aperture ratio, the existing technology usually adopts the design of overlapping the touch line TP and the data line data, such as Figure 1 In the display panel manufacturing process, the alignment accuracy of the TP line and the data line is limited by the shift margin of the photolithography process. In actual products, the overlap area between the two may fluctuate due to alignment shift, as shown in Figure 2. Figure 2 As shown, the touch line TP is offset to the left relative to the data line data. Figure 3 As shown in the figure, the touch trace TP is offset to the right relative to the data line data. Shift margin refers to the maximum tolerance for alignment shift between pattern layers during the manufacturing process. This refers to the acceptable positional offset between patterns on different layers (e.g., the TP line layer and the data line layer) during photolithography and etching processes.

[0054] Fluctuations in the overlap area between the TP lines and the data lines directly alter the coupling capacitance between them, causing the RC load in the touch signal path to become non-uniform. This RC load fluctuation reduces the consistency of touch signal response, manifesting as regional differences in touch sensitivity and coordinate drift.

[0055] To this end, the present application provides a display panel to reduce RC load fluctuations caused by alignment deviations between touch lines and data lines.

[0056] Please refer to Figures 4 to 8 , Figure 4 A schematic diagram of a planar structure of a display panel provided in an embodiment of the present application is shown. Figure 5 for Figure 4 Detailed planar structure diagram of a sub-pixel in the image. Figure 6 for Figure 5 Detailed structural diagram at M in the middle, Figure 7 for Figure 5 Detailed structural diagram at N in the figure, Figure 8 This is a schematic diagram of a partial film layer structure of a display panel 100 provided in an embodiment of the present application. The display panel 100 includes a touch trace TP and a data line Data. The touch trace TP includes a first trace portion 11 and a second trace portion 12 arranged along a first direction Y. The data line Data includes a first data line portion 21 and a second data line portion 22 arranged along the first direction Y. The first data line portion 21 and the second data line portion 22 each have one side and the other side arranged opposite each other along a second direction X, where the second direction X intersects the first direction Y.

[0057] Among them, the first routing portion 11 and the first data line portion 21 have a first overlapping portion, and the second routing portion 12 and the second data line portion 22 have a second overlapping portion, and the area of the first overlapping portion is complementary to the area of the second overlapping portion. For example, the first routing portion 11 overlaps with the one side of the first data line portion 21 and is spaced from the other side of the first data line portion 21; the second routing portion 12 overlaps with the other side of the second data line portion 22 and is spaced from the one side of the second data line portion 22.

[0058] This allows the first trace portion 11 and the second trace portion 12 to form an asymmetric, complementary overlapping structure with the first data line portion 21 and the second data line portion 22, respectively. The overlap between the first trace portion 11 and the first data line portion 21 and the overlap between the second trace portion 12 and the second data line portion 22 complement each other. This allows, when the touch trace TP undergoes alignment shift, the changes in the overlapping areas between the first trace portion 11 and the second trace portion 12 and the corresponding first data line portion 21 and the second data line portion 22 to be inversely offset. In other words, when the touch trace TP undergoes alignment shift with the data line Data, the change in the overlapping area (ΔS1) between the first trace portion 11 and the first data line portion 21 and the change in the overlapping area (ΔS2) between the second trace portion 12 and the second data line portion 22 are inversely related. For example, if the touch trace TP shifts to the left, the overlapping area between the first trace portion 11 and the first data line portion 21 decreases (ΔS1 is negative), while the overlapping area between the second trace portion 12 and the second data line portion 22 increases (ΔS2 is positive). Because the two trace portions of the touch trace TP overlap with the corresponding data line portions in opposite directions, the total overlapping area change ΔS_total = ΔS + ΔS ≈ 0, thereby achieving self-compensation for the overlapping area.

[0059] More specifically, when the touch trace TP shifts to the left relative to the data line Data, the area of the first overlapping portion between the first trace portion 11 and the first data line portion 21 decreases, while the area of the second overlapping portion between the second trace portion 12 and the second data line portion 22 increases. The decrease in the area of the first overlapping portion is equal to the increase in the area of the second overlapping portion, so that the area of the first overlapping portion and the area of the second overlapping portion are complementary, thereby achieving self-compensation of the total overlapping area; when the touch trace TP shifts to the right relative to the data line Data, the area of the first overlapping portion between the first trace portion 11 and the first data line portion 21 increases, while the area of the second overlapping portion between the second trace portion 12 and the second data line portion 22 decreases. The increase in the area of the first overlapping portion is equal to the decrease in the area of the second overlapping portion, so that the area of the first overlapping portion and the area of the second overlapping portion are complementary, thereby achieving self-compensation of the total overlapping area. In this way, the overlapping area of the touch trace TP and the data line Data remains almost unchanged before and after the touch trace TP is offset relative to the data line Data, thereby reducing the RC load fluctuation caused by the offset between the touch trace TP and the data line Data, thereby improving the technical problem of large RC load fluctuation caused by the offset between the touch trace TP and the data line Data in existing panels.

[0060] Specifically, refer to Figure 4The display panel 100 includes data lines Data arranged at intervals along the second direction X, and scan lines Gate arranged at intervals along the first direction Y. A plurality of the scan lines Gate and the plurality of data lines Data are insulated and intersected to define a plurality of sub-pixels. That is, the plurality of scan lines Gate and the plurality of data lines Data are insulated and intersected to define a plurality of pixel regions, each of which is provided with a sub-pixel.

[0061] Reference Figure 5 The touch trace TP includes a first trace portion 11, a second trace portion 12, and a first connection portion 13 connecting the first trace portion 11 and the second trace portion 12. The length of the first trace portion 11 is equal to the length of the second trace portion 12, and the first connection portion 13 has an asymmetric structure, resulting in an asymmetric arrangement of the first trace portion 11 and the second trace portion 12. The data line Data includes a first data line portion 21, a second data line portion 22, and a second connection portion 23 connecting the first data line portion 21 and the second data line portion 22. The length of the first data line portion 21 is equal to the length of the second data line portion 22, and the shape of the second connection portion 23 is different from that of the first connection portion 13. The second connection portion 23 has a symmetrical structure, such that the first data line portion 21 and the second data line portion 22 are axially symmetrical about the centerline of the second connection portion 23. The second connection portion 23 itself is also axially symmetrical about its centerline. The first connection portion 13 is asymmetric, resulting in different shapes of the first connection portion 13 and the second connection portion 23.

[0062] The shapes of two adjacent first connection parts 13 are different, and the shapes of two adjacent second connection parts 23 are also different. For example, two adjacent first connection parts 13 are the first type first connection part 13 and the second type first connection part 13, and two adjacent second connection parts 23 are the first type second connection part 23 and the second type second connection part 23. The first type first connection part 13 is arranged corresponding to the first type second connection part 23, and the second type first connection part 13 is arranged corresponding to the second type second connection part 23. The first type second connection part 23 is located between the two adjacent sub-pixels, and the second type second connection part 23 is located at the intersection of the data line Data and the scan line Gate.

[0063] Reference Figure 5 and Figure 6The first data line portion 21 has one side and another side that are oppositely arranged along the second direction X. The first routing portion 11 overlaps with the one side of the first data line portion 21 and is spaced apart from the other side of the first data line portion 21. The one side and the other side of the first data line portion 21 refer to two opposite sides of the first data line portion 21, that is, two boundaries of the first data line portion 21 in the second direction X. The first routing portion 11 overlaps with the one side of the first data line portion 21 and is spaced apart from the other side of the first data line portion 21. This can reduce the overlapping area between the first routing portion 11 and the first data line portion 21, thereby reducing the coupling capacitance between the first routing portion 11 and the first data line portion 21, and thereby reducing the RC load on the touch trace TP.

[0064] Reference Figure 5 and Figure 7 The second data line portion 22 has one side and another side that are oppositely disposed along the second direction X. The second routing portion 12 overlaps with the other side of the second data line portion 22 and is spaced apart from the one side of the second data line portion 22. The one side and the other side of the second data line portion 22 refer to two opposing sides of the second data line portion 22, i.e., two boundaries of the second data line portion 22 in the second direction X. The second routing portion 12 overlaps with the other side of the second data line portion 22 and is spaced apart from the one side of the second data line portion 22. This can reduce the overlapping area between the second routing portion 12 and the second data line portion 22, thereby reducing the coupling capacitance between the second routing portion 12 and the second data line portion 22, and further reducing the RC load on the touch trace TP.

[0065] Moreover, by making the second wiring portion 12 overlap with the other side of the second data line portion 22 and spaced from the one side of the second data line portion 22, and the second wiring portion 12 overlaps with the other side of the second data line portion 22 and spaced from the one side of the second data line portion 22, the first wiring portion 11 and the second wiring portion 12 can form an asymmetric complementary overlapping structure with the first data line portion 21 and the second data line portion 22 respectively, and the overlapping amount of the first wiring portion 11 and the first data line portion 21 is equal to that of the second wiring portion 11. 2 and the second data line portion 22 complement each other, so that when the touch trace TP is misaligned, the changes in the overlapping areas between the first trace portion 11 and the second trace portion 12 and the corresponding first data line portion 21 and the second data line portion 22 are inversely offset, thereby achieving self-compensation of the total overlapping area. In this way, the overlapping area between the touch trace TP and the data line Data remains almost unchanged before and after the touch trace TP is misaligned relative to the data line Data, thereby reducing the RC load fluctuation caused by the misalignment between the touch trace TP and the data line Data.

[0066] In some embodiments, in conjunction with reference Figure 6 and Figure 7 In the second direction X, the width of the first trace portion 11 extending beyond the first data line portion 21 is equal to the width of the second trace portion 12 extending beyond the second data line portion 22. Optionally, the width of the first trace portion 11 extending beyond the first data line portion 21 is equal to the overlapping width of the first trace portion 11 and the first data line portion 21; and the width of the second trace portion 12 extending beyond the second data line portion 22 is equal to the overlapping width of the second trace portion 12 and the second data line portion 22. By controlling the width of the overlapping portion, the overlapping area between the touch trace TP and the data line Data remains stable, thereby reducing coupling capacitance fluctuations caused by alignment offset. This can suppress RC load fluctuations caused by alignment offset between the touch trace TP and the data line Data without sacrificing the panel aperture ratio, thereby maintaining stable touch signal transmission.

[0067] like Figure 6As shown, the sum of the width L1 of the first routing portion 11 exceeding the first data line portion 21 and the overlapping width L2 between the first routing portion 11 and the first data line portion 21 is equal to the width D1 of the first routing portion 11, the spacing distance L3 between the first routing portion 11 and the other side 212 of the first data line portion 21 is greater than the overlapping width L2 between the first routing portion 11 and the first data line portion 21, and the sum of the spacing distance L3 between the first routing portion 11 and the other side 212 of the first data line portion 21 and the overlapping width L2 between the first routing portion 11 and the first data line portion 21 is equal to the width D2 of the first data line portion 21, so that the width D2 of the first data line portion 21 is greater than the width D1 of the first routing portion 11.

[0068] like Figure 7 As shown, the sum of the width L3 of the second routing portion 12 exceeding the second data line portion 22 and the overlapping width L4 between the second routing portion 12 and the second data line portion 22 is equal to the width D1 of the second routing portion 12, the spacing distance L5 between the second routing portion 12 and the one side 221 of the second data line portion 22 is greater than the overlapping width L4 between the second routing portion 12 and the second data line portion 22, and the sum of the spacing distance L5 between the second routing portion 12 and the one side 221 of the second data line portion 22 and the overlapping width L4 between the second routing portion 12 and the second data line portion 22 is equal to the width D2 of the second data line portion 22, so that the width D2 of the second data line portion 22 is greater than the width D1 of the second routing portion 12.

[0069] In some embodiments, the overlapping area of the first routing portion 11 and the first data line portion 21 is a first area, the overlapping area of the second routing portion 12 and the second data line portion 22 is a second area, and the sum of the first area and the second area is 1 / 3 to 2 / 3 of the sum of the areas of the first routing portion 11 and the second routing portion 12. For example, the sum of the first area and the second area is 1 / 2 of the sum of the areas of the first routing portion 11 and the second routing portion 12.

[0070] In some embodiments, in conjunction with reference Figure 5 and Figure 8, each of the sub-pixels includes a transistor TFT and a pixel electrode 61 connected to the transistor TFT. Specifically, the display panel 100 also includes a first substrate 40, a plurality of conductive layers arranged on the first substrate 40, and an insulating layer located between the conductive layers. Specifically, the first conductive layer 30 is arranged on one side of the first substrate 40, and the first conductive layer 30 is formed with the scan line Gate. The second conductive layer 20 is arranged on the side of the first conductive layer 30 away from the first substrate 40, and the second conductive layer 20 is formed with the data line Data and the drain of the transistor TFT. The third conductive layer 10 is arranged on the side of the second conductive layer 20 away from the first substrate 40, and the third conductive layer 10 is formed with the touch line TP. The first transparent conductive layer 50 is arranged on the side of the third conductive layer 10 away from the first substrate 40, and the first transparent conductive layer 50 is formed with a common electrode 51 and a touch electrode Sensor, and the touch electrode Sensor is connected to the touch line TP. The second transparent conductive layer 60 is disposed on a side of the first transparent conductive layer 50 away from the first substrate 40 . The pixel electrode 61 is formed on the second transparent conductive layer 60 . The pixel electrode 61 is connected to the drain electrode Dr. Of course, the display panel 100 further includes an active layer As of a transistor TFT.

[0071] The display panel 100 also includes a second substrate 70 disposed opposite the first substrate 40. A light shielding layer 71 and a color filter layer 72 are disposed on the side of the second substrate 70 facing the first substrate 40. The color filter layer 72 is located within the openings of the light shielding layer 71. The color filter layer 72 corresponds to the pixel openings, for example, corresponding to the pixel electrodes 61, and the light shielding layer 71 corresponds to the transistors TFT. Optionally, the display panel 100 also includes a planar layer 73 located on the side of the color filter layer 72 facing the first substrate 40, and support pillars 80 located on the side of the planar layer 73 facing the first substrate 40. Of course, the display panel 100 also includes a liquid crystal layer, etc., located between the planar layer 73 and the pixel electrodes 61.

[0072] In some embodiments, reference Figure 9 , Figure 9 This is a schematic diagram comparing RC load fluctuations provided in an embodiment of the present application. Figure 9 The horizontal axis represents the offset of the touch line TP relative to the data line Data, in microns, and the vertical axis represents the fluctuation of the RC load, in microseconds. Figure 9 The middle curve A is Figure 5 The RC load fluctuation corresponding to the arrangement of the touch line TP and the data line Data changes with the change trend of the touch line TP offset. Curve B is Figure 1The RC load fluctuation corresponding to the arrangement of the touch line TP and the data line Data changes with the trend of the touch line TP offset. Comparing curve A and curve B, it can be seen that the fluctuation trend of curve A is smaller than that of curve B. Therefore, compared with Figure 1 The layout of the touch line TP and data line Data in the example, Figure 5 The exemplary arrangement of the touch trace TP and the data line Data can significantly reduce the fluctuation of the RC load. The fluctuation of the RC load refers to the difference between the RC load after the touch trace TP is offset relative to the data line Data and the RC load before the touch trace TP is offset relative to the data line Data.

[0073] For example, taking the shift margin of the touch trace TP as ±1.5um, Figure 1 The touch line TP and the data line Data are completely overlapped in the design. The overlap width of the touch line TP and the data line Data is 3um. The RC load on the touch line TP is 0.545us. When the touch line TP deviates by ±1.5um, the maximum fluctuation value of the RC load on the touch line TP is 0.059us. Figure 5 The touch trace TP and the data line Data are partially overlapped in the design. The overlapping width of the touch trace TP and the data line Data is 1.5um. The RC load on the touch trace TP is 0.513us. When the touch trace TP shifts by ±1.5um, the maximum fluctuation value of the RC load on the touch trace TP is 0.005us.

[0074] The calculation of RC load size can refer to Table 1 and Table 2, where Table 1 is Figure 1 Table 2 shows the size of the RC load corresponding to the arrangement of the touch line TP and the data line Data. Figure 5 The size of the RC load corresponding to the arrangement of the touch traces TP and the data lines Data in the example.

[0075] TP shift-1.5um TP shift-1um TP shift-0.5um TP shift 0um TP shift 0.5um TP shift 1um TP shift 1.5um Aperture ratio 58％ 58％ 58％ 58％ 58％ 58％ 58％ Capacitance unit (pF) (pF) (pF) (pF) (pF) (pF) (pF) C1 11.409 11.558 11.788 11.841 11.743 11.454 11.238 C2 24.071 24.607 24.667 24.663 24.548 24.384 23.765 C3 5.133 3.876 2.507 2.184 2.413 3.681 4.775 C4 93.007 103.371 109.431 113.042 109.466 103.308 92.979 C5 0.162 0.162 0.162 0.162 0.162 0.162 0.162 C6 0.145 0.145 0.145 0.145 0.145 0.145 0.145 C7 26.545 30.990 29.388 29.006 29.577 31.399 27.101 C8 26.545 30.990 29.388 29.006 29.577 31.399 27.101 C9 30.465 30.524 30.831 30.970 30.858 30.604 30.535 C10 1.172 1.172 1.172 1.172 1.172 1.172 1.172 Ct 188.496 207.178 208.956 211.527 209.110 207.412 188.745 resistance unit (kΩ) (kΩ) (kΩ) (kΩ) (kΩ) (kΩ) (kΩ) R1 4.114 4.114 4.114 4.114 4.114 4.114 4.114 R2 0.120 0.120 0.120 0.120 0.120 0.120 0.120 R3 0.400 0.400 0.400 0.400 0.400 0.400 0.400 R4 3.434 3.434 3.434 3.434 3.434 3.434 3.434 R5 4.094 4.094 4.094 4.094 4.094 4.094 4.094 Rt 2.577 2.577 2.577 2.577 2.577 2.577 2.577 RC 0.486 0.534 0.539 0.545 0.539 0.535 0.486

[0076] Table 1

[0077]

[0078]

[0079] Table 2

[0080] Among them, in Table 1 and Table 2, C1 refers to the capacitance of the touch electrode Sensor to the scan line Gate, C2 refers to the capacitance of the touch electrode Sensor to the data line Data, C3 refers to the capacitance of the touch trace TP to the scan line Gate, C4 refers to the capacitance of the touch trace TP to the data line Data, C5 refers to the capacitance between the upper and lower touch electrode Sensors, C6 refers to the capacitance between the left and right touch electrode Sensors, C7 refers to the capacitance between the touch electrode Sensor and the touch trace TP of other touch electrode Sensors, C8 refers to the capacitance between the touch trace TP and other touch electrode Sensors, and C9 refers to the capacitance between the data line Data in the touch electrode Sensor and the touch trace TP of other touch electrode Sensors. The capacitance of the scan line Gate, C10 refers to the capacitance of the touch trace TP in the fan-out area, Ct is the total capacitance, Ct = C1 + C2 + C3 + C4 + 2*(C5 + C6) + C7 + C8; R1 refers to the resistance of a touch trace TP corresponding to the touch electrode Sensor in the display area, R2 refers to the impedance of the connection point between the touch electrode Sensor and the touch trace TP, R3 refers to the impedance of the touch trace TP in the fan-out area, R4 refers to the impedance of a data line Data, R5 refers to the impedance of a scan line Gate, Rt is the total resistance of the touch trace TP, Rt = (R1 / m) + R2 + R3, m is the number of touch traces TP corresponding to a touch electrode Sensor.

[0081] In some embodiments, reference Figure 10 , Figure 10 This is another schematic diagram of the planar structure of the sub-pixel provided in the embodiment of the present application. Figure 5 The difference between the exemplary sub-pixel arrangement and the embodiment is that, in this embodiment, the vertical orthographic projection of the second wiring portion 12 is located within the vertical orthographic projection of the first data line portion 21 , and the vertical orthographic projection of the first wiring portion 11 is located outside the vertical orthographic projection of the second data line portion 22 .

[0082] In some embodiments, reference Figure 11 , Figure 11 This is another schematic diagram of a planar structure of a sub-pixel provided in an embodiment of the present application. Figure 5 The difference between the exemplary sub-pixel arrangement and the embodiment is that, in this embodiment, the vertical orthographic projection of the first wiring portion 11 is located within the vertical orthographic projection of the first data line portion 21 , and the vertical orthographic projection of the second wiring portion 12 is located outside the vertical orthographic projection of the second data line portion 22 .

[0083] According to the above embodiments, it can be seen that:

[0084] The present application provides a display panel data line, wherein a first data line portion and a second data line portion each have one side and another side arranged opposite to each other along a second direction, wherein the first line portion of the touch line overlaps with one side of the first data line portion and is spaced from the other side of the first data line portion, and the second line portion of the touch line overlaps with the other side of the second data line portion and is spaced from one side of the second data line portion, so that the first line portion and the second line portion respectively form an asymmetric complementary overlapping structure with the first data line portion and the second data line portion, and the overlap amount of the first line portion and the first data line portion is equal to the overlap amount of the second line portion and the second data line portion. The overlapping amounts of the data line portions are complementary, so that when the touch line is misaligned, the changes in the overlapping areas of the first and second line portions and the corresponding first and second data line portions are inversely offset, thereby achieving self-compensation of the total overlapping area. In this way, the overlapping area of the touch line and the data line remains almost unchanged before and after the touch line is misaligned relative to the data line, thereby reducing the RC load fluctuation caused by the misalignment of the touch line and the data line, thereby improving the technical problem of large RC load fluctuation caused by the misalignment of the touch line and the data line in existing panels.

[0085] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0086] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A touch wiring, comprising a first wiring portion and a second wiring portion arranged along a first direction; and a data line comprising a first data line portion and a second data line portion arranged along the first direction, wherein the first data line portion and the second data line portion each have one side and another side oppositely arranged along a second direction, wherein the second direction intersects the first direction; The first routing portion overlaps with the one side of the first data line portion and is spaced from the other side of the first data line portion; the second routing portion overlaps with the other side of the second data line portion and is spaced from the one side of the second data line portion.

2. The display panel according to claim 1, wherein: The touch wiring further includes a first connecting portion connecting the first wiring portion and the second wiring portion, and the data line further includes a second connecting portion connecting the first data line portion and the second data line portion, and a shape of the second connecting portion is different from a shape of the first connecting portion.

3. The display panel according to claim 2, wherein: The first data line portion and the second data line portion are axially symmetrical about a center line of the second connecting portion; the first routing portion and the second routing portion are asymmetrically arranged.

4. The display panel according to claim 1, wherein: In the second direction, the width of the first routing portion extending beyond the first data line portion is equal to the width of the second routing portion extending beyond the second data line portion.

5. The display panel according to claim 4, wherein: The width of the first routing portion extending beyond the first data line portion is equal to the overlapping width between the first routing portion and the first data line portion; the width of the second routing portion extending beyond the second data line portion is equal to the overlapping width between the second routing portion and the second data line portion.

6. The display panel according to claim 1, wherein: The overlapping area between the first routing portion and the first data line portion is a first area, the overlapping area between the second routing portion and the second data line portion is a second area, and the sum of the first area and the second area is 1 / 3 to 2 / 3 of the sum of the areas of the first routing portion and the second routing portion.

7. The display panel according to claim 6, wherein: The vertical orthographic projection of the first wiring portion is located within the vertical orthographic projection of the first data line portion, and the vertical orthographic projection of the second wiring portion is located outside the vertical orthographic projection of the second data line portion.

8. The display panel according to claim 1, wherein: The length of the first routing portion is equal to the length of the second routing portion.

9. The display panel according to any one of claims 2 to 8, characterized in that: Also includes: a plurality of scan lines arranged at intervals along the first direction, wherein the plurality of scan lines are insulated from and cross the plurality of data lines to define a plurality of sub-pixels, each of the sub-pixels comprising a transistor and a pixel electrode connected to the transistor; Two adjacent first connection parts are a first type first connection part and a second type first connection part, and two adjacent second connection parts are a first type second connection part and a second type second connection part. The first type first connection part is arranged corresponding to the first type second connection part, and the second type first connection part corresponds to the second type second connection part. The first type second connection part is located between two adjacent sub-pixels, and the second type second connection part is located at the intersection of the data line and the scan line.

10. The display panel according to claim 9, wherein: include: a first substrate; a first conductive layer, disposed on one side of the first substrate, wherein the scanning line is formed on the first conductive layer; a second conductive layer, disposed on a side of the first conductive layer away from the first substrate, the second conductive layer being formed with the data line and the drain of the transistor; a third conductive layer, disposed on a side of the second conductive layer away from the first substrate, the touch trace being formed on the third conductive layer; a first transparent conductive layer, disposed on a side of the third conductive layer away from the first substrate, wherein the first transparent conductive layer is formed with a common electrode and a touch electrode, and the touch electrode is connected to the touch trace; The second transparent conductive layer is provided on a side of the first transparent conductive layer away from the first substrate. The pixel electrode is formed on the second transparent conductive layer, and the pixel electrode is connected to the drain electrode.

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