Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device.The display panel comprises a plurality of sub-pixels, a plurality of scanning lines and a plurality of data lines, a pixel electrode of each sub-pixel comprises at least two connected domain parts, and in the same pixel electrode, the extending directions of every two adjacent domain parts intersect; the array substrate comprises a first substrate, a semiconductor layer, a first metal layer and a second metal layer. The scanning lines are located on the first metal layer, active parts of the thin film transistors are located on the semiconductor layer and first and second poles of the thin film transistors, and the data lines are located on the second metal layer; a first insulating layer is arranged between the first metal layer and the second metal layer, the first insulating layer at least comprises a hollow part, and the hollow part penetrates through the thickness of the first insulating layer; the hollow part is located between two adjacent domain parts along the extension direction of the data line. The display device comprises the display panel. The light transmittance can be improved, the power consumption can be reduced, the cost can be reduced, and the display quality can be ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Existing display panels mainly include liquid crystal display (LCD) panels and organic light emitting diode (OLED) panels. LCDs offer advantages such as high image quality, compact size, light weight, low driving voltage, low power consumption, zero radiation, and relatively low manufacturing costs. They are widely used in a variety of electronic devices, including tablets, televisions, mobile phones, and in-car displays.

[0003] Competition in the LCD panel industry is intensifying as display products evolve and users place higher demands on them, particularly in terms of low cost, high transmittance, and high contrast. Traditional LCD panels have a relatively small aperture ratio when designing pixel layouts, creating a technical bottleneck in improving light transmittance. Simply increasing backlight brightness by increasing the drive current or the number of backlight sources increases costs and power consumption.

[0004] Therefore, providing a display panel and a display device that can further improve light transmittance while reducing power consumption, reducing costs, and ensuring display quality is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem that low cost, low power consumption and high transmittance cannot be achieved at the same time in existing liquid crystal display products, resulting in insufficient product competitiveness and affected display quality.

[0006] The present disclosure provides a display panel comprising a plurality of sub-pixels, a plurality of scan lines, and a plurality of data lines, wherein the scan lines and the data lines are intersected and insulated to define an area where the sub-pixels are located; the sub-pixels comprise electrically connected thin-film transistors and pixel electrodes; the pixel electrodes comprise at least two connected domains, wherein the extension directions of two adjacent domains in the same pixel electrode intersect;

[0007] The display panel includes an array substrate and an opposing substrate, wherein the array substrate includes a first substrate and a semiconductor layer, a first metal layer, and a second metal layer located on a side of the first substrate facing the opposing substrate; the scan lines are located on the first metal layer, the active portions of the thin film transistors are located on the semiconductor layer, and the first and second electrodes and the data lines of the thin film transistors are located on the second metal layer;

[0008] A first insulating layer is included between the first metal layer and the second metal layer. The first insulating layer includes at least a hollow portion that penetrates the thickness of the first insulating layer. Along the extension direction of the data line, the hollow portion is located between two adjacent domain portions.

[0009] Based on the same inventive concept, the present disclosure also provides a display device, which includes the above-mentioned display panel.

[0010] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0011] The display panel provided by the present disclosure can be a liquid crystal display panel. In the film structure of the display panel, a first insulating layer is included between the first metal layer and the second metal layer. The insulating layer between the first metal layer and the second metal layer can be understood as the insulating layer between the film layer where the scan line is located and the film layer where the data line is located, that is, it can be understood as an interlayer insulating layer. The first insulating layer includes at least a hollow portion, the hollow portion extends through the thickness of the first insulating layer, and along the overall extension direction of the data line, the hollow portion is located between two adjacent domains of the pixel electrode. That is, the first insulating layer is hollowed out and etched only in a portion of the sub-pixel opening area, which can effectively improve the light transmittance of local areas of the display panel, especially areas with low transmittance, thereby improving the display quality and achieving high transmittance. In addition, the hollow portion of the first insulating layer of the present disclosure is only provided in a portion of the sub-pixel opening area, and the etching area of the first insulating layer is reduced, which can effectively avoid the problem of unclean etching in the process, which affects the display quality, and thus effectively ensure that the display quality is not affected by the provision of the hollow portion of the first insulating layer. Furthermore, the disclosed method of improving light transmittance does not require increasing the backlight driving current or increasing the number of backlight sources, and can effectively reduce panel driving power consumption, thereby saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 2 yes Figure 1 Schematic diagram of the locally enlarged structure of the middle J1 region;

[0016] Figure 3 yes Figure 2 A schematic diagram of a cross-sectional structure along the A-A' direction;

[0017] Figure 4 is a comparison diagram of the display effects of sub-pixels in a display panel provided by the prior art and the display effects of sub-pixels in a display panel provided by an embodiment of the present disclosure;

[0018] Figure 5 yes Figure 2 Another cross-sectional structure schematic diagram along the A-A' direction;

[0019] Figure 6 yes Figure 2 A schematic diagram of a cross-sectional structure along the B-B' direction;

[0020] Figure 7 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0021] Figure 8 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0022] Figure 9 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0023] Figure 10 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0024] Figure 11 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0025] Figure 12 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0026] Figure 13 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0027] Figure 14 yes Figure 13 A schematic structural diagram of a pixel electrode;

[0028] Figure 15 yes Figure 13 A schematic structural diagram of the first insulating layer;

[0029] Figure 16 yes Figure 13A diagram showing the relationship between the positions of the pixel electrode and the first insulating layer;

[0030] Figure 17 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0031] Figure 18 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0032] Figure 19 yes Figure 1 Another schematic diagram of the locally enlarged structure of the middle J1 region;

[0033] Figure 20 yes Figure 19 A schematic diagram of a cross-sectional structure in the C-C' direction;

[0034] Figure 21 yes Figure 19 A schematic structural diagram of the first insulating layer;

[0035] Figure 22 It is a schematic diagram of a planar structure of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0037] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0038] Please refer to Figure 1-Figure 3 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 2 yes Figure 1 Schematic diagram of the locally enlarged structure of the J1 area in the middle. Figure 3 yes Figure 2 A schematic cross-sectional structure diagram along the A-A' direction (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 2The display panel 000 provided in this embodiment includes a plurality of sub-pixels 00, a plurality of scan lines G, and a plurality of data lines S. The scan lines G and the data lines S are cross-insulated and define an area where the sub-pixel 00 is located. The sub-pixel 00 includes an electrically connected thin film transistor 00T and a pixel electrode 00P. The pixel electrode 00P includes at least two connected domains 00P1. In the same pixel electrode 00P, the extension directions of two adjacent domains 00P1 intersect.

[0039] The display panel 000 includes an array substrate 10 and an opposing substrate 20. The array substrate 10 includes a first substrate 101 and a semiconductor layer 102, a first metal layer 103, and a second metal layer 104 located on the side of the first substrate 101 facing the opposing substrate 20. The scan line G is located on the first metal layer 103. The active portion 00TP of the thin film transistor 00T is located on the semiconductor layer 102. The first electrode 00TS and the second electrode 00TD of the thin film transistor 00T, as well as the data line S, are located on the second metal layer 104.

[0040] A first insulating layer 001 is included between the first metal layer 103 and the second metal layer 104 . The first insulating layer 001 includes at least a hollow portion 001K. The hollow portion 001K penetrates the thickness of the first insulating layer 001 . Along the extension direction Y of the data line S, the hollow portion 001K is located between two adjacent domain portions 00P1 .

[0041] Specifically, the display panel 000 provided in this embodiment is a liquid crystal display panel, and the display panel 000 includes a plurality of sub-pixels 00, a plurality of scan lines G and a plurality of data lines S. Optionally, as shown in FIG. Figure 1As shown, the display panel 000 of this embodiment is described by taking as an example a display panel in which scan lines G extend entirely along a first direction X and data lines S extend entirely along a second direction Y, and the two are insulated from each other to define an area where a sub-pixel 00 is located. It should be understood that the fact that the scan lines G extend entirely along the first direction X and the data lines S extend entirely along the second direction Y does not mean that the scan lines G and the data lines S can only be straight lines. In a specific implementation, the scan lines G and the data lines S can be curved or bent. However, the scan lines G extend entirely in the first direction X, and the data lines S extend entirely in the second direction Y. The first direction X and the second direction Y are perpendicular to each other in a direction parallel to the plane of the first substrate 101. Subsequent embodiments refer to the above explanation, i.e., the example in which the scan lines G extend entirely in the first direction X and the data lines S extend entirely in the second direction Y is taken, and no further explanation is given. The sub-pixel 00 of the display panel 000 includes an electrically connected thin film transistor 00T and a pixel electrode 00P. The thin film transistor 00T is used as a switching element of the sub-pixel 00. The thin film transistor 00T of the sub-pixel 00 can be turned on or off under the control of a scanning signal provided by the scanning line G, thereby realizing the transmission of the data voltage provided by the data line S to the pixel electrode 00P when the thin film transistor 00T is turned on.

[0042] The film layer structure of the display panel 000 provided in this embodiment includes an array substrate 10 and an opposing substrate 20. Optionally, a liquid crystal layer 30 is provided between the array substrate 10 and the opposing substrate 20. The array substrate 10 can be a substrate on which structures such as thin film transistors 00T, pixel electrodes 00P, and common electrodes are provided, and the opposing substrate 20 can be a substrate on which color resist and black matrix layers are provided. In some other optional embodiments, the color resist and black matrix layers can also be provided on one side of the array substrate 10, and the opposing substrate 20 can be a glass cover structure. This embodiment does not limit the structure of the opposing substrate 20. During specific implementation, the configuration can be selected according to actual needs. This embodiment and subsequent embodiments are all described by taking the opposing substrate 20 as a substrate on which color resist and black matrix layers are provided as an example.

[0043] The array substrate 10 of this embodiment includes a first substrate 101 and a semiconductor layer 102, a first metal layer 103, and a second metal layer 104 located on the side of the first substrate 101 facing the opposing substrate 20, wherein the first substrate 101 can be used as a carrier substrate for setting other structures of the array substrate 10. The first substrate 101 can be made of a hard material such as glass or ceramic, which is not limited in this embodiment. The semiconductor layer 102 is used to set the active part 00TP of the thin film transistor 00T, and the first metal layer 103 can be located on the side of the semiconductor layer 102 away from the first substrate 101. The first metal layer 103 is used to set the scan line G and the gate 00TG of the thin film transistor 00T. Optionally, the scan line G in at least a part of the area can be reused as the gate 00TG of the thin film transistor 00T (such as Figure 2 or in some other optional embodiments, the first metal layer 103 for making the scan line G and the gate electrode 00TG of the thin film transistor 00T may also be located on the side of the semiconductor layer 102 facing the first substrate 101. Figure 3 The first metal layer 103 is merely described as being located on a side of the semiconductor layer 102 away from the first substrate 101. The second metal layer 104 is located on a side of the first metal layer 103 away from the first substrate 101. The second metal layer 104 is used to provide a first electrode 00TS and a second electrode 00TD of the thin-film transistor 00T, as well as a data line S. It is understood that the first electrode 00TS of the thin-film transistor 00T can be either the source or the drain of the thin-film transistor 00T, and the second electrode 00TD can be either the source or the drain of the thin-film transistor 00T. This embodiment uses the first electrode 00TS as the source of the thin-film transistor 00T and the second electrode 00TD as the drain of the thin-film transistor 00T as an example. The active portion 00TP of the thin film transistor 00T (the source connection region of the active portion 00TP) is electrically connected to the first electrode 00TS of the thin film transistor 00T, and the first electrode 00TS of the thin film transistor 00T is electrically connected to the data line S; the active portion 00TP of the thin film transistor 00T (the drain connection region of the active portion 00TP) is electrically connected to the second electrode 00TD of the thin film transistor 00T, and the second electrode 00TD of the thin film transistor 00T is electrically connected to the pixel electrode 00P.

[0044] The film layer where the pixel electrode 00P of this embodiment is located can be located on the side of the second metal layer 104 away from the first substrate 101. Optionally, the array substrate 10 of the display panel 000 can further include a common electrode 00C, and the film layer where the common electrode 00C is located can be located between the pixel electrode 00P and the second metal layer 104 (e.g., Figure 3As shown), or in some other optional embodiments, the film layer where the common electrode 00C is located may also be located on the side of the pixel electrode 00P away from the first substrate 101, or the film layer where the common electrode 00C is located may be in the same layer as the pixel electrode. This embodiment is not limited here. This embodiment is only illustrated by taking the example that the film layer where the common electrode 00C is located between the pixel electrode 00P and the second metal layer 104.

[0045] When the display panel 000 of this embodiment is driven to display, the thin film transistor 00T of the sub-pixel 00 is turned on under the control of the scanning signal provided by the scanning line G, and the data voltage on the data line S is transmitted to the second electrode 00TD of the thin film transistor 00T through the first electrode 00TS of the thin film transistor 00T, thereby driving the pixel electrode 00P. The pixel electrode 00P is connected to the common electrode 00C (such as Figure 3 As shown, Figure 3 The electric field formed by the voltage difference between the sub-pixel 00 and the sub-pixel 00 (not filled) can control the deflection of the liquid crystal molecules in the liquid crystal layer 30 of each sub-pixel 00, thereby realizing the image display of the display panel 000. It should be noted that the display principle of the display panel 000 is not described in detail in this embodiment. For details, please refer to the driving and display principles of liquid crystal display panels in related technologies.

[0046] The pixel electrode 00P provided in this embodiment includes at least two connected domain portions 00P1. In the same pixel electrode 00P, the extension directions of the two adjacent domain portions 00P1 intersect, that is, the display panel 000 of this embodiment is a liquid crystal display panel with a dual-domain pixel structure. By providing the pixel electrode 00P including at least two connected domain portions 00P1, the extension directions of the two adjacent domain portions 00P1 of the same pixel electrode 00P intersect to form a certain angle, so that two domain areas can be formed in a sub-pixel 00 area. In different viewing angles, the viewing angles of the two domain areas where the two adjacent domain portions 00P1 of the same pixel electrode 00P are located can complement each other, thereby solving the viewing angle problem in the horizontal or vertical direction during display, improving the viewing angle of the display panel 000, and helping to improve the display quality.

[0047] It is understandable that the Figure 2 The shape of the middle pixel electrode 00P is only for illustration and can be designed according to actual needs during implementation, and this embodiment does not limit this. Figure 2 The layout shape of each sub-pixel 00 is only an example and does not represent the only layout structure in actual setting. During specific implementation, it can be set according to actual needs and the layout structure of the liquid crystal display panel in related technologies. This embodiment will not be described in detail here.

[0048] However, the applicant has found that when the existing liquid crystal display panel is designed as a dual-domain pixel structure, there will be a problem of low light transmittance in the local area of the sub-pixel, especially at the corner between two adjacent domains of the same pixel electrode, or at the two ends of the domain of the pixel electrode, the light transmittance (light penetration rate) is significantly reduced, thereby affecting the overall display effect of the liquid crystal display panel. In order to solve the problem of low panel transmittance, the existing technology generally increases the transmittance by increasing the number of backlight sources or increasing the backlight driving current; however, this method easily leads to excessive power consumption and increased costs. Another solution is to completely hollow out at least one insulating film layer in the film structure of the display panel (such as the interlayer insulating layer between the first metal layer where the scan line is located and the second metal layer where the data line is located) in the opening area corresponding to the sub-pixel to improve transmittance; however, in this method, since the hollowed-out etching area of the insulating layer is relatively large, etching products will be generated during the etching process, resulting in a decrease in etching rate. The periphery of the hollowed-out area is prone to problems such as incomplete etching and residual interlayer insulating layer material. The residual interlayer insulating layer material will cause a difference in electrode width between the peripheral area of the pixel electrode itself and the middle area of the pixel electrode itself after the subsequent pixel electrode process, resulting in uneven gaps (cell gaps) between the liquid crystal layers and affecting display quality.

[0049] It should be noted that the area where the sub-pixel 00 in this embodiment and subsequent embodiments is located refers to the smallest display unit of the display panel, which is usually composed of three sub-pixels of red (R), green (G), and blue (B) to form a complete pixel unit, and the opening area refers to the area in the sub-pixel 00 that is actually transmissive or luminous, that is, the effective area through which light can pass. In the liquid crystal display panel, due to the arrangement of liquid crystal molecules and the layout of the driving circuit (such as thin film transistors), the area of the opening area of the sub-pixel is usually smaller than the total area of the sub-pixel.

[0050] In order to solve the above problems, the present embodiment sets a first insulating layer 001 between the first metal layer 103 and the second metal layer 104. Optionally, the insulating layer between the semiconductor layer 102 and the first metal layer 103 can be understood as a gate insulating layer, and the insulating layer between the first metal layer 103 and the second metal layer 104 can be understood as an interlayer insulating layer. The present embodiment does not elaborate on the materials of different insulating layers. During specific implementation, an insulating layer can be set between adjacent conductive layers according to the actual film layer structure. The first insulating layer 001 includes at least a hollow portion 001K. The hollow portion 001K runs through the thickness of the first insulating layer 001, and along the overall extension direction of the data line S, that is, the second direction Y, the hollow portion 001K is located between two adjacent domain portions 00P1, and passes between the two adjacent domain portions 00P1, such as Figure 1 and Figure 2In the area between two adjacent domain portions 00P1 included in the same pixel electrode 00P in the second direction Y shown, or in the area between two adjacent pixel electrodes 00P and two adjacent domain portions 00P1 in the second direction Y of other embodiments (not shown in the figure), the first insulating layer 001 is provided with a hollow portion 001K, that is, the first insulating layer 001 is hollowed out and etched only in part of the opening area of the sub-pixel 00, which can effectively improve the light transmittance of the local area of the display panel 000, especially the area where the original low transmittance exists, so as to improve the display quality and achieve the purpose of high transmittance. Furthermore, the hollow portion 001K of the first insulating layer 001 of this embodiment is only provided in a portion of the sub-pixel 00 opening region (the orthographic projection of the hollow portion 001K of the first insulating layer 001 on the first substrate 101 is located between two adjacent domain portions 00P1). This reduces the etching area of the first insulating layer 001, effectively preventing problems such as unclean etching during the manufacturing process that could affect display quality. This effectively ensures that display quality is not affected by the provision of the hollow portion 001K of the first insulating layer 001. Furthermore, the method of improving light transmittance in this embodiment does not require increasing the backlight drive current or increasing the number of backlight sources, effectively reducing panel drive power consumption and contributing to cost savings.

[0051] As shown in Table 1 below, Table 1 is a comparison table of optical simulation data of an existing implementation scheme and an embodiment of the present disclosure, which compares the optical simulation data of the transmittance of the prior art in which the first insulating layer does not have a hollowed-out area, and the optical simulation data after the first insulating layer used in the present embodiment hollows out only part of the area with lower transmittance in the opening area of the sub-pixel to improve the transmittance, that is, in the embodiment of the present disclosure, the hollow portion 001K is opened between two adjacent domain portions 00P1 along the overall extension direction of the data line S (the second direction Y), such as the optical simulation data after the hollow portion 001K opened in the first insulating layer 001 is located between the two adjacent domain portions 00P1 included in the same pixel electrode 00P when the orthographic projection of the hollow portion 001K on the first substrate 101 is located. The above two are compared.

[0052] Table 1:

[0053] Existing technology Embodiments of the present disclosure Comparison differences Y 79.0 80 1.3% increase x 0.4606 0.4610 Improved by 0.0004 y 0.4129 0.4129 No change

[0054] As shown in Table 2 below, Table 2 is a comparison table of optical simulation data of an existing implementation scheme and another embodiment of the present disclosure, which compares the optical simulation data of the transmittance of the prior art first insulating layer without a hollowed-out area, and the optical simulation data after the first insulating layer used in the present embodiment hollows out only part of the area with lower transmittance in the opening area of the sub-pixel to improve the transmittance, that is, in the embodiment of the present disclosure, the hollow portion 001K is opened between two adjacent domain portions 00P1 along the overall extension direction of the data line S (the second direction Y), such as the optical simulation data after the hollow portion 001K opened in the first insulating layer 001 is located between the two adjacent domain portions 00P1 included in the same pixel electrode 00P when the orthographic projection of the hollow portion 001K on the first substrate 101 is located. The above two are compared.

[0055] Table 2:

[0056] Existing technology Embodiments of the present disclosure Comparison differences Y 79.0 80.7 2.15% increase x 0.4606 0.4612 Improved by 0.0006 y 0.4129 0.4129 No change

[0057] The optical simulation data of the transmittance of the prior art first insulating layer without a hollowed-out area in Table 1 and Table 2 are consistent. The difference is that in Table 1, the embodiment of the present disclosure corresponds to that along the second direction Y, the orthographic projection of the hollow portion 001K opened in the first insulating layer 001 on the first substrate 101 is located between the two adjacent domain portions 00P1 included in the same pixel electrode 00P, assuming that Table 1 simulates that the width of the hollow portion 001K in the second direction Y is W1; the embodiment of the present disclosure corresponds to that along the second direction Y, the orthographic projection of the hollow portion 001K opened in the first insulating layer 001 on the first substrate 101 is located between the two adjacent domain portions 00P1 included in the same pixel electrode 00P, assuming that Table 2 simulates that the width of the hollow portion 001K in the second direction Y is W2, and W1 is smaller than W2. For example, in Table 1, the width W1 of the hollow portion 001K in the second direction Y is 15 μm, and in Table 2, the width W2 of the hollow portion 001K in the second direction Y is 25 μm.

[0058] In Table 1, Y represents brightness, x refers to Wx, and y refers to Wy, representing white point chromaticity. Optical simulation results show a relatively small change in chromaticity, with a difference of only 0.0004. Furthermore, the partial hollowing of the first insulating layer 001 improves light transmittance by 1.3% compared to leaving the first insulating layer 001 partially hollowed out in the sub-pixel opening area. The data in Table 1 demonstrates that the partial hollowing of the first insulating layer 001 in this embodiment significantly improves transmittance.

[0059] In Table 2, Y represents brightness, x refers to Wx, and y refers to Wy, representing white point chromaticity. Optical simulation results show a relatively small change in chromaticity, with a difference of only 0.0006. Furthermore, the partial hollowing of the first insulating layer 001 improves light transmittance by 2.15% compared to leaving the first insulating layer in the sub-pixel opening region intact. The data in Table 1 also demonstrates that the partial hollowing of the first insulating layer 001 in this embodiment significantly improves transmittance.

[0060] The optical simulation data in Tables 1 and 2 above illustrate that the first insulating layer 001 of this embodiment is only partially hollowed out, compared to the prior art solution in which the first insulating layer is not hollowed out in the sub-pixel opening area, which can effectively improve the transmittance with basically no difference in chromaticity.

[0061] Furthermore, the first insulating layer 001 of this embodiment is only partially hollowed out, which can greatly reduce the risk of incomplete etching around the first insulating layer when the etching area is large, thereby greatly improving the display quality and ensuring the display quality.

[0062] As shown in Table 3 below, Table 3 is a comparison table of optical simulation data of another existing implementation scheme and the embodiment of the present disclosure, which compares the optical simulation data after the first insulating layer used in the prior art is completely hollowed out in the corresponding area of the sub-pixel opening area to improve the transmittance, and the optical simulation data after the hollow portion 001K is opened between two adjacent domain portions 00P1 along the overall extension direction of the data line S, that is, the second direction Y, used in this embodiment to improve the transmittance, such as the orthographic projection of the hollow portion 001K opened in the first insulating layer 001 on the first substrate 101 is located between two adjacent domain portions 00P1 included in the same pixel electrode 00P.

[0063] Table 3:

[0064] Existing technology Embodiments of the present disclosure Comparison differences Y 85.4 79.0 down 8.1% x 0.4629 0.4606 Down 0.002 y 0.4146 0.4129 Down 0.002

[0065] In Table 3, Y represents brightness, x refers to Wx, and y refers to Wy, which represents the white point chromaticity. From the optical simulation results, the chromaticity change is relatively small, with a difference of only 0.002. Compared with the first insulating layer 001 being completely hollowed out in the sub-pixel opening area, the light transmittance is only reduced by 8.1% when the first insulating layer 001 is only partially hollowed out. Therefore, compared with the first insulating layer 001 not having a hollowed-out area, the first insulating layer 001 of this embodiment being only partially hollowed out can significantly improve the transmittance (data comparison results in Table 1 and data comparison results in Table 2), and compared with the first insulating layer used in the prior art being completely hollowed out in the sub-pixel opening area, the decrease in transmittance is also smaller (data comparison results in Table 3).

[0066] The optical simulation data in Tables 1, 2, and 3 above can be combined to illustrate that the first insulating layer 001 of this embodiment is only partially hollowed out, which can greatly reduce the risk of unclean etching around the first insulating layer when the etching area is large, thereby greatly improving the display quality and ensuring the display quality. That is, compared with the solution of completely hollowing out the first insulating layer in the sub-pixel opening area adopted in the prior art, although the transmittance improvement has a small decrease (only a decrease of about 8%), compared with the first insulating layer not having a hollowed-out area, the light transmittance can still be effectively improved (for example, the transmittance in Table 1 is increased by 1.3%, and the transmittance in Table 2 is increased by 2.1%). It can be seen from this that the first insulating layer 001 of this embodiment is only partially hollowed out, which can avoid the risk of unclean etching around the first insulating layer caused by an excessively large etching area. Therefore, the overall process effect and display effect will be better, thereby improving the display quality while ensuring the increase in transmittance.

[0067] like Figure 4 As shown, Figure 4 is a comparison diagram of the display effects of sub-pixels in a display panel provided by the prior art and the display effects of sub-pixels in a display panel provided by an embodiment of the present disclosure, Figure 4 In the left figure, the first insulating layer is not provided with a hollow portion, that is, when the liquid crystal display panel is designed as a dual-domain pixel structure, there will be a problem of low light transmittance in the local area of the sub-pixel, especially at the corner between two adjacent domains of the same pixel electrode, or at the two ends of the domain of the pixel electrode, the light transmittance (light penetration rate) is significantly reduced, thereby affecting the overall display effect of the liquid crystal display panel. Figure 4 The right figure shows the display effect of the embodiment provided by the present invention, in which the hollow portion of the first insulating layer is located between two adjacent domains of the same pixel electrode in the orthographic projection of the first substrate along the overall extension direction of the data line, and the first insulating layer is hollowed out only in the local area where the light transmittance is affected. Figure 4 It can be seen that the configuration provided by this embodiment can significantly improve the transmittance of sub-pixels in the display panel, and the uniformity of the transmittance within the sub-pixels is also effectively improved.

[0068] It should be noted that the structure of the display panel is only exemplarily shown in the figure of this embodiment. In specific implementation, the specific structure of the display panel includes but is not limited to this, and may also include other structures that can realize display functions or other functions such as touch functions. Optionally, Figure 5 As shown, Figure 5 yes Figure 2 Another cross-sectional structure diagram along the A-A' direction, Figure 5A light-shielding metal layer 105 may be included between the semiconductor layer 102 and the first substrate 101. The light-shielding metal layer 105 is used to set a light-shielding portion 1051. The light-shielding portion 1051 covers the overlapping area between the gate 00TG and the active portion 00TP of the thin film transistor 00T, namely the channel area, and is used to block light from the backlight module to prevent light from irradiating into the channel area of the thin film transistor 00T, thereby improving the conductive performance of the thin film transistor 00T, improving the display crosstalk phenomenon, and improving the display quality; a third metal layer 106 may be included between the second metal layer 104 and the film layer where the common electrode 00C is located. The third metal layer 106 may be provided with a connecting portion 1061. The connecting portion 1061 realizes the electrical connection between the second pole 00TD of the thin film transistor 00T and the pixel electrode 00P. Other film layers may also be included. This embodiment will not be described in detail here. For details, please refer to the structure of the liquid crystal display panel in the relevant technology for understanding.

[0069] Optional, such as Figure 6 As shown, Figure 6 yes Figure 2 A schematic cross-sectional structure diagram along the B-B' direction in the middle, the first insulating layer 001 of this embodiment is located between the first metal layer 103 and the second metal layer 104, along the overall extension direction of the data line S, that is, the second direction Y, the hollow portion 001K opened in the first insulating layer 001 is located between two adjacent domain portions 00P1, at this time, after the hollow portion 001K is opened in the first insulating layer 001, its hollow position can be used in the subsequent film production with a highly transparent organic planarization layer 002 ( Figure 6 The area where the hollow portion 001K is located is filled (not filled in the middle), thereby ensuring the flatness of subsequent film layer production and avoiding affecting the product yield.

[0070] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 In this embodiment, a hollow portion 001K is provided on the first insulating layer 001 between the first metal layer 103 and the second metal layer 104. The hollow portion 001K penetrates the thickness of the first insulating layer 001 and is located between two adjacent domain portions 00P1 along the overall extension direction of the data line S, i.e., the second direction Y. The hollow portion 001K includes a first hollow portion 001K1, which is located between two adjacent domain portions 00P1 of the same pixel electrode 00P. Generally, when the display panel 000 is designed as a liquid crystal display panel with a dual-domain pixel structure, the shape of the pixel electrode 00P can be as follows: Figure 2 As shown, or the shape of the pixel electrode 00P can also be as follows Figure 7 As shown, Figure 7 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 7 (Transparency filling is performed). Since there is a corner at the intersection of the two domains 00P1 of the same pixel electrode 00P, the electric field direction is prone to sudden changes. If the liquid crystal molecules in the liquid crystal layer 30 at this location are squeezed and deflected by external force, it is difficult to return to the initial alignment state. In other words, the electric field between the pixel electrode 00P and the common electrode 00C at this location is relatively weak, which easily leads to transmittance loss. In other words, the intersection of the two domains 00P1 of the same pixel electrode 00P is prone to low transmittance. Therefore, in this embodiment, the hollow portion 001K includes a first hollow portion 001K1. The first hollow portion 001K1 is located between two adjacent domains 00P1 of the same pixel electrode 00P. This can effectively improve the light transmittance at the intersection of the two domains 00P1 of the same pixel electrode 00P, thereby improving the display quality.

[0071] Optional, such as Figure 1 、 Figure 2 and Figure 7 As shown, the first hollow portion 001K1 located between two adjacent domain portions 00P1 of the same pixel electrode 00P is an integral structure, so that the first insulating layer 001 between the two adjacent domain portions 00P1 of the same pixel electrode 00P can be hollowed out as much area as possible, which is conducive to better improving the transmittance.

[0072] Optional, such as Figure 1 and Figure 8 As shown, Figure 8 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 8 Transparency filling is performed), the first hollow portion 001K1 located between two adjacent domain portions 00P1 of the same pixel electrode 00P includes a plurality of independent first sub-hollow portions 001K11.

[0073] This embodiment explains that the first hollow portion 001K1 between two adjacent domain portions 00P1 of the same pixel electrode 00P can be set as a plurality of independently spaced small hollow areas in the shape of ellipses, triangles, rectangles, etc., that is, the first hollow portion 001K1 includes a plurality of independent first sub-hollow portions 001K11, which are arranged in parallel along the first direction X in the first insulating layer 001 between two adjacent domain portions 00P1 of the same pixel electrode 00P. The etching process of the first sub-hollow portions 001K11 with a small area is easy to implement, which can avoid the occurrence of defective etching residues and improve the process yield.

[0074] It is understandable that the Figure 8In the figure, the shape of the orthographic projection of the first sub-hollow portion 001K11 on the first substrate 101 is a rectangle. In specific implementation, the shape of the orthographic projection of the first sub-hollow portion 001K11 on the first substrate 101 includes but is not limited to this. It can also be other ellipses, triangles, etc. The shapes of multiple independent first sub-hollow portions 001K11 included in the same first hollow portion 001K1 can be the same or different, and this embodiment does not limit this.

[0075] In some optional embodiments, please refer to Figure 1 and Figure 9 、 Figure 10 、 Figure 11 , Figure 9 yes Figure 1 Another local enlarged structural diagram of the J1 area, Figure 10 yes Figure 1 Another local enlarged structural diagram of the J1 area, Figure 11 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figures 9-11 Transparency filling is performed), in this embodiment, a hollow portion 001K is provided in the first insulating layer 001 between the first metal layer 103 and the second metal layer 104. The hollow portion 001K penetrates the thickness of the first insulating layer 001 and is located between two adjacent domain portions 00P1 along the overall extension direction of the data line S, that is, the second direction Y. The hollow portion 001K includes a second hollow portion 001K2. The two domain portions 00P1 included in the pixel electrode 00P are a first domain portion 00P1A and a second domain portion 00P1B.

[0076] In the same sub-pixel 00, along the extension direction of the data line S, that is, along the second direction Y, the first domain portion 00P1A is located on a side of the second domain portion 00P1B close to the thin film transistor 00T;

[0077] The second hollow portion 001K2 is located at the first end 00PA of the pixel electrode 00P, where the first end 00PA is an end of the first domain portion 00P1A away from the second domain portion 00P1B; and / or,

[0078] The second hollow portion 001K2 is located at the second end 00PB of the pixel electrode 00P. The second end 00PB is an end of the second domain portion 00P1B away from the first domain portion 00P1A.

[0079] This embodiment explains that when the display panel 000 is generally designed as a liquid crystal display panel with a dual-domain pixel structure, the shape of the pixel electrode 00P can be as follows: Figure 2 or Figure 7As shown, there is a connection area between the longitudinal strip electrode and the transverse strip electrode at both ends of the same pixel electrode 00P in the second direction Y. The electric field direction in this area is prone to sudden change, that is, the electric field between the pixel electrode 00P and the common electrode 00C at this location is also relatively weak, which makes it easy for transmittance loss to occur, that is, the problem of low transmittance is easy to occur at both ends of the same pixel electrode 00P.

[0080] In this embodiment, in the second direction Y, the hollow portion 001K is located between two adjacent domain portions 00P1. The hollow portion 001K may include a second hollow portion 001K2. The two domain portions 00P1 included in the pixel electrode 00P are a first domain portion 00P1A and a second domain portion 00P1B. The first domain portion 00P1A in the sub-pixel 00 is closer to the thin film transistor 00T than the second domain portion 00P1B. The second hollow portion 001K2 may be located at the first end 00PA of the pixel electrode 00P. The first end 00PA refers to the end of the first domain portion 00P1A away from the second domain portion 00P1B (e.g., Figure 9 or the second hollow portion 001K2 may be located at the second end 00PB of the pixel electrode 00P, where the second end 00PB refers to an end of the second domain portion 00P1B away from the first domain portion 00P1A (as shown); Figure 10 or the second hollow portion 001K2 may be located at the first end 00PA of the pixel electrode 00P, or at the second end 00PB of the pixel electrode 00P (as shown); Figure 11 As shown), the problem of low transmittance at both ends of the same pixel electrode 00P in the second direction Y can be solved, which is beneficial to improving the transmittance.

[0081] Optional, please refer to Figure 1 and Figure 12 , Figure 12 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 12 In this embodiment, the hollow portion 001K provided in the first insulating layer 001 may only include the first hollow portion 001K1 (such as the hollow portion 001K1 located between two adjacent domain portions 00P1 of the same pixel electrode 00P) Figure 2 、 Figure 7 and Figure 8 As shown), the hollow portion 001K may only include a second hollow portion 001K2 located between two adjacent pixel electrodes 00P in the second direction Y (as shown Figure 9 、 Figure 10 and Figure 11Alternatively, the hollow portion 001K formed in the first insulating layer 001 may include a first hollow portion 001K1 located between two adjacent domain portions 00P1 of the same pixel electrode 00P, and a second hollow portion 001K2 located between two adjacent pixel electrodes 00P in the second direction Y (as shown). Figure 12 As shown), it is beneficial to further improve the transmittance while avoiding large-area hollowing of the entire surface of the first insulating layer 001 to affect the process technology.

[0082] It is understood that the second hollow portion 001K2 of this embodiment can be a unitary structure, and the shapes of the second hollow portion 001K2 and the first hollow portion 001K1 can be rectangular, elliptical, triangular, or other shapes, which are not limited in this embodiment. Alternatively, the second hollow portion 001K2 can include multiple independent sub-hollow portions, and the orthographic projections of the multiple independent sub-hollow portions included in the second hollow portion 001K2 on the first substrate 101 can be rectangular, elliptical, triangular, etc. The shapes of the multiple independent sub-hollow portions included in the same second hollow portion 001K2 can be the same or different, which are not limited in this embodiment.

[0083] In some optional embodiments, please refer to Figure 1 、 Figure 13-16 , Figure 13 yes Figure 1 Another local enlarged structural diagram of the J1 area, Figure 14 yes Figure 13 Schematic diagram of the structure of a pixel electrode, Figure 15 yes Figure 13 Schematic diagram of the structure of the first insulating layer, Figure 16 yes Figure 13 FIG. 1 shows the relationship between the positions of the pixel electrode and the first insulating layer (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 13 and Figure 16 Transparency filling is performed). In this embodiment, the pixel electrode 00P includes a plurality of strip electrodes 00P01 and a connecting electrode 00P02. The plurality of strip electrodes 00P01 are sequentially arranged along the extension direction of the scan line G (the first direction X). At least one end of the plurality of strip electrodes 00P01 is connected by the connecting electrode 00P02.

[0084] The orthographic projection of the second hollow portion 001K2 on the plane where the display panel 000 is located includes a serrated edge 001K2L, and the serrated edge 001K2L faces the area between the first domain portion 00P1A and the second domain portion 00P1B;

[0085] The jagged edge 001K2L includes a protruding portion 001K2L1 and a recessed area 001K2L2 that are arranged at intervals. The protruding portion 001K2L1 is located between two adjacent strip electrodes 00P01.

[0086] Optionally, the orthographic projection of the second hollow portion 001K2 on the plane where the display panel 000 is located covers the connecting electrode 00P02, and the orthographic projection of the second hollow portion 001K2 on the plane where the display panel 000 is located covers the connection between the strip electrode 00P01 and the connecting electrode 00P02.

[0087] This embodiment explains that in the display panel 000, i.e., the liquid crystal display panel, the shape of the pixel electrode 00P can be a plurality of strip electrodes 00P01 extending along the second direction Y as a whole, and a connecting electrode 00P02 extending along the first direction X as a whole, the plurality of strip electrodes 00P01 are arranged in sequence along the extension direction of the scan line G (the first direction X), at least one end of the plurality of strip electrodes 00P01 is connected through the connecting electrode 00P02, and the sub-pixel 00 including the pixel electrode 00P is a pixel structure of a dual-domain structure. Due to exposure and etching during the manufacturing process of the pixel electrode 00P, the strip electrode 00P01 at the top (the end of the strip electrode 00P01 at the second end 00PB of the pixel electrode 00P) and the bottom (the end of the strip electrode 00P01 at the first end 00PA of the pixel electrode 00P) will become slightly arc-shaped (such as Figure 14 As shown in the figure, the spacing between two adjacent strip electrodes 00P01 in the first direction X at the second end 00PB and the first end 00PA of the pixel electrode 00P is larger than the spacing at other positions. The electric field at the second end 00PB and the first end 00PA of the pixel electrode 00P is relatively weak, resulting in a black shadow with a jagged edge on one side due to low transmittance.

[0088] Therefore, in this embodiment, the shape of the second hollow portion 001K2 is designed as follows: Figure 15 and Figure 16As shown, the orthographic projection of the second hollow portion 001K2 on the plane where the display panel 000 is located includes a serrated edge 001K2L, the serrated edge 001K2L faces the area between the first domain portion 00P1A and the second domain portion 00P1B, and along the first direction X, the serrated edge 001K2L includes convex portions 001K2L1 and concave areas 001K2L2 that are spaced apart, one convex portion 001K2L1 is located between two adjacent strip electrodes 00P01, and the orthographic projection of the second hollow portion 001K2 on the plane where the display panel 000 is located is at least the entire The body covers the connecting electrode 00P02, and the orthographic projection of the second hollow portion 001K2 on the plane of the display panel 000 also covers the connection between the strip electrode 00P01 and the connecting electrode 00P02, which is conducive to following the low-transmittance shape at the second end 00PB and the first end 00PA of the pixel electrode 00P. The shape of the second hollow portion 001K2 is designed to improve the transmittance while avoiding too large an area of the second hollow portion 001K2 at the second end 00PB and the first end 00PA of the pixel electrode 00P, which increases the difficulty of the process.

[0089] In some optional embodiments, please continue to refer to Figure 1 and Figure 9 In this embodiment, the active portion 00TP of the thin film transistor 00T is electrically connected to the first electrode 00TS of the thin film transistor 00T through the first via hole K1, and the first electrode 00TS of the thin film transistor 00T is electrically connected to the data line S; the active portion 00TP of the thin film transistor 00T is electrically connected to the second electrode 00TD of the thin film transistor 00T through the second via hole K2, and the second electrode 00TD of the thin film transistor 00T is electrically connected to the pixel electrode 00P;

[0090] Along the extension direction of the data line S, that is, along the second direction Y, when the second hollow portion 001K2 is located at the first end 00PA of the pixel electrode 00P, the orthographic projection of the second hollow portion 001K2 on the plane where the display panel 000 is located does not overlap with the orthographic projection of the thin film transistor 00T on the plane where the display panel 000 is located;

[0091] In a direction parallel to the plane of the display panel 000 , a minimum distance D1 between the second hollow portion 001K2 and the first via hole K1 is greater than or equal to 2.5 μm, and a minimum distance D2 between the second hollow portion 001K2 and the second via hole K2 is greater than or equal to 2.5 μm.

[0092] This embodiment explains that the active portion 00TP of the thin film transistor 00T (the source connection region of the active portion 00TP) is electrically connected to the first electrode 00TS of the thin film transistor 00T through the first via hole K1, and the first electrode 00TS of the thin film transistor 00T is electrically connected to the data line S; the active portion 00TP of the thin film transistor 00T (the drain connection region of the active portion 00TP) is electrically connected to the second electrode 00TD of the thin film transistor 00T through the second via hole K2, and the second electrode 00TD of the thin film transistor 00T is electrically connected to the pixel electrode 00P, and a gate insulating layer is included between the semiconductor layer 102 and the first metal layer 103, and the first metal layer 103 is electrically connected to the pixel electrode 00P. The first insulating layer 001 between the layer 103 and the second metal layer 104 can be understood as an interlayer insulating layer. The active part 00TP of the thin film transistor 00T of the semiconductor layer 102 (the source connection area of the active part 00TP) is electrically connected to the first electrode 00TS of the thin film transistor 00T of the second metal layer 104 through the first via K1. The active part 00TP of the thin film transistor 00T of the semiconductor layer 102 (the drain connection area of the active part 00TP) is electrically connected to the second electrode 00TD of the thin film transistor 00T through the second via K2. The first via K1 and the second via K2 can be understood as vias set in the first insulating layer 001. When the second hollow portion 001K2 opened in the first insulating layer 001 is located at the first end 00PA of the pixel electrode 00P, the second hollow portion 001K2 is relatively close to the layout area of the thin film transistor 00T. At this time, the opening position of the second hollow portion 001K2 needs to avoid the thin film transistor 00T, and also needs to avoid the position of the first via K1 and the position of the second via K2. Optionally, in a direction parallel to the plane of the display panel 000, the minimum distance D1 between the second hollow portion 001K2 and the first via K1 needs to be greater than or equal to 2.5μm, and the minimum distance D2 between the second hollow portion 001K2 and the second via K2 needs to be greater than or equal to 2.5μm. This can avoid the second hollow portion 001K2 hollowed out of the first insulating layer 001 near the thin film transistor 00T from being too close to the thin film transistor 00T, such as being too close to the first pole 00TS and the second pole 00TD of the thin film transistor 00T, which affects the transmission performance of the thin film transistor 00T.

[0093] It can be understood that since the shapes of the orthographic projections of the second hollow portion 001K2, the first via K1, and the second via K2 on the plane where the display panel 000 is located may be regular or irregular, in this embodiment, in the direction parallel to the plane where the display panel 000 is located, the minimum distance D1 between the second hollow portion 001K2 and the first via K1 refers to the distance between a point where the second hollow portion 001K2 is closest to the first via K1 and a point where the first via K1 is closest to the second hollow portion 001K2; the minimum distance between the second hollow portion 001K2 and the second via K2 refers to the distance between a point where the second hollow portion 001K2 is closest to the second via K2 and a point where the second via K2 is closest to the second hollow portion 001K2.

[0094] In some optional embodiments, please refer to Figure 1 and Figure 17 , Figure 17 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 17 Transparency filling is performed), in this embodiment, the shape of the orthographic projection of the active portion 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped;

[0095] The display panel 000 includes a black matrix layer 20A ( Figure 1 (not shown), the black matrix layer 20A includes first light shielding strips 20A1, and the extension direction of the first light shielding strips 20A1 is the same as the extension direction of the scanning line G, that is, the overall extension direction of the first light shielding strips 20A1 of the black matrix layer 20A is the first direction X;

[0096] In the same sub-pixel 00, in the extending direction of the data line S, that is, in the second direction Y, the pixel electrode 00P includes a first end 00PA and a second end 00PB opposite to each other, and the distance between the first end 00PA and the thin-film transistor 00T is smaller than the distance between the second end 00PB and the thin-film transistor 00T; the first light-shielding strip 20A1 includes a first edge 20A1L proximate to the first end 00PA;

[0097] The hollow portion 001K includes a third hollow portion 001K3 ; along the extending direction of the data line S, ie, along the second direction Y, the third hollow portion 001K3 is located between the first end 00PA and the first edge 20A1L.

[0098] This embodiment illustrates a thin film transistor 00T fabricated on the array substrate 10 side of a display panel. This thin film transistor 00T may be one in which the orthographic projection of its active portion 00TP on the first substrate 101 is U-shaped. The orthographic projection of the active portion 00TP on the first substrate 101 overlaps with the orthographic projection of the scan line G on the first substrate 101 in two overlapping regions. That is, two portions of the scan line G in a sub-pixel 00 are reused as the two gate electrodes 00TG of the thin film transistor 00T. This thin film transistor 00T has advantages such as high input impedance, low power consumption under voltage control, a simple control circuit, high voltage resistance, and high current tolerance. Furthermore, the orthographic projection of the active portion 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped, which allows the entire structure of the thin film transistor 00T to be compressed to the maximum extent within the sub-pixel 00 region. This allows the first via K1, the channel region of the thin film transistor 00T, and the second via K2 to be more centrally located in a direction parallel to the plane of the display panel 000, thereby further improving the transmittance of the display panel 000.

[0099] The display panel 000 of this embodiment may further include a black matrix layer 20A. This embodiment is described by taking the black matrix layer 20A being located on the side of the opposing substrate 20 as an example. In some other optional embodiments, the black matrix layer 20A may also be located on the side of the array substrate 10. The black matrix layer 20A is used to form a grid-cross-shaped light-shielding strip, which is used to at least block the metal light leakage at the data line S, the scan line, and the G thin film transistor 00T to improve the display contrast. The black matrix layer 20A includes a first light-shielding strip 20A1. The overall extension direction of the first light-shielding strip 20A1 is the first direction X. The first light-shielding strip 20A1 can block the metal light leakage in the extension direction of the scan line G. Since the shape of the positive projection of the active part 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped, the layout space of the thin film transistor 00T is reduced. Therefore, in the second direction Y, the undivided area between the first end 00PA of the pixel electrode 00P and the scan line G is not occupied by the active part 00TP of the thin film transistor 00T (such as Figure 17 As shown in the J2 region, the first light shielding strip 20A1 in the J2 region can be hollowed out to form a groove to further improve the transmittance.

[0100] However, the applicant discovered that while the J2 region can hollow out the first light-shielding strip 20A1, the first end 00PA of the pixel electrode 00P cannot be continuously pulled down to the edge of the first light-shielding strip 20A1. This is because it is necessary to maintain a sufficient spacing between two adjacent pixel electrodes 00P in the second direction Y to prevent fluctuations in the upper and lower pixel electrodes during actual production, which could cause overlapping short circuits. Therefore, the pixel electrode 00P is not provided in the J2 region, resulting in a weaker electric field in this region than in other areas of the sub-pixel 00. This easily leads to low transmittance in the J2 region, affecting display quality.

[0101] Therefore, in this embodiment, the hollow portion 001K is provided to include a third hollow portion 001K3. Along the second direction Y, the third hollow portion 001K3 is located between the first end 00PA of the pixel electrode 00P and the first edge 20A1L of the first light-shielding strip 20A1, and the first edge 20A1L of the first light-shielding strip 20A1 is the edge of the first light-shielding strip 20A1 facing the first end 00PA, that is, the third hollow portion 001K3 opened in the first insulating layer 001 is opened in the J2 region. Optionally, the orthographic projection area of the third hollow portion 001K3 on the first substrate 101 can be slightly larger than the orthographic projection area of the J2 region on the first substrate 101, so that the third hollow portion 001K3 hollowed out by the first insulating layer 001 can effectively solve the problem of low transmittance in the J2 region, and improve the light transmittance after the orthographic projection shape of the active part 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped, thereby ensuring the display quality.

[0102] It can be understood that, in the hollow portion 001K opened in the first insulating layer 001 of the above embodiment, the hollow portion 001K may include only the first hollow portion 001K1, may include only the second hollow portion 001K2, may include only the third hollow portion 001K3, may include the first hollow portion 001K1 and the second hollow portion 001K2, may include the first hollow portion 001K1 and the third hollow portion 001K3, may include the second hollow portion 001K2 and the third hollow portion 001K3, or may include the first hollow portion 001K1, the second hollow portion 001K2 and the third hollow portion 001K3, that is, the hollow portion 001K may be any combination of the above, as long as it can meet the requirements of improving the transmittance while avoiding large-area etching of the first insulating layer 001 in the sub-pixel 00 area.

[0103] In some optional embodiments, please refer to Figure 1 and Figure 18 , Figure 18 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 18 Transparency filling is performed), in this embodiment, in this embodiment, the first insulating layer 001 further includes a hollow compensation portion 001KC, and the hollow compensation portion 001KC penetrates the thickness of the first insulating layer 001;

[0104] The pixel electrode 00P includes two domains 00P1, namely a first domain 00P1A and a second domain 00P1B. In the same sub-pixel 00, the first domain 00P1A is located on a side of the second domain 00P1B close to the thin film transistor 00T.

[0105] Along the extending direction of the data line S, ie, along the second direction Y, the length L1 of the first domain portion 00P1A is greater than the length L2 of the second domain portion 00P1B, and the hollow compensation portion 001KC is located in the area where the second domain portion 00P1B is located.

[0106] This embodiment explains the thin film transistor 00T manufactured on the side of the central array substrate 10 of the display panel. It can be a thin film transistor 00T whose active portion 00TP is in a U-shaped shape on the orthographic projection of the first substrate 101. The entire structure of the thin film transistor 00T can be compressed to the maximum extent in the sub-pixel 00 area, so that the first via K1, the channel region of the thin film transistor 00T, and the second via K2 are arranged in a relatively concentrated position in a direction parallel to the plane of the display panel 000, which is beneficial to further improve the transmittance of the display panel 000. After the layout area of the thin film transistor 00T is reduced, the distance between the first end 00PA of the pixel electrode 00P and the scanning line G becomes larger, and there is surplus space. Therefore, the length of the first domain portion 00P1A of the pixel electrode 00P in the second direction Y is generally lengthened, that is, in the same sub-pixel 00, along the second direction Y, the first domain portion 00P1A is located on the side of the second domain portion 00P1B close to the thin film transistor 00T, and the length L1 of the first domain portion 00P1A is greater than the length L2 of the second domain portion 00P1B, so as to make full use of the surplus space of the sub-pixel 00 after the layout area of the thin film transistor 00T is reduced to set the structure of the pixel electrode 00P, so as to ensure the effect of the electric field formed by the pixel electrode 00P and the common electrode in the sub-pixel to drive the liquid crystal. However, because the length L1 of the first domain 00P1A is greater than the length L2 of the second domain 00P1B, the driving electric field in the first domain 00P1A region is higher than the driving electric field in the second domain 00P1B region, which may cause horizontal stripes on the display. That is, one row is brighter and the other is darker, creating the visual effect of horizontal stripes. Therefore, this embodiment further provides a hollow compensation portion 001KC in the first insulating layer 001 located in the region where the second domain 00P1B is located. Specifically, the first insulating layer 001 is partially hollowed out in the region of the second domain 00P1B, which is the darker of the two domains 00P1. This helps improve transmittance while also balancing the brightness between the first domain 00P1A and the second domain 00P1B, thereby improving the visual effect of horizontal stripes and enhancing the display quality.

[0107] It is understood that the hollowed-out compensation portion 001KC of this embodiment can be a monolithic structure, and the shapes of the hollowed-out compensation portion 001KC and the first hollowed-out portion 001K1 can be rectangular, elliptical, triangular, or other shapes, which are not limited in this embodiment. Alternatively, the hollowed-out compensation portion 001KC can include multiple independent sub-hollowed portions, and the orthographic projections of the multiple independent sub-hollowed portions of the hollowed-out compensation portion 001KC on the first substrate 101 can be rectangular, elliptical, triangular, or other shapes. The shapes of the multiple independent sub-hollowed portions of the same hollowed-out compensation portion 001KC can be the same or different, which are not limited in this embodiment.

[0108] In some optional embodiments, please refer to Figures 1-6 and Figure 19 、 Figure 20 、 Figure 21 , Figure 19 yes Figure 1 Another partially enlarged structural diagram of the J1 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 19 Transparency filled), Figure 20 yes Figure 19 A schematic diagram of a cross-sectional structure in the C-C' direction, Figure 21 yes Figure 19 Schematic diagram of the structure of the first insulating layer in the embodiment, in the display panel 000, a liquid crystal layer 30 is further included between the array substrate 10 and the counter substrate 20, and the liquid crystal layer 30 includes positive liquid crystal molecules;

[0109] The hollow portion 001K includes a fourth hollow portion 001K4;

[0110] The pixel electrode 00P includes a plurality of strip electrodes 00P01 and a connecting electrode 00P02. The plurality of strip electrodes 00P01 are sequentially arranged along the extension direction (first direction X) of the scan line G. At least one end of the plurality of strip electrodes 00P01 is connected via the connecting electrode 00P02.

[0111] The orthographic projection shape of the fourth hollow portion 001K4 on the plane where the display panel 000 is located matches the orthographic projection shape of the strip electrode 00P01 on the plane where the display panel 000 is located;

[0112] In a direction Z perpendicular to the plane where the display panel 000 is located, the fourth hollow portion 001K4 and the strip electrode 00P01 overlap with each other.

[0113] This embodiment illustrates a display panel 000, i.e., a liquid crystal display panel, in which a pixel electrode 00P may include a plurality of strip electrodes 00P01 extending generally along a second direction Y and a connecting electrode 00P02 extending generally along a first direction X. The plurality of strip electrodes 00P01 are sequentially arranged along the extension direction of a scan line G (the first direction X), and at least one end of the plurality of strip electrodes 00P01 is connected by a connecting electrode 00P02. The sub-pixel 00 including the pixel electrode 00P has a dual-domain structure. When the liquid crystal layer 30 between the array substrate 10 and the counter substrate 20 includes positive liquid crystal molecules, there is a certain difference in the electric field between the strip electrodes 00P01 of the pixel electrode 00P and between two adjacent strip electrodes 00P01. The electric field at the strip electrodes 00P01 of the pixel electrode 00P is relatively weak, which can easily lead to low transmittance at these locations. Therefore, the hollow portion 001K provided in the first insulating layer 001 of this embodiment may include a fourth hollow portion 001K4. The orthographic projection shape of the fourth hollow portion 001K4 on the plane where the display panel 000 is located matches the orthographic projection shape of the strip electrode 00P01 on the plane where the display panel 000 is located. That is, the orthographic projection shape of the fourth hollow portion 001K4 on the plane where the display panel 000 is located is also a strip structure extending along the second direction Y as a whole. In the direction Z perpendicular to the plane where the display panel 000 is located, the fourth hollow portion 001K4 and the strip electrode 00P01 are aligned. They overlap with each other, thereby hollowing out the first insulating layer 001 at the strip electrode 00P01 of the pixel electrode 00P and the position where the electric field is weaker to form a fourth hollow portion 001K4. The opening position of the fourth hollow portion 001K4 corresponds to the setting position of the strip electrode 00P01, and the opening shape of the fourth hollow portion 001K4 matches the shape of the strip electrode 00P01. The fourth hollow portion 001K4 can be used to improve the problem of low transmittance in some areas of the sub-pixel, which is beneficial to balancing the display brightness of different areas of the sub-pixel, thereby further improving the display quality.

[0114] Optionally, when the liquid crystal layer 30 between the array substrate 10 and the opposing substrate 20 in the display panel 000 includes negative liquid crystal molecules, the orthographic projection of the fourth hollow portion 001K4 on the plane where the display panel 000 is located can be located between the orthographic projections of two adjacent strip electrodes 00P01 on the plane where the display panel 000 is located, so as to solve the problem of low transmittance in the area between two adjacent strip electrodes 00P01 in the sub-pixel.

[0115] In some alternative embodiments, please refer to Figure 22 , Figure 22 1 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 22The embodiment only uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in the embodiment of the present disclosure can be other display devices 111 with display functions, such as a computer, a television, and an in-vehicle display device, and the present invention does not impose specific limitations on this. The display device 111 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the detailed description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0116] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0117] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of sub-pixels, a plurality of scan lines and a plurality of data lines, wherein the scan lines and the data lines are intersected and insulated to define an area where the sub-pixels are located; the sub-pixels include electrically connected thin-film transistors and pixel electrodes; the pixel electrodes include at least two connected domains, and in the same pixel electrode, the extension directions of two adjacent domains intersect; The display panel includes an array substrate and an opposing substrate, wherein the array substrate includes a first substrate and a semiconductor layer, a first metal layer, and a second metal layer located on a side of the first substrate facing the opposing substrate; the scan line is located on the first metal layer, the active portion of the thin film transistor is located on the semiconductor layer, and the first and second electrodes of the thin film transistor and the data line are located on the second metal layer; A first insulating layer is included between the first metal layer and the second metal layer. The first insulating layer includes at least a hollow portion that penetrates the thickness of the first insulating layer. Along the extension direction of the data line, the hollow portion is located between two adjacent domain portions.

2. The display panel according to claim 1, wherein: The hollow portion includes a first hollow portion, and the first hollow portion is located between two adjacent domain portions of the same pixel electrode.

3. The display panel according to claim 2, wherein: The first hollow portion is an integral structure.

4. The display panel according to claim 2, wherein: The first hollow portion includes a plurality of independent first sub-hollow portions.

5. The display panel according to claim 1, wherein: The hollow portion includes a second hollow portion; The two domains included in the pixel electrode are a first domain and a second domain; In the same sub-pixel, along the extending direction of the data line, the first domain portion is located on a side of the second domain portion close to the thin film transistor; The second hollow portion is located at a first end of the pixel electrode, where the first end is an end of the first domain away from the second domain; and / or, The second hollow portion is located at a second end of the pixel electrode, and the second end is an end of the second domain portion away from the first domain portion.

6. The display panel according to claim 5, wherein: The pixel electrode includes a plurality of strip electrodes and a connecting electrode, wherein the plurality of strip electrodes are sequentially arranged along the extending direction of the scanning line, and at least one end of the plurality of strip electrodes is connected via the connecting electrode; The orthographic projection of the second hollow portion on the plane where the display panel is located includes a serrated edge, and the serrated edge faces the area between the first domain portion and the second domain portion; The serrated edge includes a protruding portion and a recessed area that are arranged at intervals, and the protruding portion is located between two adjacent strip electrodes.

7. The display panel according to claim 6, wherein: The orthographic projection of the second hollow portion on the plane where the display panel is located covers the connecting electrode, and the orthographic projection of the second hollow portion on the plane where the display panel is located covers the connection between the strip electrode and the connecting electrode.

8. The display panel according to claim 5, wherein: The active portion of the thin film transistor is electrically connected to a first electrode of the thin film transistor through a first via hole, and the first electrode of the thin film transistor is electrically connected to the data line; the active portion of the thin film transistor is electrically connected to a second electrode of the thin film transistor through a second via hole, and the second electrode of the thin film transistor is electrically connected to the pixel electrode; When the second hollow portion is located at the first end of the pixel electrode along the extending direction of the data line, the orthographic projection of the second hollow portion on the plane where the display panel is located does not overlap with the orthographic projection of the thin film transistor on the plane where the display panel is located; In a direction parallel to the plane of the display panel, a minimum distance between the second hollow portion and the first via hole is greater than or equal to 2.5 μm, and a minimum distance between the second hollow portion and the second via hole is greater than or equal to 2.5 μm.

9. The display panel according to claim 1, wherein: The active portion of the thin film transistor has an orthographic projection on the first substrate that is U-shaped; The display panel includes a black matrix layer, the black matrix layer includes a first light shielding strip, and the extension direction of the first light shielding strip is the same as the extension direction of the scanning line; In the same sub-pixel, in the extending direction of the data line, the pixel electrode includes a first end and a second end opposite to each other, the distance between the first end and the thin film transistor is smaller than the distance between the second end and the thin film transistor; the first light shielding strip includes a first edge close to the first end; The hollow portion includes a third hollow portion; along the extending direction of the data line, the third hollow portion is located between the first end and the first edge.

10. The display panel according to claim 1, wherein The first insulating layer further includes a hollow compensation portion, wherein the hollow compensation portion penetrates the thickness of the first insulating layer; The pixel electrode includes two domains, namely a first domain and a second domain. In the same sub-pixel, the first domain is located on a side of the second domain close to the thin film transistor. Along the extending direction of the data line, the length of the first domain portion is greater than the length of the second domain portion, and the hollow compensation portion is located in the area where the second domain portion is located.

11. The display panel according to claim 1, wherein The display panel further includes a liquid crystal layer, the liquid crystal layer is located between the array substrate and the opposite substrate, and the liquid crystal layer includes positive liquid crystal molecules; The hollow portion includes a fourth hollow portion; The pixel electrode includes a plurality of strip electrodes and a connecting electrode, wherein the plurality of strip electrodes are sequentially arranged along the extending direction of the scanning line, and at least one end of the plurality of strip electrodes is connected via the connecting electrode; The orthographic projection shape of the fourth hollow portion on the plane where the display panel is located matches the orthographic projection shape of the strip electrode on the plane where the display panel is located; In a direction perpendicular to the plane where the display panel is located, the fourth hollow portion and the strip electrodes overlap with each other.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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