Lithographic mask optimization method and device, computer storage medium and program product

Abstract

The invention discloses a photoetching mask optimization method and device, a computer storage medium and a program product, and relates to the technical field of semiconductors. The photoetching mask optimization method comprises the steps that edge breaking is carried out on an initial mask plate graph, multiple broken edges are obtained, and the multiple edges comprise irregular edges; determining n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and the vertical width of the irregular edge; combining the n horizontal segments and the n vertical segments, and converting to obtain a regular edge corresponding to the irregular edge and a reticle graph containing the regular edge; and performing mask optimization on the intermediate mask plate graph based on the initial mask plate graph to obtain a target mask plate graph. According to the embodiment of the invention, the photoetching mask optimization of the irregular layout can be effectively realized, so that the overall photoetching mask optimization efficiency and precision can be effectively improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a photolithography mask optimization method, device, computer storage medium and program product. Background Art

[0002] Currently, in the photolithography process, in order to achieve higher graphic resolution and manufacturing accuracy, the optimization of the photolithography layout has become crucial. The Optical Proximity Correction (OPC) technology in the photolithography process corrects the mask layout to compensate for the graphic distortion caused by optical diffraction, interference, and photoresist effects during the photolithography process. Traditional OPC methods usually optimize and correct regular layouts. However, with the increasing complexity and diversity of chip design shapes, the number of irregular graphic edges in the entire layout is increasing, and traditional OPC methods have difficulty optimizing irregular graphic edges in the layout, which affects the mask optimization results.

[0003] Based on this, the industry still urgently needs a new type of photolithography mask optimization solution to achieve the purpose of optimizing photolithography masks with irregular layout shapes, thereby effectively improving the overall photolithography mask optimization efficiency and accuracy. Summary of the Invention

[0004] The embodiments of the present application provide a lithography mask optimization method, device, computer storage medium and program product, which can effectively optimize the lithography mask of irregular layouts, thereby effectively improving the overall lithography mask optimization efficiency and accuracy.

[0005] In a first aspect, an embodiment of the present application provides a photolithography mask optimization method, the photolithography mask optimization method comprising:

[0006] Performing edge interruption on the initial mask layout to obtain a plurality of interrupted edges, wherein the plurality of edges include irregular edges;

[0007] According to the horizontal width and vertical width of the irregular edge, determine the n horizontal segments and n vertical segments corresponding to the irregular edge;

[0008] Combining the n horizontal segments and the n vertical segments, converting the irregular edges into regular edges and an intermediate mask pattern including the regular edges;

[0009] The intermediate mask layout is optimized based on the initial mask layout to obtain the target mask layout.

[0010] In some possible implementations, determining n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and vertical width of the irregular edge includes:

[0011] Determine the number of segments n and n first segments according to the preset segment unit length and the first width, where the first width is a horizontal width and the first segment is a horizontal segment, or where the first width is a vertical width and the first segment is a vertical segment;

[0012] Determine n second segments according to a ratio of the n first segments to the target width, where the second segment is one of a horizontal segment and a vertical segment that is different from the first segment;

[0013] The target width ratio is a ratio between the first width and the second width, and the second width is one of a horizontal width and a vertical width that is different from the first width.

[0014] In some possible implementations, determining the number of segments n and the n first segments according to a preset segment unit length and a first width includes:

[0015] Determine the number of segments n and n first initial segments according to a ratio between the first width and a preset segment unit length, wherein the segment length of the first initial segment is the preset segment unit length;

[0016] Calculate a first redundant length based on a difference between a target product and the first width, where the target product is the product of the number of segments n and a preset segment unit length;

[0017] The first redundancy length is distributed to at least part of the n first initial segments to determine n first segments.

[0018] In some possible implementations, determining the n second segments according to the ratio of the n first segments to the target width includes:

[0019] Determining n second initial segments according to a ratio between each first segment in the n first segments and the target width ratio;

[0020] Calculate a second redundant length according to a difference between a sum of segment lengths of the n second initial segments and the second width;

[0021] The second redundancy length is distributed to at least part of the n second initial segments to determine n second segments.

[0022] In some possible implementations, determining n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and vertical width of the irregular edge includes:

[0023] Determine the number of segments n according to either the horizontal width or the vertical width and a preset segment unit length;

[0024] Determine n horizontal segments according to the ratio between the horizontal width and the number of segments n;

[0025] According to the ratio between the vertical width and the number of segments n, the n vertical segments are determined.

[0026] In some possible implementations, combining n horizontal segments and n vertical segments to convert regular edges corresponding to irregular edges includes:

[0027] Repeat the following steps until i=n+1, and the regular edge is obtained;

[0028] Place the starting point of the i-th horizontal segment at the ending point of the i-1-th vertical segment;

[0029] Place the starting point of the i-th vertical segment at the ending point of the i-th horizontal segment;

[0030] Update i to i+1;

[0031] Wherein, i is a positive integer. When i=1, the starting point of the i-th horizontal segment coincides with the starting point of the irregular edge.

[0032] In some possible implementations, performing mask optimization on the intermediate mask layout based on the initial mask layout to obtain a target mask layout includes:

[0033] Place evaluation points in the intermediate mask layout and map the evaluation points back to the initial mask layout;

[0034] Inputting the intermediate mask layout into the lithography simulation model to perform lithography simulation to obtain a simulation profile;

[0035] Comparing the evaluation point parameters corresponding to the simulated contour with the evaluation point parameters corresponding to the ideal contour to determine the layout difference, and the ideal contour is determined based on the initial mask layout;

[0036] When the layout difference does not meet the preset conditions, the intermediate mask layout is iteratively adjusted according to the layout difference to obtain an updated intermediate mask layout, until the layout difference meets the preset conditions, and the updated intermediate mask layout is determined as the target mask layout.

[0037] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a photolithography mask optimization device, the photolithography mask optimization device comprising:

[0038] A first obtaining module is used to interrupt the edges of the initial mask layout to obtain multiple interrupted edges, including irregular edges;

[0039] A first determining module is configured to determine n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and vertical width of the irregular edge;

[0040] A first conversion module is used to combine the n horizontal segments and the n vertical segments to obtain regular edges corresponding to the irregular edges and an intermediate mask layout containing the regular edges;

[0041] The second obtaining module is used to perform mask optimization on the intermediate mask layout based on the initial mask layout to obtain the target mask layout.

[0042] In a third aspect, an embodiment of the present application provides a photolithography mask optimization device, the photolithography mask optimization device comprising:

[0043] a processor and a memory storing computer program instructions;

[0044] When the processor executes the computer program instructions, the photolithography mask optimization method provided in any one of the above embodiments of the present application is implemented.

[0045] In a fourth aspect, an embodiment of the present application provides a computer storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, a photolithography mask optimization method as provided in any one of the above-mentioned embodiments of the present application is implemented.

[0046] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a photolithography mask optimization method as provided in any one of the above-mentioned embodiments of the present application.

[0047] The embodiments of the present application provide a lithography mask optimization method, device, computer storage medium, and program product. By interrupting the edges of an initial mask layout, a plurality of interrupted edges are obtained, including irregular edges. Next, based on the horizontal and vertical widths of the irregular edges, n horizontal segments and n vertical segments corresponding to the irregular edges are determined. Then, the n horizontal segments and n vertical segments are combined to convert the regular edges corresponding to the irregular edges, as well as an intermediate mask layout containing the regular edges. Finally, mask optimization is performed on the intermediate mask layout based on the initial mask layout to effectively obtain the target mask layout.

[0048] As can be seen from the above description, the photolithography mask optimization method, device, computer storage medium, and program product of the embodiments of the present application are different from the traditional OPC method, which is difficult to optimize for irregular edges in the layout. The embodiments of the present application horizontally and vertically segment the irregular edges in the initial mask layout, and then convert the horizontal and vertical segments into regular edges corresponding to the irregular edges, thereby obtaining an intermediate mask layout including the regular edges. The intermediate mask layout can then be optimized based on the initial mask layout. In this way, the purpose of effectively optimizing the photolithography mask for irregular layout shapes is ultimately achieved, thereby fully improving the overall photolithography mask optimization efficiency and accuracy of various layouts. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 1 is a flow chart of a photolithography mask optimization method provided in one embodiment of the present application;

[0051] Figure 2 This is a schematic diagram of the structure of an irregular edge provided by an embodiment of the present application;

[0052] Figure 3 This is a schematic structural diagram of a regular edge corresponding to an irregular edge provided in an embodiment of the present application;

[0053] Figure 4 1 is a schematic structural diagram of a photolithography mask optimization device provided in one embodiment of the present application;

[0054] Figure 5 It is a structural schematic diagram of a photolithography mask optimization device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0055] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0056] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0057] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned. They should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0058] As mentioned in the background section, conventional OPC methods typically optimize and modify regular layouts. These layouts are all regular, with edges that are multiples of 45 degrees. However, conventional OPC methods struggle to optimize irregular shapes within irregular layouts and effectively handle non-45-degree edges within them. Consequently, current OPC processes are not suitable for OPC mask optimization of irregular layout shapes.

[0059] In view of the above, in order to solve the problems of the prior art, the embodiments of the present application provide a photolithography mask optimization method, device, computer storage medium and program product. It should be noted that the embodiments provided in this application are not intended to limit the scope of the disclosure of this application.

[0060] The following first introduces the photolithography mask optimization method provided in the embodiment of the present application.

[0061] Figure 1 FIG1 shows a flow chart of a photolithography mask optimization method provided by an embodiment of the present application. The photolithography mask optimization method is applied to electronic equipment. Figure 1 As shown, the photolithography mask optimization method includes the following steps:

[0062] S110, performing edge interruption on the initial mask layout to obtain a plurality of interrupted edges, wherein the plurality of edges include irregular edges;

[0063] S120, determining n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and vertical width of the irregular edge;

[0064] S130, combining the n horizontal segments and the n vertical segments to convert and obtain regular edges corresponding to the irregular edges, and an intermediate mask pattern including the regular edges;

[0065] S140, performing mask optimization on the intermediate mask layout based on the initial mask layout to obtain a target mask layout.

[0066] From the above description, it can be seen that a photolithography mask optimization method of an embodiment of the present application is difficult to optimize the irregular graphic edges in the layout compared to the traditional OPC method. The embodiment of the present application performs horizontal and vertical segmentation on the irregular edges in the initial mask layout. Then, the horizontal segmentation and vertical segmentation are combined and converted to obtain the regular edges corresponding to the irregular edges, thereby obtaining an intermediate mask layout including the regular edges. The intermediate mask layout can then be optimized based on the initial mask layout. In this way, the embodiment of the present application achieves the purpose of effective photolithography mask optimization of irregular layout shapes by cleverly converting irregular edges into regular edges for processing, thereby fully improving the overall photolithography mask optimization efficiency and accuracy of various layouts.

[0067] The photolithography mask optimization method provided in the embodiments of the present application can convert irregular edges into regular edges, thereby flexibly converting layouts of various shapes into layout shapes that can be processed in traditional OPC processes. Therefore, the photolithography mask optimization method provided in the embodiments of the present application can effectively process layouts of various angles.

[0068] The specific implementation of the above steps 110 to 140 is described in detail below.

[0069] In S110 , in an actual OPC process, an edge breaking operation is first performed on the initial mask layout to simplify subsequent processing steps, thereby more accurately correcting the optical proximity effect.

[0070] Specifically, when performing edge breaking, the initial pattern in the initial mask layout is determined, and the side to be processed and the endpoint to be measured on the initial pattern are determined. Appropriate breaking parameters are selected on the side to be processed to ensure the accuracy of the breaking.

[0071] Among them, the above-mentioned edge interruption methods include at least one of point-by-point interruption, projection-free zone interruption, projection interruption and uniform interruption, and the interruption operation can be specifically implemented using professional layout processing tools.

[0072] In this step, edge breaking can be used to break complex polygons or irregular shapes into multiple, more manageable edges, including irregular edges. In the current OPC processing flow, irregular edges specifically refer to edges that are not multiples of 45°, such as edges with angles of 30° or 50° from the horizontal.

[0073] In S120 , during specific implementation, n horizontal segments and n vertical segments corresponding to the irregular edge may be determined according to the horizontal width and vertical width of the irregular edge.

[0074] In this embodiment, in the mask layout, the horizontal width of the irregular edge may specifically refer to the width of the pattern boundary of the irregular edge measured along the horizontal direction (usually the X-axis direction). The vertical width of the irregular edge may specifically refer to the width of the pattern boundary of the irregular edge measured along the vertical direction (usually the Y-axis direction).

[0075] In an example, see Figure 2 , Figure 2 This is a schematic diagram of the structure of an irregular edge provided by an embodiment of the present application. For an irregular edge with an irregular angle, its horizontal width is the horizontal distance from the leftmost end to the rightmost end, and its vertical width is the vertical distance from the topmost end to the bottommost end. When calculating the horizontal width, the horizontal coordinates of the leftmost end and the rightmost end of the irregular edge are determined, and then the horizontal distance between these two points is calculated to obtain the horizontal width. For example, Figure 2 As shown, the coordinates of the endpoints of the irregular edge are (x1, y1) and (x2, y2), respectively. The horizontal coordinate of the leftmost end is x1, and the horizontal coordinate of the rightmost end is x2. Therefore, the horizontal width dx = x2 - x1. The vertical width can be calculated similarly, resulting in dy = y2 - y1. It should be noted that to ensure that the calculated horizontal and vertical widths are not negative, the absolute value of the coordinate difference can be taken.

[0076] In a more specific embodiment, assume that there is an irregular edge, and the coordinates of the endpoints of the irregular edge are (1, 2) and (5, 8) respectively. The horizontal coordinate of the leftmost end is 1, the horizontal coordinate of the rightmost end is 5, the vertical coordinate of the bottom end is 2, and the vertical coordinate of the top end is 8. The calculated horizontal width is: 5-1=4; the vertical width is: 8-2=6.

[0077] After determining the horizontal width and vertical width of the irregular edge, the irregular edge is divided into n horizontal segments and n vertical segments. The number of segments n can be set according to design rules or process requirements, or determined based on at least one of the horizontal width and vertical width, and is not strictly limited here.

[0078] When segmenting, the irregular edge can be evenly segmented according to the number of segments n, or processed according to a certain segmentation rule to obtain n horizontal segments and n vertical segments. These n horizontal segments and n vertical segments can provide reliable and accurate data support for the subsequent photolithography mask optimization process.

[0079] It should be added that the value of n affects the accuracy and complexity of regularization. A larger n can make the regular edges obtained by subsequent conversion closer to the original irregular edges, and a smaller n can reduce the amount of segmentation calculation. Therefore, the value of n can be flexibly determined according to the actual accuracy and computational complexity indicators.

[0080] As an optional embodiment, determining the n horizontal segments and n vertical segments corresponding to the irregular edge based on the horizontal width and vertical width of the irregular edge may specifically include:

[0081] Determine the number of segments n and n first segments according to the preset segment unit length and the first width, where the first width is a horizontal width and the first segment is a horizontal segment, or where the first width is a vertical width and the first segment is a vertical segment;

[0082] Determine n second segments according to a ratio of the n first segments to the target width, where the second segment is one of a horizontal segment and a vertical segment that is different from the first segment;

[0083] The target width ratio is a ratio between the first width and the second width, and the second width is one of a horizontal width and a vertical width that is different from the first width.

[0084] In this embodiment, the first width can be a horizontal width or a vertical width. If the first width is a horizontal width, the second width is a vertical width, and the corresponding first segment is the aforementioned horizontal segment, and the second segment is the aforementioned vertical segment. Alternatively, if the first width is a vertical width, the second width is a horizontal width, and the corresponding first segment is the aforementioned vertical segment, and the second segment is the aforementioned horizontal segment.

[0085] In a specific implementation, the specific number of segments is first determined based on a preset segment unit length and at least one of the horizontal width and the vertical width. For example, taking the first width as the horizontal width, the number of segments n and the number of n first segments are determined based on the preset segment unit length and the first width.

[0086] Next, based on the ratio of the n first segments to the target width, n second segments are calculated. When calculating the n second segments, the first segment can be divided by the target width ratio to obtain the corresponding second segment. The ratio between the first and second segments conforms to the ratio between the first and second widths of the irregular edge, thus ensuring the rationality and effectiveness of converting the actual irregular edge to the corresponding regular edge.

[0087] The first width is selected as a horizontal width or a vertical width, which can be selected randomly or determined according to the actual processing requirements of the user, and is not strictly limited here.

[0088] The above-mentioned preset segment unit length can be flexibly set according to actual design rules or segment requirements to ensure the rationality of the length of each segment and meet the subsequent data processing and calculation requirements.

[0089] To better understand the above segmentation process, in a specific example, assuming the horizontal width of an irregular edge is 9 and the preset segment unit length is 3, the number of segments n can first be determined as 3 using a uniform segmentation method, resulting in 3 horizontal segments, each of which has a length of 3. Next, the vertical width is divided into 3 corresponding vertical segments based on the number of segments 3. For example, if the vertical width is 12 and the target width ratio is 9 / 12, 3 vertical segments corresponding to the aforementioned 3 horizontal segments are calculated based on this target width ratio of 9 / 12, and each of the 3 vertical segments has a length of 4.

[0090] In this embodiment, by combining the horizontal width and vertical width of the irregular edge and setting a preset segment unit length to reasonably divide the irregular edge into n horizontal segments and n vertical segments corresponding to the above-mentioned irregular edge, the n horizontal segments and n vertical segments can lay a good data foundation for the subsequent photolithography mask optimization process, and can ensure the rationality and effectiveness of the conversion of the actual irregular edge to the corresponding regular edge.

[0091] As an optional embodiment, determining the number of segments n and the n first segments according to a preset segment unit length and a first width may specifically include:

[0092] Determine the number of segments n and n first initial segments according to a ratio between the first width and a preset segment unit length, wherein the segment length of the first initial segment is the preset segment unit length;

[0093] Calculate a first redundant length based on a difference between a target product and the first width, where the target product is the product of the number of segments n and a preset segment unit length;

[0094] The first redundancy length is distributed to at least part of the n first initial segments to determine n first segments.

[0095] In specific implementation, taking the first width as the horizontal width as an example, considering that in actual applications there are multiple possible values for the horizontal width and vertical width of the irregular edge, in some cases, the ratio between the first width and the preset segment unit length is not necessarily an integer, and there are situations where it cannot be divided. Since n is a positive integer, there will be redundant length, resulting in the coordinate offset of the starting and ending points of the final regular edge in the horizontal direction compared to the irregular edge.

[0096] Exemplarily, the first width is 10, and the preset segment unit length is 3. 10 / 3 is rounded to an integer, and the number of segments is calculated to be n, and the corresponding 3 first initial segments are obtained, and the segment length of each first initial segment is the preset segment unit length 3.

[0097] In this case, the product of the number of segments 3 and the preset segment unit length 3 is 9, that is, the target product is 9. Based on the difference between the target product 9 and the first width 10, the first redundant length is calculated to be 1. Next, the first redundant length 1 is amortized to at least one segment of the three first initial segments, thereby ultimately obtaining three first segments. The length of each first segment is a finite number, and the sum of the lengths is equal to the first width.

[0098] In a specific example, the first redundant length 1 is fully distributed to any of the three first initial segments. Alternatively, to achieve more even distribution of redundant length, the first redundant length is split into 0.3, 0.3, and 0.4, and distributed to the corresponding first initial segments respectively.

[0099] In this embodiment, the number of segments n and the number of first initial segments are obtained by rounding the ratio between the first width and the preset segment unit length. The first redundant length remaining after segmenting with the first width is then calculated. In this manner, the first redundant length is allocated to at least some of the n first initial segments in a divisible manner, ultimately resulting in n first segments.

[0100] In this way, the total length of the n first segments is equal to the first width. Therefore, it can be ensured that the starting and ending points of the subsequent regular edges in the horizontal direction coincide with the irregular edges, and the coordinate offset will not be caused by the segment length error, thereby effectively ensuring the accuracy of the overall photolithography mask process.

[0101] As an optional embodiment, determining the n second segments according to the ratio of the n first segments to the target width may specifically include:

[0102] Determining n second initial segments according to a ratio between each first segment in the n first segments and the target width ratio;

[0103] Calculate a second redundant length according to a difference between a sum of segment lengths of the n second initial segments and the second width;

[0104] The second redundancy length is distributed to at least part of the n second initial segments to determine n second segments.

[0105] In a specific implementation, taking the vertical width as the second width as an example, considering that when n first segments are determined, the lengths of each first segment vary, and the target width ratio can have multiple values depending on the horizontal and vertical widths, the ratio between the first segment and the target width ratio may be infinite. This will cause deviations in the calculation of the second segment due to the infinite value, and in turn, cause coordinate deviations between the starting and ending points of subsequent regular edges in the vertical direction and irregular edges, which is not conducive to achieving overall layout lithography mask optimization.

[0106] In response to the above situation, this embodiment first uses the ratio between each of the n first segments and the target width ratio to determine n second initial segments. For example, if the ratio between a first segment and the target width ratio is finite, then this finite number is used as the length of the corresponding second initial segment. If the ratio between a first segment and the target width ratio is infinite, then this infinite number is approximated to a finite value, and this approximated finite value is used as the length of the corresponding second initial segment. This process is repeated in this way until n second initial segments are determined.

[0107] Next, the difference between the sum of the segment lengths of the n second initial segments and the second width is calculated to obtain the second redundant length remaining after segmentation by the second width. In this manner, the second redundant length is subsequently allocated to at least some of the segments of the n second initial lengths in a divisible manner, ultimately resulting in n second segments whose total segment length is guaranteed to be equal to the second width.

[0108] In a specific example, n=3, the first width is 11, the second width is 10, and the lengths of the three first segments are 3, 4, and 4 respectively. If the target width ratio is 11 / 10, the ratio between each first segment and the target width ratio will be impossible to divide. Therefore, in this case, three second initial lengths can be obtained through approximate processing, and the lengths of the three second initial lengths are: 2.7, 3.6, and 3.6 respectively. The length of the three second initial lengths is 9.9, and the difference between the second width and 9.9 is 0.1. The calculated second redundant length is 0.1.

[0109] In this case, the second redundant length 0.1 is distributed to at least one segment of the three second initial segments according to a certain distribution rule, thereby finally obtaining three second segments, so that the length value of each second segment is a finite number, and the sum is equal to the second width.

[0110] In a specific example, the first redundant length of 0.1 is fully distributed to any of the three second initial segments, resulting in, for example, three second lengths of 2.8, 3.6, and 3.6. Alternatively, to achieve more even distribution of redundant length, the second redundant length is split into 0.03, 0.03, and 0.04 segments, each of which is distributed to the corresponding second initial segments, resulting in, for example, three second segments of 2.73, 3.63, and 3.64.

[0111] In this embodiment, the redundant length allocation process described above can fully ensure that the starting and ending points of subsequent regular edges in the vertical direction coincide with the irregular edges, and will not cause coordinate offset due to segment length errors, thereby effectively ensuring the accuracy of the overall photolithography mask process.

[0112] As an optional embodiment, determining n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and vertical width of the irregular edge may specifically include:

[0113] Determine the number of segments n according to either the horizontal width or the vertical width and a preset segment unit length;

[0114] Determine n horizontal segments according to the ratio between the horizontal width and the number of segments n;

[0115] According to the ratio between the vertical width and the number of segments n, the n vertical segments are determined.

[0116] Specifically, considering the high efficiency requirement for segmentation processing in some scenarios, in this embodiment, the number of segments n is determined directly according to either the horizontal width or the vertical width and a preset segment unit length.

[0117] Next, the number of horizontal segments n is determined based on the ratio between the horizontal width and the number of segments n, and the number of vertical segments n is determined based on the ratio between the vertical width and the number of segments n. If the divisibility is not possible, the approximate result is directly processed.

[0118] In this way, through the above-mentioned ratio calculation between the horizontal width and the number of segments n, as well as the ratio calculation between the vertical width and the number of segments n, the n horizontal segments and n vertical segments corresponding to the irregular edges can be calculated quickly and efficiently, thereby helping to improve the segmentation speed of the irregular graphic edges in the layout, fully controlling and reducing the computing power consumption in the segmentation process, and thus being able to improve the efficiency of the lithography mask optimization process as a whole.

[0119] In S130, during implementation, the n horizontal segments and n vertical segments obtained in step 120 are concatenated to convert the irregular edges into regular edges, and a reticle layout containing the regular edges is obtained. The regular edges include both horizontal and vertical edges, which can be effectively corrected in subsequent mask processing.

[0120] It should be noted that, in addition to the regular edges obtained by converting irregular edges, the intermediate mask layout also includes other regular edges obtained after edge interruption in the initial mask layout to ensure data integrity during the layout conversion process. No strict restrictions are made here.

[0121] As an optional embodiment, n horizontal segments and n vertical segments are combined to convert regular edges corresponding to irregular edges, including:

[0122] Repeat the following steps until i=n+1, and the regular edge is obtained;

[0123] Place the starting point of the i-th horizontal segment at the ending point of the i-1-th vertical segment;

[0124] Place the starting point of the i-th vertical segment at the ending point of the i-th horizontal segment;

[0125] Update i to i+1;

[0126] Wherein, i is a positive integer. When i=1, the starting point of the i-th horizontal segment coincides with the starting point of the irregular edge.

[0127] In practice, the n horizontal segments and n vertical segments are spliced together through an iterative process. The starting and ending points of the horizontal and vertical segments are sequentially connected. This is equivalent to forming a group of one horizontal segment and one horizontal segment. These n groups are then spliced together to gradually construct the regular edges corresponding to the irregular edges.

[0128] In an example, see Figure 3 , Figure 3 This is a schematic diagram of the structure of the regular edge corresponding to the irregular edge provided by an embodiment of the present application. This example specifically provides a combination of the above n horizontal segments and n vertical segments. In this example, by sorting the n horizontal segments and the n vertical segments respectively, and according to Figure 3 The method shown is used for sequential splicing.

[0129] Combine Figure 3, during the specific iteration, i = 1, the starting point of horizontal segment 1 is placed on the starting point of the irregular edge, that is, (x1, y1), and the coordinates of the ending point of horizontal segment 1 are (x1+dx1, y1); the starting point of vertical segment 1 is placed on the ending point of horizontal segment 1, that is, (x1+dx1, y1), and the coordinates of the ending point of vertical segment 1 are (x1+dx1, y1+dy1), and then i is updated to 2 to perform the splicing of the second horizontal segment and the second vertical segment.

[0130] This process continues in this way until the starting point of the nth vertical segment is placed at the ending point of the nth horizontal segment. The ending point of the nth vertical segment coincides with, or nearly coincides with, the ending point of the irregular edge. i is then updated to n+1. The iteration terminates when i = n+1, ultimately resulting in a regular boundary consisting of horizontal and vertical segments. The horizontal and vertical segments in this regular edge are easily processed by the subsequent mask optimization process. The larger n is, the more similar the regular edge is to the original irregular edge.

[0131] It should be added that, in some other embodiments of the present application, the above-mentioned iterative process can also start from the first vertical segment, that is, the starting point of the first vertical segment is placed at the starting point of the irregular edge, and the starting point of the first horizontal segment is placed at the end point of the first vertical segment, and spliced in this way to complete the process of gradually constructing n horizontal segments and n vertical segments into a regular boundary. Alternatively, the above-mentioned iterative process can also be started from the end point of the irregular edge. Considering the diversity of the above-mentioned horizontal and vertical segmentation reorganization methods, the embodiments of the present application do not list their implementation methods one by one here.

[0132] In S140, during implementation, mask optimization is performed on the intermediate mask layout based on the initial mask layout. Mask optimization can be achieved using optical proximity effect correction, light source mask collaborative optimization, or deep learning-based mask optimization. In this way, mask optimization can reduce pattern deviations caused by various factors in the lithography process, ultimately obtaining the target mask layout after mask optimization.

[0133] The specific mask optimization method chosen may depend on the actual application scenario and process requirements. For example, in this embodiment, considering the complexity of the photolithography process and the advantages of optical proximity correction in processing regular edges, optical proximity correction is chosen to achieve mask optimization, thereby improving the reliability and yield of the mask layout.

[0134] In some possible implementations, performing mask optimization on the intermediate mask layout based on the initial mask layout to obtain a target mask layout includes:

[0135] Place evaluation points in the intermediate mask layout and map the evaluation points back to the initial mask layout;

[0136] Inputting the intermediate mask layout into the lithography simulation model to perform lithography simulation to obtain a simulation profile;

[0137] Comparing the evaluation point parameters corresponding to the simulated contour with the evaluation point parameters corresponding to the ideal contour to determine the layout difference, and the ideal contour is determined based on the initial mask layout;

[0138] When the layout difference does not meet the preset conditions, the intermediate mask layout is iteratively adjusted according to the layout difference to obtain an updated intermediate mask layout, until the layout difference meets the preset conditions, and the updated intermediate mask layout is determined as the target mask layout.

[0139] In this embodiment, the evaluation points are key positions for measuring the correction effect in the optical proximity effect correction process, and can usually be set on the edge or key features of the mask pattern.

[0140] The above-mentioned evaluation point parameters such as edge placement error (EPE), critical dimension deviation or other quantitative indicators can be used to measure the deviation between the simulated profile obtained based on the intermediate mask layout and the ideal profile obtained based on the initial mask layout.

[0141] For example, the aforementioned preset conditions set a maximum EPE threshold, and the corrected EPE must be lower than this threshold. This can reduce pattern deviations caused by optical diffraction and proximity effects during the lithography process, improving the efficiency and accuracy of mask optimization.

[0142] This embodiment describes the specific mask optimization process in detail. In practice, merit points can be placed at key locations on the edges and closed edges of the reticle layout. For example, merit points can be placed at key graphic features such as line width, spacing, and corners to ensure the accuracy of corrections in these areas.

[0143] Next, the evaluation points placed in the intermediate mask layout are mapped back to the initial mask layout using, for example, vertical mapping, so as to evaluate their performance in an actual design environment.

[0144] After obtaining a reticle and initial mask layout, each with evaluation points placed on it, the reticle is then input into a lithography simulation model to generate a simulated profile after lithography simulation, which includes the evaluation points. This lithography simulation model can be modeled using formulas that incorporate physical and chemical effects during the lithography process, and can be used to simulate the physical changes in parameters such as pattern data during the lithography process.

[0145] On the other hand, an ideal contour is determined based on the initial mask layout with the evaluation points placed therein. This ideal contour includes the evaluation points. This ideal contour can refer to the expected shape contour of the initial mask layout under ideal lithographic conditions. It can be calculated using certain mathematical methods based on lithographic process parameters. The ideal contour is subsequently used as a reference standard to evaluate deviations in the actual lithographic process.

[0146] In this way, after obtaining the above-mentioned simulated contour and ideal contour, the evaluation point parameters corresponding to the simulated contour are compared with the evaluation point parameters corresponding to the ideal contour to determine the deviation between the simulated contour obtained after actual lithography simulation and the ideal contour, that is, the above-mentioned layout difference.

[0147] If the layout difference does not meet the preset conditions, the reticle layout is iteratively adjusted based on the layout difference to obtain an updated reticle layout. Layout adjustment strategies for the reticle layout include adjusting pattern shapes, adding auxiliary patterns (such as serifs or hammerheads), and shifting layout edges. Appropriate layout adjustments can effectively reduce the deviation between the actual process and the ideal profile.

[0148] After obtaining the updated intermediate mask layout, the updated simulation profile is simulated again according to the lithography simulation model, and the evaluation point parameters between the simulation profile and the ideal profile are compared to obtain a new layout difference.

[0149] If the new layout differences meet the preset conditions, the updated reticle layout is determined as the target mask layout. If the new layout differences still do not meet the preset conditions, the reticle layout is iteratively adjusted based on the layout differences. This correction process is repeated until the layout differences meet the preset conditions. Finally, the reticle layout obtained from the last iteration is output as the target mask layout. This target mask layout can achieve the desired imaging effect in the actual lithography process.

[0150] In this embodiment, the above-described mask optimization steps are iterated to ultimately achieve a target mask layout that meets the requirements, effectively improving the accuracy and reliability of mask correction. Subsequent layout fabrication and actual photolithography processing based on this target mask layout ensure that the designed pattern can be accurately implemented in actual manufacturing, thereby ensuring high-quality output from the photolithography process.

[0151] Based on the photolithography mask optimization method provided in the above embodiment, for the same inventive concept, the present application also provides a photolithography mask optimization device corresponding to the above photolithography mask optimization method. Figure 4 A detailed introduction to the photolithography mask optimization device is given.

[0152] Figure 4 A schematic structural diagram of a photolithography mask optimization device provided in one embodiment of the present application is shown. Figure 4 The photolithography mask optimization apparatus 400 shown includes:

[0153] A first obtaining module 410 is configured to interrupt the initial mask layout to obtain a plurality of interrupted edges, wherein the plurality of edges include irregular edges;

[0154] A first determining module 420 is configured to determine n horizontal segments and n vertical segments corresponding to the irregular edge based on the horizontal width and vertical width of the irregular edge;

[0155] A first conversion module 430 is configured to combine the n horizontal segments and the n vertical segments to obtain regular edges corresponding to the irregular edges and an intermediate mask layout including the regular edges;

[0156] The second obtaining module 440 is configured to perform mask optimization on the intermediate mask layout based on the initial mask layout to obtain a target mask layout.

[0157] The embodiment of the present application provides a photolithography mask optimization device. By setting corresponding functional modules, compared with the traditional OPC method, which is difficult to optimize the irregular graphic edges in the layout, the embodiment of the present application performs horizontal and vertical segmentation on the irregular edges in the initial mask layout. Then, the horizontal and vertical segmentation are combined and converted to obtain the regular edges corresponding to the irregular edges, thereby obtaining an intermediate mask layout including the regular edges. The intermediate mask layout can then be optimized based on the initial mask layout. In this way, the embodiment of the present application achieves the purpose of effective photolithography mask optimization for irregular layout shapes by cleverly converting irregular edges into regular edges for processing, thereby fully improving the overall photolithography mask optimization efficiency and accuracy of various layouts.

[0158] Based on the photolithography mask optimization method provided in the above embodiment, for the same inventive concept, the present application also provides a photolithography mask optimization device corresponding to the above photolithography mask optimization method. Figure 5 A detailed introduction to photolithography mask optimization equipment is given.

[0159] See below Figure 5 , Figure 5 It is a structural schematic diagram of a photolithography mask optimization device provided in one embodiment of the present application.

[0160] The lithography mask optimization apparatus may include a processor 501 and a memory 502 storing computer program instructions.

[0161] Specifically, the processor 501 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0162] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 502 may include removable or non-removable (or fixed) media. Where appropriate, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.

[0163] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0164] The processor 501 reads and executes computer program instructions stored in the memory 502 to implement any one of the photolithography mask optimization methods in the above embodiments.

[0165] In one example, the data lithography mask optimization device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.

[0166] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0167] Bus 510 includes hardware, software or both, and the parts of lithography mask optimization equipment are coupled to each other.For example, but not limitation, bus can include accelerated graphics port (AGP) or other graphics bus, enhanced industry standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industry standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations.In suitable cases, bus 510 can include one or more buses.Although the present application embodiment describes and shows specific bus, the application considers any suitable bus or interconnection.

[0168] The photolithography mask optimization device executes the photolithography mask optimization method in the embodiment of the present application, thereby realizing the photolithography mask optimization method described in the embodiment of the present application.

[0169] In addition, in conjunction with the photolithography mask optimization method in the above embodiments, embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any of the photolithography mask optimization methods in the above embodiments is implemented.

[0170] Based on the photolithography mask optimization method in the above-mentioned embodiment, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the photolithography mask optimization method provided in any one of the above-mentioned embodiments of the present application.

[0171] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0172] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0173] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0174] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It is also understood that each box in the block diagram and / or flowchart and the combination of the boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0175] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A photolithography mask optimization method, characterized in that: include: Performing edge interruption on the initial mask pattern to obtain a plurality of interrupted edges, wherein the plurality of edges include irregular edges; Determining n horizontal segments and n vertical segments corresponding to the irregular edge according to the horizontal width and the vertical width of the irregular edge; Combining the n horizontal segments and the n vertical segments to convert and obtain regular edges corresponding to the irregular edges and an intermediate mask pattern including the regular edges; The intermediate mask layout is subjected to mask optimization based on the initial mask layout to obtain a target mask layout.

2. The method according to claim 1, characterized in that The determining, based on the horizontal width and the vertical width of the irregular edge, n horizontal segments and n vertical segments corresponding to the irregular edge includes: Determine the number of segments n and n first segments according to a preset segment unit length and a first width, where the first width is the horizontal width and the first segment is the horizontal segment, or the first width is the vertical width and the first segment is the vertical segment; determining n second segments according to a ratio of the n first segments to a target width, where the second segment is one of the horizontal segment and the vertical segment that is different from the first segment; The target width ratio is a ratio between the first width and a second width, and the second width is one of the horizontal width and the vertical width that is different from the first width.

3. The method according to claim 2, characterized in that The step of determining the number of segments n and the n first segments according to the preset segment unit length and the first width includes: Determining the number of segments n and n first initial segments according to a ratio between the first width and the preset segment unit length, wherein the segment length of the first initial segment is the preset segment unit length; Calculating a first redundant length according to a difference between a target product and the first width, wherein the target product is a product of the number of segments n and the preset segment unit length; The first redundancy length is distributed to at least part of the n first initial segments to determine the n first segments.

4. The method according to claim 2, characterized in that The determining of n second segments according to the ratio of the n first segments to the target width includes: determining n second initial segments according to a ratio between each first segment in the n first segments and the target width ratio; Calculating a second redundant length according to a difference between a sum of segment lengths of the n second initial segments and the second width; The second redundancy length is distributed to at least part of the n second initial segments to determine the n second segments.

5. The method according to claim 1, wherein The determining, based on the horizontal width and the vertical width of the irregular edge, n horizontal segments and n vertical segments corresponding to the irregular edge includes: determining the number of segments n according to either the horizontal width or the vertical width and a preset segment unit length; Determining the n horizontal segments according to a ratio between the horizontal width and the number n of segments; The n vertical segments are determined according to a ratio between the vertical width and the number n of segments.

6. The method according to claim 1, characterized in that The combining of the n horizontal segments and the n vertical segments to convert the regular edges corresponding to the irregular edges includes: Repeat the following steps until i=n+1, and the regular edge is obtained by conversion; Place the starting point of the i-th horizontal segment at the ending point of the i-1-th vertical segment; Place the starting point of the i-th vertical segment at the ending point of the i-th horizontal segment; Update i to i+1; Wherein, i is a positive integer. When i=1, the starting point of the i-th horizontal segment coincides with the starting point of the irregular edge.

7. The method according to claim 1, characterized in that The step of performing mask optimization on the intermediate mask layout based on the initial mask layout to obtain a target mask layout includes: Placing evaluation points in the intermediate mask layout and mapping the evaluation points back to the initial mask layout; Inputting the intermediate mask pattern into a lithography simulation model to perform lithography simulation to obtain a simulation profile; Comparing evaluation point parameters corresponding to the simulated contour with evaluation point parameters corresponding to an ideal contour to determine layout differences, wherein the ideal contour is determined based on the initial mask layout; When the layout difference does not meet the preset conditions, the intermediate mask layout is iteratively adjusted according to the layout difference to obtain an updated intermediate mask layout, until the layout difference meets the preset conditions, and the updated intermediate mask layout is determined as the target mask layout.

8. A photolithography mask optimization device, characterized in that: The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the photolithography mask optimization method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the photolithography mask optimization method according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device is caused to execute the photolithography mask optimization method according to any one of claims 1 to 7.

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