Transient response enhanced LDO composite circuit and module with high voltage compensation

Abstract

The present invention provides a transient response enhanced LDO composite circuit and module with high-voltage compensation, which relates to the technical field of CMOS image sensor design. The LDO composite circuit of the present invention includes: a charge pump, a low-voltage dropout linear regulator, a high-voltage compensation circuit, and a transient response enhancement circuit. On the one hand, the present invention connects the relay voltage VCP output by the charge pump to the high-voltage compensation circuit to provide a compensation signal Vf to VCP. On the other hand, the transient response enhancement circuit is connected between the gate of the error amplifier EA in the low-voltage dropout linear regulator and the output signal Vout to control the conduction amplitude of the power tube Mp, so that the entire composite circuit is connected to the external load C load When , the high-voltage compensation circuit generates a Vf with a value of 2VDD and performs high-voltage compensation on VCP. The transient response enhancement circuit increases the conduction amplitude of Mp to enable Vout to recover quickly.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensor (CIS) design, and more specifically to: 1. a transient response enhanced LDO composite circuit with high-voltage compensation; 2. a transient response enhanced LDO composite module with high-voltage compensation; and 3. a CIS module integrating the transient response enhanced LDO composite module with high-voltage compensation. Background Art

[0002] With the increasing popularity of mobile phones, digital cameras, and other photographic products, higher requirements are being placed on image clarity. Providing a control voltage higher than the power supply voltage to CMOS image sensor (CIS) pixels can effectively reduce noise and improve image quality.

[0003] To provide pixels with a stable control voltage higher than the power supply voltage, a combination circuit of an LDO (low dropout regulator) and a charge pump (CP) is typically integrated into the chip. A key requirement for image signal processing is minimizing the output voltage recovery time after an undershoot. However, existing LDO combination circuits suffer from long output voltage recovery times and poor transient response, requiring optimization.

[0004] Furthermore, although some researchers have applied compensation technology to LDO composite circuits, effectively reducing the output voltage recovery time through additional charge injection, this approach requires additional components in the LDO composite circuit, which can easily introduce capacitor discharge noise into the output voltage, increasing output ripple and affecting image quality. Summary of the Invention

[0005] Based on the problem that the existing LDO composite circuit has a low transient response, it is necessary to provide a transient response enhanced LDO composite circuit and module with high voltage compensation.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a transient response enhanced LDO composite circuit with high-voltage compensation, comprising: a charge pump, a low-dropout linear regulator, a high-voltage compensation circuit, and a transient response enhancement circuit.

[0008] The charge pump is used to boost the input signal Vin to obtain the relay voltage VCP.

[0009] The low-dropout linear regulator (LDO) is used to regulate VCP to generate the output signal Vout. The LDO includes an error amplifier (EA) and a power transistor (MP). Mp's gate is connected to EA's output terminal (VG), its source is connected to VCP, and its drain is connected to Vout.

[0010] The high-voltage compensation circuit is connected to the VCP and is used to provide a compensation signal Vf to the VCP.

[0011] The transient response enhancement circuit is connected to VG and Vout and is used to control the conduction amplitude of Mp.

[0012] Among them, when the LDO composite circuit is not connected to the external load C load When Vf is equal to VCP, the transient response enhancement circuit does not work.

[0013] Connect the external load C to the LDO composite circuit. load When Vf is 2VDD, high voltage compensation is performed on VCP, and the transient response enhancement circuit increases the conduction amplitude of Mp to enable Vout to recover quickly.

[0014] The implementation of the transient response enhanced LDO composite circuit with high voltage compensation is based on the method or process of an embodiment of the present disclosure.

[0015] In a second aspect, the present invention discloses a transient response enhanced LDO composite module with high voltage compensation, which adopts the layout of the transient response enhanced LDO composite circuit with high voltage compensation disclosed in the first aspect.

[0016] The implementation of the transient response enhanced LDO composite module with high voltage compensation is based on the method or process of an embodiment of the present disclosure.

[0017] In a third aspect, the present invention discloses a CIS module, which integrates the transient response enhanced LDO composite module with high voltage compensation disclosed in the first aspect.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention provides a transient response enhanced LDO composite circuit with high voltage compensation. On the one hand, the intermediate voltage VCP output by the charge pump is connected to the high voltage compensation circuit to provide a compensation signal Vf to VCP. On the other hand, the transient response enhancement circuit is connected between the gate of the error amplifier EA in the low voltage drop linear regulator and the output signal Vout to control the conduction amplitude of the power tube Mp, so that the entire composite circuit is connected to the external load C loadWhen the voltage is low, the high-voltage compensation circuit generates a Vf of 2VDD and performs high-voltage compensation on VCP. The transient response enhancement circuit increases the conduction amplitude of Mp to enable Vout to recover quickly, thereby solving the problem of low transient response in the existing LDO composite circuit.

[0020] 2. Although the present invention carries out circuit design based on compensation technology, simulation shows that it does not introduce capacitor discharge noise, and on this premise improves transient response and shortens output voltage recovery time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 FIG. 4 is a circuit diagram of an existing LDO composite circuit.

[0023] Figure 2 This is a circuit diagram of a transient response enhanced LDO composite circuit with high voltage compensation provided in Example 1 of the present invention.

[0024] Figure 3 for Figure 2 Circuit diagram of the high-voltage compensation circuit in .

[0025] Figure 4 for Figure 2 Circuit diagram of the transient response enhancement circuit.

[0026] Figure 5 for Figure 2 The timing and voltage diagram of the transient response enhanced LDO composite circuit with high-voltage compensation.

[0027] Figure 6 for Figure 1 Output voltage waveform of the existing LDO composite circuit.

[0028] Figure 7 for Figure 2 Output voltage waveform of the transient response enhanced LDO composite circuit with high-voltage compensation. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0030] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] First see Figure 1 , which shows a typical design structure of the existing LDO composite circuit, which is composed of a charge pump and a low-dropout linear regulator.

[0033] 1. The charge pump is used to boost the input signal Vin to obtain the relay voltage VCP.

[0034] The charge pump can be Figure 1 The design includes: 1 switched capacitor charge pump SC-CP, 1 filter capacitor C fil The input of SC-CP is connected to Vin, and the output is connected to VCP; C fil One end is connected to VCP and the other end is connected to GND.

[0035] Of course, the charge pump may also adopt other designs, but it should meet the above functional requirements.

[0036] 2. The low-dropout linear regulator is used to stabilize VCP to obtain the output signal Vout.

[0037] Low dropout linear regulators can be used as Figure 1The design includes at least one power tube Mp. The gate of Mp is connected to the control voltage VG, the source is connected to VCP, and the drain is connected to Vout. Of course, in order to ensure the efficiency of the voltage regulation process, the low voltage drop linear regulator can also include an error amplifier EA, two feedback resistors R1~R2, and a filter capacitor C. out The same-direction input of EA is connected to the feedback signal Vfb, the reverse input is connected to the input signal Vref, and the output is connected to VG; the first end of R1 is connected to the drain of Mp, C out The first end of R2 and the second end of R2 are connected to Vfb; the second end of R2 and C out The second end is grounded GND.

[0038] Of course, the low-dropout linear regulator adopts other designs, but it should be ensured that VCP is connected to Vout through MP.

[0039] Example 1

[0040] See Figure 1 The circuit diagram of a transient response enhanced LDO composite circuit with high voltage compensation (hereinafter referred to as the present LDO composite circuit) provided in this embodiment 1 is shown. Figure 1 The existing LDO composite circuit is improved.

[0041] Functionally, this LDO composite circuit consists of four parts: a charge pump, a low-dropout linear regulator, a high-voltage compensation circuit, and a transient response enhancement circuit.

[0042] The structure and function of the charge pump and low-dropout linear regulator remain unchanged and are not further described here. The high-voltage compensation circuit is connected to VCP and provides a compensation signal, Vf, to VCP. The transient response enhancement circuit is connected to VG and Vout to control the conduction amplitude of Mp.

[0043] In summary:

[0044] In this LDO composite circuit, no external load C is connected. load When Vf is equal to VCP, the transient response enhancement circuit does not work.

[0045] In this LDO composite circuit, an external load C is connected. load When Vf is 2VDD, high voltage compensation is performed on VCP, and the transient response enhancement circuit increases the conduction amplitude of Mp to enable Vout to recover quickly.

[0046] The following is a detailed introduction to the high-voltage compensation circuit and transient response enhancement circuit:

[0047] ①, see Figure 3The high-voltage compensation circuit includes: a micro charge pump unit, three NMOS transistors Mn3~Mn5, three PMOS transistors Mp1~Mp3, and a pump capacitor C13.

[0048] First, the micro charge pump unit is used to generate the relay voltage VCP1 by combining the power supply VDD under the control of the control signals CLK1 ˜ CLK2 .

[0049] like Figure 2 As shown, the micro-charge pump section can be designed to include: two NMOS transistors Mn1 and Mn2, and two pumping capacitors C11 and C12. The drain of Mn1 is connected to VDD; the drain of Mn2 is connected to VDD, and the gate is connected to the source of Mn1; the source of Mn2 is connected to the gate of Mn1 for outputting VCP1; the first end of C11 is connected to the source of Mn1, and the second end is connected to CLK1; the first end of C12 is connected to the source of Mn2, and the second end is connected to CLK2.

[0050] Then we have:

[0051] In this LDO composite circuit, no external load C is connected. load When CLK1=VDD, CLK2=0, the first end of C11 is initialized to VDD and the first end of C12 is initialized to 0 due to charge transfer, Mn1 is turned off, Mn2 is turned on, C11 discharges to the gate of Mn2, and VDD charges the first end of C12 and VCP1 to VDD through Mn2.

[0052] In this LDO composite circuit, an external load C is connected. load When CLK1=0 and CLK2=VDD, the charge transfer causes the first terminal of C12 to become 2VDD, thereby causing VCP1 to become 2VDD, Mn1 to turn on, and VDD charges C11 (whose first terminal becomes less than VDD due to the previous discharge to the gate of Mn2) through Mn1; the gate and source voltages of Mn2 are VDD, and the drain voltage is 2VDD, causing Mn2 to turn off.

[0053] In addition, it should be noted that if this LDO composite circuit is combined with C load Periodically connected or disconnected, then, when no external load C is connected load When , the first end of C11 will be initialized to 2VDD, and the first end of C12 will be initialized to less than VDD.

[0054] Of course, the micro charge pump unit can also be designed in other ways, but it should meet the above-mentioned control requirements of CLK1, CLK2, and VCP1.

[0055] Secondly, for the other parts of the high-voltage compensation circuit, the specific connection method is:

[0056] The source of Mp1 is connected to VCP1, and the gate is connected to CLK1;

[0057] The source of Mn3 is connected to the ground GND, and the gate is connected to CLK1;

[0058] The drain of Mn3 is connected to the drain of Mp1 and is used to output the relay voltage Vck;

[0059] The source of Mp2 is connected to VDD, and the gate is connected to CLK1;

[0060] The source of Mn4 is connected to the ground GND, the gate is connected to CLK1, and the drain is connected to the drain of Mp2;

[0061] The source of Mp3 is connected to VDD, and the gate is connected to Vck;

[0062] The source of Mn5 is used to output Vf, which is connected to VCP;

[0063] The drain of Mn5 is connected to the drain of Mp3, and the gate is connected to Vck;

[0064] A first end of C13 is connected to the drain of Mp2, and a second end of C13 is connected to the drain of Mp3.

[0065] Then we have:

[0066] In this LDO composite circuit, no external load C is connected. load When CLK1=VDD, CLK2=0, VCP1=VDD, Mp1 is turned off, Mn3 is turned on, and Vck is discharged to GND through Mn3 to 0; Mp2 and Mn5 are turned off, Mp3 and Mn4 are turned on, VDD, Mp3, C13, Mn4, and GND form a path, and C13 is charged so that the voltage difference between its second end and the first end is VDD (based on the Figure 3 For example, the voltage difference between the right and left ends of C13 is VDD).

[0067] In this LDO composite circuit, an external load C is connected. load When CLK1=0, CLK2=VDD, VCP1=2VDD, then Mp1 is turned on, Mn3 is turned off, VCP1 is connected to Vck through Mp1, making Vck=2VDD; Mp2 and Mn5 are turned on, Mp3 and Mn4 are turned off, VDD, Mp2, C13, Mn5, and VCP form a path, and C13 discharges - the first end of C13 is VDD, and because there is a voltage difference of VDD at both ends of C13, the second end of C13 becomes 2VDD through charge transfer, and Vf also becomes 2VDD through Mn5, thereby providing additional charge to VCP for high-voltage compensation.

[0068] It should be noted that Vck needs to reach 2VDD to turn on Mn5 and turn off Mp3. This is because:

[0069] See above, in this LDO composite circuit, no external load C is connected. load When the second terminal of C13 is VDD and 2VDD respectively, the drain voltage of Mp3 (or Mn5) is VDD and 2VDD respectively. Then, when the drain voltage of Mp3 is 2VDD, the timing of VDD cannot turn it off, so Vck needs to reach the timing of 2VDD.

[0070] ②, see Figure 4 The transient response enhancement circuit includes: 3 PMOS transistors Mp4~Mp6, 3 NMOS transistors Mn6~Mn9, and 2 pump capacitors C14~C15.

[0071] like Figure 4 As shown in the figure, the specific connection method of each component in the transient response enhancement circuit is:

[0072] The source of Mp4 is connected to VDD;

[0073] The drain of Mn6 is connected to the drain of Mp4 and the gate of Mp4, the gate is connected to the control signal Vb, and the source is grounded GND;

[0074] The source of Mp5 is connected to VDD, and the gate is connected to the gate of Mp4;

[0075] The source of Mn7 is connected to the ground GND, the gate is connected to the gate of Mp5, and the drain is connected to the gate of Mp5;

[0076] The source of Mp6 and the gate of Mp6 are connected to VDD;

[0077] The source of Mn8 is connected to the ground GND; the drain and gate of Mn8 are connected to the drain of Mp6;

[0078] The source of Mn9 is connected to the ground GND, the drain is connected to VG, and the gate is connected to the gate of Mn8;

[0079] The first end of C14 is connected to Vout, and the second end is connected to the gate of Mp5;

[0080] A first end of C15 is connected to the drain of Mp5, and a second end of C15 is connected to the drain of Mp6.

[0081] Among them, Mp4 and Mp5 form a current mirror.

[0082] It should be noted that 0<Vb<VDD / 2, which makes Mn6 in a moderately conductive state and provides bias current to Mp4 and Mp5.

[0083] Then we have:

[0084] In this LDO composite circuit, no external load C is connected. load When , the transient response enhancement circuit does not work, Mn9 is turned off, and VG is not affected by the transient response enhancement circuit.

[0085] In this LDO composite circuit, an external load C is connected. load When C load with C out Charge transfer occurs between the two terminals, causing Vout to drop. The voltage change of Vout is coupled to the current mirror (the gates of Mp4 and Mp5) through C14, increasing the drain voltage of Mp5. This voltage is then coupled to the gate of Mn9 through C15, increasing the leakage current of Mn9. Since the drain of Mn9 is connected to VG, which in turn is connected to the gate of Mp, the gate voltage of Mp decreases, the conduction amplitude of Mp increases, and the current flowing through Mp increases, thereby enhancing Mp's drive capability. Combined with the high-voltage compensated VCP, Vout can quickly return to stability.

[0086] For easier understanding, see Figure 5 , which shows the timing voltage changes of CLK1, CLK2, VCP1, and Vck, which is consistent with the above principle introduction.

[0087] Based on the above circuit design and corresponding timing control, a high transient response of the LDO composite circuit is achieved, so that Vout can quickly recover and stabilize.

[0088] Simulation Verification

[0089] This embodiment 1 also compares the performance of the existing LDO composite circuit and the present LDO composite circuit:

[0090] The simulation conditions are: based on 0.13μm CMOS process; cycle frequency is 20MHz; VDD=3.3V; C out The tt process angle simulation is carried out at room temperature to obtain the output voltage waveforms of the two circuits. Figure 6 The output voltage waveform of the existing LDO composite circuit is shown; Figure 7 The output voltage waveform of this LDO composite circuit is shown.

[0091] contrast Figure 6 、 Figure 7 It can be seen that: the two circuits are connected to C load When the voltage drops, Vout will drop by 139mV. However, the recovery time of the existing LDO composite circuit is 206ns, while the recovery time of the LDO composite circuit is 59ns, which is a 71% reduction in recovery time.

[0092] It should also be emphasized that the output ripple of both circuits is 275μVpp, indicating that although this LDO composite circuit uses compensation technology, it does not introduce capacitor plate discharge noise.

[0093] Example 2

[0094] This embodiment 2 discloses a transient response enhanced LDO composite module with high voltage compensation, which adopts the layout of the transient response enhanced LDO composite circuit with high voltage compensation disclosed in embodiment 1. The module packaging mode facilitates the promotion and application of the above circuit.

[0095] This embodiment 2 also discloses a CIS module, which includes the above-disclosed transient response enhanced LDO composite module with high voltage compensation. Integrating the above-disclosed transient response enhanced LDO composite module with high voltage compensation into the CIS module also facilitates the promotion and application of the above-disclosed circuit.

[0096] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A transient response enhanced LDO composite circuit with high voltage compensation, comprising: Charge pump, low dropout linear regulator; The charge pump is used to boost the input signal Vin to obtain the relay voltage VCP; The low-voltage-dropout linear regulator is used to stabilize VCP to obtain an output signal Vout. The low-voltage-dropout linear regulator includes: a power transistor Mp; the gate of Mp is connected to the control voltage VG, the source is connected to VCP, and the drain is connected to Vout; and is characterized in that it also includes: a high-voltage compensation circuit connected to the VCP and configured to provide a compensation signal Vf to the VCP; and A transient response enhancement circuit, which is connected to VG and Vout and is used to control the conduction amplitude of Mp; Among them, when the LDO composite circuit is not connected to the external load C load When Vf and VCP are kept equal, the transient response enhancement circuit does not work; when the LDO composite circuit is connected to the external load C load When Vf is 2VDD and high voltage compensation is performed on VCP, the transient response enhancement circuit increases the conduction amplitude of Mp to enable Vout to recover quickly. The high-voltage compensation circuit includes: a micro charge pump unit, three NMOS transistors Mn3 to Mn5, three PMOS transistors Mp1 to Mp3, and a pump capacitor C13; The micro charge pump unit is used to generate a relay voltage VCP1 in combination with the power supply VDD under the control of the control signals CLK1-CLK2; The source of Mp1 is connected to VCP1, and the gate is connected to CLK1; The source of Mn3 is connected to the ground GND, and the gate is connected to CLK1; The drain of Mn3 is connected to the drain of Mp1 and is used to output the relay voltage Vck; The source of Mp2 is connected to VDD, and the gate is connected to CLK1; The source of Mn4 is connected to the ground GND, the gate is connected to CLK1, and the drain is connected to the drain of Mp2; The source of Mp3 is connected to VDD, and the gate is connected to Vck; The source of Mn5 is used to output Vf, which is connected to VCP; The drain of Mn5 is connected to the drain of Mp3, and the gate is connected to Vck; A first end of C13 is connected to the drain of Mp2, and a second end of C13 is connected to the drain of Mp3.

2. The transient response enhanced LDO composite circuit with high voltage compensation according to claim 1, characterized in that: The micro charge pump unit includes: two NMOS transistors Mn1~Mn2, two pump capacitors C11~C12; The drain of Mn1 is connected to VDD; The drain of Mn2 is connected to VDD, and the gate is connected to the source of Mn1; The source of Mn2 is connected to the gate of Mn1 for outputting VCP1; The first end of C11 is connected to the source of Mn1, and the second end is connected to CLK1; A first end of C12 is connected to the source of Mn2, and a second end of C12 is connected to CLK2.

3. The transient response enhanced LDO composite circuit with high voltage compensation according to claim 2, characterized in that: When the LDO composite circuit is not connected to an external load C load When CLK1=VDD, CLK2=0, VCP1=VDD; when the LDO composite circuit is connected to the external load C load When CLK1=0, CLK2=VDD, VCP1=2VDD.

4. The transient response enhanced LDO composite circuit with high voltage compensation according to claim 3, characterized in that: The transient response enhancement circuit includes: three PMOS transistors Mp4 to Mp6, three NMOS transistors Mn6 to Mn9, and two pump capacitors C14 to C15; The source of Mp4 is connected to VDD; The drain of Mn6 is connected to the drain of Mp4 and the gate of Mp4, the gate is connected to the control signal Vb, and the source is grounded GND; The source of Mp5 is connected to VDD, and the gate is connected to the gate of Mp4; The source of Mn7 is connected to the ground GND, the gate is connected to the gate of Mp5, and the drain is connected to the drain of Mp5; The source of Mp6 and the gate of Mp6 are connected to VDD; The source of Mn8 is connected to the ground GND; the drain and gate of Mn8 are connected to the drain of Mp6; The source of Mn9 is connected to the ground GND, the drain is connected to VG, and the gate is connected to the gate of Mn8; The first end of C14 is connected to Vout, and the second end is connected to the gate of Mp5; A first end of C15 is connected to the drain of Mp5, and a second end of C15 is connected to the drain of Mp6.

5. The transient response enhanced LDO composite circuit with high voltage compensation according to claim 4, characterized in that: 0<Vb<VDD / 2.

6. The transient response enhanced LDO composite circuit with high voltage compensation according to claim 1, characterized in that: The charge pump includes: 1 switched capacitor charge pump SC-CP, 1 filter capacitor C fil ; The input of SC-CP is connected to Vin, and the output is connected to VCP; C fil One end is connected to VCP and the other end is connected to GND.

7. The transient response enhanced LDO composite circuit with high voltage compensation according to claim 1, characterized in that: The low-dropout linear regulator also includes: an error amplifier EA, two feedback resistors R1~R2, and a filter capacitor C out ; The same-direction input terminal of EA is connected to the feedback signal Vfb, the reverse input terminal is connected to the input signal Vref, and the output terminal is connected to VG; The first end of R1 is connected to the drain of Mp, C out The first end of R2 and the second end of R2 are connected to Vfb; the second end of R2 and C out The second end is grounded GND.

8. A transient response enhanced LDO composite module with high voltage compensation, characterized in that: It adopts the layout of the transient response enhanced LDO composite circuit with high voltage compensation as described in any one of claims 1 to 7.

9. A CIS module, characterized in that: It integrates the transient response enhanced LDO composite module with high voltage compensation as claimed in claim 8.

Images