Control circuit, operating method and non-transitory computer readable storage medium

Abstract

A control circuit comprises a storage circuit and a processor. The storage circuit is used for storing a reread sequence table and a plurality of read voltage tables. The processor is coupled to the memory circuit for accessing a memory including a plurality of blocks. When a read error occurs in a first block of the plurality of blocks, the processor sequentially performs a reread test on the first block by using the plurality of read voltage tables according to a reread order indicated by the reread order table. When the reread historical data of the first block meets the adjustment condition, the processor adjusts the reread sequence indicated by the reread sequence table. Therefore, the reading efficiency and correctness of the memory can be improved.

Description

Technical Field

[0001] The present disclosure relates to memory technology, and more particularly to a control circuit, an operating method, and a non-transitory computer-readable storage medium for improving memory access efficiency. Background Art

[0002] The aging state of a memory device changes with environmental factors such as temperature, humidity, time, and the number of read and write cycles. Memory devices typically store multiple sets of compensation voltages provided by the memory manufacturer. Each set of compensation voltages is used to adjust the word line voltage used by the memory device during read operations. When a read failure occurs, the memory device typically selects an appropriate set of compensation voltages based on the current memory aging state for subsequent read operations. However, existing memory devices require considerable time to search for the appropriate set of compensation voltages, resulting in very low read efficiency. Summary of the Invention

[0003] The present disclosure relates to a control circuit comprising a memory circuit and a processor. The memory circuit is configured to store a reread sequence table and multiple read voltage tables. The processor is coupled to the memory circuit and configured to access a memory comprising multiple blocks. When a read error occurs in a first block among the multiple blocks, the processor performs a reread test on the first block using the multiple read voltage tables in sequence according to a reread sequence indicated by the reread sequence table. When reread history data for the first block meets an adjustment condition, the processor adjusts the reread sequence indicated by the reread sequence table.

[0004] In one embodiment, when a first block is in a programmed state and the reread history data of the first block indicates that a reread test has never been performed on the first block, the processor is configured to adjust the reread order indicated by the reread order table based on the reread history data of the second block in a programmed state before performing the reread test on the first block; wherein the first block and the second block enter the programmed state sequentially.

[0005] In one embodiment, the reread history data of the second block includes a block reread parameter of the second block. The block reread parameter of the second block represents a corresponding one of the plurality of read voltage tables used when the processor successfully performs a reread test on the second block. The processor updates the first order of the reread sequence using the block reread parameter of the second block.

[0006] In one embodiment, the storage circuit is further configured to store a link table, the link table being configured to record a plurality of programming blocks in a programmed state among the plurality of blocks. The processor is configured to sequentially record the plurality of programming blocks in the link table according to the order in which the plurality of programming blocks enter the programmed state. The plurality of programming blocks include a first block and a second block, and the processor records in the link table that the first block and the second block successively enter the programmed state.

[0007] In one embodiment, when the processor erases one of the plurality of programming blocks, the processor removes the record of the one of the plurality of programming blocks from the link table.

[0008] In one embodiment, the reread sequence includes M priority levels, where M is a positive integer greater than 1. When the processor successfully performs a reread test on the first block using a target read voltage table from the plurality of read voltage tables, the processor records the Nth priority level of the target read voltage table in the reread history data of the first block. When N is greater than or equal to a threshold, the processor adjusts the Nth priority level to the first priority level in the reread sequence, where N is a positive integer.

[0009] In one embodiment, when N is less than a threshold, the processor does not adjust the reread order.

[0010] In one embodiment, the threshold is in the range of 2 to M / 2.

[0011] The present disclosure also relates to an operating method applicable to a control circuit for accessing a memory including a plurality of blocks and storing a reread sequence table and a plurality of read voltage tables. The operating method includes: when a read error occurs in a first block among the plurality of blocks, performing a reread test on the first block using the plurality of read voltage tables in sequence according to a reread sequence indicated by the reread sequence table; and adjusting the reread sequence indicated by the reread sequence table when reread history data of the first block meets an adjustment condition.

[0012] In one embodiment, when the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table includes: when the first block is in a programmed state and the reread history data of the first block indicates that a reread test has never been performed, before performing a reread test on the first block, adjusting the reread order indicated by the reread order table based on the reread history data of the second block in a programmed state; wherein the first block and the second block enter the programmed state successively.

[0013] In one embodiment, the reread history data of the second block includes block reread parameters of the second block, and the block reread parameters of the second block represent a corresponding one of the plurality of read voltage tables used by the control circuit when successfully performing a reread test on the second block; wherein adjusting the reread order indicated by the reread order table based on the reread history data of the second block in the programmed state includes: updating a first order of the reread order using the block reread parameters of the second block.

[0014] In one embodiment, the control circuit is further configured to store a link table, the link table being configured to record a plurality of programming blocks in a programmed state among the plurality of blocks; wherein the control circuit is configured to sequentially record the plurality of programming blocks in the link table according to an order in which the plurality of programming blocks enter the programmed state; wherein the plurality of programming blocks include a first block and a second block, and the control circuit records in the link table that the first block and the second block successively enter the programmed state.

[0015] In one embodiment, when the control circuit erases one of the plurality of programming blocks, the control circuit removes the record of the one of the plurality of programming blocks from the link table.

[0016] In one embodiment, the reread sequence includes M ranks, where M is a positive integer greater than 1; wherein sequentially using the multiple read voltage tables to perform a reread test on the first block includes: when the reread test is successfully performed on the first block using a target read voltage table among the multiple read voltage tables, recording the Nth rank of the target read voltage table in the reread sequence table in the reread history data of the first block; wherein when the reread history data of the first block meets the adjustment condition, adjusting the reread sequence indicated by the reread sequence table includes: when N is greater than or equal to a threshold, adjusting the Nth rank to the first rank in the reread sequence, wherein N is a positive integer.

[0017] In one embodiment, when the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table further includes: when N is less than a threshold, not adjusting the reread order.

[0018] In one embodiment, the threshold is in the range of 2 to M / 2.

[0019] The present disclosure also relates to a non-transitory computer-readable storage medium comprising a plurality of computer-readable instructions. When executed by a processor, the plurality of computer-readable instructions cause the processor to access a memory comprising a plurality of blocks and perform the following operations: when a read error occurs in a first block among the plurality of blocks, performing a reread test on the first block using a plurality of read voltage tables in sequence according to a reread order indicated by a reread order table, wherein the reread order table and the plurality of read voltage tables are stored in a memory circuit coupled to the processor; and when reread history data of the first block meets an adjustment condition, adjusting the reread order indicated by the reread order table.

[0020] In one embodiment, when the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table includes: when the first block has a programmed state and the reread history data of the first block indicates that a reread test has never been performed, before performing a reread test on the first block, adjusting the reread order indicated by the reread order table according to the reread history data of the second block having a programmed state, wherein the first block and the second block enter the programmed state successively.

[0021] In one embodiment, the reread history data of the second block includes block reread parameters of the second block, and the block reread parameters of the second block represent a corresponding one of the plurality of read voltage tables used when the processor successfully performs a reread test on the second block; wherein adjusting the reread order indicated by the reread order table based on the reread history data of the second block in the programmed state includes: updating a first order of the reread order using the block reread parameters of the second block.

[0022] In one embodiment, the reread sequence includes M sequences, where M is a positive integer greater than 1; wherein sequentially using the multiple read voltage tables to perform a reread test on the first block includes: when the reread test is successfully performed on the first block using a target read voltage table from the multiple read voltage tables, recording the Nth sequence of the target read voltage table in the reread history data of the first block; wherein when the reread history data of the first block meets the adjustment condition, adjusting the reread sequence indicated by the reread sequence table includes: when N is greater than or equal to a threshold, adjusting the Nth sequence to the first sequence in the reread sequence, where N is a positive integer; and when N is less than the threshold, not adjusting the reread sequence.

[0023] Therefore, by dynamically adjusting the reread order indicated by the reread order table, the number of repetitions required by the processor when performing the reread test can be reduced, thereby improving the efficiency and accuracy of memory reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. 1 is a simplified functional block diagram of an electronic system according to an embodiment of the present disclosure.

[0025] Figure 2 FIG. 1 is a schematic diagram of a mapping table according to an embodiment of the present disclosure.

[0026] Figure 3 FIG. 1 is a schematic diagram of a voltage reading table according to an embodiment of the present disclosure.

[0027] Figure 4 FIG. 1 is a flow chart of an operating method according to an embodiment of the present disclosure.

[0028] Figure 5FIG. 1 is a schematic diagram of a rereading order table according to an embodiment of the present disclosure.

[0029] Figure 6 FIG. 1 is a schematic diagram of a link table according to an embodiment of the present disclosure.

[0030] Figure 7 FIG. 1 is a schematic diagram showing that a rereading order table is adjusted according to a linking table according to an embodiment of the present disclosure.

[0031] Figure 8 FIG. 1 is a schematic diagram showing an adjustment of a rereading order table according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The following drawings illustrate various embodiments of the present invention. For clarity, many practical details are included in the following description. However, it should be understood that these practical details are not intended to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not essential. Furthermore, to simplify the drawings, some conventional structures and components are depicted in simplified schematic form.

[0033] As used herein, when an element is referred to as being "connected" or "coupled," it may refer to being "electrically connected" or "electrically coupled." "Connected" or "coupled" may also refer to the coordinated operation or interaction between two or more elements. Furthermore, while terms such as "first," "second," and so on are used herein to describe different elements, these terms are intended solely to distinguish between elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms are not intended to specifically designate or imply an order or sequence, nor are they intended to limit the present invention.

[0034] As used herein, "about," "approximately," or "roughly approximately" generally refers to an error or range of a numerical value within 20%, preferably within 10%, and more preferably within 5%. Unless otherwise specified, the numerical values mentioned are deemed to be approximate values, that is, the error or range indicated by "about," "approximately," or "roughly approximately."

[0035] Figure 1 The figure is a simplified functional block diagram of an electronic system 100 according to one embodiment of the present disclosure. The electronic system 100 includes a control circuit 110 and a memory 120. The control circuit 110 is communicatively coupled to an external computing circuit (not shown), such as a central processing unit (CPU), to perform corresponding read, write, or erase operations on the memory 120 based on read, write, and erase commands provided by the external computing circuit. In some embodiments, the memory 120 can be implemented as a flash memory (e.g., a NAND memory) or other suitable non-volatile memory.

[0036] The memory 120 includes a plurality of logic units L0-L1 (LUN, or also called die), such as Figure 1 As shown, each of the logic units L0 ˜ L1 includes a plurality of blocks. For example, the logic unit L0 includes blocks B0 ˜ B49 , and the logic unit L1 includes blocks B50 ˜ B99 .

[0037] The control circuit 110 includes a processor 112 and a storage circuit 114 . The processor 112 is coupled to the storage circuit 114 and communicatively coupled to a plurality of logic units L0 - L1 of the memory 120 for performing access operations such as reading, writing or erasing on the storage circuit 114 and the memory 120 .

[0038] In some embodiments, the processor 112 includes, but is not limited to, a single processor and an integration of multiple microprocessors. The processor 112 can be implemented as a central processing unit (CPU), a system on a chip (SoC), an application processor, a digital signal processor, or a processing chip or controller for a specific function.

[0039] The storage circuit 114 stores a mapping table TA, a plurality of read voltage tables TB0-TBk, and a reread sequence table TC, where k is a positive integer greater than 1. In one embodiment, the storage circuit 114 is an internal memory of the control circuit 110, but the present disclosure is not limited thereto. Figure 1 The numbers of logic units, blocks, and read voltage tables are only examples, and the present disclosure is not limited thereto.

[0040] Figure 2 Schematic diagram of a mapping table TA according to an embodiment of the present disclosure. The mapping table TA includes a plurality of index values 0-k and records the corresponding relationship between each index value and each read voltage table TB0-TBk. Figure 2 As shown, index values 0-k correspond to read voltage tables TB0-TBk respectively.

[0041] Figure 3 This is a schematic diagram of a read voltage table TB (including TB0-TBk) according to an embodiment of the present disclosure. Figures 1 to 3 To illustrate the application of reading the voltage table TB0~TBk. Figure 3As shown, each read voltage table TB0-TBk records a plurality of threshold voltage offsets. Among them, "threshold voltage (Vth)" is the reference voltage value used by the processor 112 when reading the memory 120. When the threshold voltage is "1.5V", the processor 112 uses this threshold voltage as a reference to determine whether the data stored in each block in the memory 120 is a bit value of "0" or "1". For example, when the processor 112 reads the voltage in the block as "1.2V", since 1.2V is less than 1.5V, the result read by the processor 112 is a bit value of "0". In contrast, when the processor 112 reads the voltage in the block as "2V", since 2V is greater than 1.5V, the result read by the processor 112 is a bit value of "1".

[0042] As mentioned above, since the data in the memory 120 is easily affected by access operations (i.e., read, write, erase) and environmental factors (such as temperature) and may cause errors, when the processor 112 detects that the data in the memory 120 has errors, it will need to adjust the threshold voltage (e.g., increase 1.5V to 1.7V) to reduce the impact of these erroneous data. This operation is called a "retry read test."

[0043] The number of "threshold voltage offsets" in the read voltage tables TB0-TBk depends on the type of memory 120. When reading from the memory 120, the processor 112 sequentially applies multiple threshold voltages to the word lines according to the selected read voltage table to determine the bit values stored in the memory cells of the memory 120. Since those skilled in the art are familiar with the method for detecting errors in memory, it will not be further described here.

[0044] For example, in an embodiment where the memory 120 is a multi-level cell (MLC) memory, the processor 112 applies three different threshold voltages to the word lines in sequence. Figure 3 As shown, each of the read voltage tables TB0-TBk records a first threshold voltage offset, a second threshold voltage offset, and a third threshold voltage offset. The processor 112 adjusts the threshold voltage applied to the word lines based on the offsets recorded in the read voltage tables TB0-TBk to compensate for variations in the memory 120 under different usage conditions (e.g., ambient temperature or total usage hours).

[0045] Similarly, if the memory 120 is a triple-level cell (TLC) memory, each read voltage table records seven threshold voltage offsets. The processor 112 adjusts the threshold voltage applied to the word line based on the offsets recorded in the read voltage table. For the sake of brevity, this description is not repeated here.

[0046] Figure 4 FIG4 is a flow chart of an operating method 400 according to one embodiment of the present disclosure. Any combination of features of the operating method 400 may be implemented as a plurality of computer-readable instructions stored in a non-transitory computer-readable storage medium. When these instructions are executed by the processor 112, these instructions will cause part or all of the operating method 400 to be performed.

[0047] Please also refer to Figure 4 and Figure 5 ,in Figure 5 FIG4 is a diagram illustrating a reread sequence table TC according to an embodiment of the present disclosure. In step S410, when a read error occurs in a block (e.g., block 99) among blocks B0-B99, the processor 112 sequentially finds the corresponding read voltage tables according to the reread sequence indicated by the reread sequence table TC and sequentially performs a reread test on the block where the read error occurred according to each read voltage table.

[0048] In some embodiments, the "reread order" is associated with the order of the index values in the reread order table TC. For example, if the first through seventh columns of the reread order table TC sequentially record the index values "4, 1, 2, 3, 5, 6, 7," the processor 112 will sequentially use read voltage tables TB4, TB1, TB2, TB3, TB5, TB6, and TB7 to perform a reread test on blocks experiencing read errors. In other words, the reread order can be understood as the order in which the processor 112 uses read voltage tables TB0-TBk during the reread test. It's worth noting that the reread order does not necessarily need to match the order of the fields in the reread order table TC.

[0049] In step S420, while performing a reread test according to the reread sequence indicated by the reread sequence table TC, the processor 112 monitors the reread history data of the block (e.g., block 99) where a read error occurred to determine whether the reread history data meets an adjustment condition. If the reread history data meets the adjustment condition, the processor 112 adjusts the reread sequence indicated by the reread sequence table TC (i.e., adjusts the arrangement of the index values in the reread sequence table TC). In other words, the arrangement of the index values in the reread sequence table TC will dynamically change. The "adjustment condition" and "adjustment method" used by the processor 112 to adjust the reread sequence table TC can be pre-stored / set in the control circuit 110.

[0050] In one embodiment, the storage circuit 114 also stores a linked table TD. The linked table TD is used to record the blocks in the programmed state (i.e., data has been written to them) among blocks B0-B99. For ease of identification, the blocks in the programmed state are referred to herein as "programmed blocks." The processor 112 records the blocks in the linked table TD sequentially based on the order in which they enter the programmed state. In other words, the processor 112 uses the linked table TD to record the programmed states of the programmed blocks, and the linked table TD can reflect the relative time points and relative order in which the programmed blocks enter the programmed state.

[0051] Figure 6 FIG. 1 is a schematic diagram of a connection table TD according to an embodiment of the present disclosure. The connection table TD records a plurality of programming blocks, such as Figure 6 In the sequence shown, "2, 37, 12, 99, 7, 89," the leftmost programming block (e.g., block "2") is the serial header of link table TD, and the rightmost programming block (e.g., block "89") is the serial tail of link table TD. For example, programming blocks "2" and "37" are arranged adjacently in link table TD, indicating that these two programming blocks have been programmed consecutively. Similarly, programming blocks "37" and "12" are arranged adjacently in link table TD, indicating that these two programming blocks have been programmed consecutively. Furthermore, when processor 112 erases data within a programming block, processor 112 simultaneously removes the record of the corresponding programming block from link table TD.

[0052] The link table TD also records the reread history data of each programming block. In one embodiment, the reread history data is a block reread parameter. The "block reread parameter" represents the corresponding read voltage table used when the processor 112 successfully performs a reread test on the programming block. This parameter may correspond to the index value in the reread sequence table TC. Please refer to Figure 5 and Figure 6 As shown, the block reread parameter of programming block "37" is "5", which means that when processor 112 performs a reread test on programming block "37", processor 112 uses the read voltage table TB5 corresponding to the index value "5" to successfully pass the reread test.

[0053] Similarly, the block reread parameter for programming block "12" is "2," indicating that when processor 112 performs a reread test on programming block "37," processor 112 uses read voltage table TB2 with index value "2," resulting in a successful reread test. Furthermore, the block reread parameter for programming block "2" is "0," indicating that programming block "2" has not yet undergone a reread test.

[0054] The following further describes the implementation details of the aforementioned step S420. The "adjustment condition" for the processor 112 to adjust the reread order table TC may be "the programming block has never been reread tested", and this condition may be determined by the reread history data (block reread parameters). The "adjustment method" for the processor 112 to adjust the reread order table TC may be "adjusting the reread order according to the reread history data (block reread parameters) of the adjacent blocks in the link table TD". In other words, before performing a reread test on one of the programming blocks, if the programming block has not been reread tested, the processor 112 may use the "reread history data (block reread parameters) of the adjacent blocks in the link table TD" to adjust the reread order indicated by the reread order table TC.

[0055] Figure 7 FIG2 is a schematic diagram illustrating how a reread sequence table TC is adjusted based on a link table TD according to one embodiment of the present disclosure. In one embodiment, programming block "99" is the programming block currently undergoing a reread test. Before the reread test, the reread sequence indicated by reread sequence table TC is index values "4, 1, 2, 3, 5, 6, 7."

[0056] Since the block reread parameter of programming block "99" is "0", it means that programming block "99" has not been reread tested before. Therefore, the processor 112 will use the "reread history data (block reread parameters) of adjacent blocks in the link table TD" to adjust the reread order indicated by the reread order table TC. Figure 7 As shown, the programming block adjacent to programming block "99" in link table TD is programming block "12" or "7." Programming block "12" or "7" both enter the programmed state consecutively with programming block "99." Processor 112 has pre-set selection rules, such as selecting the previously programmed block (i.e., programming block "12") or the next programmed block (i.e., programming block "7").

[0057] Continuing with the above, the processor 112 updates the first position in the reread sequence indicated by the reread sequence table TC based on the selected programming block. For example, if the processor 112 selects to update the reread sequence table TC using the block reread parameter "2" for programming block "12," the processor 112 moves the index value "2" (corresponding to the read voltage table TB2) in the reread sequence table TC to the first position, and the remaining index values are shifted sequentially, so that the reread sequence indicated by the reread sequence table TC is changed to the index values "2, 4, 1, 3, 5, 6, 7."

[0058] Here, another embodiment of the “adjustment method” of the processor 112 for adjusting the re-reading order table TC is described. Figure 8FIG. 1 is a schematic diagram showing the adjustment of the rereading order table TC according to an embodiment of the present disclosure. Figure 8 As shown in the table on the left, the reread sequence indicated by the reread sequence table TC is index values "4, 1, 2, 3, 5, 6, 7." Based on the reread sequence, the processor 112 sequentially uses the read voltage tables TB corresponding to the index values to perform a reread test on the corresponding programming blocks (e.g., block "99"). Specifically, the processor 112 sequentially uses the threshold voltage offsets recorded in the read voltage tables TB4, TB1, TB2, TB3, TB5, TB6, and TB7 to perform the reread test.

[0059] For ease of explanation, the "read voltage table TB currently used during the reread test" is referred to herein as the "target read voltage table." When the processor 112 successfully performs a reread test on a programmed block using the target read voltage table (i.e., the data read result falls within the expected range and passes the reread test), the processor 112 records the target read voltage table as the Nth position in the reread order in the reread history data of the programmed block.

[0060] Continuing from the above, the reread sequence in this example has a total of M ranks. When the reread test is performed on the programming block using the "read voltage table TB corresponding to the index value recorded at the Nth rank in the M ranks" and the test is successful, the processor 112 will determine whether N is greater than or equal to the set threshold. If N is greater than or equal to the threshold, the processor 112 will adjust the Nth rank corresponding to the target read voltage table to the first rank in the reread sequence, where M and N are both positive integers greater than 1. That is, the processor 112 adjusts the "index value of the Nth rank in the original reread sequence" to the first rank in the reread sequence (that is, forming a new reread sequence). Conversely, if N is less than the threshold, the processor 112 will not adjust the reread sequence. Accordingly, the time waste of invalid reading and the trivial reread sequence adjustment actions can be reduced.

[0061] See also Figure 8 As shown, as described above, the processor 112 sequentially uses the threshold voltage offsets recorded in the read voltage tables TB4, TB1, TB2, TB3, TB5, TB6, and TB7 to perform a reread test on the programming block "99". If the threshold is "3", and the processor 112 successfully passes the reread test when using the read voltage table TB3 (corresponding to the index value "3"), since the order corresponding to the index value "3" is "4", which is greater than the threshold value "3", after completing the reread test on the programming block "99", the processor 112 will move the index value "3" to the first order, as shown in FIG. Figure 8 As shown in the table on the right.

[0062] On the other hand, if the threshold is "3" and the processor 112 successfully passes the reread test when using the read voltage table TB1 (corresponding index value "1"), since the order corresponding to the index value "1" is "2", which is less than the threshold "3", the processor 112 will not adjust the reread order at this time.

[0063] If the threshold is not set, the processor 112 needs to perform M / 2 reread tests on average (M is the number of digits in the reread sequence) when performing the reread test. Therefore, in one embodiment, the threshold can be set between 2 and M / 2. For example, if the reread sequence indicated by the reread sequence table TC has eight digits, the threshold can be set to any value between 2 and 4.

[0064] In the aforementioned Figure 7 In the embodiment shown, the processor 112 uses the “reread history data (block reread parameters) of adjacent blocks in the link table TD” to adjust the reread order indicated by the reread order table TC. Figure 8 In the illustrated embodiment, processor 112 determines whether the Nth rank in the reread sequence is greater than or equal to a predetermined threshold when a program block successfully passes a reread test using the target read voltage table, and selectively adjusts / updates the reread sequence. In some embodiments, the two aforementioned embodiments may be used independently or in combination.

[0065] For example, if Figure 7 As shown, when processor 112 performs a reread test on programming block "99," it can first adjust the reread order in reread order table TC based on the adjacent programming block "7." Then, when programming block "99" successfully passes the reread test, processor 112 can determine whether the Nth order of the index value corresponding to the target read voltage table used is greater than a threshold value to adjust the reread order. Accordingly, when processor 112 performs a reread test on the next programming block, it can follow the adjusted reread order.

[0066] In addition, as mentioned above, the operating method of the present disclosure can also be implemented by a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium may include a plurality of computer-readable instructions. When the processor 112 executes the computer-readable instructions, the computer-readable instructions enable the processor 112 to access the blocks B0 to B99 of the memory 120 and perform the aforementioned Figure 4 The operation method shown.

[0067] The various elements, method steps or technical features in the aforementioned embodiments may be combined with each other and are not limited to the order of description in the text or the order of presentation in the drawings in this disclosure.

[0068] Although the present disclosure has been disclosed above in the form of implementation methods, it is not intended to limit the present disclosure. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0069]

Explanation of symbols

[0070] 100: Electronic Systems

[0071] 110: Control circuit

[0072] 112: Processor

[0073] 114: Storage circuit

[0074] 120: Memory

[0075] 400: Operation method

[0076] L0-L1: Logic Unit

[0077] B0-B49: Block

[0078] B50-B99: Block

[0079] S410-S420: Steps

[0080] TA: Mapping Table

[0081] TB: Read voltage table

[0082] TB0-TBk: Read voltage table

[0083] TC: Rereading Sequence Table

[0084] TD: Link table.

Claims

1. A control circuit, characterized in that: Include: a storage circuit for storing a reread sequence table and a plurality of read voltage tables; and a processor coupled to the memory circuit and configured to access a memory comprising a plurality of blocks, wherein when a read error occurs in a first block among the plurality of blocks, the processor sequentially uses the plurality of read voltage tables to perform a reread test on the first block according to a reread order indicated by the reread order table; When the reread history data of the first block meets an adjustment condition, the processor adjusts the reread order indicated by the reread order table.

2. The control circuit according to claim 1, wherein: When the first block is in a programmed state and the reread history data of the first block indicates that the reread test has never been performed, the processor is configured to: Before performing the reread test on the first block, adjusting the reread sequence indicated by the reread sequence table according to reread history data of the second block in a programmed state; The first block and the second block successively enter a programmed state.

3. The control circuit according to claim 2, characterized in that: The reread history data of the second block includes a block reread parameter of the second block, the block reread parameter of the second block representing a corresponding one of the plurality of read voltage tables used when the processor successfully performs a reread test on the second block; The processor updates the first order of the reread sequence using the block reread parameter of the second block.

4. The control circuit according to claim 2, characterized in that: The storage circuit is further configured to store a connection table, wherein the connection table is configured to record a plurality of programming blocks in a programmed state among the plurality of blocks; wherein the processor is configured to sequentially record the plurality of programming blocks in the link table according to the order in which the plurality of programming blocks enter the programmed state; The plurality of programming blocks include the first block and the second block, and the processor uses the link table to record that the first block and the second block successively enter a programmed state.

5. The control circuit according to claim 4, characterized in that: When the processor erases one of the programming blocks, the processor removes the record of the one of the programming blocks from the link table.

6. The control circuit according to claim 1 or 2, characterized in that: The rereading order includes M digits, where M is a positive integer greater than 1; When the processor successfully performs the reread test on the first block using a target read voltage table from among the plurality of read voltage tables, the processor records the target read voltage table at an Nth position in the reread order in the reread history data of the first block; When N is greater than or equal to a threshold, the processor adjusts the Nth order to the first order in the rereading sequence, where N is a positive integer.

7. The control circuit according to claim 6, characterized in that: When N is smaller than the threshold, the processor does not adjust the reread order.

8. The control circuit according to claim 6, wherein: The threshold is in the range of 2 to M / 2.

9. An operating method, characterized in that: The invention is applicable to a control circuit for accessing a memory including a plurality of blocks and storing a reread sequence table and a plurality of read voltage tables. The operation method includes: When a read error occurs in a first block among the plurality of blocks, performing a reread test on the first block using the plurality of read voltage tables in sequence according to a reread order indicated by the reread order table; and When the reread history data of the first block meets an adjustment condition, the reread order indicated by the reread order table is adjusted.

10. The operating method according to claim 9, characterized in that: When the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table includes: When the first block is in a programmed state and the reread history data of the first block indicates that the reread test has never been performed, before performing the reread test on the first block, adjusting the reread order indicated by the reread order table according to the reread history data of the second block in a programmed state; The first block and the second block successively enter a programmed state.

11. The operating method according to claim 10, characterized in that: The reread history data of the second block includes a block reread parameter of the second block, the block reread parameter of the second block representing a corresponding one of the plurality of read voltage tables used when the control circuit successfully performs a reread test on the second block; Wherein adjusting the reread order indicated by the reread order table according to the reread history data of the second block in the programmed state comprises: The first order of the reread sequence is updated using the block reread parameter of the second block.

12. The operating method according to claim 10, characterized in that: The control circuit is further configured to store a link table, wherein the link table is configured to record a plurality of programming blocks in a programmed state among the plurality of blocks; wherein the control circuit is used to sequentially record the plurality of programming blocks in the link table according to the order in which the plurality of programming blocks enter the programmed state; The plurality of programming blocks include the first block and the second block, and the control circuit records in the link table that the first block and the second block successively enter a programmed state.

13. The operating method according to claim 12, characterized in that: When the control circuit erases one of the programming blocks, the control circuit removes the record of the one of the programming blocks from the link table.

14. The operating method according to claim 9 or 10, characterized in that: The rereading order includes M digits, where M is a positive integer greater than 1; The step of sequentially performing the reread test on the first block using the plurality of read voltage tables comprises: When the reread test is successfully performed on the first block using a target read voltage table among the plurality of read voltage tables, recording the target read voltage table at an Nth position in the reread order table in the reread history data of the first block; When the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table includes: When N is greater than or equal to a threshold, the Nth order is adjusted to the first order in the rereading sequence, where N is a positive integer.

15. The operating method according to claim 14, characterized in that: When the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table further includes: When N is smaller than the threshold, the rereading order is not adjusted.

16. The operating method according to claim 14, characterized in that: The threshold is in the range of 2 to M / 2.

17. A non-transitory computer-readable storage medium, characterized in that The system comprises a plurality of computer-readable instructions. When a processor executes the plurality of computer-readable instructions, the plurality of computer-readable instructions causes the processor to access a memory comprising a plurality of blocks and perform the following operations: When a read error occurs in a first block among the plurality of blocks, a reread test is performed on the first block using a plurality of read voltage tables in sequence according to a reread order indicated by a reread order table, wherein the reread order table and the plurality of read voltage tables are stored in a memory circuit coupled to the processor; as well as When the reread history data of the first block meets an adjustment condition, the reread order indicated by the reread order table is adjusted.

18. The non-transitory computer-readable storage medium according to claim 17, wherein: When the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table includes: When the first block has a programmed state and the reread history data of the first block indicates that the reread test has never been performed, before performing the reread test on the first block, the reread order indicated by the reread order table is adjusted according to the reread history data of the second block having a programmed state, wherein the first block and the second block enter the programmed state successively.

19. The non-transitory computer-readable storage medium according to claim 18, wherein: The reread history data of the second block includes a block reread parameter of the second block, the block reread parameter of the second block representing a corresponding one of the plurality of read voltage tables used when the processor successfully performs a reread test on the second block; The step of adjusting the reread sequence indicated by the reread sequence table according to the reread history data of the second block in the programmed state includes: The first order of the reread sequence is updated using the block reread parameter of the second block.

20. The non-transitory computer-readable storage medium according to claim 17, wherein The rereading sequence includes M sequences, where M is a positive integer greater than 1; The step of sequentially performing the reread test on the first block using the plurality of read voltage tables comprises: When the reread test is successfully performed on the first block using a target read voltage table among the plurality of read voltage tables, recording the target read voltage table at an Nth position in the reread order in the reread history data of the first block; When the reread history data of the first block meets the adjustment condition, adjusting the reread order indicated by the reread order table includes: When N is greater than or equal to a threshold, adjusting the Nth order to the first order in the rereading order, where N is a positive integer; and When N is smaller than the threshold, the rereading order is not adjusted.

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