Method and device for determining timing mode calibration delay combination of storage equipment

Abstract

The embodiment of the invention provides a storage device timing mode calibration delay combination determination method and device, and relates to the technical field of storage. The method comprises the steps of obtaining a first delay values preset for a write channel of the storage device and b second delay values preset for a read channel of the storage device, and performing timing mode calibration test by adopting all delay combinations formed by the first delay values and the second delay values; determining a first element corresponding to each delay combination according to a test result of the timing mode calibration test, and determining a first test result set; and according to the delay combination corresponding to each first element in the first test result set, determining a target delay combination, setting the delay of a write channel of the storage device as a first delay value in the target delay combination, and setting the delay of a read channel of the storage device as a second delay value in the target delay combination. By adopting the embodiment of the invention, the robustness of data transmission can be improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method and apparatus for determining a delay combination for timing mode calibration of a storage device. Background Art

[0002] In order for the storage device controller to accurately write data to and read data from the non-volatile storage medium, it is necessary to reasonably set the read delay and write delay between the storage device controller and the non-volatile storage medium.

[0003] In related technologies, when setting read delay and write delay, the performance of delay combinations consisting of different read delays and write delays is usually tested through TMC (Timing Mode Calibration). Then, based on the test results, a delay combination that can read and write normally is selected from the multiple delay combinations tested, and the read delay and write delay are configured for the storage medium according to the selected delay combination.

[0004] However, due to various limitations, the actual read and write delays may differ from the set read and write delays. Therefore, even if the selected delay combination can read and write normally, the actual read and write delays may still not work properly. Therefore, the determination of read and write delays directly affects the robustness of data transmission. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a method and apparatus for determining a combination of delays for calibrating a timing mode of a storage device to determine more reasonable read and write delays, thereby improving the robustness of data transmission. The specific technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, a method for determining a delay combination for calibrating a timing mode of a storage device is provided, the method comprising:

[0007] Obtain a first delay value pre-set for the write channel of the storage device and b second delay values pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 , and Y i >Y i+1 or Y i <Y i+1 , X i is the first delay value of the i-th node, Y j is the j-th second delay value, i = 1, 2, 3 ... a, j = 1, 2, 3 ... b, a and b are natural numbers greater than 1;

[0008] Performing a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values;

[0009] Determining, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value;

[0010] Determine, among the sets consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that the values of all first elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent;

[0011] According to the delay combination corresponding to each first element in the first test result set, a target delay combination is determined and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

[0012] In a possible implementation manner, determining the first element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes:

[0013] Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value;

[0014] The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes:

[0015] A submatrix containing the most first elements and having the first elements having the first value is determined in the first matrix as a first test result set.

[0016] In a possible implementation, determining, in the first matrix, a submatrix containing the most first elements and having first elements with the first value as the first test result set includes:

[0017] For each first element in the first matrix, determine, in sequence, a submatrix containing the first element and all of the contained elements having first values, as a first submatrix;

[0018] A first submatrix containing the most elements is determined as a first test result set.

[0019] In one possible implementation, the method further includes:

[0020] Determining, based on a test result of the timing mode calibration test, a second element corresponding to each of the delay combinations, wherein the second element is used to represent a number of bits that are erroneous when the timing mode calibration test is performed using the delay combination;

[0021] The determining a target delay combination according to the delay combination corresponding to each first element in the first test result set includes:

[0022] If the number of the first test result set is 1, determining a target delay combination according to the delay combination corresponding to each first element in the first test result set;

[0023] If the number of the first test result sets is greater than 1, then for each of the first test result sets, a sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combinations are delay combinations located in a neighborhood of the delay combination corresponding to the first test result set;

[0024] Determine a first test result set having the smallest corresponding result value as a target first test result set;

[0025] A target delay combination is determined according to the delay combinations corresponding to the first elements in the target first test result set.

[0026] In a possible implementation manner, determining the first element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes:

[0027] Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value;

[0028] The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes:

[0029] Determine, in the first matrix, a submatrix containing the most first elements, where all first elements have the first value, as a first test result set;

[0030] Determining the second element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes:

[0031] Generate a second matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and j-th column of the second matrix is a second element corresponding to a delay combination consisting of the i-th first delay value and the j-th second delay value;

[0032] The counting of the sum of the second elements corresponding to all adjacent delay combinations of the first test result set as the result value corresponding to the first test result set includes:

[0033] In the second matrix, determining a submatrix having the same position as the first test result set in the first matrix as a second submatrix;

[0034] Count the sum of all the elements in the same row and the same column of the second submatrix in the second matrix as the result value corresponding to the first test result set, wherein the elements in the same row are the elements located from the x1th row to the x2th row and do not belong to the second submatrix, and the elements in the same column are the elements located from the y1th column to the y2th column and do not belong to the second submatrix, wherein x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0035] In a possible implementation, determining, in the first matrix, a submatrix containing the most first elements and having first elements all having first values as the first test result set includes:

[0036] For each element in the first matrix in turn, determine a submatrix containing the first element and all of the contained elements have the first value, as a first test result submatrix;

[0037] Recording the first determined first test result sub-matrix;

[0038] Whenever a new first test result submatrix is determined, if the number of first elements included in the new first test result submatrix is greater than the number of first elements included in the recorded first test result submatrix, updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements included in the new first test result submatrix is equal to the number of first elements included in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is different from the position of the recorded first test result submatrix in the first matrix, recording the new first test result submatrix;

[0039] Until all first test result sub-matrices are determined, each recorded first test result sub-matrix is used as the first test result set.

[0040] In a possible implementation manner, the first value is m, and the second value is n; and determining the first element corresponding to each of the delay combinations according to a test result of the timing mode calibration test includes:

[0041] Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value;

[0042] The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes:

[0043] The first matrix is transformed into a third matrix according to a preset transformation rule, wherein the preset transformation rule is: for each first element of the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is 1; for any first element other than the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix;

[0044] For each third element in each row of the third matrix, use the third element whose value is not 0 as the target starting point, and obtain the position of the third element whose value is not 0 in the third matrix, and determine it as the target starting point position;

[0045] Traversing the third elements that meet a preset first sub-condition in the column where the target starting point is located as the fourth elements; wherein the preset first sub-condition is that the fourth elements are adjacent to each other and the values of all the fourth elements are greater than or equal to the third element;

[0046] In the first matrix, starting with the first element corresponding to the target position and the target starting position, traverse s×c first elements to the left to obtain a submatrix corresponding to the target starting point, where s is the number of the fourth element obtained by traversal plus 1;

[0047] The sub-matrix containing the largest number of first elements among the sub-matrices is determined as the target test result subset.

[0048] According to a second aspect of an embodiment of the present application, there is provided an apparatus for determining a delay combination for calibrating a timing mode of a storage device, the apparatus comprising:

[0049] An acquisition module is used to acquire a first delay value pre-set for a write channel of a storage device and b second delay values pre-set for a read channel of the storage device, X i >X i+1 or X i <X i+1 , and Y i >Y i+1 or Y i <Y i+1 , X i is the first delay value of the i-th node, Y j is the j-th second delay value, i = 1, 2, 3 ... a, j = 1, 2, 3 ... b, a and b are natural numbers greater than 1;

[0050] a testing module, configured to perform a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values;

[0051] a first element determination module, configured to determine, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; and if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value;

[0052] a set determining module, configured to determine, from a set consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that all first elements in the set have the first value and that the delay combinations corresponding to all first elements in the set are adjacent;

[0053] a delay combination determination module, configured to determine a target delay combination based on the delay combinations corresponding to the first elements in the first test result set, and to set the delay of the write channel of the storage device to the first delay value in the target delay combination, and to set the delay of the read channel of the storage device to the second delay value in the target delay combination.

[0054] In a possible implementation, the first element determination module is specifically configured to:

[0055] Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value;

[0056] The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes:

[0057] Determine, in the first matrix, a submatrix containing the most first elements and wherein the values of each first element are all the first value, as a first test result set;

[0058] In a possible implementation, determining, in the first matrix, a submatrix containing the most first elements and having first elements with the first value as the first test result set includes:

[0059] For each first element in the first matrix, determine, in sequence, a submatrix containing the first element and all of the contained elements having first values, as a first submatrix;

[0060] Determine the first submatrix containing the most elements as the first test result set;

[0061] In a possible implementation, the device further includes:

[0062] a second element determining module, configured to determine, based on a test result of the timing mode calibration test, a second element corresponding to each of the delay combinations, wherein the second element is used to represent a number of erroneous bits when the timing mode calibration test is performed using the delay combination;

[0063] The delay combination determination module is specifically configured to:

[0064] If the number of the first test result set is 1, determining a target delay combination according to the delay combination corresponding to each first element in the first test result set;

[0065] If the number of the first test result sets is greater than 1, then for each of the first test result sets, a sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combinations are delay combinations located in a neighborhood of the delay combination corresponding to the first test result set;

[0066] Determine a first test result set having the smallest corresponding result value as a target first test result set;

[0067] Determining a target delay combination according to the delay combinations corresponding to the first elements in the target first test result set;

[0068] In a possible implementation, the first element determination module is specifically configured to:

[0069] Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value;

[0070] The set determination module is specifically configured to:

[0071] Determine, in the first matrix, a submatrix containing the most first elements, where all first elements have the first value, as a first test result set;

[0072] The second element determination module is specifically configured to:

[0073] Generate a second matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and j-th column of the second matrix is a second element corresponding to a delay combination consisting of the i-th first delay value and the j-th second delay value;

[0074] The counting of the sum of the second elements corresponding to all adjacent delay combinations of the first test result set as the result value corresponding to the first test result set includes:

[0075] In the second matrix, determining a submatrix having the same position as the first test result set in the first matrix as a second submatrix;

[0076] Count the sum of all the elements in the same row and the same column of the second submatrix in the second matrix as the result value corresponding to the first test result set, wherein the elements in the same row are the elements located from the x1th row to the x2th row and do not belong to the second submatrix, and the elements in the same column are the elements located from the y1th column to the y2th column and do not belong to the second submatrix, wherein x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0077] In a possible implementation, determining, in the first matrix, a submatrix containing the most first elements and having first elements all having first values as the first test result set includes:

[0078] For each element in the first matrix in turn, determine a submatrix containing the first element and all of the contained elements have the first value, as a first test result submatrix;

[0079] Recording the first determined first test result sub-matrix;

[0080] Whenever a new first test result submatrix is determined, if the number of first elements included in the new first test result submatrix is greater than the number of first elements included in the recorded first test result submatrix, updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements included in the new first test result submatrix is equal to the number of first elements included in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is different from the position of the recorded first test result submatrix in the first matrix, recording the new first test result submatrix;

[0081] until all first test result sub-matrices are determined, and each recorded first test result sub-matrix is used as the first test result set;

[0082] In a possible implementation, the first value is m, the second value is n, and determining the first element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes:

[0083] Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value;

[0084] The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes:

[0085] The first matrix is transformed into a third matrix according to a preset transformation rule, wherein the preset transformation rule is: for each first element of the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is 1; for any first element other than the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix;

[0086] For each third element in each row of the third matrix, use the third element whose value is not 0 as the target starting point, and obtain the position of the third element whose value is not 0 in the third matrix, and determine it as the target starting point position;

[0087] Traversing the third elements that meet a preset first sub-condition in the column where the target starting point is located as the fourth elements; wherein the preset first sub-condition is that the fourth elements are adjacent to each other and the values of all the fourth elements are greater than or equal to the third element;

[0088] In the first matrix, starting with the first element corresponding to the target position and the target starting position, traverse s×c first elements to the left to obtain a submatrix corresponding to the target starting point, where s is the number of the fourth element obtained by traversal plus 1;

[0089] The sub-matrix containing the largest number of first elements among the sub-matrices is determined as the target test result subset.

[0090] According to a third aspect of the present application, a storage device is provided, wherein the storage device is configured to:

[0091] Obtain a first delay value pre-set for a write channel of a storage device, and b second delay values pre-set for a read channel of the storage device, Xi>Xi+1 or Xi<Xi+1, and Yi>Yi+1 or Yi<Yi+1, Xi is the i-th first delay value, Yj is the j-th second delay value, i=1,2,3...a, j=1,2,3...b, and a and b are natural numbers greater than 1;

[0092] Performing a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values;

[0093] Determining, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value;

[0094] Determine, among the sets consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that the values of all first elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent;

[0095] According to the delay combination corresponding to each first element in the first test result set, a target delay combination is determined and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

[0096] Beneficial effects of the embodiments of the present application:

[0097] An embodiment of the present application provides a method and apparatus for determining delay combinations for timing mode calibration of a storage device. Because the first condition is that all first elements in a set have the same value and the delay combinations corresponding to all first elements in the set are adjacent, the first elements in the first test result set determined according to the first condition all have the same value. Furthermore, because the first element has the first value, it indicates that no errors occurred when the delay combination was used for timing mode calibration testing. Therefore, it can be considered that these delay combinations have high performance. Furthermore, the delay combinations corresponding to the first elements are adjacent, meaning that the storage device meets timing requirements when using the delay combination. Therefore, it can be considered that these delay combinations are within the same window, meaning that these delay combinations can be considered TMC delay combinations. Furthermore, because the first test result set has the largest number of first elements, it can be considered that the delay combinations corresponding to the first elements in the first test result set are the optimal TMC delay combinations. In this way, the first test result subset can be determined solely by the first condition, and thus the optimal TMC delay combination can be determined, thereby improving the robustness of data transmission.

[0098] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0099] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0100] Figure 1 This is a schematic diagram of the read operation timing;

[0101] Figure 2 This is a schematic diagram of the principle of master reading data;

[0102] Figure 3 This is a schematic diagram of the write operation timing;

[0103] Figure 4 This is a schematic diagram of data transmission error;

[0104] Figure 5 A first flow chart of a method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0105] Figure 6 A second flow chart of the method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0106] Figure 7 A third flow chart of the method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0107] Figure 8 A fourth flow chart of the method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0108] Figure 9 A fifth flow chart of the method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0109] Figure 10 An example diagram of the second matrix and the second sub-matrix provided in an embodiment of the present application;

[0110] Figure 11 A sixth flow chart of the method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0111] Figure 12 A seventh flow chart of the method for determining a timing mode calibration delay combination provided in an embodiment of the present application;

[0112] Figure 13 This is an example diagram of an all-1 submatrix provided in an embodiment of the present application;

[0113] Figure 14 is an example diagram of adjacent submatrices of each all-1 submatrix in the N matrix;

[0114] Figure 15 A schematic diagram of the structure of the timing mode calibration delay combination determination device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0115] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0116] To more clearly illustrate the method for determining the timing mode calibration delay combination provided by this application, the following explanations are given of the relevant terms involved in this article:

[0117] NAND flash, NAND flash memory, a non-volatile storage technology.

[0118] FCL (Flash Control Level or Flash Control Layer) refers to the controller's operational sophistication and management strategy for storage cells in NAND flash memory management, which directly affects the performance, lifespan, and reliability of the flash memory.

[0119] FC (full name Flash Control) refers to the technology and strategy for managing and operating NAND flash memory to ensure its efficient and reliable operation.

[0120] OSC (full name oscillator) is an electronic circuit or device that can generate periodic signals, and is used in clock signal generation, radio frequency transmission, audio synthesis, etc.

[0121] DQ (full name Data Queue), DQ[7:0]: refers to DQ0 to DQ7, which is the data bus identifier in the memory interface. It represents an 8-bit wide bidirectional data bus used to transmit commands, addresses, and data between the host and NAND. When NAND is not selected, it is in a high-impedance state.

[0122] DQS (full name Data Strobe) is a source synchronous clock generated by the DQ signal sending end, and the signal receiving end latches data on the rising and falling edges of the DQS signal.

[0123] ECC (full name Error Correction Code) is a technology used to detect and correct data errors.

[0124] An Err bit (full name: Error bit) refers to a single binary bit that has an error during data transmission or storage.

[0125] err bit cnt (full name error bite count) refers to the number of binary bits that have errors during data transmission or storage.

[0126] TMC testing ensures that data is correctly transmitted and received between the data buffer and the NAND Flash cache within the operating temperature and voltage range. Correct transmission requires that the FC places data into the data buffer, writes it to the NAND Flash cache without flushing it to disk, and then reads the data from the NAND Flash cache into the data buffer without an err bit. Ideally, when the receiver uses DQS to sample data, the data is centered. However, in reality, factors such as clock frequency, DQS delay, and drive capability can affect data latching.

[0127] Different master controllers may have one or more crystal oscillators. The clocks of different control modules are obtained by frequency division or multiplication. Different clocks will generate DQ and DQS with different frequencies. When the frequency is too high, the probability of latching the correct data is small. However, the frequency directly affects the data transmission rate, that is, the performance of the disk. Therefore, it is necessary to select a frequency that can maintain a fast FCL speed and correctly latch the data.

[0128] The driving capability determines the quality of the generated signal. If the driving capability is too weak, the signal quality is low and err bits are easily generated. If the driving capability is too strong, the power consumption of the particle is too high. Therefore, it is necessary to select an appropriate driving capability to generate a good quality signal within a reasonable power consumption range.

[0129] In addition to the two factors mentioned above, DQSin / out delay (i.e., the second delay value of the read channel and the first delay value of the write channel below) is also a key factor affecting whether data can be correctly latched.

[0130] When performing a read operation on a storage device, DQ and DQS are generated by NAND Flash, such as Figure 1 As shown, Figure 1 This is a diagram of the read operation timing. To ensure that the master can latch the correct data, the edge of DQS needs to be aligned with the center of the DQ signal. Ideally, the DQ and DQS of the read operation are completely synchronized, that is, the edges are completely aligned. In order to make the edge of DQS aligned with the center of the DQ signal, the following is required: Figure 2 As shown in Figure 1, add a delay to the DQS signal line.

[0131] like Figure 3 The figure shows a schematic diagram of the write operation timing. When writing to a storage device, the DQ and DQS signals are generated by the master, and the edge of DQS is aligned with the center of the DQ signal. IO register [15:0] (a 16-bit input / output register) is a 16-bit data register, and the data D0 and D1 are generated by NEregister (Negative Edge Register, a register triggered by the falling edge of the clock signal) and pos register (Positive Edge Register, a register triggered by the rising edge of the clock signal). Ideally, the edge signal of the DQS of the write operation will be aligned with the center of the DQ signal, but delays and other phenomena may occur during data transmission, resulting in the following: Figure 4 The error shown.

[0132] The TMC test is to obtain a reasonable combination of the three parameters of driving capability, frequency, and driving capability through testing, so as to achieve the goals of fast data transmission, good signal quality, correct data transmission, low power consumption and the ability to cope with different temperatures and environments.

[0133] When adapting the signal path delay between the storage device master and non-volatile storage, TMC testing is generally performed through the following two solutions: the first is by reading FLASHID (non-volatile storage ID), and the second is by reading and writing NAND Cache (non-volatile storage flash memory cache). Since the data of the FLASH ID reading method is known and the data volume is relatively short, the result can be obtained quickly. However, due to the small amount of data, the robustness of the obtained parameters is low, and this solution solves the local optimum rather than the global optimum. In order to improve the robustness of the parameters, the method of reading and writing NAND Cache in the related art generally adjusts the OSC of the DQ and the transmission line delay first, finds a delay without ECC errors or err bits, and then adjusts the OSC and transmission line delay of the DQS. Then, the middle value is taken and the DQ delay is adjusted back to form a TMC delay combination. However, in related technologies, this solution usually uses manual search to determine the TMC delay combination. However, there are often not many delay combinations that can be adopted around the manually determined delay combination, resulting in low parameter robustness. In addition, the configuration time is probabilistic, and a feasible solution may be missed, resulting in a long adaptation time.

[0134] In order to solve the above problems, the first aspect of the embodiment of the present application provides a method for determining a delay combination of a timing mode calibration of a storage device, which is applied to a main control MCU (Microcontroller Unit) of a storage device. The storage device can be a solid state drive or other storage medium. Figure 5 , Figure 5 This is a flowchart of a first method for determining a timing mode calibration delay combination provided in an embodiment of the present application, the method comprising the following steps:

[0135] Step S10, obtaining a first delay value pre-set for a write channel of the storage device and b second delay values pre-set for a read channel of the storage device;

[0136] Among them, X i >X i+1 or X i <X i+1 , and Y i >Y i+1 or Y i <Y i+1 , that is, there are the following four situations:

[0137] Case 1: Xi >X i+1 And Y i >Y i+1 ;

[0138] Case 2: X i <X i+1 And Y i >Y i+1 ;

[0139] Case 3: X i >X i+1 And Y i <Y i+1 ;

[0140] Case 4: X i <X i+1 And Y i <Y i+1 ;

[0141] X i is the first delay value of the i-th node, Y j is the j-th second delay value, i=1,2,3...a, j=1,2,3...b, a and b are natural numbers greater than 1.

[0142] Step S20, performing a timing mode calibration test using all delay combinations formed by the first delay values and the second delay values;

[0143] Step S30, determining the first element corresponding to each delay combination according to the test result of the timing mode calibration test;

[0144] Wherein, if no error occurs when the delay combination is used to perform the timing mode calibration test, the value of the first element corresponding to the delay combination is the first value; if an error occurs when the delay combination is used to perform the timing mode calibration test, the value of the first element corresponding to the delay combination is the second value;

[0145] Step S40, among the sets consisting of the first element and satisfying the first condition, determining the set containing the most first elements as the first test result set;

[0146] The first condition is that the values of all first elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent;

[0147] Step S50: Determine a target delay combination based on the delay combinations corresponding to the first elements in the first test result set, set the delay of the write channel of the storage device to the first delay value in the target delay combination, and set the delay of the read channel of the storage device to the second delay value in the target delay combination.

[0148] Using the method of the embodiment of the present application, since the first condition is that all first elements in the set have the first value, and the delay combinations corresponding to all first elements in the set are adjacent, the first elements in the first test result set determined according to the first condition all have the first value. Furthermore, since the first element has the first value, it indicates that no error occurred when the timing mode calibration test was performed using the delay combination, which means that these delay combinations have high performance. Furthermore, the delay combinations corresponding to the first elements are adjacent, meaning that the storage device meets the timing requirements when using the delay combination. Therefore, these delay combinations can be considered to be within the same window, meaning that these delay combinations can be considered TMC delay combinations. Furthermore, since the first test result set has the largest number of first elements, the delay combinations corresponding to the first elements in the first test result set can be considered to be the optimal TMC delay combination. In this way, the first test result subset can be determined solely by the first condition, and thus the optimal TMC delay combination can be determined, thereby improving the robustness of data transmission.

[0149] The above steps S10 to S50 are described below:

[0150] It is understandable that when performing read and write operations on a storage device, there are differences in the signal transmission paths and methods within the storage device, resulting in different signal transmission times in the read channel and write channel of the storage device. Therefore, it is necessary to set delay values for the write channel and the read channel respectively to compensate for the signal transmission delay, that is, the first delay value and the second delay value in step S10 above. There can be multiple first delay values and second delay values, and the number of first delay values and second delay values can be the same or different. The first delay value, the second delay value, and the number of first delay values and second delay values are set by the user based on experience, and the embodiments of the present application are not limited to this.

[0151] When there are multiple first delay values and second delay values, the first delay values are different from each other and monotonically increase or decrease, and the second delay values are different from each other and monotonically increase or decrease.

[0152] The following describes in detail the method for determining a TMC delay combination provided in an embodiment of the present application, taking a and b as examples, where both a and b are 64, and the first delay value and the second delay value are both 0, 1, 2, 3, ..., 63. It should be understood that the above is merely an example of the first delay value and the second delay value, and does not limit the first delay value and the second delay value.

[0153] In the above step S20, when performing the TMC test, all drive capabilities are first cycled, set one by one from low to high, and the read and write delay combination is adapted each time a drive capability is set. Each time before writing data to the NAND Flash cache, a DQS delay (i.e., the second delay value) of the write channel is set to gradually increase from 0 to 63. Then, after waiting for 16K or 64K of data to be written to the NAND Flash cache, the DQS delay (i.e., the first delay value) on the read channel is set to gradually increase from 0 to 63. Then, the data is read into the data buffer through the back-end command, and the read data is compared with the previously written data to check whether the data is exactly the same. If the data is exactly the same, it means that under this drive capability, the DQS delay of the write channel and the DQS delay of the read channel are reasonable and can be adopted.

[0154] It is understood that when using different delay combinations for TMC testing, the test results differ when an error occurs and when no error occurs. That is, the value of the first element corresponding to each delay combination differs when an error occurs and when no error occurs. The value of the first element is related to the test result. If the TMC test is error-free, the value of the first element is the first value; if the TMC test is error-free, the value of the first element is the second value.

[0155] The test result can be used to indicate whether the TMC test is erroneous, or it can indicate the number of bits in which the TMC test is erroneous. In the case where the test result indicates whether the TMC test is erroneous, the first value is used to indicate that the TMC test is not erroneous, and the second value is used to indicate that the TMC test is erroneous. In this case, the first value and the second value are fixed values with different values, that is, when the TMC tests are performed with different delay combinations and no errors occur, the values of the first elements corresponding to each other are the same, and when the TMC tests are performed with different delay combinations and all errors occur, the values of the first elements corresponding to each other are also the same. For example, the first value is 0, indicating that the TMC test is erroneous, and the second value is 1, indicating that the TMC test is erroneous. It is understandable that, in this case, the first value and the second value may also be other values, and the embodiments of the present application are not limited to this.

[0156] When the test result indicates the number of bits that failed the TMC test, the first value indicates that the TMC test did not fail, that is, the first value is 0, and the second value indicates the number of bits that failed the TMC test. For example, assuming that the number of bits that failed the TMC test when a certain delay combination is used is 2, the value of the second element corresponding to the delay combination is 2.

[0157] After performing TMC testing on all delay combinations, the first element corresponding to each delay combination is obtained. A set consisting of the first elements and satisfying the first condition is then determined based on each first element. This set is referred to as a candidate set. The number of candidate sets can be one or more.

[0158] The first condition is that the values of all elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent. The delay combinations corresponding to the first elements are adjacent, which means that the first delay values corresponding to the first elements are adjacent or the second delay values are adjacent. For example, assuming that the set composed of first elements and meeting the first condition includes R11, R12, R13, R21, R22, and R23, R11 represents the test result of the TMC test using the first first delay value and the first second delay value, R12 represents the test result of the TMC test using the first first delay value and the second second delay value, R13 represents the test result of the TMC test using the first first delay value and the third second delay value, and R21 represents the test result of the TMC test using the second second delay value. R22 represents the test result of the TMC test using the first delay value and the first second delay value, R23 represents the test result of the TMC test using the second first delay value and the third second delay value. Since the first delay value is adjacent to the second first delay value, the first second delay value is adjacent, and the second second delay value is also adjacent to the third second delay value, the delay combinations corresponding to all the first elements in the set are adjacent.

[0159] To ensure a robust delay combination, a wide range of possible delay combinations surrounding the selected delay combination is required. Furthermore, the optimal TMC delay combination (TMC) must be found across different drive capabilities. It is understood that the candidate set containing the most first elements is considered to have the largest delay combination window corresponding to each first element within the set. Therefore, in step S40, among the sets consisting of first elements that meet the first condition, the set containing the most first elements is determined as the first test result set.

[0160] For example, assuming that all delay combinations are used to perform TMC tests, the first elements corresponding to each delay combination are: R11, R12, R13, R21, R22, R23, R31, R32, R33, R11 represents the test result of the TMC test using the first first delay value and the first second delay value, R12 represents the test result of the TMC test using the first first delay value and the second second delay value, R13 represents the test result of the TMC test using the first first delay value and the third second delay value, R21 represents the test result of the TMC test using the second first delay value and R22 represents the test result of the TMC test using the second first delay value and the second second delay value, R23 represents the test result of the TMC test using the second first delay value and the third second delay value, R31 represents the test result of the TMC test using the third first delay value and the first second delay value, R32 represents the test result of the TMC test using the third first delay value and the second second delay value, and R33 represents the test result of the TMC test using the third first delay value and the third second delay value.

[0161] If the first value is 1, the second value is 0, and the values of R11, R12, R13, R21, R22, R23, R31, R32, and R33 are 1, 0, 0, 1, 1, 1, 1, 1, 1 respectively, then it can be determined that the sets composed of the first element and satisfying the first condition are: set 1 and set 2, where the elements in set 1 are R11, R21, R31, and the elements in set 2 are R21, R22, R23, R31, R32, and R33.

[0162] Since set 2 contains the largest number of first elements, set 2 is the first test result set.

[0163] The first test result set can be expressed in the form of a set, that is, each first element is listed one by one, written in curly brackets, and each first element is separated by commas; it can also be expressed in the form of a matrix, where the element in the i-th row and j-th column of the matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value.

[0164] It can be understood that if the first test result set is represented in the form of a set, since the elements in the set are unordered, and in this application it is necessary to know the order of each first element when determining the first test result set, it may be necessary to additionally obtain the delay combination corresponding to each first element, which increases the amount of calculation.

[0165] Since a matrix has clear rows and columns, and each element in the matrix corresponds to a storage space, it is suitable for representing each first element in this application. Therefore, in one possible implementation, the first test result set can be represented by a matrix, and each element in the matrix can be used to represent each first element in the first test result set.

[0166] In this case, if Figure 6 FIG. 1 is a flow chart of a second method for determining a timing mode calibration delay combination provided by an embodiment of the present application. Step S30 includes:

[0167] Step S31, generating a first matrix with a rows and b columns according to the test results of the timing mode calibration test;

[0168] Among them, the element in the i-th row and j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value. The row in this application can refer to the row in the matrix or the column in the matrix. When the row in this application represents the row in the matrix, the column in this application refers to the column in the matrix. When the row in this application represents the column in the matrix, the column in this application refers to the row in the matrix. For ease of description, the row below refers to the row in the matrix, and the column below refers to the column in the matrix.

[0169] For example, assume that the first matrix is w 22 is the element in the 2nd row and 2nd column of the first matrix, w 22 The first element corresponding to the delay combination consisting of the second first delay value and the second second delay value; 31 is the element in the 3rd row and 1st column of the first matrix, w 31 The first element corresponding to the delay combination consisting of the third first delay value and the first second delay value.

[0170] The above step S40 includes:

[0171] Step S41 : determining, in the first matrix, a submatrix containing the most first elements and in which the values of each first element are all first values, as a first test result set.

[0172] Still taking the above matrix M as an example, assuming that the first element is used to indicate whether the TMC test is wrong, the first value is 1, indicating no error, and the second value is 0, indicating that the TMC test is wrong. 11 、w 12 、w 13 、w 21 、w 22 、w 23 、w 31 、w 32 、w 33The values of are 1, 0, 0, 1, 1, 1, 1, 1, 1, that is, The submatrix of the first matrix M that contains the most first elements and whose values of each first element are all 1 is Then determine M 子1 is the first test result set.

[0173] In another embodiment, assuming that the first element is used to represent the number of bits that are erroneous in the TMC test, the first value is 0, indicating that the number of bits that are erroneous in the TMC test is 0, that is, the TMC test has no errors, and the second value is the number of bits that are erroneous in the TMC test. 11 、w 12 、w 13 、w 21 、w 22 、w 23 、w 31 、w 32 、w 33 The values are 1,2,0,2,0,0,0,0,0, that is, The submatrix of the first matrix M that contains the most first elements and whose values of each first element are all 1 is Then determine M 子 is the first test result set.

[0174] By using an embodiment of the present application, a first matrix is generated based on the test results of the timing mode calibration test. When determining the submatrix containing the most first elements from the first matrix as the first test result set, the amount of computation is reduced, thereby improving the efficiency of determining the first test result set, and thereby improving the efficiency of determining the optimal TMC delay combination.

[0175] It can be understood that when determining the first test result set from the first matrix, it is also possible to first determine from the first matrix a submatrix containing the first element and the values of each first element are all first values, and then determine from multiple submatrices the submatrix containing the most first elements as the first test result set.

[0176] like Figure 7 FIG. 4 is a flowchart of a third method for determining a timing mode calibration delay combination according to an embodiment of the present application. In this case, step S41 includes:

[0177] Step S411, for each first element in the first matrix, determine, in sequence, a submatrix containing the first element and all of whose elements have the first value, as a first submatrix;

[0178] Step S412: Determine the first sub-matrix containing the most elements as the first test result set.

[0179] Still taking the above matrix M as an example, assuming that the first element is used to indicate whether the TMC test is wrong, the first value is 1, indicating no error, and the second value is 0, indicating that the TMC test is wrong. 11 、w 12 、w 13 、w 21 、w 22 、w 23 、w 31 、w 32 、w 33 The values of are 1, 0, 0, 1, 1, 1, 1, 1, 1, that is, Determine that the first matrix M includes two sub-matrices, namely, all-1 sub-matrices and Since the submatrix M 子1 The first element contained in is the largest and the value of each first element is 1, then determine M 子1 is the first test result set.

[0180] In another embodiment, assuming that the first element is used to represent the number of bits that are erroneous in the TMC test, the first value is 0, indicating that the number of bits that are erroneous in the TMC test is 0, that is, the TMC test has no errors, and the second value is the number of bits that are erroneous in the TMC test. 11 、w 12 、w 13 、w 21 、w 22 、w 23 、w 31 、w 32 、w 33 The values are 1,2,0,2,0,0,0,0,0, that is, Determine the submatrix in the first matrix M that includes three first elements whose values are all 0, that is, the all-0 submatrix as well as M 子3 =[w 31 w 32 w 33 ]=[0 0 0], since the submatrix M 子2 The first element contained in is the largest and the value of each first element is 0, then determine M 子2 is the first test result set.

[0181] By using the embodiment of the present application, multiple sub-matrices containing first elements whose values are all the first value are first determined from the first matrix, and then the sub-matrix containing the most first elements is determined from each sub-matrix as the first test result set. This can avoid missing the actual maximum matrix and improve the accuracy of determining the optimal TMC delay combination.

[0182] It is understandable that there may be more than one submatrix in the first matrix that contains the same number of elements and all of which have the first value. In this case, any one submatrix can be selected from the multiple submatrices as the first test result set. The first test result set can also be determined according to the following method, such as Figure 8 The fourth flow chart of the method for determining the timing mode calibration delay combination provided by the embodiment of the present application is shown. After following the above steps S10 to S30, the following step S301 is executed:

[0183] Step S301, determining the second element corresponding to each delay combination according to the test result of the timing mode calibration test;

[0184] Among them, the second element is used to indicate the number of erroneous bits when the timing mode calibration test is performed using a delay combination. For example, when a certain delay combination is used for TMC testing, the data written by the write channel is different from the data read by the read channel, and the number of erroneous bits is 1, then the second element corresponding to the delay combination is 1; if when a certain delay combination is used for TMC testing, the data written by the write channel is the same as the data read by the read channel, and the number of erroneous bits is 0, then the second element corresponding to the delay combination is 0; if when a certain delay combination is used for TMC testing, the data written by the write channel is different from the data read by the read channel, and the number of erroneous bits is 4, then the second element corresponding to the delay combination is 4.

[0185] In this embodiment, the above step S50 determines the target delay combination according to the delay combination corresponding to each first element in the first test result set, including:

[0186] If the number of the first test result is 1, step S501 is executed;

[0187] Step S501, determining a target delay combination according to the delay combinations corresponding to the first elements in the first test result set;

[0188] If the number of the first test results is greater than 1, then execute steps S502 to S504;

[0189] Step S502: for each first test result set, summing up the second elements corresponding to all adjacent delay combinations of the first test result set as the result value corresponding to the first test result set;

[0190] Among them, adjacent delay combinations are delay combinations that are located within the neighborhood of the delay combination corresponding to the first test result set. It is understandable that the scope of the neighborhood is determined by the user based on actual experience. For example, delay combinations with the same first delay value or second delay value as the delay combination corresponding to the first test result set can be determined as adjacent delay combinations, or delay combinations with adjacent first delay values or second delay values corresponding to the delay combination corresponding to the first test result set can be determined as adjacent delay combinations.

[0191] For example, assuming that after performing TMC testing on all delay combinations, the first elements corresponding to each delay combination are: R11, R12, R13, R21, R22, R23, R31, R32, R33, and the second elements are: S11, S12, S13, R21, S22, S23, S31, S32, S33. The first test result set is: set 1 = {R11, R12, R13}, set 2 = {R11, R21, R31}. If the adjacent delay combination is a delay combination with a first delay value or a second delay value adjacent to the delay combination corresponding to the first test result set, then the adjacent delay combinations of set 1 are determined to be: S21, S22, S33. 23. The adjacent delay combinations of set 2 are: S12, S22, S32. The calculated result value corresponding to set 1 is: S21+S22+S23, and the corresponding result value of set 2 is: S12+S22+S32. If the adjacent delay combination is a delay combination with the same first delay value or second delay value as the delay combination corresponding to the first test result set, then the adjacent delay combinations of set 1 are determined to be: S21, S22, S23, S31, S32, S33. The adjacent delay combinations of set 1 are: S12, S13, S22, S23, S32, S33. The calculated corresponding result value of set 1 is: S12+S13+S22+S23+S32+S33.

[0192] Step S503, determining the first test result set with the minimum corresponding result value as the target first test result set;

[0193] Still taking the above embodiment as an example, if the result value corresponding to set 1 is smaller than the result value corresponding to set 2, set 1 is used as the target first test result set.

[0194] Step S504 : determining a target delay combination according to the delay combinations corresponding to the first elements in the target first test result set.

[0195] According to an embodiment of the present application, the sum of the second elements corresponding to all adjacent delay combinations of the first test result set is calculated as the result value corresponding to the first test result set. The smaller the result value, the fewer errors are when performing TMC testing using delay combinations adjacent to the delay combination corresponding to the first test result. The first test result set with the smallest result value is determined as the target first test result set, and the target delay combination is determined based on the delay combinations corresponding to the first elements in the target first test result set, thereby improving the accuracy of determining the optimal TMC delay combination.

[0196] As in the above, each second element can also be represented by a matrix. Based on this, in a possible implementation, Figure 9 The fifth flow chart of the method for determining a delay combination for timing mode calibration provided by an embodiment of the present application is shown. If a first matrix is used to represent each first element, after determining, based on the first matrix, a submatrix containing the most first elements, where all first elements have the first value, the above-mentioned step S301 determines the second element corresponding to each delay combination based on the test results of the timing mode calibration test, specifically including:

[0197] Step S3011, generating a second matrix with a rows and b columns according to the test results of the timing mode calibration test;

[0198] The element in the i-th row and j-th column of the second matrix is the second element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value. It will be understood that if the row in the preceding text represents a row in a matrix, the row here also represents the row of the matrix, and if the row in the preceding text represents a column of the matrix, the row here also represents the column of the matrix.

[0199] For each second element in the second matrix, its corresponding first delay value is the same as the first delay value corresponding to the first element at the same position in the first matrix, and its corresponding second delay value is the same as the second delay value corresponding to the first element at the same position in the first matrix.

[0200] For example, assume that the first matrix is The second matrix is w 22 and v 22 The elements of the 2nd row and 2nd column in the first matrix and the second matrix respectively, w 22 The first element of the delay combination consisting of the second first delay value and the second second delay value, v 22 The second element corresponding to the delay combination consisting of the second first delay value and the second second delay value; 31 and v 31 The elements of the 3rd row and 1st column in the first and second matrices respectively, w 31The first element of the delay combination consisting of the third first delay value and the first second delay value, v 31 The second element corresponding to the delay combination consisting of the third first delay value and the first second delay value.

[0201] In this embodiment, the above step S502 specifically includes:

[0202] Step S5021: In the second matrix, determine a submatrix having the same position as the first test result set in the first matrix as a second submatrix;

[0203] Step S5022: Count the sum of all the elements in the same row and column of the second submatrix in the second matrix as the result value corresponding to the first test result set;

[0204] The in-row elements are the elements located from the x1th row to the x2th row and do not belong to the second submatrix, and the in-column elements are the elements located from the y1th column to the y2th column and do not belong to the second submatrix, wherein x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0205] For example, Figure 10 FIG. 1 shows an example diagram of a second matrix and a second sub-matrix provided in an embodiment of the present application. Figure 10 The thick solid line frame represents the second sub-matrix, and the dotted line frame represents all the elements in the same row and column of the second sub-matrix.

[0206] By using the embodiment of the present application, a first matrix and a second matrix are generated according to the test results of the timing mode calibration test, and a target first test result set is determined according to the first matrix and the second matrix, thereby determining a target delay combination, thereby improving the efficiency of determining the optimal TMC delay combination.

[0207] In the process of determining the submatrix in the first matrix that contains the most first elements and whose first elements all have the first value, a large number of intermediate results need to be saved, resulting in a waste of storage resources.

[0208] In order to reduce the occupation of storage resources, in a possible implementation, as Figure 11 FIG. 6 is a flowchart of a sixth method for determining a timing mode calibration delay combination according to an embodiment of the present application. Step S41 specifically includes:

[0209] Step S4101: for each element in the first matrix, determine, in sequence, a submatrix containing the first element and all of whose elements have the first value, as a first test result submatrix;

[0210] Step S4102, recording the first determined first test result sub-matrix;

[0211] Step S4103: Whenever a new first test result submatrix is determined, if the number of first elements included in the new first test result submatrix is greater than the number of first elements included in the recorded first test result submatrix, then updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements included in the new first test result submatrix is equal to the number of first elements included in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is different from the position of the recorded first test result submatrix in the first matrix, then recording the new first test result submatrix;

[0212] Step S4104 : until all first test result sub-matrices are determined, each recorded first test result sub-matrix is used as a first test result set.

[0213] For example, assuming that the first matrix For the first element of the first row and first column, determine the submatrix containing the first element and whose elements are all the first value. Then record the submatrix M1, and then determine the submatrix containing the first element and the values of the elements contained are all the first value for the elements in the first row and second column. If it is the same as the recorded submatrix, then determine the submatrix containing the first element and the values of the elements contained are all the first value for the elements in the first row and third column. And so on to obtain the submatrix M2 = [1 1 1] and the submatrix However, if the number of first elements in submatrix M2 is less than the number of first elements in recorded submatrix M1, submatrix M2 is not recorded. Since the position of submatrix M3 in the first matrix is different from the position of submatrix M3 in the first matrix, submatrix M1 and submatrix M3 are recorded at the same time, and submatrix M1 and submatrix M3 are respectively used as the first test result set.

[0214] In this embodiment, recording the determined first test result submatrix may refer to recording the rows, columns, and position of the first test result submatrix in the first matrix. In order to reduce space complexity, in one possible implementation, a monotone stack may be used to store the first test result submatrix. After determining the first matrix, the determined first test submatrix is compared with the first test result submatrix in the monotone stack. If the determined first test result submatrix and the first test result submatrix in the monotone stack contain the same number of first elements and have different positions in the first matrix, the determined first test result submatrix is pushed onto the stack. If the number of first elements contained in the determined first test result submatrix is less than the number of first elements contained in the first test result submatrix in the monotone stack, the determined first test result submatrix is not pushed onto the stack. If the number of first elements contained in the determined first test result submatrix is greater than the number of first elements contained in the first test result submatrix in the monotone stack, the first matrix in the monotone stack is popped and the determined first test result submatrix is pushed onto the stack.

[0215] According to an embodiment of the present application, for each element in the first matrix, a submatrix containing the first element and all the values of the contained elements are the first value is determined as the first test result submatrix and recorded, and when it is determined that a submatrix with a larger number of elements is obtained, the recorded first test result submatrix is updated. This can reduce the storage of intermediate data and the occupancy of storage resources.

[0216] In order to further improve the rate of determining the first test result set, assuming that the first value is m and the second value is n, in a possible implementation manner, as shown in FIG. Figure 12 FIG. 7 is a flowchart of a seventh method for determining a delay combination for timing mode calibration provided by an embodiment of the present application. Step S30 determines the first element corresponding to each delay combination based on the test results of the timing mode calibration test, specifically including:

[0217] Step S31, generating a first matrix with a rows and b columns according to the test results of the timing mode calibration test;

[0218] In step S40, the set containing the most first elements among the sets consisting of the first elements and satisfying the first condition is determined as the first test result set, including:

[0219] Step S401: transform the first matrix into a third matrix according to a preset transformation rule. The preset transformation rule is: for each first element of the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is 1; for any first element other than the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix;

[0220] In other words, the above preset change rule can be expressed by formula (1-1):

[0221]

[0222] Where C_i_j represents the third element in the i-th row and j-th column of the third matrix, M_i_j represents the first element in the i-th row and j-th column of the first matrix, and C_i_(j-1) represents the third element in the i-th row and j-1-th column of the third matrix. For n=0 and m=1, formula (1-1) can be rewritten as formula (1-2):

[0223]

[0224] It can be seen from formula (1-2) that when j = 0, the values of C_i_j and M_i_j are the same, so formula (1-2) can be rewritten as formula (1-3):

[0225]

[0226] Since M_i_j is equal to 1 in the third sub-formula of formula (1-3), formula (1-3) can be rewritten as formula (1-4):

[0227]

[0228] In this case, assuming that the first matrix Then the third matrix

[0229] Step S402: for each third element in each row of the third matrix, taking the third element whose value is not 0 as the target starting point and obtaining the position of the third element whose value is not 0 in the third matrix, and determining it as the target starting point position;

[0230] For example, assuming the third matrix Then the 0th row and 0th column, the 0th row and 1st column, the 1st row and 0th column, the 1st row and 1st column, the 1st row and 2nd column in the third matrix are respectively determined as the target starting positions.

[0231] Step S403, traverse the third element that meets the preset first sub-condition in the column direction of the target starting point, and use it as the fourth element;

[0232] The preset first sub-condition is: the fourth elements are adjacent to each other and the values of all the fourth elements are greater than or equal to the third element.

[0233] For example, assuming the third matrix Taking the 0th row and 0th column as the target starting position as an example, the value of the third element at the target starting position is 1. There are two other third elements in the column direction of the target starting position, namely the third element "1" in the 1st row and 0th column and the third element "0" in the 2nd row and 0th column. Since the third element "1" in the 1st row and 0th column is adjacent to the target starting position and is not less than 1, the third element "1" in the 1st row and 0th column can be regarded as the fourth element, while the third element "0" in the 2nd row and 0th column is less than 1 and therefore cannot be regarded as the fourth element.

[0234] Step S404 , starting from the first element corresponding to the target position and the target starting position in the first matrix, traverse s×c first elements to the left to obtain a submatrix corresponding to the target starting point.

[0235] Where s is the number of the fourth element obtained by traversal plus 1.

[0236] Assume that the first matrix Then the third matrix For the case where the target starting point is at row 0, column 0, as explained above, the number of the fourth element traversed is 1, so s = 2. Since the value of row 0, column 0 in the third matrix is 1, c = 1. Therefore, starting from the first element of row 0, column 0 in the first matrix, traversing the first element of 2×1 (i.e., 2 rows and 1 column) will yield the submatrix corresponding to the target starting point. This submatrix is obviously the submatrix consisting of row 0, column 0 and row 1, column 0 in the first matrix.

[0237] For the case where the target starting point is at row 1 and column 1, as explained above, the number of the fourth element traversed is 1, so s = 2. Since the value of row 1 and column 1 in the third matrix is 2, c = 2. Therefore, starting from the first element of row 1 and column 1 in the first matrix, traversing the first element of 2×2 (i.e., 2 rows and 2 columns), the submatrix corresponding to the target starting point is obtained. This submatrix is obviously the submatrix consisting of row 0 and column 0, row 0 and column 1, row 1 and column 0, and row 1 and column 1 in the first matrix.

[0238] Step S405 : Determine the sub-matrix containing the largest number of first elements among the sub-matrices as the target test result subset.

[0239] By using the embodiment of the present application, a third matrix is obtained by transforming the first matrix. Based on the third matrix, a submatrix in which the values of the first elements are all the first values can be quickly determined, and then the first test result set can be quickly determined, thereby further improving the efficiency of determining the optimal delay combination.

[0240] In order to speed up the rate of determining the first test result set, in one possible implementation, a fourth matrix can also be determined based on the first matrix and the third matrix, and the value of each element in the fourth matrix is equal to the product of the number of times the third element at the same position in the third matrix and the first element at the same position in the first matrix appear as the first value from top to bottom in the column.

[0241] For example, still taking the first matrix The third matrix For example, the "1" in the third column and second row of the first matrix appears for the first time in the third column, the "2" in the second column and first row appears for the first time in the second column, and so on, to determine the fourth matrix

[0242] Then, the position of the element with the largest value is determined in the fourth matrix, and the first test result set is determined in the first matrix using the position as a starting point.

[0243] In order to more clearly illustrate the TMC delay combination determination method provided in the embodiment of the present application, the following is described with reference to specific embodiments:

[0244] The TMC test process can be described as follows: z = f(x, y), where x is the second delay value and y is the first delay value. The range of x is [0:63] and the range of y is [0:63]. z indicates whether the data programmed into the NAND Cache can be read successfully through the data read process. z = 0 indicates data read failure, err bit cnt = w, where w indicates an err bit value or 0xFF. z = 1 indicates data read success and err bit cnt = 0. The relationship between z and w can be expressed as follows:

[0245]

[0246] When the number of erroneous bits in the read data is less than the preset bit number threshold, w=valid, where valid is the actual number of erroneous bits in the read data; when the number of erroneous bits in the read data is greater than or equal to the preset bit number threshold, w=0xFF.

[0247] Assume that the z-value matrix M (i.e. the first matrix mentioned above) can be obtained during the TMC test as follows:

[0248]

[0249] Each element of the matrix M (i.e., the first element) is used to indicate whether the data is read successfully at each value point of x and y. According to the above formula (2), the matrix N (i.e., the second matrix) can be obtained:

[0250]

[0251] Each element of matrix N (the second element above) represents the number of erroneous bits in the data read at each value of x and y. Since the TMC test aims to find the maximum error tolerance for the first and second delay values, that is, to find the all-one submatrix in the M matrix with the widest rows and columns, in other words, the TMC test aims to find the largest all-one submatrix M_P in the M matrix.

[0252] If there are multiple all-1 sub-matrices M_P of the same area in the M matrix, the all-1 sub-matrix with the smallest sum of the number of erroneous bits in the four directions of the M_P matrix (the corresponding up, down, left, and right sub-matrices in the N matrix, that is, the adjacent delay combination mentioned above) must be found as the optimal sub-matrix.

[0253] For example, the matrix

[0254] First, transform each element in the M matrix according to the above formula (1) to obtain the C matrix (corresponding to the third matrix above):

[0255]

[0256] Then continue to transform the C matrix and transform it into the S matrix. The values of each element of the S matrix are shown in formula (5):

[0257] S_i_j = R_i_j * C_i_j (5)

[0258] Where S_i_j is equal to the area of an all-1 submatrix that is expanded upward or downward with M_i_j as the vertex (or midpoint). The number of rows in this all-1 submatrix is the number of nodes (including itself) that are greater than or equal to C_i_j when scanning up and down at the (i, j) point in the column (i.e., column j) of the C matrix (i.e., column j). The expansion stops when a node smaller than itself is encountered during the expansion. According to formula (5), the C matrix can be transformed into the S matrix:

[0259]

[0260] Then compare the values of each element in the S matrix and find the maximum value to determine the area of the largest all-1 submatrix of the M matrix. For example, if the maximum value in the above S matrix is "3*3", it can be determined that the area of the largest all-1 submatrix is 9. In the process of calculating the value of each element in the S matrix, the rows, columns and four vertex values of the submatrix (that is, the first test result submatrix determined by the above record) are saved at the same time, and a monotone stack is maintained so that the nodes in the stack are always the row / column values and vertex values of the all-1 submatrix with the largest area. When pushing into the stack, it is necessary to determine whether the four vertices of the submatrix are consistent with the four vertices of the submatrix already in the stack. If they are consistent, they cannot be pushed into the stack. After calculating the value of each element in the S matrix, the S matrix can be obtained, and then the position and size of all the largest all-1 submatrices in the first matrix can be obtained.

[0261] Based on the above, we can know that there are two all-1 sub-matrices M_P_1 and M_P_2 with consistent windows in the M matrix, such as Figure 13 The following is an example diagram of an all-1 submatrix. Figure 13 The solid box in the middle represents the all-1 submatrix.

[0262] At this time, the matrix information of the largest all-1 submatrix needs to be popped out from the stack one by one, and the sum of the ERR BIT CNT in the four directions of the N matrix is calculated for each largest all-1 submatrix, such as Figure 10 and Figure 14 The following are example diagrams of adjacent submatrices of each all-1 submatrix in the N matrix: Figure 10 The solid line box represents the submatrix corresponding to the submatrix M_P_1 in the M matrix in the N matrix (that is, the second submatrix mentioned above), and the dotted line box represents all the elements in the same row and column of the second submatrix. Figure 14The solid line box represents the submatrix corresponding to the submatrix M_P_2 in the M matrix in the N matrix, and the dotted line box represents all the elements in the same row and column of the second submatrix.

[0263] according to Figure 10 The N matrix in the M matrix can be calculated to obtain the sum of the err bit cnt of the submatrix M_P_1 in the four directions of the N matrix as ERR_1. Figure 14 The N matrix in the M matrix can be calculated to obtain the sum of the err bit cnt of the sub-matrix M_P_2 in the four directions of the sub-matrix on the N matrix as ERR_2.

[0264] Then ERR_1 and ERR_2 are compared, and the smaller M_P submatrix is taken as the best submatrix in the M matrix (ie, the target first test result set mentioned above).

[0265] Corresponding to the first aspect, the second aspect of the embodiment of the present application provides a timing mode calibration delay combination determination device, such as Figure 15 FIG2 is a schematic diagram of a structure of a device for determining a timing mode calibration delay combination according to an embodiment of the present application, the device comprising:

[0266] The acquisition module 1501 is configured to acquire a first delay value set in advance for a write channel of a storage device and b second delay values set in advance for a read channel of the storage device, X i >X i+1 or X i <X i+1 , and Y i >Y i+1 or Y i <Y i+1 , X i is the first delay value of the i-th node, Y j is the j-th second delay value, i = 1, 2, 3 ... a, j = 1, 2, 3 ... b, a and b are natural numbers greater than 1;

[0267] A testing module 1502 is configured to perform a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values;

[0268] a first element determining module 1503, configured to determine, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; and if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value;

[0269] a set determining module 1504 configured to determine, from among the sets consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that all first elements in the set have the first value and that the delay combinations corresponding to all first elements in the set are adjacent;

[0270] The delay combination determination module 1505 is used to determine the target delay combination based on the delay combination corresponding to each first element in the first test result set, and set the delay of the write channel of the storage device to the first delay value in the target delay combination, and set the delay of the read channel of the storage device to the second delay value in the target delay combination.

[0271] In the embodiment of the present application, since the first condition is that all first elements in the set have the first value, and the delay combinations corresponding to all first elements in the set are adjacent, the first elements in the first test result set determined according to the first condition all have the first value. Furthermore, since the first element has the first value, it indicates that no error occurred when the timing mode calibration test was performed using the delay combination, which means that these delay combinations have high performance. Furthermore, the delay combinations corresponding to the first elements are adjacent, meaning that the storage device meets the timing requirements when using the delay combination. Therefore, these delay combinations can be considered to be within the same window, meaning that these delay combinations can be considered TMC delay combinations. Furthermore, since the first test result set has the largest number of first elements, the delay combinations corresponding to the first elements in the first test result set can be considered to be the optimal TMC delay combination. In this way, the first test result subset can be determined solely by the first condition, and thus the optimal TMC delay combination can be determined, thereby improving the robustness of data transmission.

[0272] In a possible implementation, the first element determination module is specifically configured to:

[0273] Generating, according to the test results of the timing mode calibration test, a first matrix with a rows and b columns, wherein the element in the i-th row and j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; determining, among the sets consisting of the first elements and satisfying the first condition, the set containing the most first elements as the first test result set, including: determining, in the first matrix, a submatrix containing the most first elements and wherein the values of each first element are all the first value, as the first test result set;

[0274] In a possible implementation, determining, in the first matrix, a submatrix containing the most first elements and wherein the values of each first element are all first values, as the first test result set, includes: sequentially determining, for each first element in the first matrix, a submatrix containing the first element and wherein the values of the contained elements are all first values, as the first submatrix; and determining the first submatrix containing the most elements as the first test result set;

[0275] In a possible embodiment, the device further includes: a second element determination module, configured to determine, based on the test result of the timing mode calibration test, the second element corresponding to each of the delay combinations, wherein the second element is used to represent the number of erroneous bits when the timing mode calibration test is performed using the delay combination; the delay combination determination module is specifically configured to: if the number of the first test result sets is 1, determine a target delay combination based on the delay combinations corresponding to the first elements in the first test result set; if the number of the first test result sets is greater than 1, for each of the first test result sets, count the sum of the second elements corresponding to all adjacent delay combinations of the first test result set as the result value corresponding to the first test result set, wherein the adjacent delay combinations are delay combinations located in the neighborhood of the delay combinations corresponding to the first test result set; determine the first test result set with the smallest corresponding result value as the target first test result set; determine the target delay combination based on the delay combinations corresponding to the first elements in the target first test result set;

[0276] In one possible embodiment, the first element determination module is specifically used to: generate a first matrix with a rows and b columns according to the test results of the timing mode calibration test, wherein the element in the i-th row and j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; the set determination module is specifically used to: determine a submatrix in the first matrix that contains the most first elements and whose first elements all have the first value as the first test result set; the second element determination module is specifically used to: generate a second matrix with a rows and b columns according to the test results of the timing mode calibration test, wherein the element in the i-th row and j-th column of the second matrix is the second element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; the statistics of the first test result are as follows: The sum of the second elements corresponding to all adjacent delay combinations of the test result set is used as the result value corresponding to the first test result set, including: in the second matrix, determining a submatrix with the same position as the first test result set in the first matrix as the second submatrix; counting the sum of all the same row elements and same column elements of the second submatrix in the second matrix as the result value corresponding to the first test result set, wherein the same row elements are elements located from the x1th row to the x2th row and do not belong to the second submatrix, and the same column elements are elements located from the y1th column to the y2th column and do not belong to the second submatrix, wherein x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0277] In a possible implementation, determining the submatrix in the first matrix that contains the most first elements and whose first elements all have the first value as the first test result set includes: determining, for each element in the first matrix in turn, a submatrix that contains the first element and whose elements all have the first value as the first test result submatrix; recording the first determined first test result submatrix; whenever a new first test result submatrix is determined, if the number of first elements contained in the new first test result submatrix is greater than the number of first elements contained in the recorded first test result submatrix, updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements contained in the new first test result submatrix is equal to the number of first elements contained in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is different from the position of the recorded first test result submatrix in the first matrix, recording the new first test result submatrix; until all first test result submatrices are determined, each recorded first test result submatrix is used as the first test result set;

[0278] In one possible embodiment, the first value is m and the second value is n; determining the first element corresponding to each of the delay combinations according to the test results of the timing mode calibration test includes: generating a first matrix with a rows and b columns according to the test results of the timing mode calibration test, wherein the element in the i-th row and j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; determining the set containing the most first elements in the set consisting of first elements and satisfying the first condition as the first test result set includes: transforming the first matrix into a third matrix according to a preset transformation rule, and the preset transformation rule is: for each first element of the first column in the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0, and if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is 1; for any first element in the first matrix other than the first column, if the value of the first element is n, then the The value of the third element in the third matrix that is in the same position as the first element is 0. If the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is c+1; wherein c is the value of the element to the left of the third element in the third matrix; for each third element in each row of the third matrix, the third element whose value is not 0 is used as the target starting point, and the position of the third element whose value is not 0 in the third matrix is obtained and determined as the target starting point position; the third elements that meet the preset first sub-condition in the column direction of the column where the target starting point is located are traversed as the fourth elements; wherein the preset first sub-condition is: each fourth element is adjacent to each other and the value of all fourth elements is greater than or equal to the third element; in the first matrix, starting with the first element corresponding to the target position and the target starting position, traverse s×c first elements to the left to obtain the submatrix corresponding to the target starting point, wherein s is the number of traversed fourth elements plus 1; and the submatrix containing the largest number of first elements in each submatrix is determined as the target test result subset.

[0279] The present application also provides a storage device, which is used to:

[0280] Obtain a first delay value pre-set for a write channel of a storage device, and b second delay values pre-set for a read channel of the storage device, Xi>Xi+1 or Xi<Xi+1, and Yi>Yi+1 or Yi<Yi+1, Xi is the i-th first delay value, Yj is the j-th second delay value, i=1,2,3...a, j=1,2,3...b, and a and b are natural numbers greater than 1;

[0281] Performing a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values;

[0282] Determining, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value;

[0283] Determine, among the sets consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that the values of all first elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent;

[0284] According to the delay combination corresponding to each first element in the first test result set, a target delay combination is determined and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

[0285] The storage device in this article may refer to a solid-state hard drive, a mobile storage device, or other types of storage devices, and this application does not impose any limitations on this.

[0286] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0287] Each embodiment in this specification is described in a related manner. Similar portions between the embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so their description is relatively simple. For related portions, refer to the description of the method embodiments.

[0288] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A method for determining a delay combination for calibrating a timing mode of a storage device, characterized in that: The method comprises: Obtain a first delay value pre-set for the write channel of the storage device and b second delay values pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 , and Y i >Y i+1 or Y i <Y i+1 , X i is the first delay value of the i-th node, Y j is the j-th second delay value, i = 1, 2, 3 ... a, j = 1, 2, 3 ... b, a and b are natural numbers greater than 1; Performing a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values; Determining, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value; Determine, among the sets consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that the values of all first elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent; According to the delay combination corresponding to each first element in the first test result set, a target delay combination is determined and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

2. The method according to claim 1, characterized in that Determining the first element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes: Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes: A submatrix containing the most first elements and having first elements with the first value is determined in the first matrix as a first test result set.

3. The method according to claim 2, characterized in that The determining, in the first matrix, a submatrix containing the most first elements and wherein the values of each first element are all first values, as the first test result set, includes: For each first element in the first matrix, determine, in sequence, a submatrix containing the first element and all of the contained elements having first values, as a first submatrix; A first submatrix containing the most elements is determined as a first test result set.

4. The method according to claim 1, wherein The method further comprises: Determining, based on a test result of the timing mode calibration test, a second element corresponding to each of the delay combinations, wherein the second element is used to represent a number of bits that are erroneous when the timing mode calibration test is performed using the delay combination; The determining a target delay combination according to the delay combination corresponding to each first element in the first test result set includes: If the number of the first test result set is 1, determining a target delay combination according to the delay combination corresponding to each first element in the first test result set; If the number of the first test result sets is greater than 1, then for each of the first test result sets, a sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combinations are delay combinations located in a neighborhood of the delay combination corresponding to the first test result set; Determine a first test result set having the smallest corresponding result value as a target first test result set; A target delay combination is determined according to the delay combinations corresponding to the first elements in the target first test result set.

5. The method according to claim 4, characterized in that Determining the first element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes: Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes: Determine, in the first matrix, a submatrix containing the most first elements, where all first elements have the first value, as a first test result set; Determining the second element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes: Generate a second matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and j-th column of the second matrix is a second element corresponding to a delay combination consisting of the i-th first delay value and the j-th second delay value; The counting of the sum of the second elements corresponding to all adjacent delay combinations of the first test result set as the result value corresponding to the first test result set includes: In the second matrix, determining a submatrix having the same position as the first test result set in the first matrix as a second submatrix; Count the sum of all the elements in the same row and the same column of the second submatrix in the second matrix as the result value corresponding to the first test result set, wherein the elements in the same row are the elements located from the x1th row to the x2th row and do not belong to the second submatrix, and the elements in the same column are the elements located from the y1th column to the y2th column and do not belong to the second submatrix, wherein x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

6. The method according to claim 5, characterized in that The determining, in the first matrix, of a submatrix containing the most first elements and having first elements all having the first value as the first test result set includes: For each element in the first matrix in turn, determine a submatrix containing the first element and all of the contained elements have the first value, as a first test result submatrix; Recording the first determined first test result sub-matrix; Whenever a new first test result submatrix is determined, if the number of first elements included in the new first test result submatrix is greater than the number of first elements included in the recorded first test result submatrix, updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements included in the new first test result submatrix is equal to the number of first elements included in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is different from the position of the recorded first test result submatrix in the first matrix, recording the new first test result submatrix; Until all first test result sub-matrices are determined, each recorded first test result sub-matrix is used as the first test result set.

7. The method according to claim 1, characterized in that The first value is m, and the second value is n; and determining the first element corresponding to each of the delay combinations according to the test result of the timing mode calibration test includes: Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes: The first matrix is transformed into a third matrix according to a preset transformation rule, wherein the preset transformation rule is: for each first element of the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is 1; for any first element other than the first column in the first matrix, if the value of the first element is n, the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix; For each third element in each row of the third matrix, use the third element whose value is not 0 as the target starting point, and obtain the position of the third element whose value is not 0 in the third matrix, and determine it as the target starting point position; Traversing the third elements that meet a preset first sub-condition in the column where the target starting point is located as the fourth elements; wherein the preset first sub-condition is that the fourth elements are adjacent to each other and the values of all the fourth elements are greater than or equal to the third element; In the first matrix, starting with the first element corresponding to the target position and the target starting position, traverse s×c first elements to the left to obtain a submatrix corresponding to the target starting point, where s is the number of fourth elements obtained by traversal plus 1; The sub-matrix containing the largest number of first elements among the sub-matrices is determined as the target test result subset.

8. A device for determining a delay combination for calibrating a timing mode of a storage device, characterized in that: The device comprises: An acquisition module is used to acquire a first delay value pre-set for a write channel of a storage device and b second delay values pre-set for a read channel of the storage device, X i >X i+1 or X i <X i+1 , and Y i >Y i+1 or Y i <Y i+1 , X i is the first delay value of the i-th node, Y j is the j-th second delay value, i = 1, 2, 3 ... a, j = 1, 2, 3 ... b, a and b are natural numbers greater than 1; a testing module, configured to perform a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values; a first element determination module, configured to determine, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; and if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value; a set determining module, configured to determine, from a set consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that all first elements in the set have the first value and that the delay combinations corresponding to all first elements in the set are adjacent; a delay combination determination module, configured to determine a target delay combination based on the delay combinations corresponding to the first elements in the first test result set, and to set the delay of the write channel of the storage device to the first delay value in the target delay combination, and to set the delay of the read channel of the storage device to the second delay value in the target delay combination.

9. The device according to claim 8, characterized in that The first element determination module is specifically configured to: Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes: Determine, in the first matrix, a submatrix containing the most first elements and wherein the values of each first element are all the first value, as a first test result set; The determining, in the first matrix, a submatrix containing the most first elements and wherein the values of each first element are all first values, as the first test result set, includes: For each first element in the first matrix, determine, in sequence, a submatrix containing the first element and all of the contained elements having first values, as a first submatrix; Determine the first submatrix containing the most elements as the first test result set; The device further comprises: a second element determining module, configured to determine, based on a test result of the timing mode calibration test, a second element corresponding to each of the delay combinations, wherein the second element is used to represent a number of erroneous bits when the timing mode calibration test is performed using the delay combination; The delay combination determination module is specifically used to: If the number of the first test result set is 1, determining a target delay combination according to the delay combination corresponding to each first element in the first test result set; If the number of the first test result sets is greater than 1, then for each of the first test result sets, a sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combinations are delay combinations located in a neighborhood of the delay combination corresponding to the first test result set; Determine a first test result set having the smallest corresponding result value as a target first test result set; Determining a target delay combination according to the delay combinations corresponding to the first elements in the target first test result set; The first element determination module is specifically configured to: Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; The set determination module is specifically configured to: Determine, in the first matrix, a submatrix containing the most first elements, where all first elements have the first value, as a first test result set; The second element determination module is specifically configured to: Generate a second matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and j-th column of the second matrix is a second element corresponding to a delay combination consisting of the i-th first delay value and the j-th second delay value; The counting of the sum of the second elements corresponding to all adjacent delay combinations of the first test result set as the result value corresponding to the first test result set includes: In the second matrix, determining a submatrix having the same position as the first test result set in the first matrix as a second submatrix; Counting the sum of all the elements in the same row and the same column of the second submatrix in the second matrix as the result value corresponding to the first test result set, wherein the elements in the same row are the elements located from the x1th row to the x2th row and do not belong to the second submatrix, and the elements in the same column are the elements located from the y1th column to the y2th column and do not belong to the second submatrix, wherein x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix; The determining, in the first matrix, of a submatrix containing the most first elements and having first elements all having the first value as the first test result set includes: For each element in the first matrix in turn, determine a submatrix containing the first element and all of the contained elements have the first value, as a first test result submatrix; Recording the first determined first test result sub-matrix; Whenever a new first test result submatrix is determined, if the number of first elements included in the new first test result submatrix is greater than the number of first elements included in the recorded first test result submatrix, updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements included in the new first test result submatrix is equal to the number of first elements included in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is different from the position of the recorded first test result submatrix in the first matrix, recording the new first test result submatrix; until all first test result sub-matrices are determined, and each recorded first test result sub-matrix is used as the first test result set; The first value is m, and the second value is n; the first element determination module is specifically configured to: Generate a first matrix with a rows and b columns according to the test result of the timing mode calibration test, wherein the element in the i-th row and the j-th column of the first matrix is the first element corresponding to the delay combination consisting of the i-th first delay value and the j-th second delay value; The step of determining, among the sets consisting of the first element and satisfying the first condition, a set containing the most first elements as the first test result set includes: The first matrix is transformed into a third matrix according to a preset transformation rule, wherein the preset transformation rule is: for any first element in the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is n; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is m×(c+1); where c is the number of elements in the first matrix that are to the left of the first element and in the same row as the first element and have a value of m; For each row in the third matrix, traverse the third element p with the largest value in the current row 行max , as the target starting point, and obtain the position of the target starting point in the third matrix to obtain the target starting point position; where p 行max =m×(c+1); If p does not exist in the current line 行max , take the next row as the new current row, and return the third element p with the largest value in the current row. 行max Steps; If there is p in the current line 行max , then traverse the third elements that meet the preset first sub-condition in the column direction of the target starting point to obtain the fourth element; wherein the preset first sub-condition is: each of the fourth elements is adjacent to each other and the value of all the fourth elements is greater than m×(c+1); If the fourth element that satisfies the preset first sub-condition is obtained through traversal, the number and position of the fourth elements that satisfy the preset first sub-condition are determined as the target number and target position; In the first matrix, starting with the first element corresponding to the target position and the target starting position, traverse the first element of m×c columns to the left to obtain a submatrix corresponding to the target starting point, where the number of rows of the submatrix is equal to the number of targets; If the fourth element that satisfies the preset first sub-condition is not obtained through traversal, then in the first matrix, starting with the first element corresponding to the target starting point position as the starting column, traverse the first elements of m×c columns to the left to obtain a submatrix corresponding to the target starting point, where the number of rows in the submatrix is equal to 1; The sub-matrix containing the largest number of first elements among the sub-matrices is determined as the target test result subset.

10. A storage device, characterized in that: The storage device is used for: Obtain a first delay value pre-set for a write channel of the storage device, and b second delay values pre-set for a read channel of the storage device, Xi>Xi+1 or Xi<Xi+1, and Yi>Yi+1 or Yi<Yi+1, Xi is the i-th first delay value, Yj is the j-th second delay value, i=1,2,3...a, j=1,2,3...b, and a and b are natural numbers greater than 1; Performing a timing mode calibration test using all delay combinations formed by each of the first delay values and each of the second delay values; Determining, based on a test result of the timing mode calibration test, a first element corresponding to each of the delay combinations, wherein if no error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a first value; if an error occurs when the timing mode calibration test is performed using the delay combination, the value of the first element corresponding to the delay combination is a second value; Determine, among the sets consisting of first elements and satisfying a first condition, a set containing the most first elements as a first test result set, wherein the first condition is that the values of all first elements in the set are the first value, and the delay combinations corresponding to all first elements in the set are adjacent; According to the delay combination corresponding to each first element in the first test result set, a target delay combination is determined and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

Images