Storage system, method, device, electronic device, medium and product

Abstract

The present application discloses a storage system, method, apparatus, electronic device, medium and product, relating to the field of data management technology. Memory devices external to a controller are used to store and write data, which is no longer limited by the controller, thereby improving the scalability of the storage system.

Description

Technical Field

[0001] The present application relates to the field of data management technology, and in particular to storage systems, methods, devices, electronic devices, media, and products. Background Art

[0002] With the explosive growth of data volumes and the widespread adoption of technologies like cloud computing and artificial intelligence, centralized storage systems face unprecedented performance and reliability challenges. Write caching, as a core acceleration method for storage systems, directly determines system throughput and response latency.

[0003] In related technologies, the current mainstream implementation solution relies on traditional DRAM (Dynamic Random Access Memory) memory combined with RDMA (Remote Direct Memory Access) network to achieve data backup between multiple controllers, but this architecture has the problem of low scalability. Summary of the Invention

[0004] The present application provides a storage system, method, device, electronic device, medium and product to at least solve the problem of low scalability in related technologies.

[0005] The present application provides a storage system, comprising: multiple controllers, a switch, and a memory device, wherein the switch comprises multiple first interfaces and multiple second interfaces, and the memory device comprises multiple third interfaces; wherein the multiple controllers are correspondingly connected to the multiple first interfaces, and for any target controller, the target controller is used to receive write data, store the write data in the memory of the target controller, and send the write data to the first target interface corresponding to the target controller; the multiple second interfaces are correspondingly connected to the multiple third interfaces, and the switch is used to send the write data to the corresponding third target interface through the second target interface corresponding to the write data; the memory device is installed with multiple memory sticks, and the multiple memory sticks are connected to the multiple third interfaces, and the memory device is used to store the write data in the physical address of the memory stick corresponding to the third target interface.

[0006] The present application also provides a storage method, including: receiving a write request through a controller, the write request including write data; storing the write data in the memory of the controller and sending the write data to a switch; sending the write data to a memory device through the switch, the physical address corresponding to the controller; and storing the write data through the memory device.

[0007] The present application also provides a storage device, including: a receiving module, used to receive a write request through a controller, the write request including write data; a storage module, used to store the write data in the memory of the controller and send the write data to the switch; a sending module, used to send the write data to a memory device through the switch, the physical address corresponding to the controller; and an execution module, used to store the write data through the memory device.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned storage methods when executing the computer program.

[0009] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above storage methods are implemented.

[0010] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above storage methods when executed by a processor.

[0011] Through this application, using memory devices outside the controller to store and write data is no longer limited by the controller, thereby improving the scalability of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of an application scenario of a storage system provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of a cluster provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of the storage system provided in an embodiment of the present application;

[0016] Figure 4 A schematic diagram of the structure of the controller provided in an embodiment of the present application;

[0017] Figure 5 A schematic diagram of the structure of a switch provided in an embodiment of the present application;

[0018] Figure 6A schematic diagram of the structure of the storage system provided in an embodiment of the present application;

[0019] Figure 7 A flowchart of a storage method provided in an embodiment of the present application;

[0020] Figure 8 A flowchart of a storage method provided in an embodiment of the present application;

[0021] Figure 9 A schematic diagram of the response information provided in an embodiment of the present application;

[0022] Figure 10 A schematic diagram of troubleshooting provided in an embodiment of the present application;

[0023] Figure 11 A schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0024] Figure 12 A schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0025] Figure 13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0028] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0029] For example, during host operation, data needs to be read and written. Write caching technology enables fast data read and write operations. The controller acts as a high-speed cache device, allowing the host to read and write data, enabling the host to quickly execute data operations. To mitigate controller failures and enhance data security, data backup is implemented across multiple controllers in a cluster.

[0030] In related technologies, when a host generates data during operation, it writes the data to the memory of the host's corresponding controller. The host's controller then sends the data to other controllers for data backup. If the host's controller fails, the backed-up data can be read from other controllers, thus achieving high data availability. However, since the host's controller and other controllers are located in the same cluster, this backup method is limited by the cluster architecture and suffers from low scalability.

[0031] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0032] In conjunction with the specific application environment architecture that the storage system relies on for execution, this section describes the specific application environment architecture. Figure 1 , Figure 1 This diagram shows a storage system application scenario. Data generated by the host during operation is written to the controller for write caching. When the host needs to use the data, it reads it from the controller.

[0033] In related technologies, controller data backup is achieved through clustering.

[0034] Next, combine Figure 2 Describe the cluster.

[0035] Figure 2 This is a schematic diagram of a cluster provided in an embodiment of the present application. Figure 2 As shown, controllers A and B are located in the same cluster. An RDMA link is established between them, which is used to transmit data for data backup. Host A corresponds to controller A, and host B corresponds to controller B. After host A writes data to controller A, controller A synchronizes data A to controller B to back up data A. If controller A fails, data A is not lost due to the failure of controller A because controller B stores data A. The same applies to controller B backing up data to controller A. This achieves high data availability. However, this approach requires redesigning the RDMA link when adding a new controller to the cluster, which increases the complexity of the interconnection between controllers and poses a problem of low scalability.

[0036] Figure 3 A schematic diagram of the structure of the storage system provided in the embodiment of the present application is shown in FIG. Figure 3 As shown, an embodiment of the present application provides a storage system, including: multiple controllers, switches, and memory devices, the switches including multiple first interfaces and multiple second interfaces, and the memory devices including multiple third interfaces; wherein, the multiple controllers are correspondingly connected to the multiple first interfaces, and for any target controller, the target controller is used to receive write data, store the write data in the memory of the target controller, and send the write data to the first target interface corresponding to the target controller; the multiple second interfaces are correspondingly connected to the multiple third interfaces, and the switch is used to send the write data to the corresponding third target interface through the second target interface corresponding to the write data; the memory device is installed with multiple memory sticks, and the multiple memory sticks are connected to the multiple third interfaces, and the memory device is used to store the write data to the physical address of the memory stick corresponding to the third target interface.

[0037] For example, the memory device is an independent storage device outside the controller, used for backing up data. The memory device is independent of the host and does not need to occupy the host's memory channel or slot.

[0038] Exemplarily, the memory of the controller is DRAM memory.

[0039] Optionally, the host sends an electrical signal to the controller through a circuit pin level change, where the electrical signal includes write data.

[0040] Optionally, the memory device can be a Compute Express Link (CXL) device. CXL devices are independent storage devices with advantages such as easy scalability, low latency, large capacity, and memory sharing. CXL devices offer higher transmission efficiency than RDMA, enabling fast read and write of backup data. CXL devices include multiple memory module slots, independent of the host's slot count. They can be quickly expanded by adding memory modules to increase storage capacity. CXL devices can pool multiple memory modules for shared memory.

[0041] Exemplarily, a memory device builds a memory pool to uniformly manage multiple memory sticks connected to the memory device. Any number of third interfaces can share different physical addresses of a memory stick and assign different physical addresses of a memory stick to different controllers, thereby achieving rational use of the storage space of the memory stick.

[0042] Exemplarily, a memory device supports access by multiple controllers. The memory device allocates memory regions to each of the controllers, and access to the corresponding memory regions is controlled by a switch to avoid data access conflicts. Exemplarily, each third interface of the memory device corresponds to a memory region, and the second and third interfaces have a one-to-one correspondence. The switch connects the controller's data transmission channel to the corresponding second interface to enable the controller to access the memory region corresponding to the corresponding third interface.

[0043] Illustratively, the first target interface is an interface among the plurality of first interfaces that is connected to the target controller. The second target interface is an interface among the plurality of second interfaces that is connected to the first target interface within the switch. The third target interface is an interface among the plurality of third interfaces that is connected to the second target interface.

[0044] In combination with a scenario example, for example, controller A corresponds to memory area A, and the second interface A, the third interface A, and the memory area A correspond one to one. When controller A accesses the memory through the first interface A, the switch connects the data transmission channel of controller A to the second interface A, so that controller A can access memory area A through the first interface A, the second interface A, and the third interface A.

[0045] The storage system provided in the embodiment of the present application uses a memory device external to the controller to store write data and is no longer limited by the controller, thereby improving the scalability of the storage system.

[0046] A feasible implementation method is Figure 4 A schematic diagram of the structure of the controller provided in the embodiment of the present application is shown in FIG. Figure 4 As shown, the multiple controllers include a main controller; wherein the main controller is connected to other controllers, and the main controller is used to send write permissions of memory devices of other controllers to other controllers.

[0047] Exemplarily, a main controller uniformly manages multiple controllers, and the main controller sends write permissions through connection lines between controllers. The write permissions are used to control the memory area that each controller can access.

[0048] In this scenario, each controller is assigned a memory area. The master controller assigns write permissions to each controller based on the correspondence between controllers and memory areas. Each controller's write permissions include the corresponding memory area, ensuring that each controller can access only the corresponding memory area.

[0049] Optionally, the master controller is elected from multiple controllers in the cluster.

[0050] In this feasible implementation, the master controller uniformly manages the write permissions of multiple controllers, so that each controller can only access the corresponding memory area, thereby avoiding memory access conflicts and improving the reliability of the storage system.

[0051] A feasible implementation method is Figure 5 A schematic diagram of the structure of a switch provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the target controller is used to send the target write permission to the first target interface. The switch includes a scheduler and multiple data lines, the multiple data lines are used to connect the multiple first interfaces and the multiple second interfaces. The scheduler is used to determine the second target interface based on the target write permission and connect the lines between the first target interface and the second target interface.

[0052] Exemplarily, the scheduler is connected to multiple data lines, and the scheduler is used to manage the connectivity status of the multiple data lines. The multiple data lines are internal lines of the switch, and the multiple data lines are used to connect the first interface and the second interface. The connectivity status of the multiple data lines can control the connectivity status of the first interface and the second interface.

[0053] Exemplarily, the second target interface included in the target write permission is an interface to which the target controller has permission, and the target controller can access the memory area corresponding to the memory device through the second target interface.

[0054] For example, a scheduler is set in the switch, and any target controller that accesses the memory device through the switch will be verified by the switch, thereby preventing unauthorized controllers from accessing the memory device.

[0055] In conjunction with the scenario example, the scheduler determines the second target interface corresponding to the target write permission, and the scheduler connects the second target interface with the first target interface, thereby enabling the target controller to connect to the second target interface.

[0056] In this feasible implementation, the switch scheduler verifies the controller's access to the memory device, which can effectively improve the security of the storage system.

[0057] A feasible implementation method is Figure 6 A schematic diagram of the structure of the storage system provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, the storage system also includes a hard disk component; wherein the memory device is connected to the hard disk component, and the hard disk component is used to store write data.

[0058] For example, memory devices offer high read and write speeds and temporary storage capabilities. Hard disk components provide non-volatile storage, allowing for persistent data storage even during power outages. Data written to the memory device is backed up synchronously to the hard disk component, enabling persistent data storage.

[0059] In related technologies, data exchange between memory devices and hard disk components relies on the control of the processor, resulting in a bottleneck in data reading and writing speeds.

[0060] In this application, the memory device and the hard disk component are directly connected and can interact directly, reducing the processor's copy overhead and protocol conversion delay, thereby improving data reading and writing speeds.

[0061] In this feasible implementation, persistent storage of written data is achieved through hard disk components, thereby improving the reliability of the storage system.

[0062] In a feasible implementation method, the hard disk assembly includes a hard disk box and multiple hard disks; wherein the hard disk box is connected to the memory device and is used to manage multiple hard disks; multiple hard disks are connected in parallel to the hard disk box, and the hard disks are used to store data.

[0063] For example, the hard disk box treats multiple hard disks as equivalent to a large-capacity storage device, and the memory device only needs to operate a single address space to access the hard disk. For example, the hard disk can be accessed through memory mapping access, thereby reducing the complexity of hard disk management.

[0064] Optionally, the hard drive enclosure has a built-in translation processor that converts the read and write instructions of the memory device into instructions executable by the hard drive in real time. There is no need to set up a separate software conversion layer, thereby improving storage efficiency.

[0065] Optionally, the hard disk enclosure includes multiple hard disk interfaces, and the hard disks are connected to the hard disk enclosure through the hard disk interfaces. The number of hard disks can be expanded according to user needs, thereby improving the scalability of the storage system.

[0066] In this feasible implementation, the connection between the hard disk and the memory device is directly managed by the hard disk enclosure without the involvement of the processor, which can reduce the signal transmission path and thus improve storage efficiency.

[0067] Figure 7 A flowchart of the storage method provided in the embodiment of the present application is shown in FIG. Figure 7 As shown, the embodiment of the present application provides a storage method, which is described in detail as follows:

[0068] S701: Receive a write request through a controller, where the write request includes write data.

[0069] Exemplarily, the host sends a write request to the controller, triggering the controller to perform data storage. The write data is the data instructed to be written by the host, and the controller is used to cache and store the write data so that the host can read the write data in real time when it needs to write data.

[0070] Exemplarily, the controller verifies the write request to verify whether the write request is sent by the host corresponding to the controller. After the verification is passed, the write request is parsed to obtain the write data in the write request.

[0071] Exemplarily, the write request received by the controller is sent by a host corresponding to the controller to the controller. Each host only performs data read and write operations on the corresponding controller to avoid data read and write conflicts.

[0072] S702: Store the written data in the memory of the controller and send the written data to the switch.

[0073] For example, storing the written data in the controller's memory and sending the written data to the switch can be performed simultaneously. The host can directly read the data in the controller's memory, and the data in the memory device is used for backup. In the event of a controller failure or a controller memory failure, the backup data is retrieved from the memory data.

[0074] For example, the write data is sent to the switch so that the switch stores the write data in the memory device. The switch is used to ensure that the write data is stored in the memory area corresponding to the controller to avoid data storage conflicts between multiple controllers.

[0075] S703. Send the write data to the memory device through the switch, and the physical address corresponding to the controller.

[0076] For example, a memory device pools multiple memories to create a memory pool. Each memory area in the memory pool corresponds to a physical address. The corresponding physical address is pre-assigned to the controller. The controller reads and writes data at the corresponding physical address, avoiding conflicts between multiple controllers.

[0077] Exemplarily, the switch is used to accurately send the write data to the physical address corresponding to the controller to achieve backup of the write data.

[0078] S704: Store the written data in the memory device.

[0079] Illustratively, the memory bar in the memory device is used to store write data, and the memory bar in the memory device can be expanded according to user needs.

[0080] In combination with the scenario example, in the related art, data backup is implemented through other controllers in the cluster, which is limited by the cluster architecture. In this application, data backup is performed through independent memory devices, which are easy to expand, thereby better providing storage services.

[0081] For example, the process of storing the written data in the memory device has a faster transmission speed than the related art of backing up data between controllers via RDMA, thereby improving storage efficiency.

[0082] Based on the above implementation methods, this application proposes a centralized storage write cache method that combines controllers and memory devices. Two copies of write cache data are stored: one in the controller's DRAM memory and one in a memory device outside the controller. During normal I / O, no large amounts of data are required between controllers. Compared to the RDMA circular mirror cache method in related technologies, this application has significant advantages in scalability, high availability, performance, and efficient fault handling.

[0083] The storage method provided in an embodiment of the present application receives a write request, which includes write data, through a controller; stores the write data in the controller's memory and sends the write data to a switch; sends the write data to a memory device, corresponding to the physical address of the controller, through the switch; and stores the write data in the memory device. This solution uses a memory device external to the controller to store write data, eliminating the controller's limitations and improving storage scalability.

[0084] Based on any of the above embodiments, Figure 8, the detailed process of the storage method is explained.

[0085] Figure 8 A flow chart of a storage method provided in an embodiment of the present application. Figure 8 As shown, the method includes:

[0086] S801: Receive a write request through a controller, where the write request includes write data.

[0087] It should be noted that the execution process of S801 refers to S701 and will not be repeated here.

[0088] S802: Store the written data in the memory of the controller and send the written data to the switch.

[0089] It should be noted that the execution process of S802 refers to S702 and will not be repeated here.

[0090] S803: Determine a memory pointer corresponding to the controller, where the memory pointer includes a physical address of a memory in the memory device.

[0091] For example, a memory pointer is a globally assigned unique physical address identifier. The memory pointer may include the controller identifier, the memory bank identifier, and the row and column addresses. The controller identifier is used to verify that the memory pointer corresponds to the controller, and the memory bank identifier and row and column addresses are used to accurately locate the physical address.

[0092] S804: Send the write data and the memory pointer to the switch, so that the switch sends the write data to the target memory in the memory device based on the memory pointer, and the physical address corresponds to the target memory.

[0093] Exemplarily, the switch parses the memory pointer to obtain a physical address in the memory pointer, determines a data transmission path according to the physical address, and sends the write data to the target memory through the data transmission path.

[0094] Exemplarily, the switch is connected to multiple third interfaces of the memory device through multiple second interfaces to implement access to multiple memory areas of the memory device through the multiple second interfaces, and each line of the second interface corresponds to a data transmission path.

[0095] Optionally, a mapping table containing a data transmission path is stored in the switch. The switch determines the data transmission path according to the mapping table and the physical address in the memory pointer, and sends the write data to the target memory through the data transmission path.

[0096] S805: Store the written data in the target memory.

[0097] For example, memory devices have the characteristics of high read and write speed and temporary storage. Storing written data in the target memory can quickly read the written data according to the host's needs, thereby improving the host's work efficiency.

[0098] A feasible implementation method, after storing the write data in the target memory, may further include: after storing the write data in the target memory, further including: sending response information to the host through the controller to indicate that the write request has been completed.

[0099] Exemplarily, the response information is used to indicate that the controller has completed storage and backup of the written data.

[0100] Next, combine Figure 9 Describe the response information.

[0101] Figure 9 This is a schematic diagram of the response information provided in the embodiment of the present application. Figure 9 As shown, the host sends write data to the controller, prompting it to store the data in the controller's memory. While storing the data in the controller's memory, the controller also sends write data to the memory device, prompting it to back up the data. After the memory device completes the backup, it sends a response to the controller. The controller forwards the response to the host, confirming that the controller has completed storage and backup of the data.

[0102] For example, after hashing the data shards, the host knows the controller to which the I / O should be sent. The controller's write cache module saves the I / O in DRAM, and then copies the data to the memory device through the memcpy function. At the same time, it calls the system call to flush the write data to the memory device, not only saving it in its own cache. At this time, one copy of the write data is saved in the DRAM memory, and one copy of the data is saved in the memory device. Controller 1 responds to the host: the data is written successfully. The write data is asynchronously flushed to the hard disk. After the asynchronous flush is successful, the data in the memory device is written to the hard disk. Dirty data becomes non-dirty: the write data of DRAM has been written to the hard disk, and the copy data in the memory device does not need to be flushed again, but the corresponding data status in the memory device must be converted to normal to avoid repeated flushing. The above process realizes the storage and backup of write data.

[0103] In this feasible implementation, by sending response information, the host can clearly understand the status of the current data writing, avoiding the host from waiting for a long time, thereby improving storage efficiency.

[0104] S806: Determine a target hard disk corresponding to the target memory from multiple hard disks connected to the memory device.

[0105] For example, a hard disk is a non-volatile storage device. The memory device is connected to multiple hard disks, and the written data can be stored in the hard disks as needed.

[0106] Optionally, the write request sent by the host may include a data storage indication, and the data storage indication may indicate whether the data is stored in a hard disk. If so, the target hard disk is determined.

[0107] Optionally, the write request sent by the host may include the type of the write data, and the target hard disk is determined based on the type of the write data. For example, if the write data is for one-time use, temporary use, or frequently changed data, it does not need to be stored on the target hard disk.

[0108] S807: Store the written data in the target hard disk.

[0109] For example, after completing the data transmission of write data, the controller asynchronously triggers the storage process of the target hard drive: it generates a storage instruction packet (the instruction packet may include information such as the physical address or data length) and sends the instruction to the hard drive enclosure management service (for example, by writing to the PCIe configuration space register). The hard drive enclosure hardware schedules: The hard drive enclosure executes a physical-level operation sequence: mapping the physical address to the hard drive storage location. Based on the internal structure of the hard drive, the write data is split into parallel operation instructions. The target hard drive performs atomic storage to store the written data on the target hard drive.

[0110] A feasible implementation method, after storing the written data in the target hard disk, may further include: determining target state information of the written data in the target memory; and updating the target state information to a stored state.

[0111] Exemplarily, status information is added to each data in the memory device, and the status information can be stored or not stored. Stored means that the written data has been written to the target hard disk, and not stored means that the written data has not been written to the target hard disk.

[0112] Optionally, the controller can read the status information and determine the status of the write data based on the status information, and determine subsequent operations based on the status. If the status information indicates that the data is not stored, the subsequent operation may include the controller instructing the memory device to store the write data or the controller sending information to the host to request the host's instruction.

[0113] In conjunction with the scenario example, when the target state information of the written data is not stored, if the controller and / or host determines that the written data needs to be persistently stored, a storage instruction can be sent. If the controller and / or host determines that the written data does not need to be persistently stored, the operation can be performed without knowing.

[0114] In this feasible implementation, by updating the target status information, the controller and / or host can clearly write the storage status of the data, thereby effectively guiding the controller to perform the next operation.

[0115] In a feasible implementation method, the storage method may also include: determining the initial memory from the memory pooled by the switch; mapping the initial memory to multiple initial controllers so that the multiple initial controllers can access the initial memory; calling the initial memory through the multiple initial controllers to allocate initial virtual addresses and initial physical addresses to the multiple initial controllers; aligning the multiple initial virtual addresses and multiple initial physical addresses of the multiple initial controllers through the main controller, and allocating memory to the multiple initial controllers.

[0116] Illustratively, before using a memory device to store write data of multiple controllers, an initialization operation is performed to allocate memory to each controller so that each controller can only send write data to the corresponding memory.

[0117] For example, the switch pools the memory of multiple memory sticks of the memory device to obtain a memory pool, which can be used to uniformly manage the memory of the multiple memory sticks. The initial memory is unallocated free memory. After the initial memory is allocated, multiple controllers can access the initial memory.

[0118] Optionally, after allocating the initial memory, an allocated tag is added to the initial memory. The allocated tag indicates which controllers the initial memory has been allocated to, thereby avoiding duplicate allocation problems.

[0119] For example, by calling the initial memory through multiple initial controllers, each of the initial controllers can access the initial physical address of the same initial memory through the corresponding initial virtual address. The physical address is the physical address of the initial memory, and the virtual address (i.e., the logical address) is the virtual address corresponding to each controller. Multiple initial virtual addresses are different.

[0120] For example, alignment is a hardware-level operation that reconstructs multiple discrete initial virtual addresses and initial physical addresses into a unified, continuous physical address view. This operation eliminates spatial fragmentation caused by distributed address allocation in multi-controller architectures and establishes a globally consistent memory addressing system.

[0121] Exemplarily, multiple initial controllers can access the initial memory to cope with controller failure. When any one of the multiple initial controllers fails, the initial memory is accessed through other normal initial controllers so that the host can normally access the initial memory.

[0122] Optionally, the alignment process may include: address information collection, address space reconstruction, mapping relationship generation, and distributed synchronous validation. Among them, address information collection is to actively collect the initial virtual address range allocated by each initial controller and the initial physical address range bound to it through the system interconnection bus. Address space reconstruction may include calculating the positioning coordinates of each address range in the global space, and remapping the fragmented physical address range to a continuous address sequence. Mapping relationship generation may include recording the precise mapping relationship between the initial address of each controller and the aligned address, and marking the initial controller corresponding to each address. Distributed synchronous validation may include: distributing the address mapping table to all initial controllers through a high-speed interconnection protocol, refreshing the local address conversion hardware cache of each initial controller, and establishing an atomic validation mechanism to ensure the switching of address views across the entire system.

[0123] In this feasible implementation, discrete addresses can be converted into a linear continuous layout through alignment processing, eliminating the address gaps and fragmentation of traditional multi-controller architectures, providing applications with a unified memory access view, and improving storage accuracy.

[0124] A feasible implementation method can align the initial virtual addresses and initial physical addresses of multiple initial controllers through a main controller and allocate memory to the multiple initial controllers through the following method, including: determining a main controller from multiple initial controllers; obtaining multiple initial virtual addresses and multiple initial physical addresses corresponding to the multiple initial controllers through the main controller; according to the initial memory, aligning the multiple initial virtual addresses and the multiple initial physical addresses through the main controller to obtain multiple aligned virtual addresses and multiple aligned physical addresses; sending the corresponding aligned virtual addresses and the corresponding aligned physical addresses to the multiple initial controllers respectively, so that the multiple initial controllers establish memory pointers according to the corresponding aligned virtual addresses and the corresponding aligned physical addresses, so as to allocate memory to the multiple initial controllers.

[0125] Exemplarily, the master controller is elected from a plurality of initial controllers and is used to uniformly manage addresses of the plurality of initial controllers.

[0126] Optionally, multiple initial controllers elect a master controller through a hardware arbitration protocol.

[0127] Optionally, a main controller is determined based on the loads of multiple initial controllers, and an initial controller with a lower load is determined as the main controller to avoid overload of the main controller during operation.

[0128] Exemplarily, each initial controller establishes a corresponding memory pointer, and each memory pointer includes an aligned virtual address and a corresponding aligned physical address of the corresponding initial controller.

[0129] Optionally, the main controller reads information of each initial controller, and parses the information to obtain multiple initial virtual addresses and multiple initial physical addresses corresponding to the multiple initial controllers.

[0130] Optionally, the alignment process may be performed to reorganize the virtual space based on process isolation requirements (for example, one of the initial controllers exclusively occupies the 0x4000_0000~0x4FFF_FFFF addresses) to obtain aligned virtual addresses.

[0131] Optionally, the alignment process may generate a continuous physical sequence (eg, new address = global base address + original address offset) for running an offset folding algorithm to obtain an aligned physical address.

[0132] In this feasible implementation, the main controller uniformly performs alignment processing to ensure that multiple initial controllers have their own corresponding aligned virtual addresses for the initial memory, avoiding address conflicts and thus improving the accuracy of data storage.

[0133] A feasible implementation method, the storage method also includes: calculating and processing multiple aligned virtual addresses through a hash algorithm to obtain multiple controller identifiers; establishing a mapping relationship based on the multiple aligned virtual addresses and the multiple controller identifiers; sending the mapping relationship to the host so that the host sends a write request to the controller corresponding to the specified aligned virtual address according to the mapping relationship.

[0134] Combined with the scenario example, the above solution exemplifies the allocation of addresses. Next, the allocated address is synchronized to the host so that the host can accurately select the controller to send a write request.

[0135] For example, the memory allocation and topology between the controller and memory devices are managed only at the controller level. Hosts above the controller do not need to be aware of these relationships. The mapping relationship directly reflects the correspondence between the aligned virtual address and the controller identifier. Based on this mapping, the host can directly determine which controller to send a write request to.

[0136] In this feasible implementation, the mapping relationship is sent to the host, and the host can select a controller based on the mapping relationship. The host does not need to pay attention to topology changes between the controller and the memory device, thereby improving the host's work efficiency.

[0137] In a feasible implementation method, the storage method also includes: obtaining multiple first heartbeat information of multiple initial controllers through the main controller; determining a faulty controller and multiple normal controllers from the multiple initial controllers based on the multiple first heartbeat information; obtaining multiple loads corresponding to the multiple normal controllers; determining a backup controller from the multiple normal controllers based on the multiple loads; and sending a first switching indication to the host to instruct the backup controller to take over the faulty controller, the first switching indication including an identifier of the faulty controller and an identifier of the backup controller.

[0138] Exemplarily, multiple initial controllers periodically send first heartbeat information to the master controller, and the master controller determines whether the initial controllers are operating normally based on the first heartbeat information. If a faulty controller cannot store written data, a backup controller is designated to replace the faulty controller for data storage, and the host is notified so that the backup controller clearly replaces the faulty controller.

[0139] Illustratively, the host can clearly know that the standby controller has replaced the faulty controller based on the first switching instruction, and the subsequent write requests generated by the host are sent to the standby controller instead, so that the standby controller stores the write data.

[0140] Optionally, if the master controller fails, a new master controller is elected from the other controllers.

[0141] Next, combine Figure 10 Describes troubleshooting.

[0142] Figure 10 This is a schematic diagram of the troubleshooting provided in the embodiment of the present application. Figure 10 As shown, memory is allocated to multiple controllers so that multiple controllers can access the same memory area of ​​the memory device. At any time, only one controller, such as controller A, has I / O to the memory area, and other controllers have no I / O to the memory area to avoid access conflicts. When controller A fails, controller B takes over and only controller B has I / O to the memory area to achieve continuous access to the memory area in the event of a controller A failure. It should be noted that Figure 10 The storage system architecture is simplified and switches are not shown. This is only used to illustrate takeover in the event of a failure.

[0143] In the related art, for a cluster of multiple controllers, data is backed up through the multiple controllers in a circular mirror backup manner, and only one controller failure is allowed. If multiple controllers fail, cached data will be lost.

[0144] Using a scenario example, when a controller fails, the cluster will be aware of it. The cluster's active controller (if the failed controller is the active controller, the cluster will automatically elect another controller as the active controller) collects the current load of all controllers and selects the one with the lowest load as the standby controller. The standby controller then takes over the failed controller's data. The active controller notifies the standby controller via UDP / TCP to take over the failed controller's memory device write cache, allowing the standby controller to read and write to the failed controller's memory area. The active controller notifies the host's multipathing software to redirect I / O destined for the failed controller to the standby controller. The multipathing software then forwards the failed controller's I / O to the standby controller, which writes the user I / O to the memory device and asynchronously writes the data in the memory device to the hard disk. Based on the above implementation, this process only involves the transmission of control messages between cluster controllers and between the active controller and hosts, and does not generate a large amount of I / O. This is an efficient controller failover and memory data takeover process, improving data storage efficiency.

[0145] In this feasible implementation, when a controller fails, a first switch instruction is sent to the host, causing the host to write data to a functioning controller, thereby improving data storage reliability. Using memory devices for backup supports multiple controller failures; data can be read and written normally only if at least one functioning controller remains, thus improving the high availability of the storage system.

[0146] In a feasible implementation, the storage method further includes: obtaining a second heartbeat information of the failed controller through a Compute Express Link (CXL) device for backup, replacing the controller backup, supporting multiple controller failures, and improving the high availability of the storage system; determining whether the failed controller has returned to normal based on the second heartbeat information; and if so, sending a second switching indication to instruct the failed controller to take over the backup controller.

[0147] For example, after the faulty controller resumes normal operation, the original work of the faulty controller is re-executed to avoid the backup controller being overloaded due to too many tasks.

[0148] Optionally, the second heartbeat information of the faulty controller is continuously collected so that the backup controller can be taken over in time after the faulty controller returns to normal.

[0149] In this feasible implementation, after the faulty controller returns to normal, the faulty controller takes over the backup controller, which can effectively balance the load of the backup controller and thus improve storage efficiency.

[0150] In a feasible implementation, the storage method further includes: obtaining a first working state of the memory device, where the first working state is normal operation or abnormal operation; if the first working state is abnormal operation, sending a fault indication to the host to instruct the host to read and write data from the memory of the controller.

[0151] For example, if a memory device fails and the controller is functioning normally, the host is instructed to read and write data from the corresponding controller. Specifically, the DRAM of the controller is used to read and write data.

[0152] Optionally, each controller is connected to multiple memory devices. If any memory device fails, a spare memory device is used to take over the failed memory device.

[0153] In combination with the scenario example, a fault indication is sent to the host to instruct the host to stop accessing the memory device to prevent the host from making invalid access.

[0154] In this feasible implementation, when a memory device fails, the host is instructed to access a normally functioning controller to read and write data, which can effectively improve the accuracy of data reading and writing.

[0155] A feasible implementation method, after sending a fault indication to the host, may also include: obtaining a second working state of the memory device, the second working state being normal operation or abnormal operation; if the second working state is normal operation, sending a recovery indication to the host to instruct the host to read and write data from the memory of the memory device.

[0156] Illustratively, after the memory device resumes normal operation, the original work of the memory device is re-executed. Compared with the controller, the memory device has the advantage of high availability.

[0157] Optionally, the second working state of the memory device is continuously collected so that data can be read and written through the memory device in a timely manner after the memory device returns to normal.

[0158] In this feasible implementation, after the memory device returns to normal, data can be read and written through a memory device with higher reliability, thereby improving the reliability of data reading and writing.

[0159] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0160] Figure 11 This is a schematic diagram of the structure of the storage device provided in the embodiment of the present application. Figure 11As shown, an embodiment of the present application provides a storage device, which may include: a receiving module 111, a storage module 112, a sending module 113, and an execution module 114, wherein:

[0161] The receiving module 111 is configured to receive a write request through a controller, where the write request includes write data;

[0162] The storage module 112 is used to store the written data in the memory of the controller and send the written data to the switch;

[0163] The sending module 113 is used to send the written data to the memory device through the switch and the physical address corresponding to the controller;

[0164] The execution module 114 is configured to store and write data via a memory device.

[0165] Optionally, the receiving module 111 may execute Figure 7 S701 in the embodiment.

[0166] Optionally, the storage module 112 may execute Figure 7 S702 in the embodiment.

[0167] Optionally, the sending module 113 may execute Figure 7 S703 in the embodiment.

[0168] Optionally, the execution module 114 may execute Figure 7 S704 in the embodiment.

[0169] It should be noted that the storage device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principles and beneficial effects are similar, which will not be repeated here.

[0170] In a possible implementation, the sending module 113 is specifically configured to:

[0171] Determine a memory pointer corresponding to the controller, the memory pointer including a physical address of a memory in the memory device;

[0172] The write data and the memory pointer are sent to the switch, so that the switch sends the write data to the target memory in the memory device based on the memory pointer, and the physical address corresponds to the target memory.

[0173] Figure 12 A schematic diagram of the structure of a storage device provided in an embodiment of the present application. Figure 11 Based on the embodiment shown, Figure 12As shown, the storage device 110 further includes: a determination module 115, a response module 116, an update module 117, an initialization module 118, a mapping module 119, a first switching module 1110, a second switching module 1111, a first detection module 1112, and a second detection module 1113, wherein,

[0174] The determination module 115 is configured to:

[0175] Store the written data in the target memory;

[0176] Determine the target hard disk corresponding to the target memory from multiple hard disks connected to the memory device;

[0177] Store the written data on the destination hard disk.

[0178] The response module 116 is configured to send a response message to the host via the controller to indicate that the write request has been completed.

[0179] Update module 117, used to:

[0180] Determining target state information of the write data in the target memory;

[0181] Update the target status information to the stored status.

[0182] Initialization module 118 is used to:

[0183] Determine the initial memory from the memory pooled by the switch;

[0184] Mapping the initial memory to multiple initial controllers so that multiple initial controllers can access the initial memory;

[0185] Calling the initial memory through the multiple initial controllers to allocate initial virtual addresses and initial physical addresses to the multiple initial controllers;

[0186] The main controller aligns multiple initial virtual addresses and multiple initial physical addresses of the multiple initial controllers and allocates memory to the multiple initial controllers.

[0187] In a possible implementation, the initialization module 118 is specifically configured to:

[0188] determining a primary controller from among a plurality of initial controllers;

[0189] Acquire multiple initial virtual addresses and multiple initial physical addresses corresponding to the multiple initial controllers through the main controller;

[0190] According to the initial memory, the main controller performs alignment processing on the multiple initial virtual addresses and the multiple initial physical addresses respectively to obtain multiple aligned virtual addresses and multiple aligned physical addresses;

[0191] The corresponding aligned virtual addresses and the corresponding aligned physical addresses are respectively sent to the multiple initial controllers, so that the multiple initial controllers establish memory pointers according to the corresponding aligned virtual addresses and the corresponding aligned physical addresses, so as to allocate memory to the multiple initial controllers.

[0192] The mapping module 119 is configured to:

[0193] Calculate and process multiple aligned virtual addresses using a hash algorithm to obtain multiple controller identifiers;

[0194] Establishing a mapping relationship according to multiple aligned virtual addresses and multiple controller identifiers;

[0195] The mapping relationship is sent to the host, so that the host sends a write request to the controller corresponding to the specified aligned virtual address according to the mapping relationship.

[0196] The first switching module 1110 is configured to:

[0197] Acquire multiple first heartbeat information of multiple initial controllers through the main controller;

[0198] determining a faulty controller and a plurality of normal controllers from a plurality of initial controllers according to the plurality of first heartbeat information;

[0199] Get multiple loads corresponding to multiple normal controllers;

[0200] Determine a backup controller from multiple normal controllers based on multiple loads;

[0201] A first switching instruction is sent to the host to instruct the standby controller to take over the faulty controller, where the first switching instruction includes an identifier of the faulty controller and an identifier of the standby controller.

[0202] The second switching module 1111 is configured to:

[0203] Get the second heartbeat information of the faulty controller;

[0204] Determine whether the faulty controller has returned to normal based on the second heartbeat information;

[0205] If so, a second switching instruction is sent to the controller to instruct the failed controller to take over the standby controller.

[0206] The first detection module 1112 is configured to:

[0207] Acquire a first working state of the memory device, where the first working state is normal working or abnormal working;

[0208] If the first working state is abnormal working, a fault indication is sent to the host to instruct the host to read and write data from the memory of the controller.

[0209] The second detection module 1113 is configured to:

[0210] Acquire a second working state of the memory device, where the second working state is normal working or abnormal working;

[0211] If the second working state is normal operation, a recovery instruction is sent to the host to instruct the host to read and write data from the memory of the memory device.

[0212] For the description of the features in the embodiment corresponding to the storage device, please refer to the relevant description of the embodiment corresponding to the storage method, and no further details will be given here.

[0213] Figure 13 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 13 As shown, the electronic device 130 provided in this embodiment includes: at least one processor 1301 and a memory 1302. Optionally, the electronic device 130 further includes a communication component 1303. The processor 1301, the memory 1302 and the communication component 1303 are connected via a bus.

[0214] During the specific implementation process, at least one processor 1301 executes the computer-executable instructions stored in the memory 1302, so that the at least one processor 1301 executes the above-mentioned storage method embodiment.

[0215] The specific implementation process of the processor 1301 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0216] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0217] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0218] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0219] An embodiment of the present application further provides a non-volatile computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above storage method embodiments when running.

[0220] In an exemplary embodiment, the non-volatile computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0221] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above storage method embodiments are implemented.

[0222] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above storage method embodiments are implemented.

[0223] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0224] The above is a detailed introduction to a storage system, method, device, electronic device, medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A storage system, characterized in that: include: Multiple controllers, switches, and memory devices, the switches including multiple first interfaces and multiple second interfaces, the memory devices including multiple third interfaces; wherein, The multiple controllers are connected to the multiple first interfaces correspondingly, and for any target controller, the target controller is used to receive write data, store the write data in the memory of the target controller, and send the write data to the first target interface corresponding to the target controller; The plurality of second interfaces are connected to the plurality of third interfaces correspondingly, and the switch is configured to send the write data to the corresponding third target interface through the second target interface corresponding to the write data; The memory device is installed with multiple memory sticks, the multiple memory sticks are connected to the multiple third interfaces, and the memory device is used to store the written data in the physical address of the memory stick corresponding to the third target interface; The switch is further configured to perform pooling processing on the memories of the plurality of memory banks of the memory device to determine an initial memory; Also used for mapping the initial memory to multiple initial controllers so that the multiple initial controllers access the initial memory; the multiple controllers serve as initial controllers; When the initial controllers call the initial memory, the initial virtual addresses and the initial physical addresses are allocated to the initial controllers; The multiple controllers include a main controller, and the main controller is used to align the initial virtual addresses and the initial physical addresses of the multiple initial controllers and allocate memory to the multiple initial controllers.

2. The storage system according to claim 1, wherein: The multiple controllers include a main controller; wherein, The main controller is connected to other controllers, and is used to send write permissions of memory devices of other controllers to the other controllers.

3. The storage system according to claim 2, wherein: The target controller is used to send a target write permission to the first target interface; The switch includes a scheduler and multiple data lines, the scheduler is connected to the multiple data lines, the multiple data lines are used to connect the multiple first interfaces and the multiple second interfaces, the scheduler is used to determine the second target interface based on the target write permission, and connect the lines between the first target interface and the second target interface.

4. The storage system according to claim 1, wherein: The storage system also includes a hard disk component; wherein, The memory device is connected to the hard disk assembly, and the hard disk assembly is used to store the write data.

5. The storage system according to claim 4, wherein: The hard disk assembly includes a hard disk box and multiple hard disks; wherein, The hard disk box is connected to the memory device, and the hard disk box is used to manage the multiple hard disks; The multiple hard disks are connected in parallel to the hard disk box, and the hard disks are used to store data.

6. A storage method, characterized in that: Applied to the storage system according to any one of claims 1 to 5; the method comprising: receiving, by a controller, a write request, wherein the write request includes write data; storing the written data in the memory of the controller and sending the written data to the switch; sending the write data to the memory device via the switch, to the physical address corresponding to the controller; The write data is stored in the memory device.

7. The storage method according to claim 6, characterized in that: The write data is sent to the memory device through the switch, and the physical address corresponding to the controller includes: Determining a memory pointer corresponding to the controller, wherein the memory pointer includes a physical address of a memory in a memory device; The write data and the memory pointer are sent to a switch, so that the switch sends the write data to a target memory in the memory device based on the memory pointer, and the physical address corresponds to the target memory.

8. The storage method according to claim 7, characterized in that: Storing the written data by the memory device includes: storing the written data in the target memory; Determining a target hard disk corresponding to the target memory from a plurality of hard disks connected to the memory device; The write data is stored in the target hard disk.

9. The storage method according to claim 8, characterized in that: After storing the written data in the target memory, the method further includes: The controller sends a response message to the host to indicate that the write request has been completed.

10. The storage method according to claim 8, characterized in that: After storing the written data in the target hard disk, the method further includes: Determining target state information of the write data in the target memory; The target state information is updated to the stored state.

11. The storage method according to claim 6, characterized in that: The method further comprises: Determine the initial memory from the memory pooled by the switch; mapping the initial memory to a plurality of initial controllers so that the plurality of initial controllers can access the initial memory; Calling the initial memory through the multiple initial controllers to allocate initial virtual addresses and initial physical addresses to the multiple initial controllers; The main controller aligns the multiple initial virtual addresses and the multiple initial physical addresses of the multiple initial controllers, and allocates memory to the multiple initial controllers.

12. The storage method according to claim 11, characterized in that: Aligning initial virtual addresses and initial physical addresses of the multiple initial controllers by the main controller and allocating memory to the multiple initial controllers includes: determining a primary controller from among the plurality of initial controllers; Acquire, by the main controller, a plurality of initial virtual addresses and a plurality of initial physical addresses corresponding to the plurality of initial controllers; According to the initial memory, the main controller performs alignment processing on the multiple initial virtual addresses and the multiple initial physical addresses respectively to obtain multiple aligned virtual addresses and multiple aligned physical addresses; The corresponding aligned virtual addresses and the corresponding aligned physical addresses are respectively sent to the multiple initial controllers, so that the multiple initial controllers establish memory pointers according to the corresponding aligned virtual addresses and the corresponding aligned physical addresses to allocate memory to the multiple initial controllers.

13. The storage method according to claim 12, characterized in that: The method further comprises: Calculating and processing the multiple aligned virtual addresses using a hash algorithm to obtain multiple controller identifiers; Establishing a mapping relationship according to the multiple aligned virtual addresses and the multiple controller identifiers; The mapping relationship is sent to the host, so that the host sends a write request to the controller corresponding to the specified aligned virtual address according to the mapping relationship.

14. The storage method according to claim 13, characterized in that: The method further comprises: Acquire, by the main controller, a plurality of first heartbeat information of the plurality of initial controllers; determining a faulty controller and a plurality of normal controllers from the plurality of initial controllers according to the plurality of first heartbeat information; Acquire multiple loads corresponding to the multiple normal controllers; determining a backup controller from the plurality of normal controllers according to the plurality of loads; A first switching instruction is sent to the host to instruct the standby controller to take over the faulty controller, where the first switching instruction includes an identifier of the faulty controller and an identifier of the standby controller.

15. The storage method according to claim 14, characterized in that: The method further comprises: Obtaining second heartbeat information of the faulty controller; determining, based on the second heartbeat information, whether the faulty controller has returned to normal; If so, a second switching instruction is sent to the controller to instruct the faulty controller to take over the standby controller.

16. The storage method according to claim 6, characterized in that: The method further comprises: Acquire a first working state of the memory device, where the first working state is normal working or abnormal working; If the first working state is abnormal, a fault indication is sent to the host to instruct the host to read and write data from the memory of the controller.

17. The storage method according to claim 6, characterized in that: After sending the fault indication to the host, it also includes: Acquire a second working state of the memory device, where the second working state is normal working or abnormal working; If the second working state is normal, a recovery instruction is sent to the host to instruct the host to read and write data from the memory of the memory device.

18. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the storage method according to any one of claims 6 to 17 when executing the computer program.

19. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the storage method according to any one of claims 6 to 17 when executed by a processor.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the storage method according to any one of claims 6 to 17 are implemented.

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