Numerical data processing method and related processing device

Abstract

The invention discloses a numerical data processing method, which comprises the following steps of: converting a plurality of original numerical values of data into a plurality of candidate sequences; and determining a maximum value, a minimum value and at least one survival value of the candidate sequence according to a sorting result of the plurality of candidate sequences, wherein the plurality of candidate number columns are one-hot codes.

Description

Technical Field

[0001] The present invention relates to a numerical data processing method and a related processing device, and in particular to a numerical data processing method capable of analyzing and classifying numerical values and a related processing device. Background Art

[0002] Existing deep learning data analysis applications, such as neural networks or survival path detectors, require analyzing both the data distribution and ordering to identify the data's eigenvalues. Alternatively, they need to identify the distribution and ordering of values to use as a classifier and then identify a specific range of values, a process known as survival value searching.

[0003] Existing hardware technology for implementing this method requires multiple comparators and counters to calculate data distribution, as well as a highly complex sorter network for sorting. However, as the number of inputs increases, more D-type flip-flop circuit pipelines are required, resulting in a larger hardware circuit area.

[0004] Therefore, the existing technology needs to be improved. Summary of the Invention

[0005] In view of this, the present invention provides a numerical data processing method and a related processing device thereof, which analyze and classify numerical data using a shorter circuit critical path.

[0006] An embodiment of the present invention discloses a numerical data processing method, comprising converting multiple original numerical values of data into multiple candidate number sequences; and determining a maximum value, a minimum value, and at least one survival value of the candidate number sequences based on a sorting result of the multiple candidate number sequences; wherein the multiple candidate number sequences are one-hot encoded.

[0007] An embodiment of the present invention further discloses a numerical data processing circuit, comprising a shifter circuit for receiving multiple original numerical values of data and converting the multiple original numerical values of the data into multiple candidate number sequences; a sorting circuit for sorting the multiple candidate number sequences and determining a maximum value and a minimum value of the candidate number sequences based on a sorting result of the multiple candidate number sequences; and a data distribution circuit for determining at least one survival value based on the multiple candidate number sequences; wherein the multiple candidate number sequences are one-hot encoded. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1is a schematic diagram of a numerical data processing method according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a numerical data processing device according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a sorting circuit according to an embodiment of the present invention;

[0011] Figure 4 FIG. 4 is a schematic diagram of a data distribution circuit according to an embodiment of the present invention.

[0012] Description of reference numerals:

[0013] 10: Numerical Data Processing Method 102-110: Step 20: Numerical Data Processing Device

[0014] 202: Shifter circuit 204: Sorting circuit 206: Data distribution circuit

[0015] 204_2: logical OR circuit 204_4: leading / last 1 detection circuit 206: data distribution circuit

[0016] 206_2: Adder circuit 206_4: Value distribution / classification circuit ADDER: Adder

[0017] OR: Logical OR S_1: First sequence S_2: Second sequence

[0018] shifter: shifter DETAILED DESCRIPTION

[0019] Please refer to Figure 1 , Figure 1 Figure 1 is a schematic diagram of a numerical data processing method 10 according to an embodiment of the present invention. This method 10 can be used in a multiple-input, multiple-output (MIMO) system of a wireless network. After a MIMO antenna receives a signal, it calculates the distances between signal constellation points in a constellation diagram, sorts the distance values, analyzes their distribution, and finds the eigenvalues of the numerical data. This method 10 includes the following steps:

[0020] Step 102: Start;

[0021] Step 104: receiving data;

[0022] Step 106: converting the multiple original numerical values of the data into multiple candidate number sequences;

[0023] Step 108: Determine a maximum value, a minimum value, and at least one survival value of the sequence according to a sorting result of the plurality of candidate sequence;

[0024] Step 110: End.

[0025] The numerical data processing method 10 of the embodiment of the present invention receives numerical data in step 104. In step 106, the plurality of original numerical values of the data are converted into a plurality of candidate number sequences, where the candidate number sequences are one-hot encoded, i.e., each candidate number sequence includes at most one value range of 1.

[0026] In one embodiment, step 106 converts the decimal 3-digit value into an 8-bit value. For example, the 3-digit value 6 (3'd6) is converted into the 8-bit candidate number sequence 01000000. Next, step 108 determines the maximum value, minimum value, or survival value among the candidate number sequences based on the plurality of candidate number sequences.

[0027] For details, please refer to Figure 2 , Figure 2 Figure 2 is a schematic diagram of a numerical data processing device 20 according to an embodiment of the present invention. Numerical data processing device 20 includes a shifter circuit 202, a sorting circuit 204, and a data distribution circuit 206. Sorting circuit 204 includes a logical OR circuit 204_2 and a leading / trailing 1 detection circuit 204_4. Data distribution circuit 206 includes an adder circuit 206_2 and a numerical distribution / classification circuit 206_4. In one embodiment, shifter circuit 202 includes multiple shifters, logical OR circuit 204_2 includes multiple logical ORs, and adder circuit 206_2 includes multiple adders.

[0028] The numerical data processing device 20 of the embodiment of the present invention converts the original numerical value into a candidate number sequence through the shifter circuit 202, so as to facilitate the numerical data processing device 20 to process the format of the numerical data (to implement step 106).

[0029] Regarding the method of parallel expansion of the original numerical values into candidate number sequences by the numerical data processing device 20, please refer to Figure 3 , Figure 3 FIG2 is a schematic diagram of the sorting circuit 204 according to an embodiment of the present invention. In this example, the original 3-bit values 3'd6, 3'd2, 3'd5, 3'd6, 3'd5, and 3'd3 are input to the shifter circuit 202 to be expanded in parallel into 8-bit one-hot codes (i.e., candidate sequences).

[0030] Next, the logical OR circuit 204_2 of the sorting circuit 204 performs a logical OR operation on the same bits in each candidate sequence to obtain a first sequence S_1. The leading / last 1 detection circuit 204_4 then detects the first sequence S_1, using the value corresponding to a leading 1 in the first sequence S_1 as the maximum value of the original values and the value corresponding to the last 1 in the first sequence S_1 as the minimum value of the original values.

[0031] In other words, to find the maximum value among all the original values, we can find the position of the first bit 1 in the first sequence S_1 to obtain the maximum value of the original values. Similarly, values of other order of magnitude can also be found in this way. For example, the second largest value in the first sequence S_1 is 3'd5, and the smallest value is 3'd2.

[0032] Please refer to Figure 4 , Figure 4 Figure 2 is a schematic diagram of data distribution circuit 206 according to an embodiment of the present invention. In this example, data distribution circuit 206 uses adder circuit 206_2 to perform a logical sum operation on the same bits in each candidate sequence to generate a second sequence S_2. In this case, a 1-bit counter (perhaps a T-type flip-flop) can be used to calculate second sequence S_2. By summing the values of the corresponding bits in second sequence S_2, it is determined that 3'd7 is 0, 3'd6 is 2, 3'd5 is 2, 3'd4 is 0, 3'd3 is 1, 3'd2 is 1, and 3'd0 is 0.

[0033] In this way, the data distribution circuit 206 can determine a data value distribution of the original value according to the second number sequence S_2 through the value distribution / classification circuit 206_4.

[0034] Therefore, the numerical data processing method 10 of the embodiment of the present invention can be used Figure 4 The data distribution circuit 206 calculates the number of different values to obtain the statistical information of the original value, and then combines Figure 3 The sorting circuit 204 determines the number or value that needs to be retained (i.e., the survival value) and is used to perform the survival path search function, which is then fed back to the deep learning network.

[0035] In addition, by Figure 3 as well as Figure 4 It can be seen that the sorting circuit 204 and the data distribution circuit 206 of the numerical data processing device 20 of the embodiment of the present invention are implemented in a parallel processing manner, which can reduce the number of cascade circuits in the circuit, thereby achieving a circuit design with a shorter critical path.

[0036] It is worth noting that the numerical data processing device 20 of the above embodiment can also be implemented using a field programmable gate array (FPGA). The circuit designs of the shifter circuit, adder circuit, logical OR circuit, and leading / last 1 detection circuit can be modified according to different requirements and fall within the scope of patent protection of the present invention.

[0037] In summary, the present invention discloses a numerical data processing method and a related processing device thereof to achieve circuit processing with a shorter critical path, thereby realizing the effects of data sorting and data distribution.

[0038] The above descriptions are only preferred embodiments of the present invention. Equivalent changes and modifications made according to the scope of patent protection of the present invention should fall within the scope of patent protection of the invention.

Claims

1. A numerical data processing method, comprising: Convert multiple original numerical values of the data into multiple candidate number sequences; as well as Determining a maximum value, a minimum value, and at least one survival value of the candidate number sequences according to a sorting result of the plurality of candidate number sequences; The multiple candidate number sequences are one-hot encoded.

2. The numerical data processing method according to claim 1, characterized in that: The step of determining the maximum value, the minimum value, and the at least one survival value of the candidate number sequence according to the sorting results of the plurality of candidate number sequences includes: Performing a logical OR operation on the same bits of each candidate number sequence to obtain a first number sequence; and A value corresponding to a leading value 1 of the first number sequence is used as a maximum value of the plurality of original values, and a value corresponding to a last value 1 of the first number sequence is used as a minimum value of the plurality of original values.

3. The numerical data processing method according to claim 1, characterized in that: The step of determining the maximum value, the minimum value, and the at least one survival value of the candidate number sequence according to the sorting results of the plurality of candidate number sequences includes: Performing a logical AND operation on the same bits of each candidate number sequence to obtain a second number sequence; and A data value distribution of the plurality of original values is determined according to the second number sequence.

4. The numerical data processing method according to claim 1, wherein: The conversion of the plurality of candidate number sequences into the plurality of candidate number sequences is implemented by a field programmable logic gate array.

5. The numerical data processing method according to claim 1, wherein: Also includes: A survival path search is performed based on the at least one survival value of the candidate sequence for use in a deep learning network.

6. A numerical data processing circuit comprising: a shifter circuit for receiving a plurality of original values of data and converting the plurality of original values of data into a plurality of candidate number sequences; a sorting circuit, configured to sort the plurality of candidate number sequences and determine a maximum value and a minimum value of the candidate number sequences according to a sorting result of the plurality of candidate number sequences; as well as a data distribution circuit for determining at least one survival value based on the plurality of candidate number sequences; The multiple candidate number sequences are one-hot encoded.

7. The numerical data processing device according to claim 6, characterized in that The sorting circuit includes a logical OR circuit and a leading / last 1 detection circuit, configured to perform a logical OR operation on the same bits of each candidate number sequence to obtain a first number sequence. The leading / last 1 detection circuit uses the value corresponding to a leading value 1 of the first number sequence as a maximum value of the plurality of original values, and uses the value corresponding to a last value 1 of the first number sequence as a minimum value of the plurality of original values.

8. The numerical data processing device according to claim 6, wherein The data distribution circuit includes an adder circuit and a numerical distribution / classification circuit, which is used to perform a logical AND process on the same bits of each number sequence of the candidate number sequence to obtain a second number sequence; and the numerical distribution / classification circuit determines a data value distribution of the multiple original numerical values based on the second number sequence.

9. The numerical data processing device according to claim 6, wherein: The conversion of the plurality of candidate number sequences into the plurality of candidate number sequences is implemented by a field programmable logic gate array.

10. The numerical data processing device according to claim 6, wherein The data distribution circuit further includes a value distribution / classification circuit for performing a survival path search function based on the at least one survival value of the candidate sequence for use in a deep learning network.

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