Instruction fetch module and processor

Abstract

The present invention proposes an instruction fetch module and processor. A primary prediction unit generates and sends a first predicted address based on a first historical reference address and a stack top address. An instruction queue generates and sends corresponding hit information based on the first historical reference address. In the event of a miss, the instruction cache retrieves and sends the instruction corresponding to the first historical reference address. In the event of a hit, the instruction queue sends the instruction corresponding to the hit information to a secondary prediction unit. The secondary prediction unit generates a second predicted address based on the received instruction and reference address, and if it differs from the first predicted address, it provides the second predicted address to the reference unit. The primary prediction unit ensures address prediction speed, thereby improving instruction fetch speed. Furthermore, a secondary prediction unit is provided for joint prediction, ensuring the accuracy of the prediction results. This eliminates the problem of insufficient bandwidth utilization caused by relying solely on sequential instruction fetching, and improves the processing efficiency of branch instructions.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to an instruction fetch module and a processor. Background Art

[0002] With the rapid development of artificial intelligence and high-performance computing, processor architectures are facing increasing demands for parallel computing. The VLIW (Very Long Instruction Word) architecture has been widely used in the field of specialized processors due to its high parallelism and simple hardware implementation.

[0003] The VLIW architecture is an explicitly parallel instruction computing architecture that packages multiple instructions that can be executed in parallel into a very long instruction word. Unlike superscalar processors, the VLIW architecture shifts the complexity of instruction scheduling from hardware to the compiler, thereby simplifying processor design.

[0004] The importance of the VLIW architecture to NPUs (Neural Processing Units) lies in the following aspects: It significantly improves parallel computing capabilities by packaging and executing multiple operations within a single instruction cycle. This is crucial for NPUs because deep learning tasks, such as matrix multiplication and activation functions in convolutional neural networks, are highly parallel. The VLIW architecture enables NPUs to process multiple data points or data streams simultaneously, making them highly efficient at handling large-scale parallel computing tasks. It also simplifies the hardware structure. The VLIW architecture typically has a simpler hardware structure; it only needs to execute programs compiled by the compiler without controlling resource scheduling. This design significantly reduces hardware complexity.

[0005] The VLIW architecture delegates instruction scheduling to the compiler, requiring it to identify instructions that can be executed in parallel and pack them into a very long instruction word. While this increases the complexity of the compiler, for specialized hardware like the NPU, the compiler can be optimized for specific deep learning algorithms, achieving higher performance.

[0006] Branch and jump instructions are crucial in computer programming, enabling program execution, loop control, function calls, and returns. In practical applications, branch and jump instructions account for a significant portion of program execution. However, the execution of branch and jump instructions results in a new PC address, which can create challenges for the processor's pipeline and instruction prefetching stages. Therefore, branch and jump prediction have become crucial optimization techniques in processor design, significantly improving performance. Summary of the Invention

[0007] The object of the present invention is to provide an instruction fetch module and a processor to improve the above-mentioned problem.

[0008] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0009] In a first aspect, an embodiment of the present invention provides an instruction fetch module, the instruction fetch module comprising: a reference unit, a primary prediction unit, a register group, a secondary prediction unit, an instruction queue, a return address stack, and an instruction cache;

[0010] When the instruction fetch module is in operation, the reference unit is used to generate a reference address according to the address data acquired in the current clock cycle;

[0011] The primary prediction unit is configured to generate a first predicted address based on a first historical reference address and a stack top address, and send the first predicted address to the reference unit and the register group; the first historical reference address is a reference address generated by the reference unit in a previous clock cycle, and the stack top address is an address stored at the top of a return address stack in a current clock cycle;

[0012] The instruction queue is used to generate corresponding hit information according to the first historical reference address and send the hit information to the register group and the instruction cache;

[0013] The register group is used to obtain the first historical reference address, provide the hit information received in the previous K clock cycles to the instruction queue, and provide the first predicted address received in the previous K clock cycles and its corresponding reference address to the secondary prediction unit;

[0014] The instruction cache is used to obtain the instruction corresponding to the first historical reference address when the first historical reference address does not hit the instruction queue, and send the corresponding instruction to the secondary prediction unit and the instruction queue after K clock cycles;

[0015] The instruction queue is used to send the instruction corresponding to the hit information to the secondary prediction unit when the hit information read from the register group indicates a hit;

[0016] The secondary prediction unit is configured to generate a second prediction address according to the received instruction and the reference address, and provide the second prediction address to the reference unit if the second prediction address is different from the first prediction address.

[0017] Optionally, the secondary prediction unit is further configured to generate a first type error signal to the instruction cache when the second predicted address is different from the first predicted address, so as to cause the instruction cache to suspend instruction fetching.

[0018] Optionally, the primary prediction unit includes a branch target buffer, a first adder, and a second selector;

[0019] An input terminal of the branch target buffer is connected to the reference unit, a first output terminal of the branch target buffer is connected to the control terminal of the second selector, and a second output terminal of the branch target buffer is connected to the first input terminal of the second selector;

[0020] The input terminal of the first adder is connected to the reference unit, and the output terminal of the first adder is connected to the second input terminal of the second selector;

[0021] The third input terminal of the second selector is connected to the return address stack, and the output terminal of the second selector serves as the output terminal of the preliminary prediction unit, for outputting the first predicted address.

[0022] Optionally, the branch target buffer is configured to provide a Return instruction to the control terminal of the second selector when the instruction corresponding to the first historical reference address is a Return instruction;

[0023] The second selector is configured to, upon receiving a Return indication, switch the third input terminal and the output terminal thereof to conduct, and use the stack top address as the first predicted address of the current clock cycle;

[0024] When the instruction corresponding to the first historical reference address is a non-Return instruction, the branch target buffer is configured to perform address prediction based on the first historical reference address, and when a valid predicted address is obtained, provide the valid predicted address to the second selector;

[0025] The second selector is configured to, upon receiving a valid predicted address, switch the first input terminal and the output terminal thereof to conduct, and use the predicted address of the branch target buffer as the first predicted address of the current clock cycle;

[0026] The first adder is used to obtain a sequential address according to the first historical reference address;

[0027] When the instruction corresponding to the first historical reference address is a non-Return instruction and the predicted address of the branch target buffer is invalid, the second selector is also used to switch the first input and output ends inside it to conduct, and use the sequential address generated by the first adder as the first predicted address of the current clock cycle.

[0028] Optionally, the register group includes a first register and a second register, the first register is connected to the instruction queue, the reference unit, the primary prediction unit and the second register respectively, and the second register is connected to the instruction queue and the secondary prediction unit respectively;

[0029] The first register is used to obtain a first historical reference address and a first predicted address generated in a current clock cycle, and obtain hit information generated by the instruction queue in the current clock cycle;

[0030] The second register is used to provide the reference address and first prediction address written by itself in the previous clock cycle to the secondary prediction unit, provide the hit information written by itself in the previous clock cycle to the instruction queue, and obtain the reference address, first prediction address and hit information written by the first register in the previous clock cycle.

[0031] Optionally, the secondary prediction unit includes a branch decoder, a second adder, a jump predictor, a fourth selector, and a discriminator;

[0032] The first input terminal of the branch decoder is connected to the instruction cache, the second input terminal of the branch decoder is connected to the instruction queue, the first output terminal of the branch decoder is connected to the first control terminal of the fourth selector and the return address stack, and the second output terminal of the branch decoder is connected to the first input terminal of the fourth selector;

[0033] An input terminal of the second adder is connected to the register group, and an output terminal of the second adder is connected to a second input terminal of the fourth selector and the return address stack;

[0034] The third input terminal of the fourth selector is connected to the return address stack;

[0035] The input end of the jump predictor is connected to the register group, and the output end of the jump predictor is connected to the second control end of the fourth selector;

[0036] A first input terminal of the discriminator is connected to the register group, a second input terminal of the discriminator is connected to the output terminal of the fourth selector, a first output terminal of the discriminator is connected to the reference unit, and a second output terminal of the discriminator is connected to the instruction cache.

[0037] Optionally, the branch decoder is configured to decode the received instruction, send the decoded instruction type to the fourth selector and the return address stack, and send the decoded branch target address to the fourth selector;

[0038] The second adder is used to obtain a sequential address according to the reference address read from the register group, and send the obtained sequential address to the fourth selector and the return address stack;

[0039] The jump predictor is used to generate an indication signal according to a reference address read from the register group, wherein the indication signal indicates whether a jump is required;

[0040] The fourth selector is configured to switch its internal conduction relationship according to the received instruction type and indication signal, use one of the obtained branch target address, sequential address, and stack top address as the second predicted address of the current clock cycle, and send the obtained second predicted address to the discriminator;

[0041] The discriminator is used to determine whether the second predicted address received in the current clock cycle is the same as the first predicted address, and if they are different, provide the second predicted address to the reference unit.

[0042] Optionally, when the instruction type obtained by the branch decoder is a Call instruction, the return address stack is used to push the sequential addresses received in the current clock cycle into the stack;

[0043] When the instruction type obtained by the branch decoder is a Return instruction and there is a valid address in the return address stack, the return address stack is used to push out the top address of the stack;

[0044] When the instruction type obtained by the branch decoder is a Return instruction and there is no valid address in the return address stack, the instruction fetch module changes from a running state to a waiting state until the back-end branch execution unit parses the return address of the Return instruction and transmits it as a result address to the reference unit, at which time the instruction fetch module resumes the running state.

[0045] Optionally, when the instruction type obtained by the branch decoder is a Return instruction, the fourth selector is used to switch the third input terminal and the output terminal thereof to be connected, and use the stack top address as the second predicted address of the current clock cycle;

[0046] When the instruction type obtained by the branch decoder is a Jal instruction, the fourth selector is used to switch the first input terminal and the output terminal thereof to be connected, and use the received branch target address as the second predicted address of the current clock cycle;

[0047] When the instruction type obtained by the branch decoder is a non-Jal instruction and a non-Return instruction, if the indication signal indicates that a jump is required, the fourth selector is used to switch the first input terminal and the output terminal thereof to be connected, and use the received branch target address as the second predicted address of the current clock cycle;

[0048] When the instruction type obtained by the branch decoder is a non-Jal instruction and a non-Return instruction, if the indication signal indicates that no jump is required, the fourth selector is used to switch the second input end and the output end thereof to be connected, and use the received sequential address as the second predicted address of the current clock cycle.

[0049] In a second aspect, an embodiment of the present invention provides a processor including the above-mentioned instruction fetch module.

[0050] Compared with the prior art, the embodiment of the present invention provides an instruction fetch module and processor, wherein the primary prediction unit generates a first prediction address based on the first historical reference address and the stack top address, and sends it to the reference unit and the register group; the instruction queue generates corresponding hit information based on the first historical reference address, and sends it to the register group and the instruction cache; when the first historical reference address does not hit the instruction queue, the instruction cache obtains the instruction corresponding to the first historical reference address and sends it to the secondary prediction unit and the instruction queue; when the instruction queue hits, the instruction corresponding to the hit information is sent to the secondary prediction unit; the secondary prediction unit generates a second prediction address based on the received instruction and reference address, and provides the second prediction address to the reference unit if the second prediction address is different from the first prediction address. By setting up the primary prediction unit, the address prediction speed can be guaranteed, thereby improving the instruction fetch speed. At the same time, a secondary prediction unit is also provided for joint prediction, which can ensure the accuracy of the prediction result, get rid of the problem of insufficient bandwidth utilization caused by relying solely on sequential instruction fetch, and improve the processing efficiency of branch instructions.

[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 A schematic diagram of the architecture of an instruction fetch module provided in an embodiment of the present invention.

[0054] Figure 2 A schematic diagram of the architecture of a reference unit and a preliminary prediction unit provided by an embodiment of the present invention.

[0055] Figure 3 A schematic diagram of the architecture of a secondary prediction unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0058] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0059] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0060] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0061] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0062] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0063] The present invention provides an instruction fetch module that can solve one or more of the following problems: a simple sequential instruction fetch method cannot fully utilize bandwidth; an insufficient instruction fetch prediction accuracy leads to pipeline stalls; a long instruction word cache is inefficient; and a branch instruction processing is inefficient. For details, please refer to Figure 1 , Figure 1 A schematic diagram of the architecture of an instruction fetch module provided in an embodiment of the present invention.

[0064] The instruction fetch module includes: a reference unit, a primary prediction unit, a register group, a secondary prediction unit, an instruction queue, a return address stack, and an instruction cache, wherein the register group includes K registers connected in sequence, where K is greater than or equal to 1. Figure 1 In the example, K=2 is used, that is, the register group includes a first register and a second register.

[0065] The reference unit is connected to the primary prediction unit, the first register, the instruction queue, the instruction cache and the secondary prediction unit respectively. The primary prediction unit is also connected to the return address stack and the register group. The register group is also connected to the secondary prediction unit and the instruction queue. The secondary prediction unit is also connected to the return address stack, the instruction queue and the instruction cache.

[0066] When the instruction fetch module is in operation, the reference unit is used to generate a reference address according to the address data acquired in the current clock cycle.

[0067] Among them, the address data obtained by the reference unit can be any one or more of the first predicted address generated by the primary prediction unit in the current clock cycle, the second predicted address generated by the secondary prediction unit in the current clock cycle (for example, the clock cycle is 1 second, at the 23rd second the address predicted by the primary prediction unit is 40, and the predicted address by the secondary prediction unit is 60. At 24 seconds, the first historical reference address will become 60. There is only one clock cycle from the time the prediction unit predicts the address to the time the predicted address is predicted again), a reset address, and a result address, and the result address is the target address of the branch instruction parsed by the branch execution unit.

[0068] In an optional embodiment, the priorities of the reset address, result address, second predicted address, and first predicted address are sequentially reduced. When the reference unit simultaneously obtains the above data, the reference address is determined according to the priority. Specifically, when the reset address is obtained, the reset address is used as the reference address for the current clock cycle; when the result address is obtained but the reset address is not obtained, the result address is used as the reference address for the current clock cycle; when only the first predicted address and the second predicted address are obtained, the second predicted address is used as the reference address for the current clock cycle; when only the first predicted address is obtained, the first predicted address is used as the reference address for the current clock cycle.

[0069] The Return Address Stack (RAS) is a specialized data structure used to store function call and return addresses, ensuring a correct return to the previous call point when a branch instruction is executed. The RAS provides the top address of the stack in the current clock cycle. Branch instructions are control transfer instructions defined in the RISC-V instruction set.

[0070] The primary prediction unit is used to generate a first predicted address according to the first historical reference address and the stack top address, and send the first predicted address (the first predicted address) to the reference unit and the register group.

[0071] The first historical reference address is a reference address generated by the reference unit in the previous clock cycle, and the stack top address is an address stored in the stack top of the return address stack in the current clock cycle.

[0072] The instruction queue is used to generate corresponding hit information according to the first historical reference address and send the hit information to the register group and the instruction cache.

[0073] The hit information is used to indicate whether the first historical reference address hits the instruction queue. In the case of a hit, the hit information also includes the hit address.

[0074] The register group is used to obtain the first historical reference address, provide the hit information received in the first K clock cycles to the instruction queue, and provide the first predicted address received in the first K clock cycles and its corresponding reference address to the secondary prediction unit.

[0075] Here, K represents the number of registers connected in sequence in the register group.

[0076] The instruction cache is used to obtain the instruction corresponding to the first historical reference address when the first historical reference address does not hit the instruction queue. If the first historical reference address hits the instruction cache, the corresponding instruction is sent to the secondary prediction unit and the instruction queue after K clock cycles.

[0077] The instruction cache is a high-speed memory in the processor used to quickly access instructions. It is designed to reduce the delay of reading instructions from main memory. By storing frequently used instructions, it improves the overall performance and execution efficiency of the system.

[0078] If the first historical reference address misses the instruction cache, the instruction cache generates a miss signal to stop updating registers in the instruction fetch module (including the first and second registers in the register group and the third register in the reference unit). After the instruction corresponding to the first historical reference address is retrieved from main memory, a resume signal is generated to resume updating registers in the instruction fetch module. The instructions in the instruction queue are available for call by the backend module.

[0079] The instruction queue is used to send the instruction corresponding to the hit information to the secondary prediction unit when the hit information read from the register group indicates a hit.

[0080] The instruction queue consists of a microinstruction cache, an address FIFO queue, and an instruction counter. The address FIFO queue stores the addresses of instructions that have been predicted but not yet issued, while the microinstruction cache stores instructions that have not yet been issued. The instruction counter records the number of times each instruction in the instruction queue has been issued.

[0081] The secondary prediction unit is configured to generate a second prediction address according to the received instruction and the reference address, and provide the second prediction address to the reference unit when the second prediction address is different from the first prediction address.

[0082] In the instruction fetch module provided in the embodiment of the present invention, a primary prediction unit is provided to ensure the address prediction speed and thus improve the instruction fetch speed. At the same time, a secondary prediction unit is provided for joint prediction, which can ensure the accuracy of the prediction results, get rid of the problem of insufficient bandwidth utilization caused by relying solely on sequential instruction fetch, and improve the processing efficiency of branch instructions.

[0083] In an optional embodiment, the secondary prediction unit is further configured to generate a first type error signal to the instruction cache when the second predicted address is different from the first predicted address, so as to cause the instruction cache to suspend instruction fetching.

[0084] After receiving the first type of error signal, the instruction cache suspends fetching instructions according to the reference address, optionally for one clock cycle. In addition, the secondary prediction unit controls the first register and the second register to be cleared, and the secondary prediction unit is in a suspended prediction state.

[0085] In the case that the second predicted address is the same as the first predicted address, the second predicted address and the first type error signal do not need to be sent.

[0086] In an optional embodiment, upon determining an address prediction error, the backend execution unit may also send a second type of error signal to the instruction cache, indicating a prediction error by the instruction fetch module. Upon receiving the second type of error signal, the instruction cache will also pause instruction fetching from the reference address for one clock cycle and resume fetching instructions from the reference address on the next clock cycle.

[0087] exist Figure 1 On the basis of the structure of the reference unit and the preliminary prediction unit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 A schematic diagram of the architecture of a reference unit and a preliminary prediction unit provided by an embodiment of the present invention.

[0088] The reference unit includes a first selector S1 and a third register. The first input of the first selector S1 is connected to the output of the primary prediction unit for receiving the first predicted address; the second input of the first selector S1 is connected to the output of the second prediction unit for receiving the second predicted address; the third input of the first selector S1 is used to receive the reset address; the fourth input of the first selector S1 is used to receive the result address; the output of the first selector S1 is connected to the input of the third register, and the third register is connected to the instruction queue, the first register, the primary prediction unit, and the instruction cache.

[0089] The first selector S1 can switch the internal conduction relationship according to the rule that the priorities of the reset address, result address, second predicted address and first predicted address decrease in sequence, and write the corresponding address data into the third register as the reference address of the current clock cycle.

[0090] It should be noted that the reference address written into the third register will be read and called by the instruction queue, the first register, the preliminary prediction unit and the instruction cache in the next clock cycle.

[0091] In an optional embodiment, the control end of the first selector S1 is further connected to an instruction queue. The instruction queue is configured to send a pause instruction to the first selector S1 when its internal storage space is insufficient, so that the first selector S1 stops writing the reference address to the third register, and the reference address output by the third register is invalid.

[0092] Optionally, when the remaining space in the instruction queue is less than a preset length and the first historical reference address does not hit the instruction queue, it is determined that the internal storage space is insufficient; or, when the remaining space in the instruction queue is less than a preset length, the first historical reference address hits the instruction queue, but the number of hits exceeds a preset threshold, it is determined that the internal storage space is insufficient.

[0093] After the space of the instruction queue is restored, the pause instruction is stopped from being sent to the first selector S1, so that the first selector S1 resumes writing the reference address to the third register, and the reference address output by the third register is valid.

[0094] Please continue to refer to Figure 2 The primary prediction unit includes a branch target buffer, a first adder ADD1 and a second selector.

[0095] An input terminal of the branch target buffer is connected to the reference unit, a first output terminal of the branch target buffer is connected to the control terminal of the second selector, and a second output terminal of the branch target buffer is connected to the first input terminal of the second selector.

[0096] An input terminal of the first adder ADD1 is connected to the reference unit, and an output terminal of the first adder ADD1 is connected to the second input terminal of the second selector.

[0097] The third input of the second selector is connected to the return address stack, and the output of the second selector serves as the output of the primary prediction unit (connected to the first input of the first selector in the register group and the reference unit) for outputting the first predicted address.

[0098] The branch target buffer is used to store the mapping relationship between the address of the executed branch instruction and the target address of the jump during the most recent execution, as well as whether the executed branch instruction is a Return instruction.

[0099] It should be noted that after the branch instruction is executed, the corresponding target address (result address) of the jump during execution will be written into the branch target buffer, thereby establishing a corresponding mapping relationship.

[0100] In an optional embodiment, the branch target buffer is configured to provide a Return instruction to the control terminal of the second selector when the instruction corresponding to the first historical reference address is a Return instruction.

[0101] Optionally, the branch target buffer queries whether the first historical reference address is recorded therein. If so, a further determination is made as to whether the instruction corresponding to the first historical reference address is a Return instruction. If it is not a Return instruction, the relationship between the factors is further determined, and the adjusted address corresponding to the first historical reference address is used as the predicted address.

[0102] The second selector is used to switch the third input terminal and the output terminal thereof to be connected when receiving the Return instruction, and use the stack top address as the first predicted address of the current clock cycle.

[0103] When the instruction corresponding to the first historical reference address is a non-Return instruction, the branch target buffer is used to perform address prediction based on the first historical reference address, and when a valid predicted address is obtained, the valid predicted address is provided to the second selector.

[0104] The second selector is used to switch the first input terminal and the output terminal thereof to be connected when receiving a valid predicted address, and use the predicted address of the branch target buffer as the first predicted address of the current clock cycle.

[0105] The first adder ADD1 is configured to obtain a sequential address according to the first historical reference address.

[0106] Optionally, a preset value is added to the first historical reference address to obtain a corresponding sequential address. The preset value may be, but is not limited to, 4, 8, 12, 16, etc., and is set according to the VLIW instruction length corresponding to the processor.

[0107] When the instruction corresponding to the first historical reference address is a non-Return instruction and the predicted address of the branch target buffer is invalid, the second selector is also used to switch the first input and output ends inside it to conduct, and use the sequential address generated by the first adder ADD1 as the first predicted address of the current clock cycle.

[0108] When the branch target buffer does not store the jump address corresponding to the first historical reference address, the predicted address of the branch target buffer is invalid.

[0109] Please continue to refer to Figure 1 In an optional embodiment, the register group includes a first register and a second register, the first register is respectively connected to the instruction queue, the reference unit, the primary prediction unit and the second register, and the second register is respectively connected to the instruction queue and the secondary prediction unit.

[0110] The first register is used to obtain the first historical reference address and the first predicted address generated in the current clock cycle, and obtain the hit information generated by the instruction queue in the current clock cycle.

[0111] The second register is used to provide the reference address and first prediction address written by itself in the previous clock cycle to the secondary prediction unit, provide the hit information written by itself in the previous clock cycle to the instruction queue, and obtain the reference address, first prediction address and hit information written by the first register in the previous clock cycle.

[0112] exist Figure 1 On the basis of the structure of the secondary prediction unit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 A schematic diagram of the architecture of a secondary prediction unit provided by an embodiment of the present invention.

[0113] The secondary prediction unit includes a branch decoder, a second adder ADD2, a jump predictor, a fourth selector, and a discriminator.

[0114] The first input end of the branch decoder is connected to the instruction cache, the second input end of the branch decoder is connected to the instruction queue, the first output end of the branch decoder is connected to the first control end of the fourth selector and the return address stack, and the second output end of the branch decoder is connected to the first input end of the fourth selector.

[0115] An input end of the second adder ADD2 is connected to the register group (the second register), and an output end of the second adder ADD2 is connected to the second input end of the fourth selector and the return address stack.

[0116] The third input terminal of the fourth selector is connected to the return address stack.

[0117] An input terminal of the jump predictor is connected to the register group (the second register), and an output terminal of the jump predictor is connected to the second control terminal of the fourth selector.

[0118] The first input end of the discriminator is connected to the register group (the second register), the second input end of the discriminator is connected to the output end of the fourth selector, the first output end of the discriminator is connected to the reference unit (the second input end of the first selector in the reference unit, used to output the second predicted address), and the second output end of the discriminator is connected to the instruction cache (used to output a first type error signal when the prediction results are inconsistent).

[0119] Optionally, the branch decoder is used to decode according to the received instruction, and send the decoded instruction type to the fourth selector and the return address stack, and send the decoded branch target address to the fourth selector.

[0120] The second adder ADD2 is used for acquiring sequential addresses according to the reference address read from the register group, and sending the acquired sequential addresses to the fourth selector and the return address stack.

[0121] Optionally, a preset value is added to the first historical reference address to obtain a corresponding sequential address. The preset value may be, but is not limited to, 4, 8, 12, 16, etc., and is set according to the VLIW instruction length corresponding to the processor.

[0122] The jump predictor is used to generate an indication signal according to a reference address read from the register group, where the indication signal indicates whether a jump is required.

[0123] The fourth selector is used to switch its internal conduction relationship according to the received instruction type and indication signal, and use one of the obtained branch target address, sequential address and stack top address as the second predicted address of the current clock cycle, and send the obtained second predicted address to the discriminator.

[0124] The discriminator is used to determine whether the second predicted address received in the current clock cycle is the same as the first predicted address. If different, the discriminator provides the second predicted address to the reference unit and provides a first type error signal to the instruction cache.

[0125] When the second predicted address received in the current clock cycle is the same as the first predicted address, the discriminator will not output the second predicted address and the first type error signal.

[0126] Optionally, when the instruction type obtained by the branch decoder is a Call instruction, the return address stack is used to push the sequential addresses received in the current clock cycle into the stack.

[0127] When the instruction type obtained by the branch decoder is a Return instruction and there is a valid address in the return address stack, the return address stack is used to push out the top address of the stack.

[0128] When the instruction type obtained by the branch decoder is a Return instruction and there is no valid address in the return address stack, the instruction fetch module changes from the running state to the waiting state until the back-end branch execution unit parses the return address (a target address) of the Return instruction and transmits it as the result address to the reference unit, at which point the instruction fetch module returns to the running state.

[0129] When the instruction fetch module is in the wait state, the reference address generated by the reference unit is invalid.

[0130] Optionally, when the instruction type obtained by the branch decoder is a Return instruction, the fourth selector is configured to connect its third input terminal to its output terminal, and use the top address of the stack as the second predicted address for the current clock cycle. If no valid address exists in the return address stack, the system enters a wait state without performing a prediction.

[0131] When the instruction type obtained by the branch decoder is a Jal instruction, the fourth selector is used to switch the first input terminal and the output terminal thereof to be connected, and use the received branch target address as the second predicted address of the current clock cycle.

[0132] When the instruction type obtained by the branch decoder is a non-Jal instruction and a non-Return instruction, if the indication signal indicates that a jump is required, the fourth selector is used to switch the first input end and the output end inside it to be connected, and use the received branch target address as the second predicted address of the current clock cycle.

[0133] When the instruction type obtained by the branch decoder is a non-Jal instruction and a non-Return instruction, if the indication signal indicates that no jump is required, the fourth selector is used to switch the second input end and the output end inside it to be connected, and use the received sequential address as the second predicted address of the current clock cycle.

[0134] When the instruction type obtained by the branch decoder is a Jalr instruction and does not hit the branch target buffer in the primary prediction unit, the instruction fetch module changes from the running state to the waiting state.

[0135] Optionally, please continue to refer to Figure 3 The jump predictor includes a local predictor, a global predictor, and a third selector S3. The input of the local predictor and the input of the global predictor are connected to the register bank for obtaining the reference address written to the register bank in the previous K clock cycles (for example, the reference address in the second register).

[0136] The first output of the local predictor is connected to the first input of the third selector S3, the first output of the global predictor is connected to the second input of the third selector S3, and the second output of the local predictor is connected to the control terminal of the third selector S3. The output of the third selector S3 serves as the output of the jump predictor.

[0137] The local predictor generates first index information based on the reference address read from the register group (the second register), further determines a first saturation counter and a branch prediction selector corresponding to the first index information in the local predictor, and sends the values ​​of the first saturation counter and the branch prediction selector to the third selector S3.

[0138] The global predictor performs a hash operation based on the reference address read from the register group (the second register) and the execution history of the branch instruction to generate second index information, then determines a second saturation counter corresponding to the second index information in the global predictor, and sends the value of the second saturation counter to the third selector S3.

[0139] The execution history of a branch instruction includes a record of whether the branch instruction executed within a preset window jumps. For example, if the execution history is 10011010, a 1 in the execution history indicates that the corresponding branch instruction jumps, and a 0 indicates that the corresponding branch instruction does not jump. If the branch instruction does not jump, it means that during sequential instruction fetching, the execution history is shifted left and 0 is updated into the branch history register. If the branch instruction jumps to the target address, the execution history is shifted left and 1 is updated into the branch history register.

[0140] In the embodiment of the present invention, the first saturation counter and the second saturation counter are both 2-bit saturation counters, and their count values ​​can be 00, 01, 10 and 11, where 11 represents a strong jump, 10 represents a weak jump, 01 represents a weak no jump, and 00 represents a strong no jump.

[0141] The branch prediction selector in the embodiment of the present invention is also a 2-bit saturation counter, and its count value can be 00, 01, 10, and 11.

[0142] When the values ​​in the branch prediction selector are 00 and 01, it means that the third selector S3 selects the value of the local predictor as the output result; when the values ​​in the branch prediction selector are 10 and 11, it means that the third selector S3 selects the value of the global predictor as the output result.

[0143] When the indication signal output by the third selector S3 is 11 or 10, it indicates that a jump is required. When the indication signal output by the third selector S3 is 01 or 00, it indicates that a jump is not required.

[0144] Optionally, regarding how to update the above-mentioned counter, the embodiment of the present invention also provides an optional implementation method, where after the branch execution unit completes the execution of the branch instruction, it determines its first index information in the local predictor and its second index information in the global predictor based on the address of the completed branch instruction.

[0145] If the completed branch instruction jumps, the values ​​of the first saturation counter corresponding to the first index information and the second saturation counter corresponding to the second index information are incremented by 1. If the branch instruction does not jump, the values ​​of the first saturation counter corresponding to the first index information and the second saturation counter corresponding to the second index information are decremented by 1. When the value of the saturation counter is 11, if 1 is incremented, the value in the counter remains unchanged. When the value of the saturation counter is 00, if 1 is decremented, the value in the counter remains unchanged.

[0146] If the actual result address of the completed branch instruction is consistent with the prediction result of the global predictor (whether a jump occurred) but inconsistent with the prediction result of the local predictor, the value of the branch prediction selector corresponding to the first index information is incremented by 1. If the actual result address of the completed branch instruction is inconsistent with the prediction result of the global predictor (whether a jump occurred) but consistent with the prediction result of the local predictor, the value of the branch prediction selector corresponding to the first index information is decremented by 1. In other cases, the value of the branch prediction selector remains unchanged.

[0147] The initial state of the instruction fetch module provided by the embodiment of the present invention is an idle state. When the processor is reset, the instruction fetch module jumps from the idle state to the run state, at which time the reset address is used as the reference address. When the instruction fetch module receives an execute-level exit instruction, it jumps to the idle state.

[0148] The instruction fetch module provided by the embodiment of the present invention adopts a dual prediction mechanism that combines a local predictor and a global predictor, and dynamically selects a more accurate prediction result through a branch prediction selector; the local predictor uses the instruction address for indexing, which can effectively capture the behavior pattern of a single branch instruction, and the global predictor combines the instruction address and the execution history record of the branch instruction for prediction, which can identify the correlation between different branch instructions. The combined use of the two-level prediction can better adapt to different types of branch behaviors and improve the prediction accuracy compared to a single predictor.

[0149] A dedicated microinstruction cache is set up to store unissued instructions. When a cache hit occurs, the instruction can be directly obtained from the microinstruction cache, avoiding repeated access to the instruction cache and reducing memory access power consumption.

[0150] An embodiment of the present invention further provides a processor including the above-mentioned instruction fetch module.

[0151] In summary, an embodiment of the present invention provides an instruction fetch module and processor, wherein a primary prediction unit generates a first prediction address based on a first historical reference address and a stack top address, and sends it to a reference unit and a register group; an instruction queue generates corresponding hit information based on the first historical reference address, and sends it to a register group and an instruction cache; when the first historical reference address does not hit the instruction queue, the instruction cache obtains the instruction corresponding to the first historical reference address, and sends it to a secondary prediction unit and an instruction queue; when the instruction queue hits, the instruction corresponding to the hit information is sent to a secondary prediction unit; the secondary prediction unit generates a second prediction address based on the received instruction and reference address, and provides the second prediction address to the reference unit if the second prediction address is different from the first prediction address. By setting a primary prediction unit, the address prediction speed can be guaranteed, thereby improving the instruction fetch speed. At the same time, a secondary prediction unit is also provided for joint prediction, which can ensure the accuracy of the prediction result, get rid of the problem of insufficient bandwidth utilization caused by relying solely on sequential instruction fetch, and improve the processing efficiency of branch instructions.

[0152] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0153] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. An instruction fetch module, characterized in that: The instruction fetch module includes: a reference unit, a primary prediction unit, a register group, a secondary prediction unit, an instruction queue, a return address stack and an instruction cache; When the instruction fetch module is in operation, the reference unit is used to generate a reference address according to the address data acquired in the current clock cycle; The primary prediction unit is configured to generate a first predicted address based on a first historical reference address and a stack top address, and send the first predicted address to the reference unit and the register group; the first historical reference address is a reference address generated by the reference unit in a previous clock cycle, and the stack top address is an address stored at the top of a return address stack in a current clock cycle; The instruction queue is used to generate corresponding hit information according to the first historical reference address and send the hit information to the register group and the instruction cache; The register group is used to obtain the first historical reference address, provide the hit information received in the previous K clock cycles to the instruction queue, and provide the first predicted address received in the previous K clock cycles and its corresponding reference address to the secondary prediction unit; The instruction cache is used to obtain the instruction corresponding to the first historical reference address when the first historical reference address does not hit the instruction queue, and send the corresponding instruction to the secondary prediction unit and the instruction queue after K clock cycles; The instruction queue is used to send the instruction corresponding to the hit information to the secondary prediction unit when the hit information read from the register group indicates a hit; The secondary prediction unit is configured to generate a second prediction address according to the received instruction and the reference address, and provide the second prediction address to the reference unit if the second prediction address is different from the first prediction address.

2. The instruction fetch module according to claim 1, wherein: The secondary prediction unit is further configured to generate a first type error signal to the instruction cache when the second predicted address is different from the first predicted address, so as to cause the instruction cache to suspend instruction fetching.

3. The instruction fetch module according to claim 1, wherein: The primary prediction unit includes a branch target buffer, a first adder, and a second selector; An input terminal of the branch target buffer is connected to the reference unit, a first output terminal of the branch target buffer is connected to the control terminal of the second selector, and a second output terminal of the branch target buffer is connected to the first input terminal of the second selector; The input terminal of the first adder is connected to the reference unit, and the output terminal of the first adder is connected to the second input terminal of the second selector; The third input terminal of the second selector is connected to the return address stack, and the output terminal of the second selector serves as the output terminal of the preliminary prediction unit, for outputting the first predicted address.

4. The instruction fetch module according to claim 3, wherein: The branch target buffer is configured to provide a Return instruction to the control terminal of the second selector when the instruction corresponding to the first historical reference address is a Return instruction; The second selector is configured to, upon receiving a Return indication, switch the third input terminal and the output terminal thereof to conduct, and use the stack top address as the first predicted address of the current clock cycle; When the instruction corresponding to the first historical reference address is a non-Return instruction, the branch target buffer is configured to perform address prediction based on the first historical reference address, and when a valid predicted address is obtained, provide the valid predicted address to the second selector; The second selector is configured to, upon receiving a valid predicted address, switch the first input terminal and the output terminal thereof to conduct, and use the predicted address of the branch target buffer as the first predicted address of the current clock cycle; The first adder is used to obtain a sequential address according to the first historical reference address; When the instruction corresponding to the first historical reference address is a non-Return instruction and the predicted address of the branch target buffer is invalid, the second selector is also used to switch the first input and output ends inside it to conduct, and use the sequential address generated by the first adder as the first predicted address of the current clock cycle.

5. The instruction fetch module according to claim 1, wherein: The register group includes a first register and a second register, the first register is connected to the instruction queue, the reference unit, the first-order prediction unit and the second register respectively, and the second register is connected to the instruction queue and the second-order prediction unit respectively; The first register is used to obtain a first historical reference address and a first predicted address generated in a current clock cycle, and obtain hit information generated by the instruction queue in the current clock cycle; The second register is used to provide the reference address and first prediction address written by itself in the previous clock cycle to the secondary prediction unit, provide the hit information written by itself in the previous clock cycle to the instruction queue, and obtain the reference address, first prediction address and hit information written by the first register in the previous clock cycle.

6. The instruction fetch module according to claim 1, wherein: The secondary prediction unit includes a branch decoder, a second adder, a jump predictor, a fourth selector and a discriminator; The first input terminal of the branch decoder is connected to the instruction cache, the second input terminal of the branch decoder is connected to the instruction queue, the first output terminal of the branch decoder is connected to the first control terminal of the fourth selector and the return address stack, and the second output terminal of the branch decoder is connected to the first input terminal of the fourth selector; An input terminal of the second adder is connected to the register group, and an output terminal of the second adder is connected to a second input terminal of the fourth selector and the return address stack; The third input terminal of the fourth selector is connected to the return address stack; The input end of the jump predictor is connected to the register group, and the output end of the jump predictor is connected to the second control end of the fourth selector; A first input terminal of the discriminator is connected to the register group, a second input terminal of the discriminator is connected to the output terminal of the fourth selector, a first output terminal of the discriminator is connected to the reference unit, and a second output terminal of the discriminator is connected to the instruction cache.

7. The instruction fetch module according to claim 6, wherein: The branch decoder is configured to decode the received instruction, send the decoded instruction type to the fourth selector and the return address stack, and send the decoded branch target address to the fourth selector; The second adder is used to obtain a sequential address according to the reference address read from the register group, and send the obtained sequential address to the fourth selector and the return address stack; The jump predictor is used to generate an indication signal according to a reference address read from the register group, wherein the indication signal indicates whether a jump is required; The fourth selector is configured to switch its internal conduction relationship according to the received instruction type and indication signal, use one of the obtained branch target address, sequential address, and stack top address as the second predicted address of the current clock cycle, and send the obtained second predicted address to the discriminator; The discriminator is used to determine whether the second predicted address received in the current clock cycle is the same as the first predicted address, and if they are different, provide the second predicted address to the reference unit.

8. The instruction fetch module according to claim 7, wherein: When the instruction type obtained by the branch decoder is a Call instruction, the return address stack is used to push the sequential addresses received in the current clock cycle into the stack; When the instruction type obtained by the branch decoder is a Return instruction and there is a valid address in the return address stack, the return address stack is used to push out the top address of the stack; When the instruction type obtained by the branch decoder is a Return instruction and there is no valid address in the return address stack, the instruction fetch module changes from a running state to a waiting state until the back-end branch execution unit parses the return address of the Return instruction and transmits it as a result address to the reference unit, at which time the instruction fetch module resumes the running state.

9. The instruction fetch module according to claim 7, wherein: When the instruction type obtained by the branch decoder is a Return instruction, the fourth selector is used to switch the third input terminal and the output terminal thereof to be connected, and use the stack top address as the second predicted address of the current clock cycle; When the instruction type obtained by the branch decoder is a Jal instruction, the fourth selector is used to switch the first input terminal and the output terminal thereof to be connected, and use the received branch target address as the second predicted address of the current clock cycle; When the instruction type obtained by the branch decoder is a non-Jal instruction and a non-Return instruction, if the indication signal indicates that a jump is required, the fourth selector is used to switch the first input terminal and the output terminal thereof to be connected, and use the received branch target address as the second predicted address of the current clock cycle; When the instruction type obtained by the branch decoder is a non-Jal instruction and a non-Return instruction, if the indication signal indicates that no jump is required, the fourth selector is used to switch the second input end and the output end thereof to be connected, and use the received sequential address as the second predicted address of the current clock cycle.

10. A processor, characterized in that: The invention comprises the instruction fetch module according to any one of claims 1 to 9.

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