Data conversion system and method for high-speed serial bus and low-speed parallel bus

Abstract

The invention discloses a data conversion system and method for a high-speed serial bus and a low-speed parallel bus, and relates to the technical field of data conversion, and the system comprises a data serial-to-parallel conversion module which is used for determining a conversion type according to initial data, and carrying out the serial-to-parallel conversion of the initial data based on the conversion type; wherein the data serial-to-parallel conversion module comprises each block unit adopting a redundancy architecture, and each block unit at least comprises a main conversion unit used for executing serial-to-parallel conversion and a redundancy detection unit used for executing conversion result detection. The method has the advantages that high-low speed data serial-parallel conversion is accurate and efficient.

Description

Technical Field

[0001] The present application relates to the field of data conversion technology, and in particular to a data conversion system and method between a high-speed serial bus and a low-speed parallel bus. Background Art

[0002] In fields such as industrial control and rail transit, low-speed parallel ports remain widely used as a traditional interface. This is primarily due to the crucial importance of interface compatibility in these areas, as many industrial and rail transit systems already deploy a large number of devices based on specific interface standards. To maintain the operation of these systems, new hardware and software components must be compatible with these existing systems, ensuring that new devices can be easily integrated into existing architectures without requiring major redesign or replacement. Furthermore, industrial control and rail transit systems place extremely high demands on the safety, stability, and reliability of their equipment. Due to its mature technology and extensive application history, low-speed parallel ports have proven stable operation in a variety of harsh operating environments, making them a reliable choice in these fields. Furthermore, although low-speed parallel ports are slow, they typically provide multiple parallel data channels, which can be beneficial in specific application scenarios, such as connecting multiple devices.

[0003] Among the related technologies, some use a 74LVC595-like shift register to achieve serial-to-parallel port conversion; others use dedicated chips to achieve serial-to-parallel port conversion through communication interfaces such as UART, RS232, and I2C. These conversion methods are simple to implement and low-cost, but lack data verification during the transmission process, making them unsuitable for applications with high functional safety requirements, such as rail transit. To circumvent the lack of data verification during simple chip transmission, MCU data verification and conversion methods can also be used. However, the MCU introduces new data failures during the data unpacking, verification, and re-output process. Furthermore, the serial operation characteristics of the MCU make it easy for failures to be diagnosed in a timely manner, making it unsuitable for applications with high functional safety requirements.

[0004] The patent, "A High-Speed and Low-Speed Bus Communication Method and Device," published on October 28, 2015, with publication number CN105007151A, specifically discloses write and read operations on a high-speed bus. The write operation involves address decoding of high-speed parallel data; assigning a write token to a first storage unit, writing the high-speed parallel data into the first storage unit, converting the data into low-speed serial data, and writing the data to the low-speed bus; and releasing the write token. The read operation involves assigning a write token to a second storage unit; converting the corresponding low-speed serial data into high-speed parallel data, writing the data to the second storage unit and the high-speed bus; and releasing the read token. While this solution achieves high-speed and low-speed serial-to-parallel conversion, it still presents the problem of data corruption during the conversion process, resulting in low accuracy.

[0005] The patent, "A Data Receiving System, Data Receiving Method, and Chip," published with the publication number CN119415466A and date of publication on February 11, 2025, specifically discloses that the data receiving system includes: a synchronous serial-to-parallel conversion module that converts received serial data into parallel data under a serial clock, and stores the parallel data in the form of parallel data packets; and an asynchronous-to-synchronous processing module that receives the parallel data and converts it from the serial clock domain to the local clock domain. The asynchronous-to-synchronous processing module detects the number of clock cycles required for the conversion of each parallel data packet. If the number of clock cycles required for the conversion of the parallel data packet is not within a preset range, it determines that an abnormality has occurred in the conversion of the serial data to the parallel data, and performs an asynchronous reset. This solution uses the number of clock cycles to determine whether the conversion is abnormal, but the instability of the clock signal can still cause errors in the data serial-to-parallel conversion. Summary of the Invention

[0006] The present application addresses the problem in the prior art that high-speed and low-speed data serial-to-parallel conversion cannot strike a balance between accuracy and efficiency, and provides a data conversion system and method for a high-speed serial bus and a low-speed parallel bus. A redundantly set main conversion unit and a redundant detection unit are used to perform data serial-to-parallel conversion on initial data, and a final conversion result is output based on the consistency of the conversion results of the redundant detection unit and the main conversion unit. There is no need to add an additional data unpacking process, introduce additional failure problems, or add an additional matching process. It is only necessary to compare whether the conversion results finally output by the two block units are consistent to determine whether the conversion is accurate, which is more efficient and more accurate.

[0007] In order to achieve the above-mentioned technical objectives, a technical solution provided by the present application is a data conversion system for a high-speed serial bus and a low-speed parallel bus, including: a data serial-to-parallel conversion module, used to determine the conversion type according to the initial data, and perform serial-to-parallel conversion on the initial data based on the conversion type; wherein, the data serial-to-parallel conversion module includes various block units adopting a redundant architecture, and the block unit includes at least a main conversion unit for performing serial-to-parallel conversion and a redundant detection unit for performing conversion result detection.

[0008] Furthermore, it also includes: a serial data extraction module, connected to the data serial-to-parallel conversion module and the high-speed interface, for extracting valid data from the serial data on the high-speed serial bus, and outputting the valid data as initial data to the data serial-to-parallel conversion module.

[0009] Furthermore, it also includes: a parallel port protocol conversion module, connected to the data serial-to-parallel conversion module and the low-speed interface, for performing security verification on the initial data and the conversion result.

[0010] Furthermore, the main conversion unit and the redundant detection unit adopt a heterogeneous redundant architecture.

[0011] Another technical solution provided by the present application is a data conversion method between a high-speed serial bus and a low-speed parallel bus, which is applied to a data conversion system between a high-speed serial bus and a low-speed parallel bus as described above, and includes the following steps: a data serial-to-parallel conversion module obtains initial data, determines a conversion type according to the type of the initial data, performs synchronous serial-to-parallel conversion of a main conversion unit and a redundant detection unit according to the conversion type, and outputs a consistent conversion result.

[0012] Furthermore, performing serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type further includes: performing asynchronous serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type and a preset conversion interval.

[0013] Furthermore, it also includes: in response to serial data acquisition, the serial data extraction module repeatedly checks the serial data according to a preset number of transmission and reception times. If the check results are consistent, the initial data is output according to the valid data in the serial data. If the check results are inconsistent, an error alarm is executed.

[0014] Furthermore, the method further includes: in response to receiving the parallel data or the conversion result, the parallel port protocol conversion module performs identity verification and data verification according to the parallel data or the conversion result.

[0015] Furthermore, the parallel port protocol conversion module performs identity verification and data verification based on the parallel data or the conversion result, including: matching the ID coding information of the parallel data or the conversion result with the pre-stored ID coding information. If the match is successful, the identity verification is considered to have passed; when the identity verification passes, the parallel port protocol conversion module performs data integrity verification, data frame sequence verification and conversion failure verification based on the parallel data or the conversion result.

[0016] Furthermore, the performing of the serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type also includes: obtaining historical error data of the main conversion unit under historical timing, and obtaining high-risk time periods and low-risk time periods based on the historical error data using a machine learning algorithm; if the current timing belongs to a high-risk time period, performing the serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type; if the current timing belongs to a low-risk time period, performing the serial-to-parallel conversion of the main conversion unit according to the conversion type.

[0017] The beneficial effects of the present application are as follows: 1. The data serial-to-parallel conversion module redundantly sets up several block units with the same structure. The main conversion unit is used to perform serial-to-parallel conversion on the initial data, and the redundant detection unit is used to perform real-time comparison on the conversion results of the main conversion unit. When the outputs of the main conversion unit and the redundant detection unit are consistent, the entire serial-to-parallel conversion process can be output normally, avoiding the problem of data conversion errors caused by failure of the conversion unit and improving the accuracy of data conversion.

[0018] 2. When there is erroneous conversion data in either the main conversion unit or the redundant detection unit, the correct conversion data cannot be confirmed. Multiple redundant detection units verify each other. When any two block units output the same conversion result, the conversion result is output as the correct conversion result. At the same time, the block unit that outputs the erroneous conversion result is treated as a faulty unit and an alarm is issued.

[0019] 3. The serial data extraction module sends and receives the same data multiple times for verification to ensure that the initial data to be converted is accurate, thereby ensuring the accuracy of subsequent conversion results. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the overall structure of the data conversion system of the high-speed serial bus and the low-speed parallel bus of this application.

[0021] Figure 2 This is a structural diagram of a data serial-to-parallel conversion module in the data conversion system between a high-speed serial bus and a low-speed parallel bus of the present application.

[0022] Figure 3 This is a schematic diagram of the data serial-to-parallel conversion process in the data conversion system between a high-speed serial bus and a low-speed parallel bus of this application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of this application more clear, the application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific implementation method described here is only an optimal embodiment of this application, which is only used to explain this application and does not limit the scope of protection of this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0024] like Figure 1 、 Figure 2 As shown, the data conversion system between a high-speed serial bus and a low-speed parallel bus includes: A data serial-to-parallel conversion module, configured to determine a conversion type according to the initial data and perform serial-to-parallel conversion on the initial data based on the conversion type; The data serial-to-parallel conversion module includes various block units with a redundant architecture, and the block units at least include a main conversion unit for performing serial-to-parallel conversion and a redundant detection unit for performing conversion result detection.

[0025] In this embodiment, the data serial-to-parallel conversion module redundantly sets up several block units with the same structure. The main conversion unit is used to perform serial-to-parallel conversion on the initial data, and the redundant detection unit is used to compare the conversion results of the main conversion unit in real time. When the outputs of the main conversion unit and the redundant detection unit are consistent, the entire serial-to-parallel conversion process can be output normally, avoiding the problem of data conversion errors caused by failure of the conversion unit and improving the accuracy of data conversion.

[0026] In some cases, the main conversion unit and the redundant detection unit adopt a homogeneous redundant architecture, and implement data serial-to-parallel conversion processing through a consistent code structure, ensuring the impact of single-thread failure on system continuity and improving the reliability of data serial-to-parallel conversion.

[0027] In other cases, the main conversion unit includes a data parsing structure and a data reassembly structure, and the redundancy detection unit includes a data parsing structure and a data reassembly structure, wherein the main conversion unit and the redundancy detection unit adopt a heterogeneous redundancy architecture.

[0028] The main conversion unit and redundant detection unit adopt a heterogeneous redundant architecture. While maintaining functional equivalence, the risk of common-mode design defects is eliminated through an asymmetric coding structure, thereby reducing the possibility of common-cause failures due to code bugs and improving the accuracy of data serial-to-parallel conversion.

[0029] like Figure 3 As shown in the figure, the data serial-to-parallel conversion module extracts the valid data of the initial data, such as read-write flags, configuration information, address information, and data information, and divides them into two parts: read operation and write operation through data reorganization. During the data reorganization process, the parsed configuration information is reallocated to the address or data, so that the overall structure is aligned with the standard parallel port, completing the serial-to-parallel conversion.

[0030] In this embodiment, the data serial-to-parallel conversion module includes a main conversion unit and a redundant detection unit. In other embodiments, the data serial-to-parallel conversion module may also include a main conversion unit and multiple redundant detection units. When either the main conversion unit or the redundant detection unit has erroneous conversion data, the correct conversion data cannot be confirmed. The multiple redundant detection units verify each other. When any two block units output the same conversion result, the conversion result is output as the correct conversion result, and the block unit that outputs the erroneous conversion result is identified as a faulty unit and an alarm is issued.

[0031] The data conversion system between the high-speed serial bus and the low-speed parallel bus further includes: The serial data extraction module is connected to the data serial-to-parallel conversion module and the high-speed interface, and is used to extract valid data from the serial data on the high-speed serial bus and output the valid data as initial data to the data serial-to-parallel conversion module.

[0032] The serial data extraction module extracts serial data on a high-speed serial bus (such as PCIE, SATA, SGMII, etc.) and puts the valid data in the serial data into the cache for extraction by the data serial-to-parallel conversion module.

[0033] In this embodiment, the serial data includes protocol data, valid data, and check data. Among them, the protocol data is an essential part of the communication protocol, and the valid data is put into the cache as the initial data for the data serial-to-parallel conversion module to perform serial-to-parallel conversion. The check data is used to verify the validity of the protocol data and the valid data. The serial data extraction module uses a SerDes hard core. When parsing the data, the SerDes hard core only uses methods such as CRC to verify the integrity of the data, and does not re-unpack or unpack the data content. At this time, the serial data extraction module repeatedly checks the serial data based on the preset number of transmissions and receptions. When the check passes, the serial data is sent as the initial data to the data serial-to-parallel conversion module to ensure the validity of the data and avoid additional failures introduced by processes such as data unpacking.

[0034] The data conversion system of the high-speed serial bus and the low-speed parallel bus also includes: The parallel port protocol conversion module is connected to the data serial-to-parallel conversion module and the low-speed interface, and is used to perform security verification on the initial data and the conversion result.

[0035] When receiving parallel data from the low-speed parallel bus, the parallel port protocol conversion module performs a security check on the parallel data. If the security check passes, the valid data in the parallel data is output as the initial data to the data serial-to-parallel conversion module for serial-to-parallel conversion. When receiving the conversion result output from the data serial-to-parallel conversion module, the conversion result is also subjected to a security check. If the security check passes, the conversion result is output to the low-speed interface, thus ensuring the security and reliability of data transmission.

[0036] As a second embodiment of the present application, a method for converting data between a high-speed serial bus and a low-speed parallel bus is applied to a data conversion system between a high-speed serial bus and a low-speed parallel bus, comprising the following steps: The data serial-to-parallel conversion module obtains initial data, determines the conversion type according to the type of the initial data, performs serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type, and outputs a consistency conversion result.

[0037] In this embodiment, the data serial-to-parallel conversion module obtains initial data. If the initial data is serial data, it determines the conversion type to be serial to parallel data. If the initial data is parallel data, it determines the conversion type to be parallel to serial data. This process then calls the corresponding conversion routines of the main conversion unit and the redundant detection unit. After the main conversion unit and the redundant detection unit output conversion results, if the conversion result of the main conversion unit is consistent with the conversion result of the redundant detection unit, the conversion result is considered accurate and output. If the conversion result is inaccurate, a fail-safe mode is output. This prevents single-bit errors or sticking failures. The entire process utilizes a hardware redundancy mechanism. Specifically, during the data serial-to-parallel conversion process, two functionally identical blocks are used: the main conversion unit for data processing and the redundant detection unit for functional testing. The conversion results are compared in real time during the conversion process. Only when the data in the buffers of the main conversion unit and the redundant detection unit are consistent will the entire serial-to-parallel conversion process be successfully output. Otherwise, a fail-safe mode is output to ensure the accuracy of the data conversion. In some cases, the main conversion unit and the redundant detection unit perform serial-to-parallel conversion synchronously to ensure that the conversion results are output synchronously for comparison.

[0038] In some other cases, performing serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type further includes performing asynchronous serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type and a preset conversion interval.

[0039] In this case, a preset conversion interval allows the serial-to-parallel conversion of the main conversion unit and the redundant detection unit to start at different times, thereby avoiding common cause failures caused by external interference and ensuring the accuracy of the detection results of the redundant detection unit. The preset conversion interval can be set based on the delay time interval for transmission and reception in actual applications.

[0040] In still other cases, performing the serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type further includes: obtaining historical error data of the main conversion unit in a historical time sequence, and obtaining a high-risk period and a low-risk period based on the historical error data using a machine learning algorithm; If the current timing belongs to a high-risk period, the serial-to-parallel conversion of the main conversion unit and the redundant detection unit is performed according to the conversion type; if the current timing belongs to a low-risk period, the serial-to-parallel conversion of the main conversion unit is performed according to the conversion type.

[0041] By analyzing the historical error timing of the main conversion unit through machine learning algorithms, the redundant detection unit is dynamically enabled during high-risk periods, while the redundant unit is not enabled during low-risk periods (data stability period), reducing power consumption while maintaining high reliability of data serial-to-parallel conversion.

[0042] The data conversion method between a high-speed serial bus and a low-speed parallel bus further includes: In response to serial data acquisition, the serial data extraction module repeatedly verifies the serial data according to a preset number of transmission and reception times. If the verification results are consistent, the module outputs initial data according to the valid data in the serial data. If the verification results are inconsistent, the module issues an error alarm.

[0043] In this embodiment, the initial data includes at least a frame header and valid data. The serial data extraction module sends and receives the same data multiple times for verification to ensure that the initial data to be converted is accurate, thereby ensuring that the subsequent conversion results are accurate.

[0044] The data conversion method between a high-speed serial bus and a low-speed parallel bus further includes: In response to receiving the parallel data or the conversion result, the parallel port protocol conversion module performs identity verification and data verification according to the parallel data or the conversion result.

[0045] When the parallel port protocol conversion module receives parallel data or conversion results, it performs identity verification and data verification on the received data. Only when the verification passes, the parallel port protocol conversion module forwards the data, thereby improving the security and reliability of data transmission.

[0046] Specifically, the parallel port protocol conversion module performs identity verification and data verification based on the parallel data or the conversion result, including: The ID code information of the parallel data or the conversion result is matched with the pre-stored ID code information. If the match is successful, the identity verification is considered to be passed; When the identity verification is passed, the parallel port protocol conversion module performs data integrity verification, data frame sequence verification, and conversion failure verification based on the parallel data or the conversion result.

[0047] The parallel data and the conversion result include at least control information, address information and data information.

[0048] The control information consists of three parts: chip select signal, read / write signal and status signal. The chip select signal is designed to be active low and is used to select the communication module. The read / write signal is defined as a level-triggered flag to clarify the direction of data transmission. The status signal is the result of the identity verification and is active low. This signal serves as the communication enable gating condition. Only when the identity verification passes, the status signal is valid and the data channels of the two communicating parties can be activated. Otherwise, all data signal lines are forced into a high-impedance state to ensure bus security isolation in illegal access scenarios.

[0049] Address information includes ID code information, packet sequence number, operation address, and checksum data. The ID code information is used to select the authorized device. Only when the ID code information is consistent, the status signal is valid and normal communication between the two parties can be carried out. The packet sequence number is a flag for detection and error correction, mainly used to determine whether the packet is lost or wrong, and respond to the correction mechanism when an error is detected. The checksum data ensures that the address information has not been tampered with during transmission.

[0050] The data information includes the ID code information, packet sequence number, operation address, data positive code, data negative code, and check data. Among them, the communication ID, packet sequence number, and operation address are copies of the address information and are used for verification. The data positive and negative codes enable the communication data to be self-verified. The check data is used to ensure that the data information has not been tampered with during transmission.

[0051] To ensure that data can only be received and sent by authorized devices, ID code information is added to the address signal of the parallel data or conversion result. The parallel port protocol conversion module pre-stores the data serial-to-parallel conversion module ID code information and the low-speed interface ID code information. Identity verification is considered successful when the parallel data ID code information matches the low-speed interface ID code information. Similarly, identity verification is considered successful when the conversion result ID code information matches the pre-stored data serial-to-parallel conversion module ID code information. This ensures the security and reliability of information transmission.

[0052] Data integrity checks include at least cyclic redundancy checks (CRCs) and forward and reverse code checks. To ensure that transmitted data has not been tampered with during transmission, verification measures such as CRCs (cyclic redundancy checks) are implemented in both address and data signals. For communication data, forward and reverse code checks are used to further enhance data verification performance. When packet loss or error is detected, automatic repeat request (ARQ) or forward error correction (FEC) is used to detect data transmission errors.

[0053] Data frame sequence verification includes: Based on the error detection mechanism, a packet sequence number is added to each set of parallel data or conversion results. During each transmission process, the packet sequence number is automatically incremented, and the data frame sequence check is performed based on the continuity and monotony of the packet sequence number.

[0054] An error detection mechanism adds a packet sequence number to each set of communication data. The packet sequence number automatically increments by one with each communication operation to prevent packet loss caused by data delays, data collisions, and other factors, which could lead to security issues. If the packet sequence number is inconsistent or monotonically increasing, the packet is considered lost or erroneous, triggering Automatic Repeat Request (ARQ) or Forward Error Correction (FEC) to prevent data transmission errors.

[0055] Conversion failure detection involves determining whether a conversion failure exists based on whether the conversion result conforms to the parallel data format. During data conversion, if an output error occurs due to temporary or permanent FPGA failure, the failure is determined by whether the conversion result conforms to the parallel data format. Continuous conversion failure detection results over a long timeframe can also be used to determine whether the failure is temporary.

[0056] The specific implementation described above is a preferred implementation of the data conversion system and method for the high-speed serial bus and the low-speed parallel bus of the present application, and is not intended to limit the specific implementation scope of the present application. The scope of the present application includes but is not limited to the specific implementation. Any equivalent changes made in accordance with the shape and structure of the present application are within the scope of protection of the present application.

Claims

1. A data conversion system for a high-speed serial bus and a low-speed parallel bus, characterized by: include: A data serial-to-parallel conversion module, configured to determine a conversion type according to the initial data and perform serial-to-parallel conversion on the initial data based on the conversion type; The data serial-to-parallel conversion module includes various block units with a redundant architecture, and the block units at least include a main conversion unit for performing serial-to-parallel conversion and a redundant detection unit for performing conversion result detection.

2. The data conversion system for a high-speed serial bus and a low-speed parallel bus according to claim 1, wherein: Also includes: The serial data extraction module is connected to the data serial-to-parallel conversion module and the high-speed interface, and is used to extract valid data from the serial data on the high-speed serial bus and output the valid data as initial data to the data serial-to-parallel conversion module.

3. The data conversion system for a high-speed serial bus and a low-speed parallel bus according to claim 1, wherein: Also includes: The parallel port protocol conversion module is connected to the data serial-to-parallel conversion module and the low-speed interface, and is used to perform security verification on the initial data and the conversion result.

4. The data conversion system for a high-speed serial bus and a low-speed parallel bus according to claim 1, wherein: The main conversion unit and the redundant detection unit adopt a heterogeneous redundant architecture.

5. A method for converting data between a high-speed serial bus and a low-speed parallel bus, the method being applied to a system for converting data between a high-speed serial bus and a low-speed parallel bus according to any one of claims 1 to 4, wherein: The steps include: The data serial-to-parallel conversion module obtains initial data, determines the conversion type according to the type of the initial data, performs synchronous serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type, and outputs a consistent conversion result.

6. The method for converting data between a high-speed serial bus and a low-speed parallel bus according to claim 5, wherein: The performing serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type further includes: Asynchronous serial-to-parallel conversion of the main conversion unit and the redundant detection unit is performed according to a conversion type and a preset conversion interval.

7. The method for converting data between a high-speed serial bus and a low-speed parallel bus according to claim 5, wherein: Also includes: In response to serial data acquisition, the serial data extraction module repeatedly verifies the serial data according to a preset number of transmission and reception times. If the verification results are consistent, the module outputs initial data according to the valid data in the serial data. If the verification results are inconsistent, the module issues an error alarm.

8. The method for converting data between a high-speed serial bus and a low-speed parallel bus according to claim 5, wherein: Also includes: In response to receiving the parallel data or the conversion result, the parallel port protocol conversion module performs identity verification and data verification according to the parallel data or the conversion result.

9. The method for converting data between a high-speed serial bus and a low-speed parallel bus according to claim 8, wherein: The parallel port protocol conversion module performs identity verification and data verification according to the parallel data or the conversion result, including: The ID code information of the parallel data or the conversion result is matched with the pre-stored ID code information. If the match is successful, the identity verification is considered to be passed; When the identity verification is passed, the parallel port protocol conversion module performs data integrity verification, data frame sequence verification, and conversion failure verification based on the parallel data or the conversion result.

10. The method for data conversion between a high-speed serial bus and a low-speed parallel bus according to claim 5, wherein: The performing serial-to-parallel conversion of the main conversion unit and the redundant detection unit according to the conversion type further includes: Obtain historical error data of the main conversion unit in historical time series, and use machine learning algorithms to obtain high-risk and low-risk periods based on the historical error data; If the current timing belongs to a high-risk period, the serial-to-parallel conversion of the main conversion unit and the redundant detection unit is performed according to the conversion type; if the current timing belongs to a low-risk period, the serial-to-parallel conversion of the main conversion unit is performed according to the conversion type.

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