Test method of network processor, electronic equipment and medium
Through the testing method combined with software and hardware, test data packets are generated and processed, which solves the problem of limited coverage of network processor performance evaluation and achieves more comprehensive testing and verification.
Patent Information
- Application Number
- CN202510547970.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-08
AI Technical Summary
When evaluating the performance of network processors, the coverage range is limited and lacks dynamicity, making it difficult to fully reflect the complex situation in the real network environment.
Using a combination of software and hardware, multiple test items are generated through the test data generation module, test data packets are generated, and processed in the software simulation module and the hardware test module. The result comparison module is used to compare the results to determine the test results of the network processor.
It realizes the expansion of network processor verification coverage under dynamic monitoring conditions, and can conduct testing and verification more comprehensively and efficiently.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of network processor testing, and in particular to a network processor testing method, electronic equipment, and medium. Background Art
[0002] The Network Processor (NP) is designed to provide sufficient flexibility and performance to support a variety of network protocols and Quality of Service (QoS) requirements, while also allowing users to customize its behavior through programming to suit specific application scenarios.
[0003] When evaluating the performance of network processors, existing technologies only rely on building a simulation platform to perform functional verification on NPs, resulting in limited coverage of functional verification. Summary of the Invention
[0004] The purpose of the embodiments of the present application is to provide a network processor testing method, electronic device and medium to solve the above-mentioned problems existing in the prior art and to expand the coverage of NP verification under dynamic monitoring conditions.
[0005] In a first aspect, a network processor testing method is provided, which is applied to a testing system including a test data generation module, a software simulation module, a hardware testing module, and a result comparison module. The method may include:
[0006] The test data generation module determines multiple test items based on the application scenario of the network processor;
[0007] Generate a test data message according to the configured test message structure and multiple test items, and send the test data message to the software simulation module and the hardware test module respectively; the test data includes multiple test cases;
[0008] Obtaining a first processing result of each test case in the test data message processed by the software simulation module and a second processing result of each test case in the test data message processed by the hardware testing module, and sending the first processing result and the second processing result to the result comparison module;
[0009] The result comparison module determines a test result of the network processor based on the first processing result and the second processing result.
[0010] In a possible implementation, the test message structure includes: a flow identification field, a packet sequence number field, a timestamp field, and a plurality of test case fields connected in sequence.
[0011] In a possible implementation, the test items include: test case type, test case length, and test case content.
[0012] In a possible implementation, before sending the test data packet message to the software simulation module and the hardware test module respectively, the method further includes:
[0013] Based on the configured test item constraints, multiple test items are combined to obtain a test case sequence composed of multiple test cases.
[0014] In a possible implementation, the software simulation module and the hardware test module process the test cases in sequence according to the order of the test cases in the test case sequence.
[0015] In a possible implementation, the first processing result includes: an expected data result and / or an expected data transmission rate; the second processing result includes: an actual data result and / or an actual data transmission rate.
[0016] In one possible implementation, determining a test result of the network processor based on the first processing result and the second processing result includes:
[0017] If the actual data result is consistent with the expected data result and the actual data transmission rate meets the configured rate threshold, the test result of the network processor is functionally qualified; wherein the rate threshold is determined based on the expected data transmission rate.
[0018] In a possible implementation, the length of the test case type is 1 byte; the length of the test case and the length of the test case content are respectively integer multiples of 2 bytes.
[0019] In a second aspect, an electronic device is provided, the electronic device including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;
[0020] Memory for storing computer programs;
[0021] The processor is configured to implement any of the method steps described in the first aspect when executing a program stored in the memory.
[0022] In a third aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any method step described in the first aspect is implemented.
[0023] The present application provides a method for testing a network processor, the method comprising: a test data generation module determining a plurality of test items based on an application scenario of the network processor; generating a test data message according to a configured test message structure and a plurality of test items, and sending the test data message to a software simulation module and a hardware test module respectively; obtaining a first processing result of each test case in the test data message processed by the software simulation module and a second processing result of each test case in the test data message processed by the hardware test module, and sending the first processing result and the second processing result to the result comparison module; and determining the test result of the network processor based on the first processing result and the second processing result. The present application randomly combines different test items and test cases according to different business needs or business scenarios, so as to perform more targeted testing and verification on the NP to be tested. An automated testing system for the NP is built by combining software and hardware, that is, the software automatically and randomly generates test data messages for various complex business scenarios and injects them into the software simulation module and the hardware test module, and automatically compares and determines the test results and reports the information, so as to test and verify the NP to be tested more comprehensively and efficiently. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0025] Figure 1 An architectural diagram of a network processor test system provided in an embodiment of the present application;
[0026] Figure 2 A flowchart of a method for testing a network processor provided in an embodiment of the present application;
[0027] Figure 3 An architectural diagram of the hardware testing module provided in an embodiment of the present application;
[0028] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0030] The network processor test provided by the embodiment of the present application can be applied to Figure 1 In the system architecture shown in Figure 1 As shown, the system may include: a test data generation module, a software simulation module, a hardware test module and a result comparison module; wherein the hardware test module and the software simulation module are both configured with an NP to be tested.
[0031] A network processor (NP) is a high-performance, programmable chip designed specifically for efficient network traffic processing. It integrates multiple microengines and hardware coprocessors, enabling parallel processing of network packets to meet the complex demands of modern high-speed networks. NPs are designed to provide sufficient flexibility and performance to support a wide range of network protocols and Quality of Service (QoS) requirements, while also allowing users to customize their behavior through programming to suit specific application scenarios.
[0032] Traditional testing methods and their limitations:
[0033] When evaluating the performance of network processors, traditional testing methods rely primarily on functional verification using pre-stored data packets. This approach typically involves the following steps:
[0034] Preparation phase: Collect or generate a set of representative network packets and store them in a database.
[0035] Execution phase: Input these predefined data packets into the network processor under test and observe and record the processor's behavior.
[0036] Analysis phase: Based on the network processor's response to these fixed data packets, its performance indicators such as throughput, latency, packet loss rate, etc. are evaluated.
[0037] Although this approach is simple and easy to implement, it has several significant limitations:
[0038] Limited coverage: Since only predefined data packets can be tested, this testing method often cannot fully reflect the various situations that the network processor may encounter in actual complex network environments.
[0039] Lack of dynamism: Real network environments are full of changes and uncertainties, including bursty traffic, various types of network attacks, and fluctuating service demands. Traditional testing methods struggle to simulate these dynamic conditions. Insufficient real-world simulation: To accurately evaluate the actual performance of a network processor, it is necessary to be able to test it under conditions close to the real world. This includes not only the content and type of data packets, but also factors such as network topology and load patterns.
[0040] Therefore, the present application provides a network processor testing method to solve the above-mentioned problems existing in the prior art and to expand the coverage of NP verification under the condition of dynamic monitoring.
[0041] The preferred embodiments of the present application are described below in conjunction with the drawings in the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application and are not used to limit the present application. In addition, the embodiments and features in the embodiments of the present application can be combined with each other if there is no conflict.
[0042] Figure 2 A flow chart of a method for testing a network processor provided in an embodiment of the present application. Figure 2 As shown, the method may include:
[0043] Step S210: The test data generation module determines a plurality of test items based on the application scenario of the network processor.
[0044] Specifically, to comprehensively evaluate the performance of a network processor, a series of specific test objectives or standards need to be set based on its application scenario (network or storage). Each test item targets a specific aspect of the network processor, such as performance, functional correctness, reliability, security, etc.
[0045] Here are some examples of possible tests:
[0046] Performance testing: This includes testing of metrics such as throughput, latency, and packet loss rate. It evaluates the performance of the network processor under high load by sending a large number of data packets.
[0047] Compatibility testing: Ensures that the network processor works well with different network protocols, operating systems, and other hardware and software components.
[0048] Stability testing: Runs the network processor for extended periods of time and simulates various workloads to check for memory leaks, crashes, and other issues.
[0049] Security testing: Using known security attack patterns as incentives, the network processor's ability to protect against security threats such as DDoS attacks and malware is tested.
[0050] Functional testing: Verify whether the network processor can correctly perform the expected functions, such as routing, packet filtering, etc.
[0051] Fault recovery test: simulates hardware or software failures to check the failover capability and recovery speed of the network processor and its application system.
[0052] Resource utilization efficiency test: Evaluates the efficiency of the network processor in using CPU, memory and other resources when processing tasks.
[0053] Step S220: Generate a test data message according to the configured test message structure and multiple test items, and send the test data message to the software simulation module and the hardware test module respectively.
[0054] The test data includes multiple test cases.
[0055] The test message structure includes the following: flow identification field, packet sequence number field, timestamp field and multiple test case fields connected in sequence. The details are shown in Table 1:
[0056] Table 1
[0057] Flow ID Package number Timestamp Test Case 1 Test Case 2 Test Case 3 ……
[0058] The flow identifier is a number used to distinguish different service flows (it can also be understood as a code for the current application scenario). The packet sequence number uniquely numbers each test data point to identify packet loss and out-of-order conditions. The timestamp adds time information to each test data point to calculate the delay information of each data packet.
[0059] The test case is divided into test case type, test case length, and test case content. The test case type occupies 1 byte. The test case length unit is bytes, and the test case length of each test case is an integer multiple of 2 bytes. The test case content contains several bits of data and needs to be aligned with 2 bytes and is an integer multiple of 2 bytes. Multiple test cases are combined into a test item sequence, as shown in Table 2:
[0060] Table 2
[0061]
[0062] Furthermore, each test case is designed based on one or more specific test items. These test items evaluate different aspects of the network processor, such as performance, security, and stability. To ensure the effectiveness and comprehensiveness of the test, it is necessary to consider the interrelationships and dependencies between the test items, whether they can be reasonably combined, and whether the logic of the entire test process is reasonable.
[0063] Test item constraints can include:
[0064] Interdependencies: Some test items may need to be executed only after certain conditions or other test items have been completed. For example, basic functional correctness may need to be verified before more complex performance or security testing can be performed.
[0065] Internal processing composability: Test items should be able to be combined in a meaningful way to effectively cover all necessary test scenarios. Performance testing can be combined with compatibility testing to test the system's performance in different environments by simulating different workloads.
[0066] Semantic rationality of overall logic: The combination of all test items should follow a certain logical order and rules, making the entire testing process comprehensive and non-redundant. For example, before performing fault recovery testing, it is best to complete stability testing to ensure that the system can recover as expected in the event of a fault.
[0067] Based on the above constraints, different test items are combined to form a series of test cases. In other words, this method generates various combinations of test data packets based on different test items. The content corresponding to the test data packets is the action performed by the microcode. Different combinations of test items can be randomly generated for testing based on the defined rules and random ranges. Each test case is a set of specific operation steps and expected results designed to check the behavior of the network processor under specific circumstances. Ultimately, these test cases are combined to form an orderly test plan for comprehensively evaluating the performance and reliability of the network processor. The purpose of this is to ensure that each part is fully tested and there are no omissions or duplications between the various test links.
[0068] In one example, the test case is shown in Table 3:
[0069]
[0070]
[0071]
[0072] Step S230: Obtain the first processing result of each test case in the test data message processed by the software simulation module and the second processing result of each test case in the test data message processed by the hardware test module, and send the first processing result and the second processing result to the result comparison module.
[0073] Specifically, the software simulation module and the hardware test module are processed in sequence according to the order of each test case in the test case sequence.
[0074] The software simulation module and the hardware test module are also configured with correspondences between different positions and different data identifiers in the test message structure, so that the software simulation module and the hardware test module can determine test cases based on positions.
[0075] In A, for any test case, the software simulation module simulates hardware behavior to generate expected data results, that is, obtains a first processing result. This first processing result can be: expected data results and / or expected data transmission rate. Specifically, the software simulation module is configured with a traffic model, which simulates hardware behavior and generates traffic statistics using the traffic model.
[0076] B. For any test case, the NP under test configured in the hardware test module processes the corresponding test case to obtain an actual data result, i.e., a second processing result. The second processing result includes: an actual data result and / or an actual data transmission rate. Specifically, the hardware test module generates actual traffic statistics by performing traffic statistics.
[0077] It can be understood that the expected data transmission rate and the actual data transmission rate are determined based on the timestamp in the test message.
[0078] Combine Figure 3 As shown in the figure, PPE Clusters (Processing Element Clusters) are processing element clusters responsible for performing packet processing tasks. Each cluster contains multiple processing elements (PEs) for parallel processing of network packets. Queue: Each PPE Cluster has a queue for buffering packets awaiting processing. DDR Memory: Double Data Rate (DDR) memory, used to store large amounts of data and program code. It is typically used for high-speed data transmission. QoS Cache: Quality of Service Cache, used to store data related to quality of service, ensuring that packets for critical applications receive priority processing. Packet Buffer: Packet buffer, used to temporarily store packets to ensure that packets are not lost during processing. Ingress Controller: Responsible for receiving incoming packets and assigning them to appropriate processing paths. Egress Controller: Responsible for sending processed packets into the network. Traffic Manager: Responsible for managing and scheduling packet flows, ensuring that packets are processed and forwarded according to predetermined policies. MAC ST: Stimulus Generator. MAC CMP: Result Comparator. NOC (Network on Chip): Network on chip, used for internal communication, ensuring efficient data transmission between various components. BUS: Bus system, used to connect various components, ensuring efficient data transmission between different modules.
[0079] This architecture processes packets in parallel through multiple PPE clusters, utilizing queues and caches to optimize packet processing. The ingress and egress controllers are responsible for receiving and sending packets, respectively, while the traffic manager ensures efficient packet scheduling. DDR memory provides high-speed data storage, while the network-on-chip (NOC) ensures efficient internal communications.
[0080] The hardware test module processes the test cases as follows:
[0081] 1. The stimulus generator replaces the MAC or NOC, inputs the test case to the Ingress Controller, stores the test case in the packet buffer, and sends the test task descriptor to a PPE (Packet Processing Engine) Cluster.
[0082] 2. The queues in the PPE Cluster receive test tasks and distribute them within the Cluster. The PPEs within the Cluster process the tasks. During processing, the PPEs read and write data in the shared packet buffer and perform a series of table operations through the DOE. Once processing is complete, the tasks are distributed to other Clusters via the bus.
[0083] 3. After the last level Cluster completes processing, it sends the packet descriptor to Traffic Manager. Traffic Manager schedules the test task and sends the data to the NP output port through the Egress Controller.
[0084] 4. The NP output port outputs the second processing result.
[0085] Step S240: The result comparison module determines the test result of the network processor based on the first processing result and the second processing result.
[0086] Among them, the result comparison module includes: a test result comparator and a traffic statistics comparator.
[0087] Specifically, if the actual data result is consistent with the expected data result, and the actual data transmission rate meets the configured rate threshold, the test result of the network processor is qualified;
[0088] The rate threshold is determined based on the expected data transmission rate. A certain ratio can be set to determine the rate threshold based on the expected data transmission rate.
[0089] If the actual data result is inconsistent with the expected data result, a prompt message indicating that the test result of the network processor is unqualified is generated and sent to the corresponding staff.
[0090] If the actual data results are consistent with the expected data results, but the actual data transmission rate does not meet the configured rate threshold, the test case is retested. If the actual data results are consistent with the expected data results, but the actual data transmission rate still does not meet the configured rate threshold, the threshold-based decision logic (increasing the packet buffer size when the test queue exceeds a certain threshold) or using a machine learning model to predict future traffic demand is used to expand the packet buffer. The corresponding test case is then retested to determine the test results. Similarly, when the test queue falls below a certain threshold, the packet buffer is reduced.
[0091] Based on the test results determined by the test result comparer and the traffic statistics comparer, a test log is generated and output.
[0092] In one embodiment, if the actual data transmission rate still does not meet the configured rate threshold during retesting of the corresponding test case after expanding the buffer, a congestion control algorithm can be configured in the TCP protocol of the NP to prevent packet loss and severe transmission delays caused by network overload. The congestion control algorithm can be: if three consecutive duplicate ACKs are received, it is considered that minor congestion has occurred, the lost packets are immediately retransmitted, and the fast recovery phase is entered to quickly restore normal data flow. Once fast retransmission is triggered, the fast recovery phase may include the following steps: Adjusting the congestion window (cwnd): During fast recovery, the sender no longer increases cwnd, but it also does not halve it as in traditional TCP. Instead, cwnd generally remains at a high level, allowing the sender to continue sending data segments. Retransmitting lost data segments: The sender directly retransmits lost data segments based on received duplicate ACKs. Monitoring new ACKs: If the sender begins to receive new ACKs (i.e., non-duplicate ACKs), this indicates that the lost data segments have been successfully accepted by the receiver and network conditions have improved. At this point, the sender exits the fast recovery phase and gradually restores cwnd to its normal value. This approach prevents the loss of a single data segment from causing a sharp drop in overall connection performance. By maintaining a relatively large cwnd value, data flow can be ensured even in the face of small amounts of packet loss. Fast retransmit and fast recovery mechanisms work together to enable TCP to respond more flexibly to network congestion or data loss, reducing downtime caused by data loss and helping to improve overall network reliability and efficiency. These mechanisms are crucial for maintaining stable communications on the internet.
[0093] The present application provides a method for testing a network processor, the method comprising: a test data generation module determining a plurality of test items based on an application scenario of the network processor; generating a test data message according to a configured test message structure and a plurality of test items, and sending the test data message to a software simulation module and a hardware test module respectively; obtaining a first processing result of each test case in the test data message processed by the software simulation module and a second processing result of each test case in the test data message processed by the hardware test module, and sending the first processing result and the second processing result to the result comparison module; and determining the test result of the network processor based on the first processing result and the second processing result. The present application randomly combines different test items and test cases according to different business needs or business scenarios, so as to perform more targeted testing and verification on the NP to be tested. An automated testing system for the NP is built by combining software and hardware, that is, the software automatically and randomly generates test data messages for various complex business scenarios and injects them into the software simulation module and the hardware test module, and automatically compares and determines the test results and reports the information, so as to test and verify the NP to be tested more comprehensively and efficiently.
[0094] The present application also provides an electronic device, such as Figure 4 As shown, it includes a processor 410 , a communication interface 420 , a memory 430 and a communication bus 440 , wherein the processor 410 , the communication interface 420 , and the memory 430 communicate with each other via the communication bus 440 .
[0095] Memory 430, for storing computer programs;
[0096] The processor 410 is configured to execute the program stored in the memory 430 by performing the following steps:
[0097] The test data generation module determines multiple test items based on the application scenario of the network processor;
[0098] Generate a test data message according to the configured test message structure and multiple test items, and send the test data message to the software simulation module and the hardware test module respectively; the test data includes multiple test cases;
[0099] Obtaining a first processing result of each test case in the test data message processed by the software simulation module and a second processing result of each test case in the test data message processed by the hardware testing module, and sending the first processing result and the second processing result to the result comparison module;
[0100] The result comparison module determines a test result of the network processor based on the first processing result and the second processing result.
[0101] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.
[0102] The communication interface is used for communication between the above electronic device and other devices.
[0103] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.
[0104] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.
[0105] The implementation methods and beneficial effects of the various components of the electronic device in the above embodiments to solve the problems can be found in Figure 2 The various steps in the embodiment shown are implemented, therefore, the specific working process and beneficial effects of the electronic device provided by the embodiment of the present application are not repeated here.
[0106] In another embodiment provided by the present application, a computer-readable storage medium is provided, which stores instructions. When the computer-readable storage medium is executed on a computer, the computer executes a network processor testing method described in any of the above embodiments.
[0107] In another embodiment provided by the present application, a computer program product including instructions is further provided. When the computer program product is run on a computer, the computer executes a network processor testing method described in any one of the above embodiments.
[0108] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the embodiments of the present application can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the embodiments of the present application can be implemented in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0109] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0110] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0112] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0113] Although preferred embodiments have been described in the present application, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the present application is intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.
[0114] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the embodiments of the present application and their equivalents, the embodiments of the present application are also intended to include these modifications and variations.
Claims
1. A method for testing a network processor, characterized in that: Applied to a test system including a test data generation module, a software simulation module, a hardware test module, and a result comparison module, the method includes: The test data generation module determines multiple test items based on the application scenario of the network processor; Generate a test data message according to the configured test message structure and multiple test items, and send the test data message to the software simulation module and the hardware test module respectively; the test data includes multiple test cases; Obtaining a first processing result of each test case in the test data message processed by the software simulation module and a second processing result of each test case in the test data message processed by the hardware testing module, and sending the first processing result and the second processing result to the result comparison module; The result comparison module determines a test result of the network processor based on the first processing result and the second processing result.
2. The method according to claim 1, wherein The test message structure includes: a flow identification field, a packet sequence number field, a timestamp field and a plurality of test case fields connected in sequence.
3. The method according to claim 2, wherein The test items include: test case type, test case length and test case content.
4. The method according to claim 3, wherein Before sending the test data packet message to the software simulation module and the hardware test module respectively, the method further includes: Based on the configured test item constraints, multiple test items are combined to obtain a test case sequence composed of multiple test cases.
5. The method according to claim 4, wherein The software simulation module and the hardware test module process the test cases in sequence according to the order of the test cases in the test case sequence.
6. The method according to claim 1, wherein The first processing result includes: an expected data result and / or an expected data transmission rate; the second processing result includes: an actual data result and / or an actual data transmission rate.
7. The method according to claim 6, wherein Determining a test result of the network processor based on the first processing result and the second processing result includes: If the actual data result is consistent with the expected data result and the actual data transmission rate meets the configured rate threshold, the test result of the network processor is functionally qualified; wherein the rate threshold is determined based on the expected data transmission rate.
8. The method according to claim 3, wherein The length of the test case type is 1 byte; the length of the test case and the length of the test case content are respectively integer multiples of 2 bytes.
9. An electronic device, characterized in that: The electronic device includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; A processor, configured to implement the method steps described in any one of claims 1 to 8 when executing a program stored in a memory.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of claims 1 to 8 are implemented.