SATA communication detection method and equipment and SATA hardware simulator

Abstract

The invention provides an SATA (Serial Advanced Technology Attachment) communication detection method and equipment and an SATA hardware simulator, and relates to the technical field of computers and communication. According to the implementation scheme, the method is applied to SATA communication detection equipment integrated on a PIPE interface, the first end of the PIPE interface is used for being connected with an SATA host, the second end of the PIPE interface is used for being connected with SATA storage equipment, and in response to an inspection request for the communication process between the SATA host and the SATA storage equipment, a corresponding signal monitoring sequence is determined based on the communication process; based on the signal monitoring sequence, monitoring whether corresponding monitoring signals from the SATA host normally arrive at the first end of the PIPE interface according to the sequence, and monitoring whether corresponding monitoring signals from the SATA storage device normally arrive at the second end of the PIPE interface according to the sequence; and determining whether the communication process is normal based on the monitoring result of the monitoring signal. The detection efficiency can be improved, and the hardware cost can be reduced.

Description

Technical Field

[0001] The present application relates to the field of communications and computer technology, and in particular to a SATA communication detection method, device, and SATA hardware emulator. Background Art

[0002] SATA (Serial Advanced Technology Attachment) is a high-speed serial interface standard for connecting a host computer to storage devices such as hard drives, solid-state drives, and optical drives. SATA has become a mainstream storage interface technology and is widely used in servers, laptops, and other embedded system-on-chips. Therefore, pre-simulation design verification of SATA controllers can ensure that SATA designs fully comply with protocol specifications.

[0003] In the related art, SATA controllers are generally pre-designed and verified using simulation debugging tools or SATA protocol analyzer tools. However, this approach requires manual coordination and has high hardware costs. Summary of the Invention

[0004] This application aims to solve, at least to some extent, one of the technical problems in the related art. To this end, this application proposes a SATA communication detection method, device, and SATA hardware emulator. The main technical solutions adopted in this application include: In a first aspect, an embodiment of the present application provides a SATA communication detection method, which is applied to a SATA communication detection device, wherein the SATA communication detection device is integrated in a PIPE interface, wherein the first end of the PIPE interface is used to connect to a SATA host, and the second end of the PIPE interface is used to connect to a SATA storage device. The method comprises: in response to a request for checking the communication process between the SATA host and the SATA storage device, determining a corresponding signal monitoring sequence based on the communication process; based on the signal monitoring sequence, monitoring whether the corresponding monitoring signal from the SATA host arrives at the first end of the PIPE interface normally in sequence, and monitoring whether the corresponding monitoring signal from the SATA storage device arrives at the second end of the PIPE interface normally in sequence; and determining whether the communication process is normal based on the monitoring result of the monitoring signal.

[0005] The embodiment of the present application integrates a SATA communication detection device into the PIPE interface. Since the SATA communication detection device is integrated into the PIPE interface, the SATA communication detection device can not only detect the communication process between the SATA host and the SATA storage device connected to the two ends of the PIPE interface, but also has low hardware cost because it is integrated into the PIPE interface. Moreover, the SATA communication detection device can respond to an inspection request for the communication process between the SATA host and the SATA storage device, and determine the corresponding signal monitoring sequence based on the type of the communication process, thereby monitoring whether the corresponding monitoring signal from the SATA host arrives at the first end of the PIPE interface in sequence and normally, and monitoring whether the corresponding monitoring signal from the SATA storage device arrives at the second end of the PIPE interface in sequence and normally, and based on the monitoring results of the monitoring signal, determine whether the communication process is normal. In this way, the SATA communication detection device determines the corresponding signal monitoring sequence according to different types of communication processes, and can accurately monitor whether the monitoring signal of the communication process arrives normally. Such classified detection can improve detection efficiency and accuracy.

[0006] In one embodiment, based on a signal monitoring sequence, monitoring whether corresponding monitoring signals from a SATA host arrive at the first end of a PIPE interface in sequence and normally, and monitoring whether corresponding monitoring signals from a SATA storage device arrive at the second end of the PIPE interface in sequence and normally, includes: based on the signal transmission time of the communication process, in accordance with the signal monitoring sequence, sequentially monitoring whether corresponding monitoring signals arrive at corresponding ports in the PIPE interface normally; when the currently monitored monitoring signal arrives at the corresponding port in the PIPE interface normally, monitoring the next monitoring signal. In this example, in accordance with the signal transmission time and signal monitoring sequence of the communication process, sequentially monitoring whether corresponding monitoring signals arrive at corresponding ports in the PIPE interface normally, monitoring the next monitoring signal only when the currently monitored monitoring signal arrives at the corresponding port in the PIPE interface normally. In this way, it is possible to accurately monitor whether the communication process is normal.

[0007] In one embodiment, the method further includes: if the currently monitored monitoring signal fails to properly arrive at the corresponding port in the PIPE interface, setting a status register corresponding to the currently monitored monitoring signal high to indicate that the transmission process of the currently monitored monitoring signal is abnormal; wherein the status register is provided in the SATA communication detection device. In this example, if the currently monitored monitoring signal fails to properly arrive at the corresponding port in the PIPE interface, setting the status register corresponding to the currently monitored monitoring signal high indicates that the transmission process of the currently monitored monitoring signal is abnormal, thereby facilitating the provision of a prompt signal indicating this abnormality to the SATA controller for corresponding functional verification.

[0008] In one embodiment, the above-mentioned determination of the corresponding signal monitoring sequence based on the communication process includes: when the communication process is a link initialization process between a SATA host and a SATA storage device, determining the signal monitoring sequence to be a first monitoring sequence; wherein the first monitoring sequence is the order in which a communication reset signal from the SATA host at the first end of the PIPE interface, a communication initialization signal from the SATA storage device at the second end of the PIPE interface, a first wake-up signal from the SATA host at the first end of the PIPE interface, and a second wake-up signal from the SATA storage device at the second end of the PIPE interface arrive in sequence. In this example, when detecting the link initialization process between the SATA host and the SATA storage device, the first monitoring sequence is used as the signal monitoring sequence to monitor the arrival signals at the first and second ends of the PIPE interface. In this way, it can be accurately determined whether the link initialization process between the SATA host and the SATA storage device is normal.

[0009] In one embodiment, determining whether the communication process is normal based on the monitoring result of the monitoring signal includes: determining that the link initialization process between the SATA host and the SATA storage device has been normally completed when a second wake-up signal from the SATA storage device is detected to have normally arrived at the second end of the PIPE interface. In this example, when the link initialization process between the SATA host and the SATA storage device is detected according to a first monitoring sequence, the normal arrival of the signals and the normal arrival of the second wake-up signal from the SATA storage device at the second end of the PIPE interface are detected, thereby determining that the link initialization process between the SATA host and the SATA storage device has been normally completed.

[0010] In one embodiment, the method further includes: upon determining that the link initialization process between the SATA host and the SATA storage device has been completed normally, obtaining the device-negotiated maximum rate between the SATA host and the SATA storage device via the second end of the PIPE interface; and determining the signal transmission time of the rate negotiation process between the SATA host and the SATA storage device based on the device-negotiated maximum rate. In this example, upon determining that the link initialization process between the SATA host and the SATA storage device has been completed normally, the device-negotiated maximum rate between the SATA host and the SATA storage device can be obtained from the SATA storage device via the second end of the PIPE interface. Thus, based on the device-negotiated maximum rate, the signal transmission time of the rate negotiation process can be determined. Based on this signal transmission time, it is possible to accurately detect whether the signal during the rate negotiation process has arrived normally.

[0011] In one embodiment, determining a corresponding signal monitoring sequence based on the communication process includes: when the communication process is a rate negotiation process between a SATA host and a SATA storage device, determining the signal monitoring sequence to be a second monitoring sequence; wherein the second monitoring sequence is the order in which a first byte alignment primitive from the SATA storage device at the second end of the PIPE interface, a second byte alignment primitive from the SATA host at the first end of the PIPE interface, a first synchronization primitive from the SATA storage device at the second end of the PIPE interface, and a second synchronization primitive from the SATA host at the first end of the PIPE interface arrive in sequence. In this example, when detecting the rate negotiation process between the SATA host and the SATA storage device, the second monitoring sequence is used as the signal monitoring sequence to monitor the arrival signals at the first and second ends of the PIPE interface. In this way, it can be accurately determined whether the rate negotiation process between the SATA host and the SATA storage device is normal.

[0012] In one embodiment, determining whether the communication process is normal based on the monitoring result of the monitoring signal includes: determining that the rate negotiation process between the SATA host and the SATA storage device has been completed normally when a first synchronization primitive from the SATA storage device is detected to have arrived normally at the second end of the PIPE interface, and a second synchronization primitive from the SATA host is detected to have arrived normally at the first end of the PIPE interface. In this example, when the first synchronization primitive from the SATA storage device is detected to have arrived normally at the second end of the PIPE interface, and the second synchronization primitive from the SATA host is detected to have arrived normally at the first end of the PIPE interface, it is determined that the SATA host and the SATA storage device can send synchronization primitives to each other. In this way, it can be accurately determined that the rate negotiation process between the SATA host and the SATA storage device has been completed normally.

[0013] In one embodiment, determining a corresponding signal monitoring sequence based on a communication process is configured as follows: when the communication process is a data read / write process between a SATA host and a SATA storage device, monitoring an interface data frame start character from the SATA host via the first end of a PIPE interface; when the interface data frame start character is detected arriving at the first end of a SATA communication detection device, monitoring a register FIS from the SATA host via the first end of the PIPE interface; and determining a signal monitoring sequence based on the register FIS from the SATA host. In this example, when detecting a data read / write process between a SATA host and a SATA storage device, monitoring whether the interface data frame start character from the SATA host arrives at the first end of the PIPE interface is performed. If the interface data frame start character is detected arriving at the first end of the PIPE interface, monitoring the register FIS from the SATA host is performed, and determining a corresponding signal monitoring sequence based on the read / write operation type of the register FIS of the SATA host. In this manner, monitoring the data read process or write process separately according to the signal monitoring sequence corresponding to the read / write operation type can improve detection accuracy.

[0014] In one embodiment, determining a signal monitoring sequence based on a register FIS from a SATA host includes: when detecting that the register FIS from the SATA host is a DMA write operation type, determining the signal monitoring sequence to be a third monitoring sequence; wherein the third monitoring sequence is the order in which the register FIS from the SATA storage device at the second end of the PIPE interface, the data start transmission FIS from the SATA host at the first end of the PIPE interface, the activation FIS from the SATA host at the first end of the PIPE interface, the data FIS from the SATA host at the first end of the PIPE interface, and the write command execution completion FIS from the SATA host at the second end of the PIPE interface arrive in sequence. In this example, when detecting that the register FIS from the SATA host is a DMA write operation type, the data write process between the SATA host and the SATA storage device is monitored according to the third monitoring sequence corresponding to the write operation type, thereby accurately detecting whether the data write process is normal.

[0015] In one embodiment, the method further includes: upon detecting that a register FIS from the SATA host is a DMA read operation type, determining a signal monitoring sequence to be a fourth monitoring sequence; wherein the fourth monitoring sequence is the order in which the register FIS from the SATA storage device at the second end of the PIPE interface, the data start transfer FIS from the SATA storage device at the second end of the PIPE interface, the data FIS from the SATA storage device at the second end of the PIPE interface, and the read command execution completion FIS from the SATA host at the first end of the PIPE interface arrive in sequence. In this example, upon detecting that the register FIS from the SATA host is a DMA read operation type, the data read process between the SATA host and the SATA storage device is monitored according to the fourth monitoring sequence corresponding to the write operation type, thereby accurately detecting whether the data read process is normal.

[0016] In a second aspect, an embodiment of the present application provides a SATA communication detection device, which is integrated into a PIPE interface. A first end of the PIPE interface is used to connect to a SATA host, and a second end of the PIPE interface is used to connect to a SATA storage device. The SATA communication detection device is configured to: In response to a request for checking a communication process between a SATA host and a SATA storage device, determining a corresponding signal monitoring order based on the communication process; Based on the signal monitoring sequence, monitoring whether the corresponding monitoring signals from the SATA host arrive at the first end of the PIPE interface normally in sequence, and monitoring whether the corresponding monitoring signals from the SATA storage device arrive at the second end of the PIPE interface normally in sequence; Based on the monitoring result of the monitoring signal, determine whether the communication process is normal.

[0017] In a third aspect, an embodiment of the present application provides a SATA hardware emulator, comprising a SATA host, a PIPE interface, and a SATA communication detection device, wherein the SATA host is connected to a first end of the PIPE interface, the second end of the PIPE interface is used to connect to a SATA storage device, and the SATA communication detection device is integrated into the PIPE interface.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present application. Figure 1AThis is a diagram of the data transmission system architecture based on the SATA protocol according to an embodiment of the present application; Figure 1B This is an architecture diagram of a data transmission system based on the SATA protocol according to another embodiment of the present application; Figure 2 This is a flow chart of a SATA communication detection method according to an embodiment of the present application; Figure 3 is a flow chart of a SATA communication detection method according to another embodiment of the present application; Figure 4 This is a detection flow chart of the link initialization process of an embodiment of the present application; Figure 5 This is a detection flow chart of the rate negotiation process according to an embodiment of the present application; Figure 6 This is a detection flow chart of the data writing process of an embodiment of the present application; Figure 7 This is a detection flow chart of the data reading process of an embodiment of the present application; Figure 8 This is an application scenario diagram of a SATA communication detection device according to an embodiment of the present application; Figure 9 This is an application scenario diagram of a SATA hardware emulator according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0021] In related technologies, SATA hardware emulation accelerator verification is one of the important means of verifying SATA protocol implementation. By establishing a hardware emulation accelerator verification environment for the SATA controller, link initialization, rate negotiation, hot plugging, compatibility, low-power functionality verification, and protocol consistency can be verified during the pre-simulation design phase of the SATA controller. Currently, hardware emulation verification environments can significantly increase simulation speed through hardware, but hardware emulation accelerator verification also faces challenges such as verification and debugging resource consumption, debugging complexity, high costs, and debugging efficiency. Continuous improvement of simulation and debugging methods is needed to improve simulation efficiency and debugging capabilities.

[0022] In terms of existing pre-simulation verification methods for SATA controllers, the common method for detecting problems in the SATA communication process generally relies on hardware such as SATA analyzers or simulation adjustment tools to debug and detect the signal waveform. However, this requires manual debugging and has problems such as high instrument costs and low manual analysis efficiency.

[0023] Based on this, according to an embodiment of the present application, a SATA communication detection method and a SATA communication detection device are provided. The SATA communication detection method is applied to the SATA communication detection device. Because the SATA communication detection device is integrated into the PIPE interface, the SATA communication detection device can not only detect the communication process between the SATA host and the SATA storage device connected at both ends of the PIPE interface, but also has low hardware cost due to its integration into the PIPE interface. Moreover, when responding to a request to check the communication process between the SATA host and the SATA storage device, the SATA communication detection device determines a corresponding signal monitoring sequence based on the type of communication process; based on the signal monitoring sequence, monitors whether the corresponding monitoring signal from the SATA host arrives at the first end of the PIPE interface in sequence and normally, and monitors whether the corresponding monitoring signal from the SATA storage device arrives at the second end of the PIPE interface in sequence and normally; and determines whether the communication process is normal based on the monitoring results of the monitoring signals. In this way, the SATA communication detection device determines the corresponding signal monitoring sequence according to different types of communication processes, and can accurately monitor whether the monitoring signal of the communication process arrives normally. Such classified detection can improve detection efficiency and accuracy.

[0024] Based on this, according to an embodiment of the present application, a SATA hardware emulator is provided, which includes a SATA host, a PIPE interface and a SATA communication detection device. The SATA host is connected to the first end of the PIPE interface, the second end of the PIPE interface is used to connect to the SATA storage device, and the SATA communication detection device is integrated into the PIPE interface. In this example, since the SATA communication detection device is integrated into the PIPE interface, not only can the communication process between the SATA host and the SATA storage device be detected, but the hardware cost is also low. Moreover, the SATA communication detection device is set in the same emulator as the SATA host and the PPIE interface, which can provide the detection results to the SATA host for simulation debugging, improve the simulation verification efficiency of the SATA host, and reduce the resource occupancy of the SATA communication detection device.

[0025] The following describes the SATA communication detection method proposed in the embodiment of the present application through a scenario example. Figure 1AThe SATA communication detection method can be applied to a SATA communication detection device, which is integrated into a PIPE interface. Thus, the SATA communication detection device can be applied to Figure 1A In the system architecture shown. The system architecture may include an environment end and a device end. The environment end includes a SATA host, a PIPE interface and a physical layer encapsulation module (which may be referred to as an encapsulation module for short). The environment end may also be considered as the SATA hardware emulator of an embodiment of the present application. The device end includes a speed bridge and a SATA storage device (which may be referred to as a SATA device for short). Among them, the SATA communication detection device is integrated into the PIPE interface, the first end of the PIPE interface is connected to the SATA host, the second end of the PIPE interface is connected to the physical layer encapsulation module, and the physical layer encapsulation module is connected to the SATA storage device through the speed bridge. In this way, the PIPE interface realizes the communication between the SATA host and the SATA storage device, and the SATA communication detection device in the PIPE interface can detect the communication process between the SATA host and the SATA storage device, thereby reducing hardware costs and improving inspection efficiency.

[0026] Among them, the SATA communication detection device can set a detection model in the form of software to detect the communication process between the SATA host and the SATA storage device. For example, the SATA communication detection device can call the detection model to execute the SATA communication detection method of the embodiment of the present application to detect the transmission signal of the PIPE interface. The function of the detection model includes detecting the link initialization process, rate negotiation process and data reading and writing process between the SATA host and the SATA storage device, and providing the detection results. The detection results include whether the transmission process of each signal in the communication process is normal, such as whether it arrives at a timeout, etc. In this way, it is convenient for the environment end to locate whether the error occurs on the SATA host side or on the SATA storage device side.

[0027] The inspection model can be divided into multiple sub-models. The sub-models can include: a link initialization inspection model or module for detecting the link initialization process between the SATA host and the SATA storage device, a rate negotiation inspection model or module for detecting the rate negotiation process between the SATA host and the SATA storage device, and a data read and write inspection model or module for detecting the data read and write process between the SATA host and the SATA storage device.

[0028] like Figure 1AAs shown, the SATA communication detection device can be integrated into any PIPE interface or mounted on any PIPE interface. This allows for communication checks to be performed on multiple architectures consisting of a SATA host, PIPE interface, physical layer encapsulation module, speed bridge, and SATA storage device, depending on the testing requirements. The speed bridge can buffer and transfer data between SATA hosts and SATA storage devices operating at different interface rates. The SATA host can transmit signals or data to the SATA storage device via the PIPE interface, physical layer encapsulation module, and speed bridge, and the SATA storage device can also transmit data to the SATA host via the speed bridge, physical layer encapsulation module, and PIPE interface.

[0029] like Figure 1B As shown, in actual application, an example of the implementation of the inspection model in the SATA communication detection device is as follows: The inspection model includes a link initialization inspection model, a rate negotiation model, and a data reading and writing model written in Verilog language, which respectively checks the normality of the transmission signals during the link initialization process, the rate negotiation process, and the data reading and writing process.

[0030] The top-level module is an instantiation of three check models written in Verilog language (i.e. Figure 1B The initialization link check module, rate negotiation check module, and read / write flow check module in the Module are described. This module defines the top-level interface and the conditional compilation preprocessing directives (`ifdef`) written in Verilog for each check model instantiation. The top-level module excludes code blocks in response to check requests based on predefined macro switches for each of the three check models, enabling independent control of the effectiveness of the three check models.

[0031] The interface connection module is used to bind the port of the PIPE interface with the port of the top-level file corresponding to each inspection model, so that the inspection model can detect whether the signal from the SATA host or the SATA storage device reaches the corresponding port in the PIPE interface.

[0032] The interface file (CSV) table is used to generate the import file for the interface connection module using a Python script. The contents of the interface file (CSV) table include the identifier of the SATA host to which the PIPE interface is connected, the identifier of the signal from the SATA host, and the "Inspection Model Input Signal" in the top-level module of the inspection model.

[0033] The Python script is used to execute the SATA communication test device. Based on the interface file CSV table, the script generates a module file, i.e., an interface connection module, that connects the PIPE interface to the input interface of the top module of the inspection model.

[0034] In the embodiment of the present application, Figure 1A and 1B The SATA communication detection device is integrated into the PIPE interface in the architecture, which can not only detect the communication process between the SATA host and the SATA storage device, but also reduce hardware costs. Moreover, since the SATA communication detection device is set at the PIPE interface and is close to the SATA host, it can provide detection results for the environment end where the SATA host is located to perform pre-simulation design verification and debugging, reducing the resource occupation of the SATA communication detection device during the debugging process and improving resource utilization.

[0035] exist Figure 1A and 1B In the architecture, for the communication process between the SATA host and the SATA storage device, the SATA communication detection device can perform the following Figure 2 The SATA detection method shown detects the communication process, specifically including: S210, in response to a request for checking a communication process between a SATA host and a SATA storage device, determining a corresponding signal monitoring order based on the communication process; S220, based on the signal monitoring sequence, monitoring whether corresponding monitoring signals from the SATA host arrive at the first end of the PIPE interface normally in sequence, and monitoring whether corresponding monitoring signals from the SATA storage device arrive at the second end of the PIPE interface normally in sequence; S230: Determine whether the communication process is normal based on the monitoring result of the monitoring signal.

[0036] In one example, the communication process between a SATA host and a SATA storage device may include link initialization, rate negotiation, and data read / write. The signal monitoring sequence for each communication process can be different. For example, the signal monitoring sequence for the link initialization process is different from that for the rate negotiation process, and also different from that for the data read / write process. Another example is that the signal monitoring sequence for the rate negotiation process is different from that for the data read / write process. The signals involved in each communication process are also different. The link initialization process includes OOB (Out of Band) signals, such as the communication reset signal (comreset), the communication initialization signal (cominit), and the communication wakeup signal (comwake). The rate negotiation process includes alignment primitives (ALIGN) and synchronization primitives (SYNC). The data read / write process includes the non-data FIS (Frame Information Structure) and the data FIS. For example, the non-data FIS includes primitives for DMA (Direct Memory Access) reads or DMA writes.

[0037] In one example, the SATA communication detection device integrated in the PIPE interface may use a preset detection model to perform the above steps S210 to S230.

[0038] In one example, a SATA communication detection device integrated in a PIPE interface can respond to a request for checking the communication process between a SATA host and a SATA storage device. In step S210, based on the communication process, a corresponding sub-model is called, and the sub-model is preset with a corresponding signal monitoring sequence and a signal detection mechanism. The sub-model may include a link initialization check model, a rate negotiation model, and a data reading and writing model. Since the SATA communication detection device is integrated in the PIPE interface, whether the communication process between the SATA host and the SATA storage device is normal is determined by detecting the transmission signal in the PIPE interface. The transmission signal is a signal from the SATA host and arriving at the first end of the PIPE interface or a signal from the SATA storage device and arriving at the second end of the PIPE interface. Therefore, it can be understood that the signal monitoring sequence includes the arrival order of each signal at the PIPE interface during the corresponding communication process.

[0039] Then, the SATA communication detection device executes step S220 and step S230 through the sub-model, that is, monitoring whether the corresponding monitoring signal from the SATA host arrives at the first end of the PIPE interface normally in sequence, and monitoring whether the corresponding monitoring signal from the SATA storage device arrives at the second end of the PIPE interface normally in sequence, and based on the monitoring results of the monitoring signal, determines whether the communication process is normal.

[0040] In one example, the monitoring result of the monitoring signal may include that the monitoring signal arrives at the corresponding port in the PIPE interface normally, for example, that the monitoring signal arrives at the corresponding port in the PIPE interface in order and without timeout. Alternatively, the monitoring result of the monitoring signal may include that the monitoring signal does not arrive at the corresponding port in the PIPE interface normally, for example, that the monitoring signal times out or does not arrive at the corresponding port in the PIPE interface after timeout.

[0041] It is understandable that if any monitoring signal during the communication process does not normally arrive at the corresponding port in the PIPE interface, the communication process can be determined to be abnormal, and the transmission process of the monitoring signal can be determined to be abnormal. If each monitoring signal during the communication process normally arrives at the corresponding port in the PIPE interface, the communication process can be determined to be normal.

[0042] In one example, a log is used to record the monitoring result of the monitoring signal and information on whether the communication process is normal, so that the user can easily view the detection status of the communication process by the SATA communication detection device.

[0043] According to an embodiment of the present application, a SATA communication detection method is applied to a SATA communication detection device. Since the SATA communication detection device is integrated into a PIPE interface, the SATA communication detection device can not only detect the communication process between the SATA host and the SATA storage device connected to the two ends of the PIPE interface, but also has low hardware cost because it is integrated into the PIPE interface. When responding to a request to check the communication process between the SATA host and the SATA storage device, the SATA communication detection device determines a corresponding signal monitoring sequence based on the type of the communication process; based on the signal monitoring sequence, monitors whether the corresponding monitoring signal from the SATA host arrives at the first end of the PIPE interface in sequence and normally, and monitors whether the corresponding monitoring signal from the SATA storage device arrives at the second end of the PIPE interface in sequence and normally; and determines whether the communication process is normal based on the monitoring results of the monitoring signal. The SATA communication detection device determines the corresponding signal monitoring sequence according to different types of communication processes, and can accurately monitor whether the monitoring signal of the communication process arrives normally. Such classified detection can improve detection efficiency and accuracy.

[0044] exist Figure 1A and1B In the architecture, for the communication process between the SATA host and the SATA storage device, the SATA communication detection device can perform the following Figure 3 The SATA detection method shown detects the communication process, specifically including: S310, in response to a request for checking a communication process between a SATA host and a SATA storage device, determining a corresponding signal monitoring order based on the communication process; S320, based on the signal transmission time of the communication process and in accordance with the signal monitoring order of the communication process, sequentially monitoring whether the corresponding monitoring signal normally arrives at the corresponding port in the PIPE interface; In step S330, if the currently monitored monitoring signal arrives normally at the corresponding port in the PIPE interface, the next monitoring signal is monitored. The process then returns to step S320 to monitor the next monitoring signal, and monitoring stops until the last monitoring signal is detected or the monitoring signal fails to arrive normally at the corresponding port in the PIPE interface.

[0045] In one example, the signal transmission time is not necessarily the same for different communication processes. For example, during the rate negotiation process, the signal transmission time can be determined based on the maximum rate negotiated between the SATA host and the SATA storage device. For another example, for the link initialization process, the signal transmission time of the link initialization process can be determined according to a preset time. For another example, for the data reading and writing process, the signal transmission time of the data reading and writing process is determined according to the signal transmission time of the rate negotiation process at this time when it is determined that the rate negotiation process has been completed normally. The signal transmission time can be used to determine whether the monitoring signal can reach the corresponding port in the PIPE interface within the specified time. If it fails to reach the corresponding port in the PIPE interface within the specified time, it is determined that the monitoring signal did not reach the PIPE interface normally, and there is an abnormality in the sending process of the monitoring signal. This may be due to an abnormality in the sending device of the monitoring signal.

[0046] In one example, the SATA communication detection device integrated in the PIPE interface may use a preset inspection model to perform the above steps S310 to S330 .

[0047] In one example, a SATA communication detection device integrated into a PIPE interface can respond to a request to check the communication process between a SATA host and a SATA storage device. In step S310, based on the communication process, it invokes a corresponding sub-model, which is pre-configured with a corresponding signal monitoring sequence and signal detection mechanism. The sub-models may include a link initialization check model, a rate negotiation model, and a data read / write model. The SATA communication detection device then executes steps S320 and S330 using the sub-models.

[0048] In one example, if Figure 3 The SATA detection method shown further includes the following steps: S340, when the currently monitored monitoring signal does not normally reach the corresponding port in the PIPE interface, the status register corresponding to the currently monitored monitoring signal is set high to indicate that the sending process of the currently monitored monitoring signal is abnormal; wherein the status register is set in the SATA communication detection device.

[0049] In this example, when the SATA communication detection device detects that the currently monitored monitoring signal has not properly arrived at the corresponding port in the PIPE interface, it determines that the transmission process of the currently monitored monitoring signal is abnormal and sets the status register corresponding to the currently monitored monitoring signal high. In this way, the high setting of the status register can indicate that the transmission process of the currently monitored monitoring signal is abnormal.

[0050] In one example, Figure 1A and 1B The SATA host in the environment end can determine, during the debugging process, from the high status register through the debugging window whether the sending process of the monitoring signal corresponding to the status register is abnormal.

[0051] In one example, the SATA communication detection device may record the monitoring result of the monitoring signal and the result of whether the communication process is normal in a local log. Figure 1A and 1B The SATA host on the environment side can use the debug window to obtain monitoring results of each communication process from the local log of the SATA communication detection device, as well as information on the normality of each communication process. Examples include "XXX signal timed out or did not arrive normally during link initialization," "Link initialization completed normally," "Rate negotiation completed normally," and "XXX signal received from the SATA storage device during data reading or writing." The SATA host on the environment side can use this information for simulation verification and debugging, improving simulation verification efficiency.

[0052] According to an embodiment of the present application, a SATA communication detection method is applied to a SATA communication detection device. Since the SATA communication detection device is integrated into a PIPE interface, the SATA communication detection device can not only detect the communication process between a SATA host and a SATA storage device connected at both ends of the PIPE interface, but also has low hardware cost due to its integration into the PIPE interface. When responding to a request to check the communication process between a SATA host and a SATA storage device, the SATA communication detection device determines the corresponding signal monitoring sequence and signal transmission time based on the type of communication process, and thereby monitors whether the corresponding monitoring signal arrives in sequence and normally at the corresponding port in the PIPE interface. When the currently monitored monitoring signal arrives normally at the corresponding port in the PIPE interface, the next monitoring signal is monitored, and the signals are monitored in this order until the last signal is detected to have arrived normally, thereby accurately determining that the communication process has completed normally. Furthermore, when a monitoring signal does not arrive normally at the corresponding port in the PIPE interface, the corresponding status register is set high to indicate that the transmission process of the currently monitored monitoring signal is abnormal. This facilitates the SATA host to obtain corresponding indication information from the status register in the SATA communication detection device for debugging, thereby improving debugging efficiency.

[0053] like Figure 1B and Figure 4 As shown, the process of the SATA communication detection device detecting the link initialization process is as follows: In the above-mentioned step S210 or S310, based on the communication process, a corresponding signal monitoring sequence is determined, including: when the communication process is a link initialization process between a SATA host and a SATA storage device, determining the signal monitoring sequence to be a first monitoring sequence; wherein the first monitoring sequence is the order of arrival of a communication reset signal from the SATA host at the first end of the PIPE interface, a communication initialization signal from the SATA storage device at the second end of the PIPE interface, a first wake-up signal from the SATA host at the first end of the PIPE interface, and a second wake-up signal from the SATA storage device at the second end of the PIPE interface.

[0054] In the above step S230 , when it is detected that the second wake-up signal from the SATA storage device has normally arrived at the second end of the PIPE interface, it is determined that the link initialization process between the SATA host and the SATA storage device has been normally completed.

[0055] like Figure 1BAs shown, when the inspection model in the SATA communication detection device determines that the communication process targeted by the inspection request is the link initialization process between the SATA host and the SATA storage device, the link initialization inspection model is called, and the corresponding monitoring signal is monitored in sequence according to the first monitoring sequence recorded in the link initialization inspection model to determine whether it reaches the corresponding port in the PIPE interface normally.

[0056] The link initialization check model receives the out-of-band (OOB) signal from the PIPE interface bound to the interface connection module as its input signal. The PIPE interface's clock and reset signals are also transmitted to the link initialization check model. The link initialization check model checks whether these input signals are detected sequentially within a predetermined timeframe, according to a first monitoring sequence.

[0057] Among them, the above-mentioned oob signal includes a communication reset signal (comreset) from the SATA host at the first end of the PIPE interface, a communication initialization signal (cominit) from the SATA storage device at the second end of the PIPE interface, a first wake-up signal (comwake) from the SATA host at the first end of the PIPE interface, and a second wake-up signal (comwake) from the SATA storage device at the second end of the PIPE interface.

[0058] During the link initialization process, the link initialization check model receives the reset signal provided by the PIPE interface, and then monitors in sequence based on the first monitoring sequence and the signal transmission time corresponding to the link initialization process whether the above-mentioned oob signal can reach the PIPE interface normally, that is, arrives at the PIPE interface within the predetermined time corresponding to the signal transmission time.

[0059] like Figure 4 As shown, the link initialization check model receives the reset signal provided by the PIPE interface and monitors whether the communication reset signal (comreset) from the SATA host can reach the first end of the PIPE interface within a predetermined time based on the signal transmission time.

[0060] If the communication reset signal (comreset) from the SATA host fails to reach the first end of the PIPE interface within a predetermined time, it is determined that the communication reset signal (comreset) from the SATA host has timed out, and the first status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the sending process of the communication reset signal (comreset) by the SATA host. Figure 1BThe environment (SATA hardware emulator) can use the debug window to obtain the setting information of the first status register in the SATA communication detection device. If the setting information is set high (set to 1), the debug window will output a log. This log includes the setting information of the first status register and the message "An error occurred during the transmission of the communication reset signal (comreset) by the SATA host." This log information can help the SATA hardware emulator optimize or modify the link initialization process.

[0061] If the communication reset signal (comreset) from the SATA host reaches the first end of the PIPE interface within the predetermined time, the communication initialization signal (cominit) from the SATA storage device is continuously monitored to see whether it can reach the second end of the PIPE interface within the predetermined time based on the signal transmission time.

[0062] If the communication initialization signal (cominit) from the SATA storage device fails to arrive at the second end of the PIPE interface within a predetermined time, it is determined that the communication initialization signal (cominit) from the SATA storage device has timed out, and the second status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the sending process of the communication initialization signal (cominit) by the SATA storage device. Figure 1B The environment terminal can use the debug window to obtain the setting information of the second status register in the SATA communication detection device. If the setting information is high (set to 1), the debug window will output a log containing the setting information of the second status register and the message "An error occurred during the transmission of the communication initialization signal (cominit) by the SATA storage device." This log information can assist the SATA hardware emulator in optimizing or modifying the link initialization process.

[0063] If the communication initialization signal (cominit) from the SATA storage device can reach the second end of the PIPE interface within the predetermined time, then based on the signal transmission time, the first wake-up signal (comwake) from the SATA host is continuously monitored to see whether it can reach the first end of the PIPE interface within the predetermined time.

[0064] If the first wake-up signal (comwake) from the SATA host fails to arrive at the first end of the PIPE interface within a predetermined time, it is determined that the first wake-up signal (comwake) from the SATA host has timed out, and the third status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the sending process of the first wake-up signal (comwake) by the SATA host. Figure 1BThe environment terminal can use the debug window to obtain the setting information of the third status register in the SATA communication detection device. If the setting information is set high (set to 1), the debug window will output a log containing the setting information of the third status register and the message "An error occurred during the transmission of the first wake-up signal (comwake) by the SATA host." This log information can assist the SATA hardware emulator in optimizing or modifying the link initialization process.

[0065] If the first wake-up signal (comwake) from the SATA host can reach the first end of the PIPE interface within the predetermined time, then the second wake-up signal (comwake) from the SATA storage device is continuously monitored to see whether it can reach the second end of the PIPE interface within the predetermined time based on the signal transmission time.

[0066] If the second wake-up signal (comwake) from the SATA storage device fails to arrive at the second end of the PIPE interface within a predetermined time, it is determined that the second wake-up signal (comwake) from the SATA storage device has timed out, and a fourth status register corresponding to the signal is set high (set to 1) to indicate that an error occurs in the sending process of the second wake-up signal (comwake) by the SATA storage device. Figure 1B The environment terminal can use the debug window to obtain the setting information of the fourth status register in the SATA communication detection device. If the setting information is set high (set to 1), the debug window will output a log containing the setting information of the fourth status register and the message "an error occurred during the sending of the second wake-up signal (comwake) by the SATA storage device." This log information can assist the SATA hardware emulator in optimizing or modifying the link initialization process.

[0067] If the second wake-up signal (comwake) from the SATA storage device can reach the second end of the PIPE interface within a predetermined time, it is determined that the link initialization process between the SATA host and the SATA storage device has been completed normally. Figure 1B The environment end in the debug window can obtain log information, which includes the information that the link initialization process between the SATA host and the SATA storage device has been completed normally.

[0068] According to an embodiment of the present application, the corresponding signals during the link initialization process between the SATA host and the SATA storage device are monitored based on the order of arrival of the communication reset signal from the SATA host at the first end of the PIPE interface, the communication initialization signal from the SATA storage device at the second end of the PIPE interface, the first wake-up signal from the SATA host at the first end of the PIPE interface, and the second wake-up signal from the SATA storage device at the second end of the PIPE interface. This allows accurate monitoring of whether the transmission process of these signals is normal, and accurately locates which signal transmission process has an abnormality. This can accurately assist the emulator corresponding to the SATA host in optimizing the link initialization process, thereby improving optimization efficiency. Furthermore, since the signals are monitored in sequence, when the second wake-up signal from the SATA storage device is monitored to arrive at the second end of the PIPE interface, it can be determined that the link initialization process between the SATA host and the SATA storage device has been completed normally.

[0069] like Figure 1B and Figure 5 As shown, the process of the SATA communication detection device detecting the rate negotiation process is as follows: The above method also includes: when it is determined that the link initialization process between the SATA host and the SATA storage device has been completed normally, obtaining the device negotiated maximum rate between the SATA host and the SATA storage device through the second end of the PIPE interface; and determining the signal transmission time of the rate negotiation process between the SATA host and the SATA storage device based on the device negotiated maximum rate.

[0070] In the above-mentioned step S210 or S310, based on the communication process, a corresponding signal monitoring order is determined, including: when the communication process is a rate negotiation process between a SATA host and a SATA storage device, determining the signal monitoring order to be a second monitoring order; wherein the second monitoring order is the order of arrival of a first byte alignment primitive from the SATA storage device at the second end of the PIPE interface, a second byte alignment primitive from the SATA host at the first end of the PIPE interface, a first synchronization primitive from the SATA storage device at the second end of the PIPE interface, and a second synchronization primitive from the SATA host at the first end of the PIPE interface.

[0071] In the above step S230, based on the monitoring result of the monitoring signal, determining whether the communication process is normal includes: when it is monitored that the first synchronization primitive from the SATA storage device arrives normally at the second end of the PIPE interface, and the second synchronization primitive from the SATA host arrives normally at the first end of the PIPE interface, determining that the rate negotiation process between the SATA host and the SATA storage device has been completed normally.

[0072] like Figure 1B As shown, when the inspection model in the SATA communication detection device determines that the communication process targeted by the inspection request is the rate negotiation process between the SATA host and the SATA storage device, the rate negotiation inspection model is called to first obtain the maximum device negotiation rate between the SATA host and the SATA storage device, and accordingly determine the signal transmission time of the rate negotiation process. Based on the second monitoring sequence recorded in the rate negotiation inspection model and the signal transmission time, the corresponding monitoring signal is sequentially monitored to see whether it arrives at the corresponding port in the PIPE interface normally.

[0073] like Figure 1B As shown, the rate negotiation check model receives the physical layer (PHY) rate interface signal and parallel data signal from the PIPE interface bound to the interface connection module as input signals to the rate negotiation check model. The PIPE interface's clock signal and reset signal are also transmitted to the rate negotiation check model. The rate negotiation check model, based on the second monitoring sequence, sequentially monitors whether these input signals arrive at the PIPE interface within a predetermined time.

[0074] The physical layer (PHY) rate interface signal includes the device negotiation maximum rate between the SATA host and the SATA storage device. The physical layer (PHY) rate interface signal comes from Figure 1B The physical layer encapsulation module in Figure 1B The second end of the PIPE interface can obtain the physical layer (PHY) rate interface signal. The parallel data signal includes primitives transmitted during rate negotiation between the SATA host and the SATA storage device, such as the alignment primitive (ALIGN) and the synchronization status primitive (SYNC).

[0075] like Figure 5 As shown, after determining that the link initialization process between the SATA host and the SATA storage device has completed normally, the rate negotiation check model obtains the device-negotiated maximum rate between the SATA host and the SATA storage device via the second end of the PIPE interface. Based on the device-negotiated maximum rate, the rate negotiation check model determines the signal transmission time of the rate negotiation process between the SATA host and the SATA storage device. Then, based on this signal transmission time, the rate negotiation check model monitors whether the first byte alignment primitive from the SATA storage device arrives at the second end of the PIPE interface within a predetermined time.

[0076] If the first byte alignment primitive (ALIGN) from the SATA storage device fails to arrive at the second end of the PIPE interface within a predetermined time, it is determined that the first byte alignment primitive (ALIGN) from the SATA storage device has timed out, and the fifth status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the sending process of the first byte alignment primitive (ALIGN) sent by the SATA storage device. Figure 1B The environment can use the debug window to obtain the setting information of the fifth status register in the SATA communication detection device. If the setting information is set high (set to 1), the debug window will output a log containing the setting information of the fifth status register and the message "An error occurred during the transmission of the first byte alignment primitive (ALIGN) by the SATA storage device." This log information can help the SATA hardware emulator optimize or modify the rate negotiation process.

[0077] If the first byte alignment primitive (ALIGN) from the SATA storage device can reach the second end of the PIPE interface within the predetermined time, then based on the above-determined signal transmission time, continue to monitor whether the second byte alignment primitive (ALIGN) from the SATA host reaches the first end of the PIPE interface within the predetermined time.

[0078] If the second byte alignment primitive (ALIGN) from the SATA host fails to arrive at the first end of the PIPE interface within a predetermined time, it is determined that the second byte alignment primitive (ALIGN) from the SATA host has timed out, and the sixth status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the sending process of the second byte alignment primitive (ALIGN) sent by the SATA host. Figure 1B The environment can use the debug window to obtain the setting information of the sixth status register in the SATA communication detection device. If the setting information is high (set to 1), the debug window will output a log containing the setting information of the sixth status register and the message "An error occurred during the transmission of the second byte alignment primitive (ALIGN) by the SATA host." This log information can help the SATA hardware emulator optimize or modify the rate negotiation process.

[0079] If the second byte alignment primitive (ALIGN) from the SATA host can reach the first end of the PIPE interface within the predetermined time, then based on the determined signal transmission time, the first synchronization primitive (SYNC) from the SATA storage device is continuously monitored to see whether it reaches the second end of the PIPE interface within the predetermined time, and the second synchronization primitive (SYNC) from the SATA host is also monitored to see whether it reaches the first end of the PIPE interface within the predetermined time. In other words, the SATA host and the SATA storage device are continuously monitoring whether they can send synchronization status primitives.

[0080] If the first synchronization primitive (SYNC) from the SATA storage device fails to arrive at the second end of the PIPE interface within a predetermined time, it is determined that the first synchronization primitive (SYNC) from the SATA storage device has timed out, and the seventh status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the sending process of the first synchronization primitive (SYNC) by the SATA storage device. Figure 1B The environment terminal can use the debug window to obtain the setting information of the seventh status register in the SATA communication detection device. If the setting information is set high (set to 1), the debug window will output a log containing the setting information of the seventh status register and the message "An error occurred during the transmission of the first synchronization status primitive (SYNC) by the SATA storage device." This log information can help the SATA hardware emulator optimize or modify the rate negotiation process.

[0081] If the second synchronization primitive (SYNC) from the SATA host fails to arrive at the first end of the PIPE interface within a predetermined time, it is determined that the second synchronization primitive (SYNC) from the SATA host has timed out, and an eighth status register corresponding to the signal is set high (set to 1) to indicate that an error occurs in the sending process of the second synchronization primitive (SYNC) by the SATA host. Figure 1B The environment terminal can use the debug window to obtain the setting information of the eighth status register in the SATA communication detection device. If the setting information is set high (set to 1), the debug window will output a log containing the setting information of the eighth status register and the "SATA host sending the second synchronization primitive (SYNC) process." This log information can assist the SATA hardware emulator in optimizing or modifying the rate negotiation process.

[0082] If a first synchronization primitive (SYNC) from the SATA storage device can reach the second end of the PIPE interface within a predetermined time, and a second synchronization primitive (SYNC) from the SATA host can reach the first end of the PIPE interface within a predetermined time, it is determined that both the SATA host and the SATA storage device can continuously send synchronization status primitives, and furthermore, it is determined that the rate negotiation process between the SATA host and the SATA storage device has been completed normally. Figure 1B The environment end in the debug window can obtain log information, which includes the information that the rate negotiation process between the SATA host and the SATA storage device has been completed normally.

[0083] It should be noted that when the monitoring process determines that any of the above primitives has timed out, it means that the rate negotiation process is erroneous or has failed, and the SATA host and the SATA storage device will renegotiate the rate, such as reducing the rate. Therefore, when the monitoring process determines that any of the above primitives has timed out, the SATA communication detection device can return to continue executing the steps of "obtaining the device negotiated maximum rate between the SATA host and the SATA storage device through the second end of the PIPE interface; and determining the signal transmission time of the rate negotiation process between the SATA host and the SATA storage device based on the device negotiated maximum rate." In this way, the device negotiated maximum rate is updated, the signal transmission time of the rate negotiation process is re-determined, and based on the re-determined signal transmission time, starting from the first monitoring signal in the second monitoring sequence, it is monitored in sequence whether the above input signals can reach the PIPE interface in sequence within the predetermined time. Subsequently, the signal transmission time of the data reading and writing process can also be determined based on the signal transmission time of the rate negotiation process, which can improve the monitoring accuracy of the data reading and writing process.

[0084] According to an embodiment of the present application, when it is determined that the link initialization has been completed normally, the maximum rate of device negotiation between the SATA host and the SATA storage device is obtained through the second end of the PIPE interface, thereby accurately determining the signal transmission time of the rate negotiation process between the SATA host and the SATA storage device. Then, based on the arrival order of the first byte alignment primitive from the SATA storage device at the second end of the PIPE interface, the second byte alignment primitive from the SATA host at the first end of the PIPE interface, the first synchronization primitive from the SATA storage device at the second end of the PIPE interface, and the second synchronization primitive from the SATA host at the first end of the PIPE interface, as well as the above-determined signal transmission time, the corresponding signals during the link initialization process between the SATA host and the SATA storage device are monitored, and whether the transmission process of these signals is normal can be accurately monitored, and which signal transmission process has an abnormality can be accurately located, which can accurately assist the emulator in optimizing the rate negotiation process and improve the optimization efficiency.

[0085] Furthermore, since the signals are monitored sequentially, when it is monitored that the first synchronization primitive (SYNC) from the SATA storage device can normally arrive at the second end of the PIPE interface, and the second synchronization primitive (SYNC) from the SATA host can normally arrive at the first end of the PIPE interface, it can be determined that the rate negotiation process between the SATA host and the SATA storage device has been normally completed.

[0086] like Figure 1B 、 Figure 6 and Figure 7 As shown, the process of the SATA communication detection device detecting the data reading and writing process is as follows: In the above-mentioned step S210 or S310, the above-mentioned determination of the corresponding signal monitoring order based on the communication process is configured as follows: when the communication process is a data reading and writing process between a SATA host and a SATA storage device, the interface data frame start character from the SATA host is monitored through the first end of the PIPE interface; when the interface data frame start character is detected to arrive at the first end of the SATA communication detection device, the register FIS from the SATA host is monitored through the first end of the PIPE interface; and the signal monitoring order is determined based on the register FIS from the SATA host.

[0087] In one example, determining a signal monitoring order based on a register FIS from a SATA host includes: when it is detected that the register FIS from the SATA host is a DMA write operation type, determining the signal monitoring order to be a third monitoring order; wherein the third monitoring order is the order of arrival of the register FIS from the SATA storage device at the second end of the PIPE interface, the data start transmission FIS from the SATA host at the first end of the PIPE interface, the activation FIS from the SATA host at the first end of the PIPE interface, the data FIS from the SATA host at the first end of the PIPE interface, and the write command execution completion FIS from the SATA host at the second end of the PIPE interface.

[0088] In one example, the above method also includes: when it is detected that the register FIS from the SATA host is a DMA read operation type, determining the signal monitoring order to be a fourth monitoring order; wherein the fourth monitoring order is the order of arrival of the register FIS from the SATA storage device at the second end of the PIPE interface, the data start transmission FIS from the SATA storage device at the second end of the PIPE interface, the data FIS from the SATA storage device at the second end of the PIPE interface, and the read command execution completion FIS from the SATA host at the first end of the PIPE interface.

[0089] like Figure 1B As shown, when the inspection model in the SATA communication detection device determines that the communication process targeted by the inspection request is a data read / write process between a SATA host and a SATA storage device, it invokes the data read / write inspection model. The model first detects the interface data frame start character, then monitors the register FIS from the SATA host via the first end of the PIPE interface. Based on the read / write type information in the register FIS from the SATA host, the model determines whether the current data read / write process is a data read or write process, thereby determining the corresponding signal monitoring sequence. Then, based on this signal monitoring sequence, the model sequentially monitors whether the corresponding monitoring signals have arrived at the corresponding ports in the PIPE interface normally.

[0090] like Figure 1B As shown, the data access check model obtains parallel data signals from the PIPE interface bound to the interface connection module as input signals for the data access check model. During read and write operations between the SATA host and the SATA storage device, the data access check model parses the FIS structure data packets to extract key primitive information and FIS types used for data transmission. Simultaneously, the clock and reset signals of the PIPE interface are also transmitted to the data access check model. Based on the third or fourth monitoring sequence described above, the data access check model sequentially monitors whether the input signals arrive at the PIPE interface within the predetermined timeframe.

[0091] When the SATA communication detection device detects an interface data frame start character from a SATA host, it monitors the register FIS from the SATA host via the first end of the PIPE interface. If the register FIS from the SATA host is a write operation type, i.e., a DMA write type, a DMA write check state machine is used, which includes a third monitoring sequence, to monitor the subsequent data flow. If the register FIS from the SATA host is a read operation type, i.e., a DMA read type, a DMA read check state machine is used, which includes a fourth monitoring sequence, to monitor the subsequent data flow.

[0092] like Figure 6As shown, when it is detected that the register FIS (Host-to-Device FIS) from the SATA host is a DMA write operation type, the register FIS (Device-to-Host FIS) from the SATA storage device at the second end of the PIPE interface, the data start transmission FIS from the SATA host at the first end of the PIPE interface, the activation FIS from the SATA host at the first end of the PIPE interface, the data FIS from the SATA host at the first end of the PIPE interface, and the write command execution completion FIS from the SATA host at the second end of the PIPE interface arrive in sequence, and the respective signals are monitored in sequence to see whether they arrive at the corresponding port within a predetermined time.

[0093] like Figure 7 As shown, when it is detected that the register FIS (Host-to-Device FIS) from the SATA host is a DMA read operation type, according to the order in which the register FIS (Device-to-Host FIS) from the SATA storage device at the second end of the PIPE interface, the data start transfer FIS from the SATA storage device at the second end of the PIPE interface, the data FIS from the SATA storage device at the second end of the PIPE interface, and the read command execution completion FIS from the SATA host at the first end of the PIPE interface arrive in sequence, it is monitored in sequence whether each signal arrives at the corresponding port within a predetermined time.

[0094] In the above monitoring process, if a signal fails to reach the corresponding port within the predetermined time, the status register corresponding to the signal is set high (set to 1) to indicate that there is an error in the signal transmission process. Figure 1B The debug window of the environment end can locate the erroneous signal sending process by setting the status register high, so as to quickly locate whether the problem occurs in the SATA host or device end of the environment end.

[0095] According to an embodiment of the present application, when a SATA communication detection device determines that the communication process targeted by a check request is a data read / write process between a SATA host and a SATA storage device, it first detects the interface data frame start character, then monitors the register FIS from the SATA host via the first end of the PIPE interface. Based on the DMA read / write type information from the register FIS of the SATA host, it determines whether the current data read / write process is a data read process or a data write process, thereby determining the corresponding signal monitoring sequence. Then, based on this signal monitoring sequence, the corresponding monitoring signals are sequentially monitored to determine whether they have arrived at the corresponding ports in the PIPE interface normally. This improves detection accuracy.

[0096] It should be understood that, although the various steps in the above flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the above flowchart may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0097] like Figure 8 As shown, an embodiment of the present application further provides a SATA communication detection device, which is integrated into a PIPE interface. The first end of the PIPE interface is used to connect to a SATA host, and the second end of the PIPE interface is used to connect to a SATA storage device. SATA communication detection device, configured as: In response to a request for checking a communication process between a SATA host and a SATA storage device, determining a corresponding signal monitoring order based on the communication process; Based on the signal monitoring sequence, monitoring whether the corresponding monitoring signals from the SATA host arrive at the first end of the PIPE interface normally in sequence, and monitoring whether the corresponding monitoring signals from the SATA storage device arrive at the second end of the PIPE interface normally in sequence; Based on the monitoring result of the monitoring signal, determine whether the communication process is normal.

[0098] For specific limitations on the functions of the SATA communication detection device, please refer to the above limitations on the SATA communication detection method, which will not be repeated here.

[0099] like Figure 9 As shown, an embodiment of the present application provides a SATA hardware emulator, including a SATA host, a PIPE interface and a SATA communication detection device, wherein the SATA host is connected to the first end of the PIPE interface, the second end of the PIPE interface is used to connect to the SATA storage device, and the SATA communication detection device is integrated into the PIPE interface.

[0100] The specific limitations on the functions of the SATA hardware emulator and the SATA communication detection device can be found above and will not be repeated here.

[0101] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

[0102] The SATA communication detection method and device described in the above embodiments can be implemented by a computer chip or entity, or by a product with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0103] For the convenience of description, the above device is described in terms of functions and each unit is described separately. Of course, when implementing this application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0104] Those skilled in the art will appreciate that the embodiments of the present application can provide a SATA communication detection device and a SATA hardware emulator, as well as a SATA communication detection method, system, or computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware.

[0105] This application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0106] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0107] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in detail. Each embodiment focuses on the differences from other embodiments. Since it is basically similar to the method embodiment, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment.

[0108] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

[0109] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A SATA communication detection method, characterized in that: Applied to a SATA communication detection device, the SATA communication detection device is integrated into a PIPE interface, a first end of the PIPE interface is used to connect to a SATA host, and a second end of the PIPE interface is used to connect to a SATA storage device, the method comprising: In response to a request for checking a communication process between the SATA host and the SATA storage device, determining a corresponding signal monitoring order based on the communication process; Based on the signal monitoring sequence, monitoring whether corresponding monitoring signals from the SATA host arrive at the first end of the PIPE interface normally in sequence, and monitoring whether corresponding monitoring signals from the SATA storage device arrive at the second end of the PIPE interface normally in sequence; Based on the monitoring result of the monitoring signal, it is determined whether the communication process is normal.

2. The method according to claim 1, characterized in that The step of monitoring whether corresponding monitoring signals from the SATA host arrive at the first end of the PIPE interface normally and in sequence, and monitoring whether corresponding monitoring signals from the SATA storage device arrive at the second end of the PIPE interface normally and in sequence based on the signal monitoring sequence includes: Based on the signal transmission time of the communication process, and in accordance with the signal monitoring order, sequentially monitoring whether the corresponding monitoring signal normally arrives at the corresponding port in the PIPE interface; When the currently monitored monitoring signal arrives normally at the corresponding port in the PIPE interface, the next monitoring signal is monitored.

3. The method according to claim 2, characterized in that Also includes: When the monitoring signal currently being monitored fails to reach the corresponding port in the PIPE interface normally, the status register corresponding to the monitoring signal currently being monitored is set high to indicate that the sending process of the monitoring signal currently being monitored is abnormal; Wherein, the status register is set in the SATA communication detection device.

4. The method according to any one of claims 1 to 3, characterized in that The determining of a corresponding signal monitoring sequence based on the communication process includes: In a case where the communication process is a link initialization process between the SATA host and the SATA storage device, determining that the signal monitoring sequence is a first monitoring sequence; Among them, the first monitoring sequence is the order of arrival of the communication reset signal from the SATA host at the first end of the PIPE interface, the communication initialization signal from the SATA storage device at the second end of the PIPE interface, the first wake-up signal from the SATA host at the first end of the PIPE interface, and the second wake-up signal from the SATA storage device at the second end of the PIPE interface.

5. The method according to claim 4, characterized in that The determining, based on the monitoring result of the monitoring signal, whether the communication process is normal includes: In the case that it is monitored that the second wake-up signal from the SATA storage device arrives normally at the second end of the PIPE interface, it is determined that the link initialization process between the SATA host and the SATA storage device has been normally completed.

6. The method according to claim 5, characterized in that Also includes: When it is determined that the link initialization process between the SATA host and the SATA storage device has been completed normally, obtaining a device negotiated maximum rate between the SATA host and the SATA storage device through the second end of the PIPE interface; Based on the device negotiated maximum rate, a signal transmission time of a rate negotiation process between the SATA host and the SATA storage device is determined.

7. The method according to claim 6, characterized in that The determining of a corresponding signal monitoring sequence based on the communication process includes: In a case where the communication process is a rate negotiation process between the SATA host and the SATA storage device, determining that the signal monitoring order is a second monitoring order; Among them, the second monitoring order is the arrival order of the first byte alignment primitive from the SATA storage device at the second end of the PIPE interface, the second byte alignment primitive from the SATA host at the first end of the PIPE interface, the first synchronization primitive from the SATA storage device at the second end of the PIPE interface, and the second synchronization primitive from the SATA host at the first end of the PIPE interface.

8. The method according to claim 7, characterized in that The determining, based on the monitoring result of the monitoring signal, whether the communication process is normal includes: When it is monitored that the first synchronization primitive from the SATA storage device arrives normally at the second end of the PIPE interface and the second synchronization primitive from the SATA host arrives normally at the first end of the PIPE interface, it is determined that the rate negotiation process between the SATA host and the SATA storage device has been completed normally.

9. The method according to any one of claims 1 to 3, characterized in that The determining of a corresponding signal monitoring sequence based on the communication process includes: In a case where the communication process is a data reading and writing process between the SATA host and the SATA storage device, an interface data frame start character from the SATA host is monitored through the first end of the PIPE interface; When it is detected that the start character of the interface data frame arrives at the first end of the SATA communication detection device, monitoring the register FIS from the SATA host through the first end of the PIPE interface; The signal monitoring order is determined based on a register FIS from the SATA host.

10. The method according to claim 9, characterized in that The determining of the signal monitoring sequence based on a register FIS from the SATA host includes: In the case where it is detected that the register FIS from the SATA host is a DMA write operation type, determining the signal monitoring order to be a third monitoring order; Among them, the third monitoring order is the arrival order of the register FIS from the SATA storage device at the second end of the PIPE interface, the data start transmission FIS from the SATA host at the first end of the PIPE interface, the activation FIS from the SATA host at the first end of the PIPE interface, the data FIS from the SATA host at the first end of the PIPE interface, and the write command execution completion FIS from the SATA host at the second end of the PIPE interface.

11. The method according to claim 10, characterized in that Also includes: When it is detected that the register FIS from the SATA host is a DMA read operation type, determining the signal monitoring order to be a fourth monitoring order; Among them, the fourth monitoring order is the arrival order of the register FIS from the SATA storage device at the second end of the PIPE interface, the data start transmission FIS from the SATA storage device at the second end of the PIPE interface, the data FIS from the SATA storage device at the second end of the PIPE interface, and the read command execution completion FIS from the SATA host at the first end of the PIPE interface.

12. A SATA communication detection device, characterized in that: The SATA communication detection device is integrated into a PIPE interface, a first end of the PIPE interface is used to connect to a SATA host, and a second end of the PIPE interface is used to connect to a SATA storage device; The SATA communication detection device is configured to: In response to a request for checking a communication process between the SATA host and the SATA storage device, determining a corresponding signal monitoring order based on the communication process; Based on the signal monitoring sequence, monitoring whether corresponding monitoring signals from the SATA host arrive at the first end of the PIPE interface normally in sequence, and monitoring whether corresponding monitoring signals from the SATA storage device arrive at the second end of the PIPE interface normally in sequence; Based on the monitoring result of the monitoring signal, it is determined whether the communication process is normal.

13. A SATA hardware emulator, characterized in that: The device comprises a SATA host, a PIPE interface and the SATA communication detection device according to claim 12, wherein the SATA host is connected to a first end of the PIPE interface, a second end of the PIPE interface is used to connect to a SATA storage device, and the SATA communication detection device is integrated into the PIPE interface.

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