Bus system-level verification method and device based on Emulator

Abstract

The invention relates to an Emulator-based bus system level verification method and device, and the method comprises the steps: generating an Emulator hardware module; constructing a use case library, and generating a plurality of test cases with uniform formats and different test requirements based on the use case library; analyzing the test case by using a case pipeline to form a data stream, sending the data stream to the Emulator hardware module for verification, and recording a verification process and a verification result; and automatically analyzing and evaluating the verification process and the verification result by using a use case pipeline. According to the invention, the verification speed can be improved, and efficient, accurate and comprehensive system-level verification can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of chip bus verification, and in particular to an emulator-based bus system-level verification method and device. Background Art

[0002] With the rapid development of integrated circuits, for a large chip consisting of a multi-core SoC, multiple high-speed peripherals, and a series of relatively complex communication algorithm modules, the bus system is a key part that connects the various components in the system. Its performance and stability are crucial to the operation of the entire system. Traditional bus verification methods usually rely on BT (Block Test) level verification of EDA (Electronic Design Automation) and software-level verification of the chip's real application scenarios. EDA's BT-level verification is limited by the performance of a single server, the simulation speed is slow, and BT-level verification is difficult to cover the chip's system-level verification points; software-level verification of the chip's real application scenarios is limited by its difficulty in covering all possible operating scenarios and abnormal conditions. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a bus system-level verification method and device based on an emulator, which can improve the verification speed while achieving efficient, accurate and comprehensive system-level verification.

[0004] The present invention solves the technical problem by providing a bus system-level verification method based on an emulator, comprising the following steps:

[0005] Generate an Emulator hardware module, which includes a bus system to be tested, a master component replaced with a virtual IP, and a real Slave module component;

[0006] Build a use case library and generate multiple test cases with a unified format and different test requirements based on the use case library;

[0007] Utilize the use case pipeline to parse the test case to form a data stream, send the data stream to the Emulator hardware module for verification, and record the verification process and verification results;

[0008] The verification process and verification results are automatically analyzed and evaluated using a use case pipeline.

[0009] The Emulator hardware module is generated by using a signal connection tool to replace each Master port module on the bus system to be tested with a virtual IP that has the functions and performance of simulating a real Master device, and the bus protocol of the bus system to be tested covers the AMBA bus AXI4 and AHB3 protocols, and communicates with the real Slave module components according to the bus protocol and chip system requirements.

[0010] The signal connection tool is a fully automated tool that can disconnect the Master port signal on the bus system under test and connect the Master signal on the bus system under test with the signal of the transaction processor of the Emulator hardware module.

[0011] The multiple test cases with different test requirements include: initialization chip configuration case, single business traffic and bus performance test case, and multi-business concurrent traffic and bus performance test case.

[0012] The use case pipeline is used to parse the test case to form a data stream, and the data stream is sent to the emulator hardware module for verification. Specifically, based on the software and hardware interface API function provided by the emulator manufacturer, a software layer pipeline is constructed to connect the test case and the transaction processor of the emulator hardware module. The software layer pipeline is used to parse and transform the file information of the test case, and connect to the software and hardware interface API function to form a data stream to impact the bus system to be tested of the emulator hardware module.

[0013] The use case pipeline is used to automatically analyze and evaluate the verification process and verification results, specifically: the verification process and verification results are presented in the form of files and icons, and the verification results are automatically analyzed and evaluated.

[0014] The technical solution adopted by the present invention to solve the technical problem is to provide a bus system-level verification device based on an emulator, comprising:

[0015] A generation module is used to generate an emulator hardware module, wherein the emulator hardware module includes a bus system to be tested, a master component replaced with a virtual IP, and a real slave module component;

[0016] A construction module is used to build a use case library and generate multiple test cases with a unified format and different test requirements based on the use case library;

[0017] A test module, configured to parse the test case using a use case pipeline to form a data stream, send the data stream to the emulator hardware module for verification, and record the verification process and results;

[0018] The verification module is used to automatically analyze and evaluate the verification process and verification results using the use case pipeline.

[0019] The technical solution adopted by the present invention to solve its technical problem is: to provide an electronic device, including a memory, a processor and a computer program stored in the memory and capable of running on the processor, and when the processor executes the computer program, the steps of the above-mentioned emulator-based bus system-level verification method are implemented.

[0020] The technical solution adopted by the present invention to solve its technical problem is: providing a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned emulator-based bus system-level verification method are implemented.

[0021] Beneficial effects

[0022] Due to the adoption of the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention adopts the Emulator hardware platform and replaces the Master node on the bus with VIP, thereby improving the verification speed and reducing the verification time cost, while retaining the behavioral characteristics of the real Slave module, thereby improving the accuracy and authenticity of the verification. The present invention can cover various possible operating scenarios and abnormal scenarios of the bus system by generating diverse verification test cases, ensuring the comprehensiveness of the verification. The VIP module and verification test cases support flexible configuration and can adapt to different verification scenarios and testing requirements. The present invention supports bus IPs of different manufacturers and bus systems of different projects, has high portability and is easy to transplant. The VIP module and verification test cases are optimized and improved according to the verification results, thereby improving the overall performance and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flowchart of a bus system-level verification method based on an emulator according to a first embodiment of the present invention. DETAILED DESCRIPTION

[0024] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0025] The first embodiment of the present invention relates to a bus system level verification method based on an emulator, such as Figure 1 As shown, the following steps are included:

[0026] Step 1: Generate an Emulator hardware module, which includes a bus system to be tested, a master component replaced with a virtual IP, and a real Slave module component.

[0027] This step specifically involves using a signal connection tool to replace each Master port module on the bus system under test with a virtual IP that closely simulates the functionality and performance of a real Master device. This tool also ensures that the bus protocol of the bus system under test covers both AMBA AXI4 and AHB3 protocols, enabling communication with real Slave module components in accordance with these bus protocols and chip system requirements. The signal connection tool is a fully automated tool capable of precisely disconnecting Master port signals on the bus system under test and connecting Master signals on the bus system under test to signals from the transaction processor of the Emulator hardware module.

[0028] Step 2: Build a use case library and generate multiple test cases with a unified format and different test requirements based on the library. The multiple test cases with different test requirements in this step include: initial chip configuration test cases, single-service traffic and bus performance test cases, and multi-service concurrent traffic and bus performance test cases. These cover a variety of possible normal and abnormal scenarios, thus fully verifying the stability and reliability of the bus system.

[0029] Step 3: Use the use case pipeline to parse the test case to form a data stream, send the data stream to the emulator hardware module for verification, and record the verification process and results. This step specifically involves building a software-layer pipeline connecting the test case and the emulator hardware module's transaction processor based on the software and hardware interface API functions provided by the emulator manufacturer. The software-layer pipeline is used to parse and transform the test case's file information and connect to the software and hardware interface API functions to form a data stream that impacts the emulator hardware module's bus system under test.

[0030] Step 4: Automatically analyze and evaluate the verification process and verification results using the use case pipeline. This step specifically refers to presenting the verification process and verification results in the form of files and icons, and automatically analyzing and evaluating the verification results.

[0031] It is not difficult to find that the present invention improves the verification speed and reduces the verification time cost by adopting the Emulator hardware platform and replacing the Master node on the bus with VIP, while retaining the behavioral characteristics of the real Slave module and improving the accuracy and authenticity of the verification. The present invention can cover various possible operating scenarios and abnormal scenarios of the bus system by generating diverse verification test cases, ensuring the comprehensiveness of the verification. The VIP module and verification test cases support flexible configuration and can adapt to different verification scenarios and testing requirements. The present invention supports bus IPs of different manufacturers and bus systems of different projects. It has high portability and is easy to transplant. The VIP module and verification test cases are optimized and improved according to the verification results to improve the overall performance and stability of the system.

[0032] A second embodiment of the present invention relates to an emulator-based bus system-level verification device, comprising:

[0033] A generation module is used to generate an emulator hardware module, wherein the emulator hardware module includes a bus system to be tested, a master component replaced with a virtual IP, and a real slave module component;

[0034] A construction module is used to build a use case library and generate multiple test cases with a unified format and different test requirements based on the use case library;

[0035] A test module, configured to parse the test case using a use case pipeline to form a data stream, send the data stream to the emulator hardware module for verification, and record the verification process and results;

[0036] The verification module is used to automatically analyze and evaluate the verification process and verification results using the use case pipeline.

[0037] The generation module uses a signal connection tool to replace each Master port module on the bus system to be tested with a virtual IP that has the functions and performance of simulating a real Master device, and makes the bus protocol of the bus system to be tested cover the AMBA bus AXI4 and AHB3 protocols, and communicates with the real Slave module components according to the bus protocol and chip system requirements.

[0038] The signal connection tool is a fully automated tool that can disconnect the Master port signal on the bus system under test and connect the Master signal on the bus system under test with the signal of the transaction processor of the Emulator hardware module.

[0039] The multiple test cases with different test requirements include: initialization chip configuration case, single business traffic and bus performance test case, and multi-business concurrent traffic and bus performance test case.

[0040] The test module builds a software layer pipeline connecting the test case and the transaction processor of the emulator hardware module based on the software and hardware interface API functions provided by the emulator manufacturer. The software layer pipeline is used to parse and transform the file information of the test case, and connect to the software and hardware interface API functions to form a data flow to impact the bus system under test of the emulator hardware module.

[0041] The verification module presents the verification process and verification results in the form of files and icons, and automatically analyzes and evaluates the verification results.

[0042] A third embodiment of the present invention relates to an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the emulator-based bus system-level verification method of the first embodiment are implemented.

[0043] A fourth embodiment of the present invention relates to a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements the steps of the emulator-based bus system-level verification method of the first embodiment.

[0044] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0045] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0046] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction method, which is implemented in the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0047] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0048] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A bus system-level verification method based on an emulator, characterized in that: The following steps are involved: Generate an Emulator hardware module, which includes a bus system to be tested, a master component replaced with a virtual IP, and a real Slave module component; Build a use case library and generate multiple test cases with a unified format and different test requirements based on the use case library; Utilize the use case pipeline to parse the test case to form a data stream, send the data stream to the Emulator hardware module for verification, and record the verification process and verification results; The verification process and verification results are automatically analyzed and evaluated using a use case pipeline.

2. The bus system-level verification method based on emulator according to claim 1, characterized in that: The Emulator hardware module is generated by using a signal connection tool to replace each Master port module on the bus system to be tested with a virtual IP that has the functions and performance of simulating a real Master device, and the bus protocol of the bus system to be tested covers the AMBA bus AXI4 and AHB3 protocols, and communicates with the real Slave module components according to the bus protocol and chip system requirements.

3. The bus system-level verification method based on emulator according to claim 2, characterized in that: The signal connection tool is a fully automated tool that can disconnect the Master port signal on the bus system under test and connect the Master signal on the bus system under test with the signal of the transaction processor of the Emulator hardware module.

4. The bus system-level verification method based on emulator according to claim 1, characterized in that: The multiple test cases with different test requirements include: initialization chip configuration case, single business traffic and bus performance test case, and multi-business concurrent traffic and bus performance test case.

5. The bus system-level verification method based on emulator according to claim 1, characterized in that: The use case pipeline is used to parse the test case to form a data stream, and the data stream is sent to the emulator hardware module for verification. Specifically, based on the software and hardware interface API function provided by the emulator manufacturer, a software layer pipeline is constructed to connect the test case and the transaction processor of the emulator hardware module. The software layer pipeline is used to parse and transform the file information of the test case, and connect to the software and hardware interface API function to form a data stream to impact the bus system to be tested of the emulator hardware module.

6. The bus system-level verification method based on emulator according to claim 1, characterized in that: The use case pipeline is used to automatically analyze and evaluate the verification process and verification results, specifically: the verification process and verification results are presented in the form of files and icons, and the verification results are automatically analyzed and evaluated.

7. A bus system-level verification device based on an emulator, characterized in that: include: A generation module is used to generate an emulator hardware module, wherein the emulator hardware module includes a bus system to be tested, a master component replaced with a virtual IP, and a real slave module component; A construction module is used to build a use case library and generate multiple test cases with a unified format and different test requirements based on the use case library; A test module, configured to parse the test case using a use case pipeline to form a data stream, send the data stream to the emulator hardware module for verification, and record the verification process and results; The verification module is used to automatically analyze and evaluate the verification process and verification results using the use case pipeline.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the emulator-based bus system-level verification method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the emulator-based bus system-level verification method according to any one of claims 1 to 6 are implemented.

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