Cache coherence directory entry merging method and device, chip, component, electronic equipment and storage medium

Abstract

The invention provides a cache coherence directory entry merging method and device, a chip, a component, electronic equipment and a storage medium, and the method comprises the steps: detecting that a cache coherence directory is modified, and determining at least two entries meeting a first target condition, the first target condition being that at least two destination addresses are continuous and adjacent, the state information of the same computing nodes in the at least two entries is the same, and the first identifiers of the entries represent that the entries are unmerged entries; and merging the at least two entries to obtain a first target entry, the first identifier of the first target entry representing that the first target entry is a merged entry, and the second identifier of the first target entry representing the number of the merged entries of the first target entry.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a cache consistency directory entry merging method, device, chip, component, electronic device and storage medium. Background Art

[0002] Cache consistency is a crucial technology in multi-core processors and multi-way server systems. Its main goal is to ensure that multiple processor cores and multiple processors in a shared memory system maintain consistent access to cached data. Taking a multi-core processor as an example, in a multi-core processor, each processor core usually has its own cache to reduce the latency of accessing main memory. However, when multiple processor cores access shared data at the same time, if there is no effective cache consistency mechanism, data inconsistency may occur. To solve this problem, cache consistency protocols such as the MESI protocol (a cache consistency protocol) are usually used. These protocols control the state of cache lines to ensure that each core always sees the latest copy of data when reading and writing data.

[0003] The module that handles system cache consistency transactions is usually an HN (Home Node) or HA (Home Agent) module. In order to improve the processing speed of cache consistency transactions, the HN or HA module is generally configured with a cache consistency directory to record the shared status of the corresponding memory address in each computing node. As the system memory capacity continues to increase, the consistency directory has become difficult to record the shared status of the entire system memory address in all computing nodes due to hardware overhead limitations. Once a cache consistency request is initiated for an unrecorded memory address, the HN or HA module can only send a snoop transaction to other computing nodes to obtain the corresponding cache line status or dirty data in each computing node. This situation will reduce the efficiency of cache consistency maintenance, thereby affecting the parallel computing efficiency of the entire system. Therefore, how to enable the directory to record more cache status information in the computing nodes corresponding to memory addresses with limited hardware overhead, and how to reduce the hardware overhead of the directory without reducing system performance, has become the current research focus in the field of cache consistency maintenance technology. Summary of the Invention

[0004] The present application provides a cache consistency directory entry merging method, device, chip, component, electronic device and storage medium.

[0005] In one aspect, an embodiment of the present application provides a method for merging cache coherence directory entries, the method comprising:

[0006] detecting that a cache coherence directory has been modified, determining at least two entries that meet a first target condition, wherein the first target condition is that addresses of the at least two entries are continuous and adjacent, state information of the same computing node in the at least two entries is the same, and a first identifier of the entry indicates that the entry is an unmerged entry;

[0007] The at least two entries are merged to obtain a first target entry, wherein the first identifier of the first target entry indicates that the first target entry is a merged entry, and the second identifier of the first target entry indicates the number of entries merged by the first target entry.

[0008] The detecting that the cache consistency directory is modified includes:

[0009] detecting that an entry in the cache coherence directory is modified, determining that the cache coherence directory is modified;

[0010] Alternatively, if a new entry is detected in the cache coherence directory, it is determined that the cache coherence directory is modified.

[0011] The step of determining at least two items that meet the first target condition includes:

[0012] Determining a candidate entry, where the candidate entry is the modified or newly added entry;

[0013] Determining whether there is at least one entry that satisfies the first target condition as the candidate entry;

[0014] If so, the candidate entry and the at least one entry are determined as the at least two entries that meet the first target condition.

[0015] The method further comprises:

[0016] In response to a query request for a target address, matching an entry in the cache coherence directory with the target address;

[0017] If an entry matching the target address exists, entry information of the entry is returned, where the entry information at least includes status information of the computing node.

[0018] The step of matching the entry in the cache coherence directory with the target address includes:

[0019] Determine whether there is an entry in the cache coherence directory whose address is consistent with the target address or whose address and a second identifier satisfy a second target condition, where the second target condition is that the target address falls within an address range indicated by the address and the second identifier;

[0020] If so, it is determined that there is an entry matching the target address.

[0021] The method further comprises:

[0022] Determining that the number of entries satisfying the first target condition is equal to a first preset number, and merging the first preset number of entries to obtain second target entries;

[0023] The second target entry is stored in a second storage area, where the second storage area indicates that the second target entry is a merged entry and the number of merged entries is a first preset number.

[0024] The method further comprises:

[0025] detecting that a second target entry in the second storage area is modified, and determining at least two second target entries that meet a first target condition;

[0026] If the number of second target items that meet the first target condition is equal to a second preset number, merging the second preset number of second target items to obtain a third target item;

[0027] The third target entry is stored in a third storage area, where the third storage area indicates that the third target entry is a merged entry and the number of merged entries is a first preset number multiplied by a second preset number.

[0028] The method further comprises:

[0029] In response to a query request for a target address, determining whether there is a second target entry or a third target entry whose address satisfies a third target condition, wherein the third target condition is that the target address falls within an address range indicated by the address and the first preset number or the address, the first preset data, and the second preset number;

[0030] If there is a second target entry or the third target entry matching the target address, entry information of the second target entry or the third target entry is returned, where the entry information includes at least status information of the computing node.

[0031] The method further comprises:

[0032] detecting that a new entry is added to the cache coherence directory and that the cache coherence directory is full, traversing all entries in the cache coherence directory;

[0033] Determine the number of computing nodes whose status information in the current entry indicates a shared state;

[0034] After the traversal is completed, the entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added entry is stored in the cache consistency directory.

[0035] The method further comprises:

[0036] detecting that a new second target entry is added to the second storage area and that the second storage area is full, traversing all second target entries in the second storage area;

[0037] Determine the number of computing nodes whose status information in the current second target entry indicates a shared state;

[0038] After the traversal is completed, the second target entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added second target entry is stored in the second storage area;

[0039] A first preset number of entries is determined based on the deleted second target entry, and the first preset number of entries is stored in the cache coherence directory.

[0040] The method further comprises:

[0041] detecting that a third target entry is newly added to the third storage area and that the third storage area is full, traversing all third target entries in the third storage area;

[0042] Determine the number of computing nodes whose status information in the current third target entry indicates a shared state;

[0043] After the traversal is completed, the third target entry having the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added third target entry is stored in the third storage area;

[0044] A second preset number of second target entries is determined based on the deleted third target entries, and the second preset number of second target entries is stored in the second storage area.

[0045] Wherein, when the state information is merged state information, if any one of the two different state information included in the merged state information indicates a shared state, the merged state information is state information indicating a shared state.

[0046] Another aspect of the present application provides a method for merging cache coherence directory entries, the method comprising:

[0047] detecting that the cache coherence directory is modified, and determining two entries that meet a fourth target condition, wherein the fourth target condition is that addresses of the two entries differ by only one bit, and a first identifier of the entry indicates that the entry is an unmerged entry;

[0048] The two entries are merged to obtain a fifth target entry, wherein the first identifier of the fifth target entry indicates that the fifth target entry is a merged entry, the third identifier of the fifth target entry indicates the number of bits with different addresses of the two entries, and the status information of the computing node of the fifth target entry is obtained by merging the status information of the computing nodes of the two entries.

[0049] The state information of the computing node of the fifth target entry is obtained by merging the state information of the computing nodes of the two entries, including:

[0050] If the state information of the computing nodes in the two entries is the same, determining the state information as the state information of the computing node in the fifth target entry;

[0051] If the state information of the computing nodes in the two entries is different, the two different state information are merged into merged state information, and the merged state information is determined as the state information of the computing node in the fifth target entry.

[0052] Another aspect of the present application provides a cache coherence directory entry merging device, the device comprising:

[0053] a computing module configured to detect that a cache coherence directory has been modified and determine at least two entries that meet a first target condition, wherein the first target condition is that addresses of the at least two entries are continuous and adjacent, state information of the same computing node in the at least two entries is the same, and a first identifier of the entry indicates that the entry is an unmerged entry;

[0054] The processing module is configured to merge the at least two entries to obtain a first target entry, wherein the first identifier of the first target entry indicates that the first target entry is a merged entry, and the second identifier of the first target entry indicates the number of entries merged by the first target entry.

[0055] The processing module is further configured to determine that the number of entries satisfying the first target condition is equal to a first preset number, and merge the first preset number of entries to obtain a second target entry;

[0056] The processing module is further configured to store the second target entry in a second storage area, where the second storage area indicates that the second target entry is a merged entry and the number of merged entries is a first preset number.

[0057] Another aspect of an embodiment of the present application provides a chip, the chip including a processor, the processor being capable of executing the cache consistency directory entry merging method.

[0058] Another aspect of an embodiment of the present application provides a component, which includes a chip. The chip includes a processor, and the processor is capable of executing the cache consistency directory entry merging method.

[0059] Another aspect of an embodiment of the present application provides an electronic device, which includes a component, wherein the component includes a chip, and the chip includes a processor, and the processor is capable of executing the cache consistency directory entry merging method.

[0060] Another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the cache consistency directory entry merging method.

[0061] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description.

[0062] The embodiments of the present application have the following beneficial effects: after detecting that the cache consistency directory has been modified, when the first target condition is met (the addresses are continuous and adjacent and the status information of the same computing node is consistent), multiple independent entries are merged into a single first target entry, and the merge status and the number of merges are recorded through the identification field. This method compresses multiple entries that originally need to be stored independently into a single merged entry while ensuring the correctness of the consistency protocol, directly reducing the occupied scale of the number of entries in the directory. For application scenarios with continuous address access modes or batch operations of computing nodes, the storage capacity requirements of the directory can be significantly reduced, saving on-chip storage resources, and is particularly suitable for scenarios where directory storage overhead is sensitive in large-scale multi-core systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an illustrative and non-limiting manner, in which:

[0064] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0065] Figure 1 A flowchart of a cache coherence directory entry merging method according to an embodiment of the present application is shown;

[0066] Figure 2A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0067] Figure 3 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0068] Figure 4 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0069] Figure 5 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0070] Figure 6 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0071] Figure 7 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0072] Figure 8 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0073] Figure 9 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0074] Figure 10 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0075] Figure 11 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0076] Figure 12 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0077] Figure 13 A flowchart of a cache coherence directory entry merging method according to another embodiment of the present application is shown;

[0078] Figure 14 A schematic structural diagram of a cache consistency directory entry merging device according to an embodiment of the present application is shown;

[0079] Figure 15 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0080] In order to make the purpose, features, and advantages of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0081] In order to enable the directory to record more cache status information in the computing node corresponding to the memory address under limited hardware overhead, and to reduce the hardware overhead of the directory without reducing system performance, an embodiment of the present application provides a cache consistency directory entry merging method, such as Figure 1 As shown, the method includes:

[0082] Step 101: Detect that the cache consistency directory has been modified, and determine at least two entries that meet a first target condition, wherein the first target condition is that the addresses of the at least two entries are continuous and adjacent, and the status information of the same computing nodes in the at least two entries are the same, and the first identifier of the entry indicates that the entry is an unmerged entry.

[0083] In this embodiment, the cache coherence directory can be used to record cache data status information in a multi-core processor or multi-way server system. When the cache coherence directory is used to record the status of a multi-core processor, the computing node is the processor core. When the cache coherence directory is used to record the status of a multi-way server system, the computing node is the server.

[0084] For example, as shown in Table 1, Table 1 shows the directory entries after the cache consistency directory is modified. Among them, the valid bit indicates whether the entry is valid. If the valid bit is 0, it indicates that the entry does not track any address (or has been released). If the valid bit is 1, it indicates that the entry is tracking the consistency state of a certain address. The first identifier indicates whether the entry is a merged entry. If the first identifier is 0, it indicates that the entry is an unmerged entry. If the first identifier is 1, it indicates that the entry is a merged entry. The second identifier indicates the number of entry merges and is stored in binary. The address indicates the memory block address tracked by the entry. Compute node 1 and subsequent compute nodes are all status information of the corresponding compute nodes. The status information includes U (Unique), SD (Shared Dirty), SC (Shared Clean), and I (Invalid). As shown in Table 1, the addresses of the first entry, the second entry, the third entry, and the fifth entry in Table 1 are continuous and adjacent, and the status information of the same compute nodes of these four entries is the same, then these four entries are determined to be entries that meet the first target condition.

[0085] Valid bits First logo Second identification address Compute node 1 Compute Node 2 ... Compute node 4 1 0 000 0000 I U ... I 1 0 000 0001 I U ... I 1 0 000 0010 I U ... I 1 0 000 1111 SD SC ... I 1 0 000 0011 I U ... I

[0086] Table 1

[0087] Step 102: Merge the at least two entries to obtain a first target entry, wherein a first identifier of the first target entry indicates that the first target entry is a merged entry, and a second identifier of the first target entry indicates the number of entries merged by the first target entry.

[0088] Continuing with the above example, after determining the entries that meet the first target condition, these four entries are merged to obtain the first target entry. The merged cache consistency directory is shown in Table 2, and the second entry, the third entry, and the fifth entry are merged into the first entry. The first identifier of the first entry is modified to 1, indicating that the first entry is a merged entry, and the second identifier of the first entry is modified to 001, indicating that the first entry merges entries whose addresses are 001+1 bits lower than the addresses of the first entry (entries with addresses 00XX, i.e., entries with addresses 0001, 0010, and 0011). The valid bits of the second entry, the third entry, and the fifth entry are modified to 0, indicating that these three entries have been merged and can be overwritten by other newly added entries. In this embodiment, the second identifier uses the number of bits to represent the number of entries merged, so the number of merges is related to the number of bits. For example, when the second identifier is 001, the number of bits is 2, indicating that 4 entries (including the first target entry) have been merged. For another example, when the second identifier is 010, the number of bits is 3, indicating that 8 entries are merged. The above method limits the number of merges, and the first target entry needs to be the entry with the highest address among the multiple entries that meet the first target condition. In other embodiments, the second identifier can also be represented by a direct number. For example, when the second identifier is 001, it indicates that 2 entries (including the first target entry) are merged. For another example, when the second identifier is 010, it indicates that 3 entries are merged. The above method does not limit the number of merges, nor does it limit the conditions of the first target entry, and is more flexible.

[0089] Valid bits First logo Second identification address Compute node 1 Compute Node 2 ... Compute node 4 1 1 001 0000 I U ... I 0 0001 I U ... I 0 0010 I U ... I 1 0 000 1111 SD SC ... I 0 0011 I U ... I

[0090] Table 2

[0091] In the above scheme, after detecting that the cache consistency directory has been modified, when the first target condition is met (the addresses are continuous and adjacent and the status information of the same computing node is consistent), multiple independent entries are merged into a single first target entry, and the merge status and the number of merges are recorded through the identification field. This method compresses multiple entries that originally need to be stored independently into a single merged entry while ensuring the correctness of the consistency protocol, directly reducing the occupied scale of the number of entries in the directory. For application scenarios with continuous address access patterns or batch operations of computing nodes, it can significantly reduce the storage capacity requirements of the directory and save on-chip storage resources. It is especially suitable for scenarios in large-scale multi-core systems that are sensitive to directory storage overhead.

[0092] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 2 As shown, the detection that the cache consistency directory is modified includes:

[0093] Step 201: If it is detected that an entry in the cache coherence directory has been modified, it is determined that the cache coherence directory has been modified.

[0094] That is, if the status information of an entry in the cache coherence directory changes and a modification occurs, it is determined that the cache coherence directory is modified.

[0095] Or, in step 202, a new entry is detected in the cache coherence directory, and then it is determined that the cache coherence directory is modified.

[0096] When an address that has not been recorded in the cache consistency directory is accessed or otherwise operated upon, a corresponding entry is added to the cache consistency directory based on the status information of each computing node regarding the address, and the cache consistency directory is determined to be modified.

[0097] In the above solution, by real-time detection of entry modifications (such as status information updates) or entry additions in the cache consistency directory, dynamic changes in the directory can be accurately determined. This active monitoring mechanism can instantly capture directory status updates, ensuring real-time response to directory modifications, thereby providing accurate triggering for subsequent consistency operations (such as merges, replacements, or status information synchronization). By strengthening the perception granularity of directory modification events, the system can more efficiently maintain the correctness of the consistency protocol, avoid redundant communications or status information conflicts caused by delayed detection, and significantly improve the timeliness and reliability of directory management, especially in high-concurrency scenarios.

[0098] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 3 As shown, the determining of at least two items that meet the first target condition includes:

[0099] Step 301: Determine candidate entries, where the candidate entries are the modified or newly added entries.

[0100] For example, as shown in Table 3, among the four entries shown in Table 3, there are no at least two entries that meet the first target condition. When it is detected that the cache coherence directory has been modified, the modified cache coherence directory is shown in Table 4, where the second entry is modified. Therefore, the second entry is determined as a candidate entry.

[0101]

[0102]

[0103] Table 3

[0104] Valid bits First logo Second identification address Compute node 1 Compute Node 2 ... Compute node 4 1 0 000 0000 I U ... I 1 0 000 0001 I U ... I 1 0 000 0010 I U ... I 1 0 000 1111 SD SC ... I

[0105] Table 4

[0106] Step 302: Determine whether there is at least one entry that satisfies the first target condition as the candidate entry.

[0107] Step 303: If so, determine the candidate entry and the at least one entry as the at least two entries that meet the first target condition.

[0108] Continuing with the above example, after determining a candidate entry, the candidate entry (i.e., the second entry in Table 4) is compared with the status information of the computational nodes adjacent to it. The candidate entry in Table 4 has an address of 0001. The computational node status information of the candidate entry is compared with the entry with address 0000 (the first entry in Table 4). If the status information of all the identical computational nodes is the same, the entry with address 0000 is determined to be the entry that meets the first target condition with the candidate entry. If there are adjacent entries with higher addresses, the comparison continues. If not, the comparison is performed with adjacent entries with lower addresses. The computational node status information of the candidate entry is compared with the entry with address 0010 (the third entry in Table 4). If the status information of all the identical computational nodes is the same, the entry with address 0010 is determined to be the entry that meets the first target condition with the candidate entry. If there are adjacent entries with lower addresses, the comparison continues. If not, the comparison is stopped. After the comparison is completed, it is determined that there are two entries that meet the first target condition with the candidate entry. Therefore, the candidate entry and these two entries are determined to meet the first target condition.

[0109] In the above scheme, by marking the modified or newly added entries in the cache consistency directory as candidate entries, and dynamically filtering the unmerged entries that are consecutively adjacent to the candidate entries and have consistent status information, multiple entries that meet the merge conditions are quickly matched. Through the directional matching mechanism of candidate entries (i.e. matching from the address to the high and low bits), redundant calculations of the entire directory traversal are avoided, and the time for determining the merge conditions is significantly shortened. At the same time, it ensures that the merge operation is only performed on locally associated entries, thereby improving the accuracy and efficiency of entry merging. While ensuring the effectiveness of entry merging, this mechanism further optimizes the entry merging process, enabling it to utilize storage resources with lower overhead, and is particularly suitable for dynamic scenarios where directories are frequently updated.

[0110] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 4 As shown, the method further includes:

[0111] Step 401: In response to a query request for a target address, matching entries in the cache coherence directory with the target address.

[0112] For example, when a query request is received, and the query request includes a target address 0010, the address 0010 is matched with the addresses of each entry in the cache coherence directory.

[0113] Step 402: If there is an entry matching the target address, then the entry information of the entry is returned, where the entry information at least includes status information of the computing node.

[0114] Continuing with the above example, address 0010 is matched with the addresses of the entries in the cache coherence directory shown in Table 3. If the second entry in the cache coherence directory is matched, the status information of the entry is returned to the requester.

[0115] In this solution, a query request for a target address is received, the target address is quickly matched against entries in the cache coherence directory, and if a matching entry exists, its status information is returned. This allows efficient response to queries in the coherence protocol, further ensuring the real-time and accuracy of cache coherence management.

[0116] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 5 As shown, matching the entry in the cache coherence directory with the target address includes:

[0117] Step 501: Determine whether there is an entry in the cache coherence directory whose address is consistent with the target address or whose address and second identifier meet a second target condition, where the second target condition is that the target address falls within the address range indicated by the address and the second identifier.

[0118] Step 502: If so, determine whether there is an entry matching the target address.

[0119] In this embodiment, whether there is an entry matching the target address in the cache coherence directory is determined in two ways:

[0120] The first one is to determine whether there is an entry in the cache coherence directory with an address that is consistent with the target address.

[0121] For example, when a query request is received, and the query request includes a target address 0010, the address 0010 is matched with the addresses of each entry in the cache consistency directory shown in Table 3. The address of the second entry in the cache consistency directory in Table 3 is also 0010, which is consistent with the target address. It is determined that there is an entry that matches the target address, and the status information of the entry is returned to the requester.

[0122] The second method is to determine whether there is an entry in the cache coherence directory whose address and the address range indicated by the second identifier include the target address.

[0123] For example, when a query request is received, and the query request includes the target address 0010, the address 0010 is matched with the addresses of each entry in the cache consistency directory as shown in Table 2. The address of the first entry in the cache consistency directory in Table 2 is 0000. Based on the first identifier of the entry, it can be known that the entry is a merged entry. Based on the second identifier of the entry, it can be known that the entry merges entries with addresses 0001, 0010 and 0011. The address range included in the entry is 0000, 0001, 0010 and 0011, including the target address 0010. It is determined that there is an entry that matches the target address, and the status information of the entry is returned to the requester.

[0124] In this solution, two matching methods are used to ensure that even after the directory entries are merged, the status information of the compute nodes associated with the target address can still be accurately located, avoiding query delays or information loss that may be caused by the merge operation. By optimizing the matching and feedback process, the system maintains the storage resource savings of merging while further ensuring the real-time and accurate data consistency management, providing reliable low-latency support for multi-core collaborative computing.

[0125] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 6 As shown, the method further includes:

[0126] Step 601: Determine whether the number of entries that meet a first target condition is equal to a first preset number, and merge the first preset number of entries to obtain a second target entry.

[0127] Step 602: Store the second target entry in a second storage area, where the second storage area indicates that the second target entry is a merged entry and the number of merged entries is a first preset number.

[0128] In this embodiment, the first preset number can be any pre-set value. When the number of entries that meet the first target condition is equal to the first preset number, these entries are merged, and the merged second target entries are stored in the second storage area. It should be noted that the second storage area also belongs to the cache consistency directory. The second storage area is a storage area set in the cache consistency directory for storing secondary directories. The second target entries stored in the second storage area are merged entries by default, and the merged number is the first preset number.

[0129] For example, the first preset number is set to four. There are only two entries (the third entry and the fifth entry) that meet the first target condition in the cache consistency directory shown in Table 5, which does not reach the first preset number and therefore cannot be merged. However, when the cache consistency directory shown in Table 5 is modified, the modified cache consistency directory is shown in Table 6. There are four entries in Table 6 that meet the first target condition, which is the same as the first preset number. These four entries are merged to obtain the second target entry, and the second target entry is stored in the second storage area. The merged cache consistency directory is shown in Table 7. The valid bits of the four merged entries are all changed to 0, and a second target entry is added to the second storage area. The second target entries stored in the second storage area are merged entries by default, and the merge quantity is 4. The addresses of the merged entries are calculated from the address of the second target entry to the lower bits.

[0130] Valid bits address Compute node 1 Compute Node 2 ... Compute node 4 1 0000 I U ... I 1 0001 I I ... I 1 0010 I U ... I 1 1111 SD SC ... I 1 0011 I U ... I

[0131] Table 5

[0132]

[0133]

[0134] Table 6

[0135]

[0136] Table 7

[0137] In the above scheme, by presetting a first preset number for merging entries, when the number of entries that meet the first target condition reaches the first preset number, they are merged into the second target entry and stored in the second storage area. This storage area implicitly marks the merge attribute and the merge quantity through physical division, without the need to additionally store the first identifier (merge attribute) and the second identifier (merge quantity), and directly uses the storage structure itself to transmit the merge information. On the basis of reducing storage occupancy by merging entries, the redundant overhead of the identification field is further eliminated, making the directory storage space utilization more compact. It is especially suitable for scenarios where the scale of entry merging is fixed or predictable, and achieves higher-density storage compression through hierarchical storage optimization.

[0138] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 7 As shown, the method further includes:

[0139] Step 701: Detect that a second target entry in the second storage area is modified, and determine at least two second target entries that meet a first target condition.

[0140] Step 702: If the number of second target items that meet the first target condition is equal to a second preset number, merge the second preset number of second target items to obtain a third target item.

[0141] Step 703: Store the third target entry in a third storage area, where the third storage area indicates that the third target entry is a merged entry and the number of merged entries is the multiplication of the first preset number and the second preset number.

[0142] In this embodiment, the second preset number can be any preset value. The second preset number can be the same as the first preset number or different. When the number of second target entries that meet the first target condition is equal to the second preset number, these second target entries are merged, and the merged third target entries are stored in the third storage area. It should be noted that the third storage area also belongs to the cache consistency directory. The third storage area is a storage area set in the cache consistency directory for storing three-level directories. The third target entries stored in the third storage area are merged entries by default, and the merge quantity is the first preset quantity multiplied by the second preset quantity.

[0143] For example, the second preset number is set to two. It is detected that the second target entry in the second storage area shown in Table 8 is modified, and it is determined that the number of second target entries that meet the first target condition after the modification reaches the second preset number (the first second target entry and the second second target entry). The two second target entries are merged, and the third target entry obtained after the merger is stored in the third storage area. The merged second storage area and the third storage area are shown in Table 9. The valid bit of the merged second target entry is modified to 0, and a new third target entry is added to the third storage area. The third target entry stored in the third storage area is a merged entry by default, and the merge quantity is 2x4. The address of the merged entry is calculated from the address of the third target entry to the low bit.

[0144]

[0145] Table 8

[0146]

[0147] Table 9

[0148] It should be noted that if the storage scale is very large, a fourth storage area, a fifth storage area, or even more storage areas can be added to further improve the utilization of the storage space.

[0149] In the above scheme, by adding a third storage area, the entries in the second storage area that meet the merging conditions are merged twice to generate a third target entry of a higher level. The third storage area implicitly records the number of merged entries (the product of the first preset number and the second preset number) through a hierarchical structure, and there is no need to additionally store the first identifier (merge attribute) and the second identifier (merge number). On the basis of the second storage area, the scale of entry aggregation is further expanded through multi-level merging, covering a larger range of continuous address blocks with fewer storage units, significantly improving the space utilization of the directory. It is especially suitable for scenarios where massive entries are managed in ultra-large-scale systems, and realizes step-by-step optimization of storage overhead.

[0150] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 8 As shown, the method further includes:

[0151] Step 801, in response to a query request for a target address, determine whether there is a second target entry or a third target entry whose address satisfies a third target condition, wherein the third target condition is that the target address belongs to the address range indicated by the address and the first preset number or the address, the first preset data and the second preset number.

[0152] Step 802: If there is a second target entry or the third target entry matching the target address, return entry information of the second target entry or the third target entry, where the entry information at least includes status information of the computing node.

[0153] After receiving the query request including the target address, if the matching fails in the unmerged entries, a match may be further performed with the second target entry in the second storage area and the third target entry in the third storage area.

[0154] For example, a query request with a target address of 0010 is received. After failing to match the unmerged entries in Table 7, a match is performed against the second target entry in the second storage area in Table 7. Based on the first preset number four, the second target entry with address 0000 in the second storage area includes addresses 0000, 0001, 0010, and 0011, which includes the target address 0010. Therefore, the status information of the second target entry is returned to the requesting party.

[0155] For another example, a query request with a target address of 0010 is received. After failing to match the unmerged entries in Table 9, a match is then performed against the second target entry in the second storage area in Table 9. If this match also fails, a match is then performed against the third target entry in the third storage area in Table 9. The third target entry in the third storage area has an address of 0000. Based on the first preset number of four and the second preset number of two, this third target entry includes an address range of 0000, 0001, 0010, 0011, 0100, 0101, 0110, and 0111, which includes the target address 0010. Therefore, the status information of the second target entry is returned to the requesting party.

[0156] In the above scheme, by hierarchically matching the target address of the query request with the address range of the merged entries in the second and third storage areas (based on the continuous address blocks defined by the first preset number and the second preset number), the merged entry that may cover the address is directly located. After the entry has been merged and compressed at multiple levels, the address range can still be used to quickly determine the entry to which it belongs, and its status information can be returned, ensuring that the response efficiency of the multi-layer directory structure to query requests is not affected by the merge operation based on the merge storage optimization. By implicitly associating address ranges instead of explicit identification, the system avoids the increase in query complexity caused by multi-level merging while maintaining low storage overhead, thereby ensuring the real-time and accuracy of cache consistency management.

[0157] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 9 As shown, the method further includes:

[0158] Step 901: It is detected that a new entry is added to the cache coherence directory and the cache coherence directory is full, and all entries in the cache coherence directory are traversed.

[0159] Step 902: Determine the number of computing nodes whose status information in the current entry indicates a shared state.

[0160] In this embodiment, SC and SD are regarded as status information indicating a shared state. In other implementations, adjustments can be made based on specific needs.

[0161] Step 903: After the traversal is completed, the entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added entry is stored in the cache consistency directory.

[0162] For example, as shown in Table 10, Table 10 shows a cache consistency directory that is full. When a new entry is added to the cache consistency directory, all entries in the cache consistency directory are traversed to determine the number of computing nodes whose status information indicates a shared state in each entry. The status information of the four computing nodes in the first entry are I, U, I, and I, respectively, and the number of computing nodes whose status information indicates a shared state is 0. The status information of the four computing nodes in the second entry are SC, SD, SC, and I, respectively, and the number of computing nodes whose status information indicates a shared state is 3. Therefore, the second entry is deleted, and the newly added entry is stored in the cache consistency directory (the newly added entry replaces the second entry).

[0163] Valid bits address Compute node 1 Compute Node 2 Compute node 3 Compute node 4 1 0000 I U I I 1 0001 SC SD SC I

[0164] Table 10

[0165] It should be noted that full capacity means that the number of entries is full and the valid bits of all entries are 1. If there are entries with valid bits of 0, the capacity is considered not full. Entries with valid bits of 0 can be directly replaced by newly added entries.

[0166] Preferably, when calculating the number of computing nodes whose status information indicates a shared state, newly added entries may also be calculated to avoid adding entries with a larger number of computing nodes whose status information indicates a shared state.

[0167] In the above solution, when the cache consistency directory is full, entries with the largest number of shared state compute nodes are replaced first, as they require more resources to track the state synchronization of these compute nodes. By replacing these high-maintenance entries with new entries, the system directly reduces the number of shared nodes that require real-time monitoring, significantly reducing the management burden of the consistency protocol. This strategy optimizes the dynamic allocation efficiency of directory resources in capacity-constrained scenarios, ensuring the timely inclusion of new entries with high-frequency access. It also alleviates the communication and coordination pressure caused by multi-node sharing, improving the overall system response speed.

[0168] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 10 As shown, the method further includes:

[0169] Step 1001: It is detected that a new second target entry is added to the second storage area and the capacity of the second storage area is full, and all second target entries in the second storage area are traversed.

[0170] Step 1002: Determine the number of computing nodes whose status information in the current second target entry indicates a shared state.

[0171] Step 1003: After the traversal is completed, the second target entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added second target entry is stored in the second storage area.

[0172] Step 1004: Determine a first preset number of entries based on the second target entry to be deleted, and store the first preset number of entries in the cache coherence directory.

[0173] For example, as shown in Table 11, the four entries at addresses 1000, 1001, 1010, and 1011 in Table 11 all have the same status information for the same computing nodes, and thus can be merged into a second target entry and stored in the second storage area. However, the second storage area is currently full, so the second storage area is traversed to find the second target entry with the largest number of computing nodes in the second storage area whose status information indicates a shared state, i.e., the second target entry at address 0100. As shown in Table 12, the four entries at addresses 1000, 1001, 1010, and 1011 in Table 11 are merged into a new second target entry, replacing the second target entry at address 0000 in the second storage area. The second target entry at address 0000 is then decomposed into four entries at addresses 0000, 0001, 0010, and 0011 based on the first preset number of four, which exactly replace the merged four entries at addresses 1000, 1001, 1010, and 1011.

[0174]

[0175]

[0176] Table 11

[0177]

[0178] Table 12

[0179] In the above solution, when the capacity of the second storage area is full, the second target entry with the largest number of shared state computing nodes is replaced first, decomposed into the original first preset number of entries and saved back to the main directory, while the newly added second target entry is included. By eliminating the merged entries with a high number of shared nodes, the system directly reduces the scale of shared nodes that need to be continuously tracked, reducing the communication pressure for consistency maintenance. At the same time, the decomposed and rolled-back entries remain in the main directory to ensure that data integrity is not affected. In the process of dynamic allocation of storage space, both the efficiency of entry replacement and the stability of the protocol are taken into account, further optimizing the resource management capabilities under the multi-level directory architecture.

[0180] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 11 As shown, the method further includes:

[0181] Step 1101: It is detected that a third target entry is newly added to the third storage area and the capacity of the third storage area is full, and all third target entries in the third storage area are traversed.

[0182] Step 1102: Determine the number of computing nodes whose status information in the current third target entry indicates a shared state.

[0183] Step 1103 : After the traversal is completed, the third target entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added third target entry is stored in the third storage area.

[0184] Step 1104 : Determine a second preset number of second target entries based on the deleted third target entry, and store the second preset number of second target entries in the second storage area.

[0185] For example, as shown in Table 13, the two entries at addresses 0010_0000 and 0100_0000 in Table 13 have identical status information for the respective compute nodes, and thus can be merged into a third target entry and stored in the third storage area. However, the third storage area is currently full, so the third storage area is traversed to find the third target entry with the largest number of compute nodes in the third storage area whose status information indicates a shared state, namely, the third target entry at address 0000_1000. As shown in Table 14, the two entries with addresses 0010_0000 and 0100_0000 in Table 13 are merged into a new third target entry, replacing the third target entry with address 0000_1000 in the third storage area, and the third target entry with address 0000_1000 is decomposed into two second target entries with addresses 0000, 0001, 0010 and 0011 based on the second preset number four, which just replace the two second target entries with addresses 0010_0000 and 0100_0000 that have been merged.

[0186]

[0187]

[0188] Table 13

[0189]

[0190] Table 14

[0191] In the above solution, when the capacity of the third storage area is full, the third target entry with the largest number of shared state computing nodes is replaced first, decomposed into a second preset number of second target entries and stored back in the second storage area, while the newly added third target entry is included. By eliminating merged entries with a high number of shared nodes, the system directly reduces the scale of shared nodes that need to be continuously tracked, reducing the communication pressure for consistency maintenance. At the same time, the decomposed and rolled-back entries remain in the main directory to ensure that data integrity is not affected. In the process of dynamic allocation of storage space, both entry replacement efficiency and protocol stability are taken into account, further optimizing the resource management capabilities under the multi-level directory architecture.

[0192] In an example of the present application, a cache consistency directory entry merging method is also provided, including:

[0193] When the state information is merged state information, if any one of two different state information included in the merged state information indicates a shared state, the merged state information is state information indicating a shared state.

[0194] For example, any status information indicating a shared state among SD, SD / I, I / SD, SC, SC / I, I / SC, U / SD, SD / U, U / SC, SC / U, SD / SC, SC / SD, etc. is regarded as status information indicating a shared state.

[0195] In order to significantly improve the flexibility and coverage of entry merging while ensuring basic consistency, further expand the scope of storage optimization, and reduce directory management overhead, another embodiment of the present application provides a cache consistency directory entry merging method, such as Figure 12 As shown, the method further includes:

[0196] Step 1201: Detect that the cache coherence directory is modified, and determine two entries that meet a fourth target condition. The fourth target condition is that the addresses of the two entries differ by only one bit, and the first identifier of the entry indicates that the entry is an unmerged entry.

[0197] For example, as shown in Table 15, Table 15 shows the directory entries after the cache coherence directory is modified. The third identifier identifies the number of bits that differ in the addresses of the two entries before merging. As shown in Table 15, the addresses of the first entry and the second entry in Table 15 differ by only one bit, and these two entries are determined to meet the fourth target condition. The addresses of the third and fourth entries in Table 15 also differ by only one bit, and these two entries are determined to meet the fourth target condition.

[0198] Valid bits The third mark address Compute node 1 Compute Node 2 ... Compute node 4 1 0000_0000 I U ... I 1 0000_0100 SC SD ... I 1 0100_1111 SC SC ... I 1 0000_1111 SD SC ... I 1 0000_0011 I U ... I

[0199] Table 15

[0200] Step 1202: Merge the two entries to obtain a fifth target entry, wherein the first identifier of the fifth target entry indicates that the fifth target entry is a merged entry, and the third identifier of the fifth target entry indicates the number of different bits in the addresses of the two entries. The status information of the computing node of the fifth target entry is obtained by merging the status information of the computing nodes of the two entries.

[0201] Continuing with the above example, the first entry and the second entry in Table 15 are merged to obtain a fifth target entry. The third entry and the fourth entry in Table 15 are merged to obtain a fifth target entry. The merged cache consistency directory is shown in Table 16, and the valid bits of the merged second entry and the merged fourth entry are modified to 0. Since the addresses of the first entry and the second entry are different in the third bit, the third identifier of the fifth target entry after the first entry and the second entry are merged is 00011, indicating that the addresses of the two entries before the fifth target entry are different in the third bit. Since the addresses of the third entry and the fourth entry are different in the seventh bit, the third identifier of the fifth target entry after the third entry and the fourth entry are merged is 00111, indicating that the addresses of the two entries before the fifth target entry are different in the seventh bit. And the status information of each computing node after the merger is composed of the status information of the same computing nodes in the two entries before the merger.

[0202] Valid bits The third mark address Compute node 1 Compute Node 2 ... Compute node 4 1 00011 0000_0000 I / SC U / SD ... I 0 0000_0100 SC SD ... I 1 00111 0100_1111 SC / SD SC ... I 0 0000_1111 SD SC ... I 1 0000_0011 I U ... I

[0203] Table 16

[0204] It should be noted that the number of digits that can be identified by the third identifier can also be increased by means of a preset function. For example, the number of digits that differ between the addresses of the two entries before merging can be determined based on the third identifier using the following formula:

[0205] 2 b3 +1

[0206] Among them, b3 is the third identifier.

[0207] In addition, it should be noted that the fifth target entry obtained by the above merging method can be merged again when it meets the first target condition, and can be marked with the third identifier. It can also be stored in the second storage area and the third storage area by merging, and can also be marked with the third identifier.

[0208] In the above scheme, the conditions for merging entries are relaxed by allowing unmerged entries with only one address difference to be merged (such as addresses 0000_0000 and 0000_0100), and generating aggregated state information based on the state information before the merge (for example, merging I and U into I / U). By recording the address difference bit information through the third identifier, the system does not need to force the state information of the merged entries to be consistent, and can merge more scattered entries with similar addresses into a single fifth target entry. While ensuring basic consistency, the flexibility and coverage of entry merging are significantly improved, especially for scenarios with sparse address distribution or dynamic state changes, further expanding the scope of storage optimization and reducing directory management overhead.

[0209] In an example of the present application, a cache consistency directory entry merging method is also provided, such as Figure 13 As shown, the state information of the computing node of the fifth target entry is obtained by merging the state information of the computing nodes of the two entries, including:

[0210] Step 1301: If the state information of the computing nodes in the two entries is the same, determine the state information as the state information of the computing node in the fifth target entry.

[0211] Step 1302: If the state information of the computing nodes in the two entries is different, merge the two different state information into merged state information, and determine it as the state information of the computing node in the fifth target entry.

[0212] For example, as shown in Table 17, Table 17 shows two entries before the merger, and the status information of computing node 4 in these two entries is both 1, which is the same. Therefore, the fifth target entry obtained after the merger of these two entries is shown in Table 18, and the status information of computing node 4 in the fifth target entry is 1. However, before the merger of these two entries, the status information of computing node 1 in the first entry is 1, and the status information of computing node 2 is U, and the status information of computing node 1 in the second entry is SC, and the status information of computing node 2 is SD, which are all different. Therefore, the fifth target entry obtained after the merger of these two entries is shown in Table 18, and the status information of computing node 1 in the fifth target entry is I / SC, indicating that the status information of computing node 1 in the two entries before the merger is 1 and SC respectively. The status information of computing node 2 in the fifth target entry is U / SD, indicating that the status information of computing node 2 in the two entries before the merger is U and SD respectively.

[0213] It should be noted that the merged status information is displayed in order. When the status information of two entries is different, the status information with the higher address is displayed first, and the status information with the lower address is displayed later.

[0214] Valid bits The third mark address Compute node 1 Compute Node 2 ... Compute node 4 1 0000_0000 I U ... I 1 0000_0100 SC SD ... I

[0215] Table 17

[0216] Valid bits The third mark address Compute node 1 Compute Node 2 ... Compute node 4 1 00011 0000_0000 I / SC U / SD ... I 0 0000_0100 SC SD ... I

[0217] Table 18

[0218] In this solution, by recording address difference bits through a third identifier, the system can merge more dispersed entries with similar addresses into a single fifth target entry without requiring consistent state information for the merged entries. While maintaining basic consistency, this significantly improves the flexibility and coverage of entry merging, making it particularly suitable for scenarios with sparse address distribution or dynamically changing states. This further expands the scope of storage optimization and reduces directory management overhead.

[0219] In order to implement the above cache consistency directory entry merging method, as shown in Figure 14 As shown, an example of the present application provides a cache consistency directory entry merging device, including:

[0220] A computing module 1401 is configured to detect that a cache coherence directory has been modified and determine at least two entries that meet a first target condition, wherein the first target condition is that addresses of the at least two entries are continuous and adjacent, state information of the same computing node in the at least two entries is the same, and a first identifier of the entry indicates that the entry is an unmerged entry;

[0221] The processing module 1402 is configured to merge the at least two entries to obtain a first target entry, wherein the first identifier of the first target entry indicates that the first target entry is a merged entry, and the second identifier of the first target entry indicates the number of entries merged by the first target entry.

[0222] The calculation module 1401 is further configured to detect that an entry in the cache consistency directory has been modified, and then determine that the cache consistency directory has been modified;

[0223] Alternatively, the calculation module 1401 is further configured to detect a new entry in the cache coherence directory, and then determine that the cache coherence directory has been modified.

[0224] The calculation module 1401 is further configured to determine candidate entries, where the candidate entries are the modified or newly added entries.

[0225] The calculation module 1401 is further configured to determine whether there is at least one entry that satisfies the first target condition as the candidate entry;

[0226] The calculation module 1401 is further configured to determine the candidate entry and the at least one entry as the at least two entries satisfying the first target condition, if any.

[0227] The calculation module 1401 is further configured to, in response to a query request for a target address, match an entry in the cache coherence directory with the target address;

[0228] The processing module 1402 is further configured to return entry information of an entry matching the target address if there is one, where the entry information at least includes status information of a computing node.

[0229] The calculation module 1401 is further configured to determine whether there is an entry in the cache coherence directory whose address is consistent with the target address or whose address and the second identifier satisfy a second target condition, where the second target condition is that the target address falls within an address range indicated by the address and the second identifier;

[0230] The calculation module 1401 is further configured to determine whether an entry matching the target address exists, if any.

[0231] The processing module 1402 is further configured to determine that the number of entries satisfying the first target condition is equal to a first preset number, and merge the first preset number of entries to obtain a second target entry;

[0232] The processing module 1402 is further configured to store the second target entry in a second storage area, where the second storage area indicates that the second target entry is a merged entry and the number of merged entries is a first preset number.

[0233] The calculation module 1401 is further configured to detect that the second target entry in the second storage area is modified, and determine at least two second target entries that meet the first target condition;

[0234] The processing module 1402 is further configured to, if the number of second target items meeting the first target condition is equal to a second preset number, merge the second preset number of second target items to obtain a third target item;

[0235] The processing module 1402 is further configured to store the third target entry in a third storage area, where the third storage area indicates that the third target entry is a merged entry and the number of merged entries is a first preset number multiplied by a second preset number.

[0236] The calculation module 1401 is further configured to, in response to a query request for a target address, determine whether there is a second target entry or a third target entry whose address satisfies a third target condition, wherein the third target condition is that the target address falls within an address range indicated by the address and the first preset number or the address, the first preset data, and the second preset number;

[0237] The processing module 1402 is further configured to return entry information of a second target entry or a third target entry matching the target address if there is a second target entry or a third target entry, where the entry information includes at least status information of a computing node.

[0238] The calculation module 1401 is further configured to detect that the cache coherence directory is modified, and determine two entries that meet a fourth target condition, wherein the fourth target condition is that the addresses of the two entries differ by only one bit, and the first identifier of the entry indicates that the entry is an unmerged entry;

[0239] The processing module 1402 is also used to merge the two entries to obtain a fifth target entry, the first identifier of the fifth target entry indicates that the fifth target entry is a merged entry, the third identifier of the fifth target entry indicates the number of different bits in the addresses of the two entries, and the status information of the computing node of the fifth target entry is obtained by merging the status information of the computing nodes of the two entries.

[0240] The calculation module 1401 is further configured to determine the state information as the state information of the computing node of the fifth target entry if the state information of the computing nodes in the two entries is the same;

[0241] The calculation module 1401 is further configured to merge the two different state information into merged state information if the state information of the computing nodes in the two entries is different, and determine the merged state information as the state information of the computing node in the fifth target entry.

[0242] The calculation module 1401 is further configured to detect that a new entry is added to the cache consistency directory and the cache consistency directory is full, and traverse all entries in the cache consistency directory;

[0243] The computing module 1401 is further configured to determine the number of computing nodes whose status information in the current entry indicates a shared state;

[0244] The computing module 1401 is further configured to delete, after the traversal is completed, the entry with the largest number of computing nodes indicated as being in a shared state in the state information, and store the newly added entry in the cache consistency directory.

[0245] The calculation module 1401 is further configured to detect that a new second target entry is added to the second storage area and the second storage area is full, and traverse all second target entries in the second storage area;

[0246] The computing module 1401 is further configured to determine the number of computing nodes whose status information in the current second target entry indicates a shared state;

[0247] The computing module 1401 is further configured to, after the traversal is completed, delete the second target entry having the largest number of computing nodes indicated as being in a shared state by the state information, and store the newly added second target entry in the second storage area;

[0248] The calculation module 1401 is further configured to determine a first preset number of entries based on the second target entry to be deleted, and store the first preset number of entries in the cache coherence directory.

[0249] The calculation module 1401 is further configured to detect that a third target entry is newly added to the third storage area and that the third storage area is full, and traverse all third target entries in the third storage area;

[0250] The computing module 1401 is further configured to determine the number of computing nodes whose status information in the current third target entry indicates a shared state;

[0251] The computing module 1401 is further configured to, after the traversal is completed, delete the third target entry having the largest number of computing nodes indicated as being in a shared state by the state information, and store the newly added third target entry in the third storage area;

[0252] The calculation module 1401 is further configured to determine a second preset number of second target entries based on the deleted third target entries, and store the second preset number of second target entries in the second storage area.

[0253] The calculation module 1401 is further configured to: when the state information is merged state information, if any one of the two different state information included in the merged state information indicates a shared state, then the merged state information is state information indicating a shared state.

[0254] An embodiment of the present application further provides a chip, which includes a processor capable of executing the cache consistency directory entry merging method provided in the embodiment of the present application.

[0255] An embodiment of the present application further provides a component, which includes a chip, and the chip includes a processor. The processor can execute the cache consistency directory entry merging method provided in the embodiment of the present application.

[0256] In some optional embodiments, the component may be a mainboard, a micro control unit, etc.

[0257] An embodiment of the present application further provides an electronic device, which includes components, the components include a chip, the chip includes a processor, and the processor is capable of executing the cache consistency directory entry merging method provided in the embodiment of the present application.

[0258] Figure 15 A schematic block diagram of an example electronic device 1500 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0259] like Figure 15 As shown, device 1500 includes a computing unit 1501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1502 or a computer program loaded from a storage unit 1508 into a random access memory (RAM) 1503. Various programs and data required for the operation of device 1500 can also be stored in RAM 1503. Computing unit 1501, ROM 1502, and RAM 1503 are connected to each other via a bus 1504. An input / output (I / O) interface 1505 is also connected to bus 1504.

[0260] Various components in device 1500 are connected to I / O interface 1505, including an input unit 1506, such as a keyboard and mouse; an output unit 1507, such as various types of displays and speakers; a storage unit 1508, such as a magnetic disk and optical disk; and a communication unit 1509, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 1509 allows device 1500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0261] Computing unit 1501 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of computing unit 1501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. Computing unit 1501 performs the various methods and processes described above, such as the cache coherence directory entry merging method. For example, in some embodiments, the cache coherence directory entry merging method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 1508. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 1500 via ROM 1502 and / or communication unit 1509. When the computer program is loaded into RAM 1503 and executed by computing unit 1501, one or more steps of the cache coherence directory entry merging method described above may be performed. Alternatively, in other embodiments, the computing unit 1501 may be configured to perform the cache coherence directory entry merging method in any other appropriate manner (eg, by means of firmware).

[0262] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein a computer program is stored therein, and the computer program is used to execute the cache consistency directory entry merging method provided by the embodiment of the present application.

[0263] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0264] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0265] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0266] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0267] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0268] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0269] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0270] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0271] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A cache consistency directory entry merging method, characterized in that: The method comprises: detecting that a cache coherence directory has been modified, determining at least two entries that meet a first target condition, wherein the first target condition is that addresses of the at least two entries are continuous and adjacent, state information of the same computing node in the at least two entries is the same, and a first identifier of the entry indicates that the entry is an unmerged entry; The at least two entries are merged to obtain a first target entry, wherein the first identifier of the first target entry indicates that the first target entry is a merged entry, and the second identifier of the first target entry indicates the number of entries merged by the first target entry.

2. The method according to claim 1, characterized in that The detecting that the cache consistency directory is modified includes: detecting that an entry in the cache coherence directory is modified, determining that the cache coherence directory is modified; Alternatively, if a new entry is detected in the cache coherence directory, it is determined that the cache coherence directory is modified.

3. The method according to claim 2, characterized in that The determining of at least two items that meet the first target condition includes: Determining a candidate entry, where the candidate entry is the modified or newly added entry; Determining whether there is at least one entry that satisfies the first target condition as the candidate entry; If so, the candidate entry and the at least one entry are determined as the at least two entries that meet the first target condition.

4. The method according to claim 1, wherein The method further comprises: In response to a query request for a target address, matching an entry in the cache coherence directory with the target address; If an entry matching the target address exists, entry information of the entry is returned, where the entry information at least includes status information of the computing node.

5. The method according to claim 4, characterized in that Matching the entry in the cache coherence directory with the target address includes: Determine whether there is an entry in the cache coherence directory whose address is consistent with the target address or whose address and a second identifier satisfy a second target condition, where the second target condition is that the target address falls within an address range indicated by the address and the second identifier; If so, it is determined that there is an entry matching the target address.

6. The method according to claim 1, characterized in that The method further comprises: Determining that the number of entries satisfying the first target condition is equal to a first preset number, and merging the first preset number of entries to obtain second target entries; The second target entry is stored in a second storage area, where the second storage area indicates that the second target entry is a merged entry and the number of merged entries is a first preset number.

7. The method according to claim 6, characterized in that The method further comprises: detecting that a second target entry in the second storage area is modified, and determining at least two second target entries that meet a first target condition; If the number of second target items that meet the first target condition is equal to a second preset number, merging the second preset number of second target items to obtain a third target item; The third target entry is stored in a third storage area, where the third storage area indicates that the third target entry is a merged entry and the number of merged entries is a first preset number multiplied by a second preset number.

8. The method according to claim 6 or 7, characterized in that The method further comprises: In response to a query request for a target address, determining whether there is a second target entry or a third target entry whose address satisfies a third target condition, wherein the third target condition is that the target address falls within an address range indicated by the address and the first preset number or the address, the first preset data, and the second preset number; If there is a second target entry or the third target entry matching the target address, entry information of the second target entry or the third target entry is returned, where the entry information includes at least status information of the computing node.

9. The method according to claim 1, characterized in that The method further comprises: detecting that a new entry is added to the cache coherence directory and that the cache coherence directory is full, traversing all entries in the cache coherence directory; Determine the number of computing nodes whose status information in the current entry indicates a shared state; After the traversal is completed, the entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added entry is stored in the cache consistency directory.

10. The method according to claim 6, characterized in that The method further comprises: detecting that a new second target entry is added to the second storage area and that the second storage area is full, traversing all second target entries in the second storage area; Determine the number of computing nodes whose status information in the current second target entry indicates a shared state; After the traversal is completed, the second target entry with the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added second target entry is stored in the second storage area; A first preset number of entries is determined based on the deleted second target entry, and the first preset number of entries is stored in the cache coherence directory.

11. The method according to claim 7, characterized in that The method further comprises: detecting that a third target entry is newly added to the third storage area and that the third storage area is full, traversing all third target entries in the third storage area; Determine the number of computing nodes whose status information in the current third target entry indicates a shared state; After the traversal is completed, the third target entry having the largest number of computing nodes indicated as being in a shared state is deleted, and the newly added third target entry is stored in the third storage area; A second preset number of second target entries is determined based on the deleted third target entries, and the second preset number of second target entries is stored in the second storage area.

12. The method according to claim 9, 10 or 11, characterized in that When the state information is merged state information, if any one of two different state information included in the merged state information indicates a shared state, the merged state information is state information indicating a shared state.

13. A cache consistency directory entry merging method, characterized in that: The method comprises: detecting that the cache coherence directory is modified, and determining two entries that meet a fourth target condition, wherein the fourth target condition is that addresses of the two entries differ by only one bit, and a first identifier of the entry indicates that the entry is an unmerged entry; The two entries are merged to obtain a fifth target entry, wherein the first identifier of the fifth target entry indicates that the fifth target entry is a merged entry, the third identifier of the fifth target entry indicates the number of bits with different addresses of the two entries, and the status information of the computing node of the fifth target entry is obtained by merging the status information of the computing nodes of the two entries.

14. The method according to claim 13, characterized in that The state information of the computing node of the fifth target entry is obtained by combining the state information of the computing nodes of the two entries, including: If the state information of the computing nodes in the two entries is the same, determining the state information as the state information of the computing node in the fifth target entry; If the state information of the computing nodes in the two entries is different, the two different state information are merged into merged state information, and the merged state information is determined as the state information of the computing node in the fifth target entry.

15. A cache consistency directory entry merging device, characterized in that: The device comprises: a computing module configured to detect that a cache coherence directory has been modified and determine at least two entries that meet a first target condition, wherein the first target condition is that addresses of the at least two entries are continuous and adjacent, state information of the same computing node in the at least two entries is the same, and a first identifier of the entry indicates that the entry is an unmerged entry; The processing module is configured to merge the at least two entries to obtain a first target entry, wherein the first identifier of the first target entry indicates that the first target entry is a merged entry, and the second identifier of the first target entry indicates the number of entries merged by the first target entry.

16. The device according to claim 15, characterized in that The device comprises: The processing module is further configured to determine that the number of entries satisfying the first target condition is equal to a first preset number, and merge the first preset number of entries to obtain a second target entry; The processing module is further configured to store the second target entry in a second storage area, where the second storage area indicates that the second target entry is a merged entry and the number of merged entries is a first preset number.

17. A chip, characterized in that: The chip includes a processor, and the processor is capable of executing the cache consistency directory entry merging method according to any one of claims 1 to 15.

18. A component, characterized in that The component comprises the chip according to claim 17.

19. An electronic device, characterized in that: The electronic device comprises the component according to claim 18.

20. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and the computer program is used to execute the cache consistency directory entry merging method according to any one of claims 1 to 15.

Images