Processor, data access method and electronic equipment

Abstract

The invention discloses a processor, a data access method and electronic equipment. The processor comprises a plurality of computing units, the plurality of computing units are divided into at least one computing unit cluster, and each computing unit cluster comprises at least part of the plurality of computing units; a plurality of broadcasting units, the plurality of broadcasting units and the plurality of computing units are in one-to-one correspondence, and each broadcasting unit of the plurality of broadcasting units is configured to: in response to the acquired target data, broadcast the target data to the computing unit cluster where the target computing unit is located, so that each computing unit in the computing unit cluster stores the target data, the target calculation unit is a calculation unit corresponding to the broadcast unit in the plurality of calculation units. The processor can effectively process repeated data, so that the problem of time period waste caused by the fact that the buffer memory transmits the repeated data is effectively solved, and the pressure of the buffer memory can be greatly reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processor, a data access method, and an electronic device. Background Art

[0002] Traditional processors (such as CPUs or GPUs) can only process one instruction sequence at a time, commonly called a thread. During thread processing, the processor's processing unit must continuously load instructions and data for processing. As processor technology advances, processor frequency and performance continue to increase, requiring an ever-increasing speed at which instructions and data must be loaded. Unfortunately, memory technology has not kept pace with processor development, and memory often cannot provide enough instructions and data for the processor to process.

[0003] In order to improve the utilization of the processing units in the processor, thread-level parallel technology is proposed, that is, executing more than one instruction sequence in the core of the processor. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a processor, comprising: a plurality of computing units, the plurality of computing units being divided into at least one computing unit cluster, each computing unit cluster including at least some of the plurality of computing units; a plurality of broadcast units, the plurality of broadcast units corresponding one-to-one to the plurality of computing units, each of the plurality of broadcast units being configured to: in response to acquiring target data, broadcast the target data to the computing unit cluster where the target computing unit is located, so that each computing unit in the computing unit cluster stores the target data, the target computing unit being the computing unit among the plurality of computing units corresponding to the broadcast unit.

[0005] For example, in a processor provided in an embodiment of the present disclosure, each broadcast unit is configured to: in response to obtaining first data from a cache unit, determine whether the first data is the target data based on the data type of the first data; and in response to the first data being the target data, broadcast the target data to the computing unit cluster where the target computing unit is located.

[0006] For example, in the processor provided by an embodiment of the present disclosure, each of the plurality of broadcast units is further configured to: in response to the first data not being the target data, provide the first data to the target computing unit.

[0007] For example, in the processor provided in one embodiment of the present disclosure, each broadcast unit is further configured to: when the first data is not the target data and during the provision of the first data to the target computing unit, the broadcast unit receives second data broadcast by another broadcast unit, suspend providing the first data to the target computing unit, provide the second data to the target computing unit, and broadcast the second data.

[0008] For example, in a processor provided by an embodiment of the present disclosure, a thread group distribution unit is configured to: distribute multiple thread groups sharing the target data to the at least some computing units respectively, and each computing unit in the at least some computing units is configured to execute instructions in the thread group of the multiple thread groups distributed to each computing unit.

[0009] For example, in a processor provided in an embodiment of the present disclosure, the thread group distribution unit is further configured to: create at least one execution group for each of the multiple thread groups, wherein each execution group includes allocation information and an identifier of the allocation information; and provide the allocation information and the identifier of the allocation information to the multiple broadcast units, and each of the multiple broadcast units is configured to: store the allocation information in response to a match between the identifier of the allocation information and the identifier of the broadcast unit itself, and broadcast the target data according to the allocation information.

[0010] For example, in a processor provided by an embodiment of the present disclosure, the allocation information includes a mapping relationship between the thread group identifier of the thread group to which each execution group belongs and the respective unit identifiers of at least some of the computing units, and each of the multiple broadcast units is configured to: in response to obtaining the target data from the cache unit, query the mapping relationship to determine the unit identifier based on the current thread group identifier carried by the target data; determine the at least some of the computing units to which the target data is broadcast based on the unit identifier; and broadcast the target data to the at least some of the computing units.

[0011] For example, in the processor provided by an embodiment of the present disclosure, the allocation information also includes a mapping relationship between the thread group identifier and the base address, and each of at least some of the computing units is configured to: determine the target address based on the base address and the address offset information carried by the target data, and store the target data at the target address.

[0012] For example, in a processor provided by an embodiment of the present disclosure, each of the multiple computing units is further configured to: in response to executing a current instruction related to the target data, provide the unit identifier of the computing unit and the thread group identifier of the thread group to which the current instruction belongs to the thread group distribution unit; the thread group distribution unit is further configured to: in response to receiving the unit identifier of the computing unit and the thread group identifier of the thread group to which the current instruction belongs, provide the unit identifier of the computing unit to multiple broadcast units corresponding to the computing unit cluster indicated by the thread group identifier; each of the multiple broadcast units is configured to: add the unit identifier provided by the thread group distribution unit to the broadcast order array of the broadcast unit itself; each of the multiple broadcast units broadcasts the target data in the broadcast order indicated by the broadcast order array.

[0013] For example, in the processor provided in one embodiment of the present disclosure, each of the multiple broadcast units is configured to: in response to obtaining the target data, query the broadcast order array; in response to the target computing unit being in the first order in the broadcast order array, broadcast the target data to the computing unit cluster where the target computing unit is located.

[0014] For example, in the processor provided in one embodiment of the present disclosure, each of the multiple broadcast units is further configured to: in response to the target computing unit corresponding to the broadcast unit not being the first in the broadcast sequence array, the broadcast unit enters a waiting state, and the waiting state is used to wait for the computing unit located before the target computing unit in the broadcast sequence array to complete the broadcast and then broadcast the target data.

[0015] For example, in the processor provided in one embodiment of the present disclosure, each of the multiple broadcast units is further configured to: in response to the completion of the broadcast of the target data, broadcast a completion indication signal, and delete the identification information of the computing unit that executes the current instruction related to the target data from the broadcast order array.

[0016] For example, in the processor method provided in one embodiment of the present disclosure, the at least some computing units are adjacent, and the multiple broadcast units corresponding to the at least some computing units are coupled in sequence, and at least one of the multiple broadcast units corresponding to the at least some computing units is coupled to the thread distribution unit.

[0017] For example, in a processor method provided in an embodiment of the present disclosure, each of the multiple broadcast units includes a cache, and the cache is configured to store data to be broadcast. Each of the multiple broadcast units is configured to: in response to the first data being the target data, query whether the data to be broadcast exists in the cache of a broadcast unit adjacent to the broadcast unit; in response to the existence of the data to be broadcast, store the target data in the broadcast unit until the data to be broadcast does not exist in the cache of the adjacent broadcast unit, and broadcast the target data.

[0018] For example, in a processor method provided in an embodiment of the present disclosure, multiple broadcast units are located in a first-level cache.

[0019] At least one embodiment of the present disclosure provides a data access method, which is applied to the processor provided by any embodiment of the present disclosure, the method comprising: in response to a target broadcast unit among the multiple broadcast units acquiring target data, determining a computing unit cluster where a target computing unit corresponding to the target broadcast unit is located; and broadcasting the target data to the computing unit cluster.

[0020] At least one embodiment of the present disclosure provides an electronic device, including the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0022] Figure 1A A schematic structural diagram of a buffer memory is shown;

[0023] Figure 1B A schematic diagram showing a computing unit performing matrix calculations;

[0024] Figure 2 A schematic diagram of a processor provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 3 A schematic diagram illustrating a data broadcast implementation provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 4 A schematic diagram showing a combination of two computing unit clusters provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 5 A flowchart of a data access method provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 6A schematic block diagram of an electronic device provided for some embodiments of the present disclosure; and

[0029] Figure 7 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0032] In parallel computing, tasks are divided into multiple threads (workitems), which can be executed in parallel on, for example, a general-purpose graphics processing unit (GPGPU). Typically, multiple threads form an execution group, typically 32 or 64 threads. Multiple execution groups can also form a thread group (workgroup). Different thread groups are assigned to different compute units (CUs).

[0033] Different computing units contain multiple arithmetic logic units (ALUs), static memory (SRAM), and a local storage module (LSM) to ensure data storage and parallel processing of data across multiple threads. Data for computations must be read from memory and passed through cache memory to the local storage module or SRAM of the computing unit.

[0034] Cache memory operates between the main memory and the computing unit. It is relatively small but offers fast access speeds. Because the computing unit's computational speed is much higher than the memory access speed, reading data directly from the main memory requires a long wait period. Using cache memory, data can be temporarily stored. The next time the computing unit module needs to access data at the same address, it can quickly retrieve the data from the cache memory without going through the main memory. This effectively increases processor access speed. Cache memory typically consists of a first-level cache (L1 cache) and a second-level cache (L2 cache).

[0035] Figure 1A A schematic structural diagram of a buffer memory is shown.

[0036] like Figure 1A As shown, this example includes multiple computing units, namely computing unit pu0, computing unit pu1, computing unit pu2, and computing unit pu3. Each computing unit has a local storage module. The buffer memory includes L1 cache and L2 cache. The L2 cache reads data from the main memory. The L1 cache reads data from the L2 cache and provides the data to the corresponding computing unit.

[0037] Typically, L1 cache is closer to the computing unit and has the same number as the computing unit. It has a smaller capacity and faster access speed. L2 cache is farther away from the computing unit, has a larger capacity, but slower access speed, and is also smaller in number.

[0038] Figure 1B A schematic diagram showing a computing unit performing matrix calculations is shown.

[0039] like Figure 1BAs shown in the figure, during the matrix calculation A*B=C, matrix A includes data A0, A1, A2, and A3, with data A0, A1, A2, and A3 forming a column. Matrix B includes data B0, B1, B2, and B3, with data B0, B1, B2, and B3 forming a row. The target matrix C is divided into 16 parts, C0 to C15, each corresponding to a thread group. Different thread groups are then assigned to different compute units. Each compute unit has multiple execution groups, which work together to continuously read data from memory and perform computations. Finally, the results are consolidated and stored in memory.

[0040] There are usually two ways to process matrix operations. The first is that during the matrix calculation process, each calculation unit directly reads the required data from the memory and then performs arithmetic operations. Figure 1B As shown in the figure, when calculating the result of part C0, it is necessary to read the A0 data in matrix A and the B0 data in matrix B into the calculation unit. Due to the limitation of the storage capacity of the calculation unit, it is possible to read only part of the A0 or B0 data and stack the calculated results on the C0 part in the form of accumulation. Figure 1B It can be seen that the C0, C1, C2, and C3 parts all need to use the B0 data. Therefore, even if the data read by the four computing units is the same, whether reading from the memory or reading from the buffer memory, it takes a fixed clock cycle to transmit the data. When the number of computing units increases, the time consumed in transmitting data will also increase. Figure 1A As shown in the figure, after receiving the request from the computing unit, the L1 Cache will generate a large number of misses due to its own capacity limitation, thus initiating data requests to the L2 Cache. However, the L2 Cache is smaller in number than the L1 Cache, so after receiving the L1 Cache data request, it cannot process multiple L1 Cache requests at the same time and can only return the data of these requests one by one in a certain order. Therefore, the computing unit needs to wait a long time before actually obtaining the data and starting the calculation. Figure 1BThis matrix calculation reveals that many of these requests contain duplicate data, and returning this duplicate data also takes a certain amount of time, resulting in significant wasted time. As the matrix size increases, the number of compute units required for the calculation also increases, dramatically increasing the amount of data the L1 cache needs to process. Consequently, the L1 cache becomes increasingly burdened, and the time it takes to return data increases. A second approach is to use a global storage module to prepare the data required by multiple compute units. When needed, data is directly read from the global storage module. Because the L1 cache has a small capacity, misses are prone to occur. However, the global storage module, like the L1 cache, is close to the compute units and doesn't have to consider hits or misses, resulting in faster data reads. While this second approach can save some data in advance, reducing the burden on the L1 cache and speeding up data return, the global storage module itself has a limited capacity, and therefore the amount of data it can cache is also limited. As the matrix size increases and the number of compute units increases, the data storage provided by the global storage module cannot effectively reduce the burden on the L1 cache.

[0041] With the development of big data and artificial intelligence, the scale of matrices required for computation in practical applications has become enormous. Buffer memory, limited by its number of data and transmission bandwidth, is under immense pressure. Furthermore, much of the data transmitted by the buffer memory is duplicated, wasting significant time cycles.

[0042] Some embodiments of the present disclosure provide a processor comprising a plurality of computing units and a plurality of broadcasting units. The plurality of computing units are divided into at least one computing unit cluster, and each computing unit cluster comprises at least some computing units among the plurality of computing units. The plurality of broadcasting units correspond one to one with the plurality of computing units, and each of the plurality of broadcasting units is configured to: in response to acquiring target data, broadcast the target data to the computing unit cluster where the target computing unit is located, so that each computing unit in the computing unit cluster stores the target data, and the target computing unit is the computing unit corresponding to the broadcasting unit among the plurality of computing units. These embodiments of the present disclosure can effectively process duplicate data by broadcasting it to different computing units through a plurality of broadcasting units, thereby effectively solving the waste of time cycles caused by the transfer of duplicate data by the buffer memory, and can also greatly reduce the pressure on the buffer memory.

[0043] Figure 2 A schematic diagram of a processor 200 provided by at least one embodiment of the present disclosure is shown.

[0044] like Figure 2As shown, the processor 200 includes multiple computing units 201 and multiple broadcasting units 202. There is a one-to-one correspondence between the multiple computing units 201 and the multiple broadcasting units 202. For example, the multiple computing units 201 include computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3. The multiple broadcasting units 202 include broadcasting units BK0, broadcasting unit BK1, broadcasting unit BK2, and broadcasting unit BK3. There is a one-to-one correspondence between computing units PU0, PU1, PU2, and PU3 and broadcasting units BK0, BK1, BK2, and BK3.

[0045] Multiple computing units 201 are divided into at least one computing unit cluster. For example, computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3 form one computing unit cluster. For another example, computing unit PU0 and computing unit PU1 form one computing unit cluster, and computing unit PU2 and computing unit PU3 form another computing unit cluster.

[0046] Figure 2 Multiple caches (Cache) can be, for example, Figure 1A In the L1 Cache, each L1 Cache corresponds to multiple computing units one by one and is used to provide data to multiple computing units.

[0047] In some embodiments of the present disclosure, the number of the plurality of computing units may be a multiple of 4, and every 4 computing units may serve as a computing unit cluster.

[0048] For example, in Figure 1B In the example, part C0 is allocated to computing unit PU0 for calculation, part C1 is allocated to computing unit PU1 for calculation, part C2 is allocated to computing unit PU2 for calculation, and part C3 is allocated to computing unit PU3 for calculation. Part C0, part C1, part C2, and part C3 all need to use the data of B0, that is, the data of B0 is shared by computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3, and the data of B0 is an example of target data. In the example of the present disclosure, the data shared by at least some of the computing units in the plurality of computing units is referred to as target data. In some embodiments of the present disclosure, the target data may be required by each computing unit in the computing unit cluster, or may be required by some computing units in the computing unit cluster.

[0049] Each of broadcast unit BK0, broadcast unit BK1, broadcast unit BK2, broadcast unit BK3, etc. is configured to: in response to obtaining target data, broadcast the target data to the computing unit cluster where the target computing unit is located, so that each computing unit in the computing unit cluster stores the target data, and the target computing unit is the computing unit corresponding to the broadcast unit among multiple computing units.

[0050] For example, after broadcast unit BK0 acquires B0 data, it broadcasts the data to broadcast units BK1, BK2, and BK3. These units then provide the data to their corresponding computing units, thereby broadcasting the target data to the computing unit cluster where the target computing unit resides. The target computing unit is computing unit PU0, which corresponds to broadcast unit BK0. Broadcast unit BK0 not only provides the B0 data to target computing unit PU0 but also broadcasts the data to other broadcast units BK1, BK2, and BK3 in the computing unit cluster where broadcast unit BK0 resides.

[0051] In some embodiments of the present disclosure, multiple broadcast units are coupled in sequence, and each broadcast unit communicates with adjacent broadcast units, and communicates with other non-adjacent broadcast units through adjacent broadcast units. For example, when broadcast unit BK0 broadcasts the B0 data to broadcast unit BK1, broadcast unit BK2, and broadcast unit BK3, broadcast unit BK0 first broadcasts the B0 data to broadcast unit BK1 adjacent to broadcast unit BK0, and then broadcast unit BK1 broadcasts the B0 data to broadcast unit BK2 adjacent to broadcast unit BK1, and so on. For another example, if broadcast unit BK2 first obtains the B0 data, then broadcast unit BK2 broadcasts the B0 data to its adjacent broadcast units BK1 and BK3, and then broadcast unit BK1 broadcasts the B0 data to broadcast unit BK0.

[0052] The processor broadcasts shared data to different computing units through multiple broadcast units, and can effectively process duplicate data, thereby effectively solving the waste of time cycles caused by the buffer memory transmitting duplicate data and reducing the pressure on the buffer memory.

[0053] In some embodiments of the present disclosure, each broadcast unit is configured to: in response to obtaining first data from a cache unit, determine whether the first data is target data based on the data type of the first data; and in response to the first data being target data, broadcast the target data to the computing unit cluster where the target computing unit is located.

[0054] The cache unit is, for example, the buffer memory described above, for example, an L1 Cache.

[0055] For example, one or more bits in the first data are used to identify the data type. For example, if the bit value is 1, it indicates that the data is shared data, namely target data; if the bit value is 0, it indicates that the data is not shared data.

[0056] Those skilled in the art may also indicate whether data is shared data in other ways, and this disclosure does not limit this.

[0057] In some embodiments of the present disclosure, only shared data is broadcast by the broadcast unit, which can avoid unnecessary broadcasts and save broadcast resources.

[0058] In some embodiments of the present disclosure, each broadcast unit is further configured to: in response to the first data not being the target data, provide the first data to the target computing unit. If the data obtained by the broadcast unit from the cache unit is not the target data, the data is provided only to the target computing unit corresponding to the broadcast unit, and the data is not broadcast within the computing unit cluster.

[0059] It should be noted that the “first data”, “second data”, etc. in the present disclosure are only used to distinguish different data, and “first” and “second” do not indicate a certain order or a special meaning.

[0060] In some embodiments of the present disclosure, each broadcast unit is further configured to: when the first data is not the target data and during the provision of the first data to the target computing unit, the broadcast unit receives second data broadcast by another broadcast unit, suspend providing the first data to the target computing unit, provide the second data to the target computing unit, and broadcast the second data.

[0061] For example, if broadcast unit BK1 receives first data from a cache unit (unshared data) and receives second data from broadcast unit BK2 while providing the first data to a target computing unit (i.e., computing unit PU1), broadcast unit BK1 will pause providing the first data to computing unit PU1 and provide the second data to computing unit PU1 instead. In addition to providing the second data to computing unit PU1, broadcast unit BK1 also continues to broadcast the second data to broadcast unit BK0.

[0062] In this embodiment, when shared data and non-shared data conflict, the broadcast unit prioritizes the shared data, thereby ensuring that the shared data can be broadcast in a timely manner without delaying other computing units from obtaining the shared data in a timely manner.

[0063] like Figure 2 As shown, in some embodiments of the present disclosure, the processor 200 includes, in addition to multiple computing units 201 and multiple broadcasting units 202 , a thread group distribution unit 203 .

[0064] In some embodiments of the present disclosure, the thread group distribution unit 203 is coupled to the nearest broadcast unit, and forwards the command information to other broadcast units in sequence through the broadcast unit. The command information includes, for example, the allocation information described below. Figure 2As shown, the thread group distribution unit 203 is coupled to the broadcast unit BK0 and provides command information to the broadcast unit BK0 , and transmits the command information to each broadcast unit in sequence through the broadcast unit BK0 .

[0065] The thread group distribution unit 203 is configured to: distribute multiple thread groups sharing target data to at least some computing units respectively, and each computing unit in at least some computing units is configured to execute instructions in the thread group distributed to each computing unit among the multiple thread groups.

[0066] For example, if four compute units form a compute unit cluster, the thread group distribution unit will simultaneously check the four compute units to see if they have sufficient resources. If so, four thread groups will be created and then assigned to each of the four compute units, with each compute unit processing one thread group.

[0067] For example, in Figure 1B In the example, the computations for parts C0, C1, C2, and C3 each correspond to a thread group, and the four thread groups are assigned to computing units PU0, PU1, PU2, and PU3, respectively. Computing units PU0, PU1, PU2, and PU3 execute the read, write, and computation (for example, addition, subtraction, multiplication, and division) instructions in these four thread groups, respectively.

[0068] In some embodiments of the present disclosure, the thread group distribution unit 203 is further configured to: create at least one execution group for each of the multiple thread groups, each execution group including allocation information and an identifier of the allocation information; and provide the allocation information and the identifier of the allocation information to the multiple broadcast units. Each of the multiple broadcast units is configured to: in response to a match between the identifier of the allocation information and the identifier of the broadcast unit itself, store the allocation information and broadcast target data based on the allocation information.

[0069] An execution group is the smallest execution unit of a computing unit. Computing units perform calculations according to execution groups. Each computing unit has multiple execution groups, which work together to continuously read data from memory and perform calculations. The results are then consolidated and stored in memory. The thread group distribution unit 203 subdivides each thread group into multiple execution groups and then provides these execution groups to the corresponding computing units.

[0070] In some embodiments of the present disclosure, the allocation information includes, for example, a mapping relationship between a thread group identifier of a thread group to which each execution group belongs and respective unit identifiers of at least some of the computing units, wherein the at least some of the computing units are computing units included in the computing unit cluster to which the thread group indicated by the thread group identifier is allocated.

[0071] For example, the thread group identifier to which each execution group belongs is represented as cluster_id. The thread group identifier cluster_id can determine a unique computing unit cluster, which is used to execute the thread represented by the thread group identifier. The unit identifier PU_id is, for example, the name of the computing unit or a unique number. The allocation information includes, for example, {cluster_id: PU0, PU1, PU2, PU3}. In the allocation information, cluster_id serves as the key in the mapping table, and PU0, PU1, PU2, PU3 are the values of PU_id. For example, cluster_id is 1, and the meaning of the allocation information can be that the computing unit cluster assigned to thread group identifier 1 includes computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3. The thread dispatch unit 203 assigns an identifier to the allocation information, which is used to indicate which broadcast unit the allocation information belongs to. For example, the identifier of {1: PU0, PU1, PU2, PU3} is BK0. If the identifier of the allocation information matches the identifier of the broadcast unit itself, it indicates that the allocation information belongs to the broadcast unit and is stored by the broadcast unit, so that the broadcast unit determines to which computing units the target data is broadcast based on the allocation information.

[0072] When creating an execution group, the thread group distribution unit 203 packages the thread group identifier cluster_id of the thread group to which the execution group belongs and the unit identifiers PU_id of at least some computing units, and allocates a new identifier (i.e., an identifier of allocation information), which corresponds one-to-one to the broadcast unit.

[0073] For example, if the identifier of the allocation information is consistent with the identifier of the broadcast unit itself, it indicates that the allocation information belongs to the broadcast unit. For another example, if the identifier of the allocation information and the identifier of the broadcast unit itself correspond to each other in the correspondence table, it indicates that the allocation information belongs to the broadcast unit.

[0074] For example, after receiving the command information, the broadcast unit will forward the command information to the next broadcast unit, and the broadcast unit will determine whether the identifier of the allocation information in the command information is consistent with the identifier of the broadcast unit. If the identifier of the allocation information is consistent with the identifier of the broadcast unit, the allocation information is for its own use and it will be stored.

[0075] For example, if the matrix is divided into 16 thread groups and there are 4 computing units in total, then each computing unit is responsible for the calculation of 4 thread groups. Then the thread group distribution unit 203 allocates 4 thread group identifiers to each computing unit, corresponding to the 4 thread groups respectively.

[0076] In some embodiments of the present disclosure, each broadcast unit is configured to: in response to obtaining target data from a cache unit, query a mapping relationship to determine a unit identifier based on a current thread group identifier carried by the target data; determine at least some of the computing units to which the target data is broadcast based on the unit identifier; and broadcast the target data to at least some of the computing units.

[0077] For example, if the current thread group identifier carried by the target data is 1, then the unit identifier PU_id obtained by querying the mapping relationship is PU0, PU1, PU2, PU3. Then the computing units to which the target data is broadcast are computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3, thereby broadcasting the target data to computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3.

[0078] In some embodiments of the present disclosure, the allocation information further includes a mapping relationship between thread group identifiers and base address information. The base address information is allocated by the thread dispatch unit 203, and each thread group is allocated different base address information.

[0079] Figure 3 A schematic diagram illustrating a data broadcast implementation provided by at least one embodiment of the present disclosure is shown.

[0080] like Figure 3 As shown, the allocation information includes {cluster_id: base_addr, PU0, PU1, PU2, PU3}, where base_addr represents the base address of the thread group cluster_id.

[0081] In some embodiments of the present disclosure, the allocation information stored by multiple broadcast units corresponding to multiple computing units in a computing unit cluster is the same for the same thread group. That is, for the same thread group cluster_id, the base address and the computing units are the same. However, the offset address of each shared data is different.

[0082] In some embodiments of the present disclosure, each computing unit is configured to: determine a target address according to a base address and address offset information carried by the target data, and store the target data at the target address.

[0083] The address offset information is, for example, an offset address, target address = base_addr + offset_addr, where base_addr represents the base address and offset_addr is equal to the offset address. After obtaining the target address, the computing unit stores the shared data to the target address in the local storage module or static memory of the computing unit.

[0084] In some embodiments of the present disclosure, each computing unit is further configured to, in response to executing a current instruction associated with target data, provide the thread group distribution unit with the unit identifier of the computing unit and the thread group identifier of the thread group to which the current instruction belongs. For example, when computing unit PU0 executes the current instruction and the data used by the current instruction needs to be shared, computing unit PU0 provides the thread group distribution unit 203 with the unit identifier PU_id of computing unit PU0, i.e., PU_id = PU0, and the thread group identifier of the current instruction (e.g., cluster_id = 1).

[0085] The thread group distribution unit 203 is further configured to: in response to receiving the unit identifier of the computing unit (e.g., PU_id=PU0) and the thread group identifier of the thread group to which the current instruction belongs (e.g., cluster_id=1), provide the unit identifier of the computing unit to multiple broadcast units corresponding to the computing unit cluster indicated by the thread group identifier. For example, through cluster_id=1, the thread group distribution unit 203 clearly states that the computing unit cluster to which the data needs to be broadcast is the computing unit cluster assigned with thread group cluster_id=1, and the computing units included in the computing unit cluster include computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3. Then, the thread group distribution unit 203 broadcasts the unit identifier PU_id of the computing unit, i.e., PU0, to the broadcast units BK0, BK1, BK2, and BK3 corresponding to computing unit PU0, computing unit PU1, computing unit PU2, and computing unit PU3, respectively, so that each broadcast unit in the computing unit cluster clearly states that computing unit PU0 requests to broadcast the target data.

[0086] Each broadcast unit is configured to add the unit identifier PU_id provided by the thread group distribution unit 203 to its own broadcast sequence array, and each of the multiple broadcast units broadcasts the target data according to the broadcast sequence indicated by the broadcast sequence array.

[0087] For example, Figure 3 As shown, each broadcast unit stores not only the allocation information {cluster_id: base_addr, PU0, PU1, PU2, PU3}, but also the broadcast order array order, which indicates the order in which multiple computing units request to broadcast different target data. Figure 3 In the example, the broadcasting order of multiple computing units requesting to broadcast different target data is computing unit PU0, computing unit PU3, computing unit PU1, and computing unit PU2, that is, each broadcasting unit first broadcasts the target data requested by computing unit PU0, and then broadcasts the target data requested by computing unit PU3, and so on.

[0088] In some embodiments of the present disclosure, each broadcast unit is configured to: query the broadcast order array in response to obtaining target data; and broadcast the target data to the computing unit cluster where the target computing unit is located in response to the target computing unit being ranked first in the broadcast order array.

[0089] The target data may be data acquired from a cache unit and need to be shared, or may be data broadcasted by other broadcast units.

[0090] For example, when the first data currently received by the broadcast unit BK1 and provided by the cache unit is target data that needs to be shared, the broadcast unit BK1 queries the broadcast sequence array stored in itself. If the unit identifier PU_id of the computing unit carried by the first data ranks first in the broadcast sequence array, that is, the first element in the broadcast sequence array, the target data is broadcast to the computing unit cluster where the target computing unit corresponding to PU_id is located.

[0091] The broadcast order array (order) effectively resolves data transmission conflicts without requiring additional hardware, reducing processor cost and complexity. For example, during a broadcast, if broadcast unit BK2 simultaneously receives data from both broadcast units BK1 and BK3, data loss may occur. Without the constraints of the broadcast order array, additional hardware would be required to store these conflicting data.

[0092] In some embodiments of the present disclosure, each of the multiple broadcast units is further configured to: in response to the target computing unit corresponding to the broadcast unit not being the first in the broadcast order array, the broadcast unit enters a waiting state, and the waiting state is used to wait for the computing unit located before the target computing unit in the broadcast order array to complete the broadcast and then broadcast the target data.

[0093] For example, when the first data currently received by the broadcast unit BK1 and provided by the cache unit is the target data that needs to be shared, the broadcast unit BK1 queries the broadcast sequence array stored in itself. If the unit identifier PU_id=PU1 of the computing unit carried by the first data is not ranked first in the broadcast sequence array, the broadcast unit BK1 enters a waiting state to wait for the computing unit that is located before the target computing unit in the broadcast sequence array (in Figure 3 In the example, the target data is broadcast after the broadcast is completed for computing unit PU0 and computing unit PU3).

[0094] It should be noted that in the waiting state, the broadcast unit simply does not broadcast the first data corresponding to the computing unit PU1 received from the cache unit, but this does not mean that the broadcast unit is not working. The broadcast unit still broadcasts the data that needs to be broadcast received from other broadcast units.

[0095] In some embodiments of the present disclosure, each of the multiple broadcast units is further configured to: in response to completion of the target data broadcast, broadcast a completion indication signal, and delete the identification information of the computing unit executing the current instruction related to the target data from the broadcast order array.

[0096] For example, taking the broadcast unit BK1 as an example, when the data broadcast of the broadcast unit BK1 is completed, its last data will be accompanied by a completion indication signal and broadcast to other broadcast units. At the same time, the broadcast unit BK1 will also remove PU1 from the broadcast order array. When other broadcast units receive the completion indication signal, they will also remove the relevant PU_id from their own broadcast order array. In this way, the broadcast operation of the next broadcast unit can be executed. At the same time, these completion indication signals are also transmitted one level at a time in the broadcast unit until they are transmitted to the thread group distribution unit 203. The thread group distribution unit 203 will count these signals to determine whether the broadcast operations of the thread group have been completed.

[0097] In other embodiments of the present disclosure, each broadcast unit may not store the broadcast sequence array, but may include a buffer configured to store data to be broadcasted. For example, during a broadcast, when broadcast unit BK2 simultaneously receives data broadcasted by broadcast units BK1 and BK3, it stores the data broadcasted by broadcast units BK1 and BK3 in the buffer.

[0098] In these embodiments, for example, each broadcast unit is configured to: in response to first data being target data, query whether there is data to be broadcast in the buffer of an adjacent broadcast unit; in response to the presence of data to be broadcast, store the target data in the broadcast unit until there is no data to be broadcast in the buffer of the adjacent broadcast unit, at which point the target data is broadcast. This embodiment reduces time costs compared to using a broadcast sequence array.

[0099] For example, when broadcast unit BK1 receives first data provided by a cache unit as target data, it queries the caches of broadcast units BK0 and BK2 to determine whether there is data to be broadcast. For example, all data stored in the caches is data to be broadcast. If there is data in the caches, it indicates that there is data to be broadcast; if there is no data, it indicates that there is no data to be broadcast. Alternatively, in other embodiments, the caches store not only data to be broadcast but also data not to be broadcast, and a broadcast identifier is used to mark whether the data is data to be broadcast. For example, if the broadcast identifier is 1, it indicates that the data is data to be broadcast; if the broadcast identifier is 0, it indicates that the data is not data to be broadcast.

[0100] In response to the presence of data to be broadcast in the buffer, the target data is stored in the broadcast unit until the buffer of the adjacent broadcast unit no longer contains the data to be broadcast, at which point the target data is broadcast. For example, if the buffers of broadcast unit BK0 and broadcast unit BK2 do not contain the data to be broadcast, broadcast unit BK1 will broadcast the first data.

[0101] Those skilled in the art may also design other arbitration logics to resolve data conflicts, and this disclosure does not limit this.

[0102] The following combination Figure 3 Further explanation of the embodiments of the present disclosure. In some embodiments of the present disclosure, data access is divided into three phases, namely, an initialization phase, a data capture phase, and a data return phase.

[0103] During the initialization phase, the thread group distribution unit 203 determines which computational units (CUs) different execution groups are assigned to and identifies which CUs constitute a CU cluster. When creating an execution group, the PU_id and cluster_id information for the execution group are packaged together with a new allocation identifier (which can be understood as a block_id, corresponding one-to-one with the PU_id). These packaged signals are then sent to each broadcast unit.

[0104] After receiving the command information, the broadcast unit will forward it to the next broadcast unit. At the same time, it will judge the block_id information inside. If it is equal to the identifier of the broadcast unit, then the allocation information in the command information is for its own use, and it will be stored. After all the storage is completed, you can get Figure 3 The mapping relationship shown.

[0105] During the data capture phase, there is a module inside the computing unit that is specifically responsible for capturing instructions. When it finds that the captured instruction is an instruction involving data sharing or forwarding, it will send the cluster_id and PU_id information of the thread group to which the current execution group belongs to the thread group distribution unit 203. When the thread group distribution unit 203 receives this information, it will forward this data to each broadcast unit. When each broadcast unit receives this information, it will also forward the command information to the next block. At the same time, the cluster_id value is extracted from the command information to determine whether the value is in this broadcast unit. If so, the PU_id value of the command information is placed in the broadcast order array list. Then you can get Figure 3 The broadcast order array order shown in . The broadcast order array order indicates that the computing unit PU0 first captures the instruction involving data sharing or forwarding, followed by PU3, PU1, and PU2.

[0106] exist Figure 3 In the example, each computing unit is directly connected to the thread group distribution unit 203. In practice, they may be coupled one level at a time, like a broadcast unit, with data being transmitted sequentially through the computing units. Those skilled in the art may design the hardware connection relationship based on whether other hardware (e.g., data paths) in the processor is reused, and this disclosure does not limit this.

[0107] During the data return phase, when a broadcast unit receives data returned from an external source, it contains not only the data it needs but also some instruction information. (Of course, this information may not be included, and the broadcast unit may instead record all previous instructions internally.) At this point, the broadcast unit can determine whether the instruction corresponding to the returned data involves data sharing or forwarding, as well as its cluster_id and PU_id. If data sharing or forwarding is not involved, the data is returned directly to its corresponding computing unit. If data sharing or forwarding is involved, the unit determines whether the PU_id of the current computing unit matches the PU_id of the first data item stored in its internal order list. If so, the unit sends the data directly to the current computing unit. The unit also copies the data and sends it to other broadcast units. If the PU_id of the current computing unit differs from the PU_id of the first data item stored in its internal order list, it indicates that other instructions preceded it. To prevent data interference, the unit enters a waiting state.

[0108] Therefore, in some embodiments of the present disclosure, the thread group distribution unit 203 first distributes multiple thread groups to multiple adjacent computing units, and then sends the cluster_id, relevant computing unit information (e.g., PU_id), and base address information related to the thread group to each relevant broadcast unit. The computing unit information allows the broadcast unit to clearly identify the target computing unit when broadcasting data. When the data broadcast by other broadcast units reaches this broadcast unit, this computing unit can obtain the final address of the target based on the address offset information transmitted by other broadcast units and the base address base_addr of the thread group, and store the data in a local relevant location. When the execution group executes an instruction that needs to be broadcast, it will send the PU_id of this computing unit and the cluster_id of the current thread group to the thread group distribution unit. The thread group distribution unit will then send the PU_id to all broadcast units corresponding to the thread group, and the broadcast unit will place the obtained PU_id into its own broadcast order array. When the broadcast unit receives data and broadcasts it, it will broadcast it in the order of this broadcast order array.

[0109] For example, when broadcast unit BK3 first receives data that can be broadcast, it checks its broadcast order array. If it finds PU2 at the top of the list, it pauses its own broadcast operation and waits until broadcast unit BK2 completes its broadcast operation before executing its own. When broadcast unit BK2 receives data that can be broadcast, it finds PU2 at the top of the broadcast order array and begins its broadcast operation, simultaneously sending data to computing unit PU2 and broadcast units BK1 and BK3. In the next time period, if broadcast unit BK1 receives broadcast data from broadcast unit BK2 and is currently performing a non-broadcast data transmission, it interrupts its current operation and sends the broadcast data to broadcast unit BK1, while continuing to broadcast the data to broadcast unit BK0. When broadcast unit BK1 completes its data broadcast, its final data entry is broadcast to the other broadcast units with a completion indicator. PU1 is also removed from the broadcast order array. When other broadcast units receive the completion signal, they also remove the relevant PU information from their own broadcast order arrays. This allows the next broadcast unit to proceed. Meanwhile, the completion signal is passed through the broadcast units one level at a time until it reaches the thread group distribution unit.

[0110] Figure 4 A schematic diagram of a combination of two computing unit clusters provided by at least one embodiment of the present disclosure is shown.

[0111] exist Figure 1B In the example, suppose that reading data from A0 or B0 during the computation of C0 requires n instructions. In the original logic, C0 would need to send 2n requests to the buffer memory. If each request requires m time cycles to return data (usually m is less than or equal to 16), then the buffer memory will need 2n × m time cycles to return the data. n and m are positive integers.

[0112] For example, in Figure 4 In the example (a), parts C0, C1, C2, and C3 share data B0. Four thread groups each perform computations on parts C0, C1, C2, and C3, and these four thread groups are assigned to four adjacent compute units. For example, part C0 is executed by compute unit PU0, part C1 is executed by compute unit PU1, part C2 is executed by compute unit PU2, and part C3 is executed by compute unit PU3. Computation units PU1, PU2, PU3, and PU4 form a compute resource cluster.

[0113] When reading data from B0, each compute unit can read 1 / 4×n requests, then broadcast the shared data to multiple broadcast units. Therefore, each compute unit requires a total of 5 / 4×n instructions, while the buffer memory takes 5 / 4×n×m cycles to return the data. Compared to the original instructions, the actual number of cycles transmitted within the broadcast unit remains unchanged, and the number of cycles required for broadcasting between multiple broadcast units is almost negligible. Therefore, the performance optimization can improve by approximately (2n×m – 5 / 4×n×m) / 2n×m = 37.5%. Furthermore, there is a bias in the number of data requests for matrix A and matrix B. From the perspective of multiple broadcast units, matrix A receives more requests than matrix B, and its probability of being replaced across multiple broadcast units is also lower. Alternatively, if matrix B is sufficiently wide, multiple broadcast units can effectively utilize matrix A.

[0114] For example, in Figure 4 In the example (b), parts C0 and C1 share B0 data, parts C4 and C5 share B1 data, parts C0 and C4 share A0 data, and parts C1 and C5 share A1 data. For example, part C0 is executed by computing unit PU0, part C1 is executed by computing unit PU1, part C2 is executed by computing unit PU2, and part C3 is executed by computing unit PU3. Computing units PU1, PU2, PU3, and PU4 form a computing resource cluster.

[0115] For example, in Figure 4 In example (b), when reading data, C0 can only read data from A0 or B0. Each compute unit can then read n requests, with the remaining requests broadcasted by other units. Therefore, each compute unit requires n instructions, and the buffer memory requires n × m cycles to return data. Compared to the original instructions, each broadcast unit must broadcast data that it doesn't need (for example, compute unit PU1 only needs data from A1 and B0, but it also broadcasts data from A0 and B1, and the same applies to other compute units). The broadcast unit's time consumption doubles. However, the number of L1 and L2 caches in the buffer memory is typically quite different. When returning data, the L1 cache can only return data for some compute units, so the performance loss caused by the broadcast unit's forwarding is not significant. Therefore, the performance improvement is less than (2n × m – n × m) / 2n × m = 50%. Further performance improvement can be achieved by adding caches instead of broadcasting sequential arrays.

[0116] In some embodiments of the present disclosure, the command information provided by the thread group distribution unit can enable the broadcast unit to specify some computing units in the computing unit cluster when broadcasting data, rather than broadcasting to all computing units in the computing unit cluster, thereby further improving performance.

[0117] In some embodiments of the present disclosure, at least some computing units are adjacent, and multiple broadcast units corresponding to at least some computing units are coupled in sequence, and at least one of the multiple broadcast units corresponding to at least some computing units is coupled to a thread distribution unit.

[0118] For example, the computing units included in the computing unit cluster are adjacent, and the broadcast units corresponding to the computing units included in the computing unit cluster are coupled in sequence, and the broadcast unit closest to the thread distribution unit is coupled to the thread group distribution unit. Figure 3 This connection method can save hardware costs.

[0119] In some embodiments of the present disclosure, multiple broadcast units are located in the first-level cache (L1 cache). In this embodiment, the first-level cache is improved so that it not only has storage functions but also broadcast functions. For example, the data transmission interface of the first-level cache is modified to enable it to broadcast data in different directions. In this embodiment, no additional structure is required, and the location of multiple broadcast units in the first-level cache is more easily implemented.

[0120] In other embodiments of the present disclosure, the multiple broadcast units may also be independent structures. In this embodiment, there is no need to modify the first-level cache, and the compatibility is better.

[0121] The processor provided by the embodiments of the present disclosure can effectively reduce the burden on the buffer memory and improve the execution efficiency of the GPGPU or CPU.

[0122] Another aspect of the present disclosure provides a data access method, which is applied to the processor provided in any embodiment of the present disclosure.

[0123] Figure 5 A flowchart of a data access method provided by at least one embodiment of the present disclosure is shown.

[0124] like Figure 5 As shown, the data access method includes steps S501 to S502.

[0125] Step S501: In response to a target broadcast unit among multiple broadcast units acquiring target data, determining a computing unit cluster where a target computing unit corresponding to the target broadcast unit is located.

[0126] Step S502: Broadcast target data to the computing unit cluster.

[0127] The data access method broadcasts target data through multiple broadcast units, and does not require each computing unit to read the target data from the buffer memory separately, thereby effectively reducing the burden of the buffer memory and improving the execution efficiency of the GPGPU or CPU.

[0128] For steps S501 and S502 , please refer to the above description.

[0129] In some embodiments of the present disclosure, each broadcast unit of the processor is configured to: in response to obtaining first data from the cache unit, determine whether the first data is target data based on the data type of the first data; and in response to the first data being target data, broadcast the target data to the computing unit cluster where the target computing unit is located.

[0130] In some embodiments of the present disclosure, the processor further includes: a thread group distribution unit, the thread group distribution unit being configured to: distribute multiple thread groups that share target data to at least some of the computing units respectively, and each computing unit in at least some of the computing units being configured to execute instructions in the thread group in the multiple thread groups that is distributed to each computing unit.

[0131] The computing unit and broadcasting unit can be hardware, software, firmware, or any feasible combination thereof. For example, the computing unit and broadcasting unit can be dedicated or general-purpose circuits, chips, or devices. The embodiments of this disclosure do not limit the specific implementation of each of the above-mentioned units. The computing unit and broadcasting unit correspond to the various steps of the data access method. For details about the data access method, please refer to the relevant description of the processor and will not be repeated here.

[0132] Figure 6 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 6 As shown, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 610 is used to execute the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by the processor 610, one or more steps in the data access method described above can be performed. The memory 620 and the processor 610 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0133] The processor 601 may be the processor provided by any embodiment of the present disclosure.

[0134] For example, the processor 610 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 610 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 600 to perform desired functions.

[0135] For example, the memory 620 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 610 may execute one or more computer program modules to implement various functions of the electronic device 600. The computer-readable storage medium may also store various applications and various data, as well as various data used and / or generated by the applications.

[0136] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 600 can be referred to the above description of the processor, which will not be repeated here.

[0137] Figure 7 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 700 is suitable for implementing the data access method provided in the embodiments of the present disclosure. The electronic device 700 may be a terminal device, etc. It should be noted that, Figure 7 The electronic device 700 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0138] like Figure 7 As shown, the electronic device 700 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 710, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 720 or a program loaded from a storage device 780 to a random access memory (RAM) 730. The processing device 710 may be, for example, the processor provided in any embodiment of the present disclosure.

[0139] Various programs and data required for the operation of the electronic device 700 are also stored in the RAM 730. The processing device 710, the ROM 720, and the RAM 730 are connected to each other via a bus 740. An input / output (I / O) interface 750 is also connected to the bus 740.

[0140] Typically, the following devices may be connected to the I / O interface 750: an input device 760 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 770 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 780 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 790. The communication device 790 may allow the electronic device 700 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 7 The electronic device 700 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 700 may instead implement or possess more or fewer devices.

[0141] There are a few points to note:

[0142] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0143] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0144] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A processor, comprising: a plurality of computing units, wherein the plurality of computing units are divided into at least one computing unit cluster, and each computing unit cluster includes at least some computing units in the plurality of computing units; A plurality of broadcast units, each of the plurality of broadcast units corresponding one to one to the plurality of computing units, wherein each of the plurality of broadcast units is configured as follows: In response to acquiring the target data, the target data is broadcast to the computing unit cluster where the target computing unit is located, so that each computing unit in the computing unit cluster stores the target data, wherein the target computing unit is the computing unit corresponding to the broadcasting unit among the multiple computing units.

2. The processor according to claim 1, wherein: Each broadcast unit is configured as follows: In response to acquiring first data from the cache unit, determining whether the first data is the target data according to a data type of the first data; and In response to the first data being the target data, the target data is broadcast to the computing unit cluster where the target computing unit is located.

3. The processor according to claim 2, wherein: Each of the plurality of broadcasting units is further configured to: In response to the first data not being the target data, the first data is provided to the target computing unit.

4. The processor according to claim 3, wherein: Each of the broadcasting units is further configured to: When the first data is not the target data and, during the provision of the first data to the target computing unit, the broadcasting unit receives second data broadcast by another broadcasting unit, the provision of the first data to the target computing unit is suspended, and the second data is provided to the target computing unit and broadcast.

5. The processor of claim 1 , further comprising: A thread group distribution unit, wherein the thread group distribution unit is configured as follows: Allocate the plurality of thread groups sharing the target data to the at least part of the computing units respectively; Each computing unit in the at least some of the computing units is configured to execute instructions in a thread group in the plurality of thread groups that is assigned to each computing unit. The processor according to claim 5 , wherein: The thread group distribution unit is further configured as: creating at least one execution group for each of the plurality of thread groups, wherein each execution group includes allocation information and an identifier of the allocation information; and Providing the allocation information and the identifier of the allocation information to the plurality of broadcast units, each of the plurality of broadcast units being configured to: In response to the identification of the allocation information matching the identification of the broadcast unit itself, the allocation information is stored, and the target data is broadcast according to the allocation information.

7. The processor according to claim 6, wherein: The allocation information includes a mapping relationship between the thread group identifier of the thread group to which each execution group belongs and the unit identifiers of at least some of the computing units. Each of the plurality of broadcast units is configured as: In response to obtaining the target data from the cache unit, querying the mapping relationship to determine the unit identifier according to the current thread group identifier carried by the target data; determining, according to the unit identifiers, the at least some computing units to which the target data is broadcast; as well as The target data is broadcast to at least some of the computing units.

8. The processor according to claim 7, wherein: The allocation information also includes a mapping relationship between the thread group identifier and the base address. Each of the at least some computing units is configured as: A target address is determined according to the base address and address offset information carried by the target data, and the target data is stored at the target address.

9. The processor according to claim 6, wherein: Each of the plurality of computing units is further configured to: In response to executing a current instruction associated with the target data, providing the thread group distribution unit with a unit identifier of the computing unit and a thread group identifier of the thread group to which the current instruction belongs, The thread group distribution unit is further configured as: In response to receiving the unit identifier of the computing unit and the thread group identifier of the thread group to which the current instruction belongs, providing the unit identifier of the computing unit to multiple broadcast units corresponding to the computing unit cluster indicated by the thread group identifier, Each of the plurality of broadcast units is configured as: The unit identifier provided by the thread group distribution unit is added to the broadcast sequence array of the broadcast unit itself, wherein each of the multiple broadcast units broadcasts the target data according to the broadcast sequence indicated by the broadcast sequence array.

10. The processor of claim 9, wherein: Each of the plurality of broadcast units is configured as: In response to acquiring the target data, querying the broadcast order array; In response to the target computing unit being ranked first in the broadcast order array, the target data is broadcast to the computing unit cluster where the target computing unit is located.

11. The processor according to claim 10, wherein: Each of the plurality of broadcasting units is further configured to: In response to the target computing unit corresponding to the broadcast unit not being in the first position in the broadcast sequence array, the broadcast unit enters a waiting state, which is used to broadcast the target data after the computing unit located before the target computing unit in the broadcast sequence array is broadcasted.

12. The processor according to claim 9, wherein: Each of the plurality of broadcasting units is further configured to: In response to the target data being broadcasted, a broadcast completion indication signal is generated, and identification information of a computing unit executing a current instruction related to the target data is deleted from the broadcast sequence array.

13. The processor according to claim 2, wherein: The at least some computing units are adjacent to each other, and the multiple broadcast units corresponding to the at least some computing units are coupled in sequence, and at least one of the multiple broadcast units corresponding to the at least some computing units is coupled to the thread dispatching unit.

14. The processor of claim 2, wherein: Each of the plurality of broadcast units includes a buffer configured to store data to be broadcasted. Each of the plurality of broadcast units is configured as: In response to the first data being the target data, querying whether the to-be-broadcasted data exists in a buffer in a broadcast unit adjacent to the broadcast unit; In response to the existence of the data to be broadcasted, the target data is stored in the broadcast unit until the data to be broadcasted no longer exists in the buffer in the adjacent broadcast unit, and the target data is broadcasted.

15. The processor of claim 1, wherein: The plurality of broadcast units are located in a first level cache.

16. A data access method, applied to the processor according to any one of claims 1 to 15, the method comprising: In response to a target broadcast unit among the plurality of broadcast units acquiring target data, determining a computing unit cluster where a target computing unit corresponding to the target broadcast unit is located; as well as The target data is broadcast to the computing unit cluster.

17. An electronic device comprising the processor according to any one of claims 1 to 15.

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