Very low frequency circuit frequency response parameter calibration system

Abstract

The invention relates to a very-low-frequency circuit frequency response parameter calibration system, which is suitable for high-precision frequency response calibration of a signal processing circuit working in a frequency range of 300 Hz to 100 kHz. The system comprises a signal acquisition module and an FPGA, the signal acquisition module comprises three synchronous acquisition channels, two output channels respectively connected with a to-be-calibrated circuit, and GPIO (General Purpose Input / Output) for outputting a calibration signal by the FPGA, and the FPGA is configured to generate the calibration signal after receiving a configuration instruction of an upper computer system; the calibration signal is divided into three paths: one path enters the very low frequency signal acquisition module to serve as a reference signal for calibration comparison; the other two paths are respectively injected into two input channels of the to-be-calibrated circuit to drive the to-be-calibrated circuit to generate corresponding outputs; three sampling channels of the very low frequency signal acquisition module are synchronously controlled, data acquisition is started, an isochronous sampling task is completed, and synchronism of three paths of data in a time domain is ensured; after sampling is completed, three-channel data are preprocessed, and then the preprocessed data are uploaded to an upper computer system for visualization processing.

Description

Technical Field

[0001] This invention belongs to the field of very low frequency (VLF) fluctuation detection and application technology, specifically to a VLF circuit frequency response parameter calibration system. This system is used to improve the frequency response accuracy and system stability of VLF signal detection equipment in the VLF band. It is suitable for high-precision signal calibration and performance evaluation in geophysical exploration, space environment monitoring, bioelectrical signal analysis, and other VLF signal application scenarios. Background Art

[0002] In extremely low frequency (ELF / VLF) signal detection and its applications, the frequency response characteristics of electronic systems have a critical impact on overall signal quality and data accuracy. This frequency band, typically covering approximately 0.1 Hz to 30 kHz, features slow signal fluctuations and extremely weak energy, making it highly susceptible to environmental noise, electromagnetic interference, geomagnetic disturbances, and system noise floor. Accurate measurement and analysis within this frequency band requires stable and predictable frequency response characteristics across all links in the signal acquisition chain (such as preamplifiers, voltage followers, filtering, and analog-to-digital converters). Traditional calibration methods often rely on manually injecting standard excitation signals for point-by-point comparison. However, in the VLF range, calibration signal sources are difficult to generate, response times are long, and the system noise contribution is high. This results in inefficient and unstable calibration processes, making them difficult to meet the scientific and engineering requirements for high sensitivity and long-term operation.

[0003] Currently, common frequency response test systems on the market are primarily designed for electronic circuits operating in the audio band and above. Their capabilities for testing responses to very low frequency (VLF) signals are limited. This is especially true for signals with long periods, low amplitudes, and non-steady-state fluctuations. Traditional testing methods like frequency sweeps and stimulus response analysis are prone to problems such as insufficient accuracy and severe noise masking. Furthermore, during long-period measurements, environmental changes, component drift, and power supply fluctuations can cause the system's frequency response characteristics to dynamically change over time. Inaccurate frequency response models can directly lead to deviations in amplitude and phase estimates, compromising the reliability of the entire signal processing chain. For example, in geophysical exploration, VLF signals are used to detect changes in underground media or ground stress activity. These subtle characteristics require high-precision frequency response control to accurately extract them. Therefore, there is an urgent need to develop specialized frequency response parameter calibration techniques suitable for this frequency band to improve the accuracy of detection equipment and the robustness of the system.

[0004] With the widespread application of very low frequency detection technology in multidisciplinary fields, such as space environment monitoring, bioelectric signal research, structural health monitoring, power system fault analysis, etc., higher requirements are placed on signal quality, data stability and repeatability. Complex application scenarios pose challenges to the stability and consistency of circuit frequency response. Traditional static calibration methods are difficult to deal with sensor performance differences, parameter drift caused by environmental disturbances, and accuracy consistency issues in multi-channel parallel operations of the system. Therefore, there is an urgent need for a frequency response parameter calibration technology with an automated control strategy to achieve accurate identification and correction of circuit response characteristics. The implementation of this technology will not only help improve the overall performance of the measurement system in very low frequency applications, but also provide solid technical support for the standardization, modularization and intelligentization of very low frequency detection equipment. Summary of the Invention

[0005] The present invention provides a very low frequency circuit frequency response parameter calibration system, which is suitable for performing high-precision frequency response calibration on a signal processing circuit operating in the frequency range of 300 Hz to 100 kHz.

[0006] Firstly, a very low frequency circuit frequency response parameter calibration system is proposed, including a very low frequency signal acquisition module and an FPGA. The very low frequency signal acquisition module includes three synchronous acquisition channels, wherein the first and second channels of the three synchronous acquisition channels are respectively used to connect to the two output channels of the circuit to be calibrated, and the third channel is connected to the GPIO of the FPGA output calibration signal. The FPGA is configured as follows: after receiving the configuration instruction of the computer system, the FPGA generates a calibration signal, and the calibration signal is divided into three channels: one channel enters the very low frequency signal acquisition module as a reference signal for calibration comparison; the other two channels are respectively injected into the two input channels of the circuit to be calibrated to drive them to generate corresponding outputs; the FPGA synchronously controls the three sampling channels of the very low frequency signal acquisition module, starts data acquisition and completes the isochronous sampling task to ensure the synchronization of the three channels of data in the time domain; after the sampling is completed, the FPGA preprocesses the three-channel data, and then uploads the preprocessed data to the computer system for visualization processing.

[0007] The FPGA preprocesses the three-channel data by first performing a fast Fourier transform or a short-time Fourier transform, followed by amplitude extraction, phase calculation, and fundamental frequency point identification.

[0008] The calibration signal is a square wave signal or an m-sequence.

[0009] In a second aspect, a host computer is proposed, comprising: a processor; a memory; and one or more program modules, wherein the one or more program modules are stored in the memory and configured to be executed by the processor, and the one or more program modules include instructions for performing the following steps: obtaining a parameter range of a calibration process set by a user; sending a configuration instruction to the FPGA of the very low frequency circuit frequency response parameter calibration system, so that the FPGA generates a calibration signal according to the set parameter range, and preprocesses the data collected by three sampling channels; and obtaining the data preprocessed by the FPGA and performing visualization processing.

[0010] The parameter range includes the start and end range of the calibration frequency, the frequency interval mode, the sampling time of each frequency point, and the calibration signal amplitude.

[0011] The visualization processing includes: based on the fundamental frequency point identification results, in the spectrum results of the three synchronous acquisition channels, energy integration is performed in a certain bandwidth near the frequency point to obtain the signal strength, and then the signal strength and phase information of the first channel and the second channel are differentially analyzed with the reference signal collected by the third channel to extract the frequency response characteristic parameters of the circuit to be calibrated for the input signal at this frequency; by comparing the first channel and the second channel signals with the reference signal respectively, the frequency response difference curve of the circuit to be calibrated at this frequency point is constructed; after the frequency response parameters of all frequency points are extracted, a set of frequency response curves is formed.

[0012] In a third aspect, a readable storage medium is provided. The readable storage medium stores a program that, when executed on a host computer, performs the following steps: obtaining a calibration parameter range set by a user; sending configuration instructions to an FPGA of the very low frequency circuit frequency response parameter calibration system, causing the FPGA to generate a calibration signal within the set parameter range; and preprocessing data collected by the three sampling channels; and obtaining and visualizing the data preprocessed by the FPGA. The specific method for visualization is described in the second aspect above.

[0013] The very low frequency circuit frequency response parameter calibration system proposed in the present invention has significant advantages in terms of structural design, function implementation and performance. Traditional frequency response calibration mostly relies on manual comparison of single-channel serial reference sources, or adopts simplified modeling methods, which are difficult to cope with the characteristics of very low frequency signals such as weak energy, slow response, and high noise ratio. In the existing technology, it is often impossible to achieve simultaneous measurement of input and output signals, resulting in the introduction of large systematic errors in frequency response extraction, especially in multi-channel measurement or dynamic calibration scenarios, where the accuracy and stability are insufficient. The system of the present invention adopts a three-channel synchronous acquisition structure, in which one channel is used to acquire the input reference signal, and the other two channels respectively acquire the dual-channel output of the calibrated circuit, which can perform closed-loop response analysis on the signal path at the same time and frequency point, significantly improving the measurement accuracy and consistency of frequency response modeling. At the same time, the excitation control and data processing logic are realized through FPGA, and the acquisition, comparison, and analysis processes are integrated into the automated process, effectively improving the calibration efficiency, and supporting frequency scanning response analysis and online real-time calibration. In addition, this system supports batch equipment calibration, frequency point customization, and graphical presentation of host computer responses. It has good scalability and engineering application value and is particularly suitable for fields such as geophysics, electromagnetic detection, and biomedicine that require extremely high VLF signal calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of a very low frequency circuit calibration system according to an embodiment of the present invention.

[0015] Figure 2 is a flow chart of VLF circuit calibration according to an embodiment of the present invention.

[0016] Figure 3 is a signal source generated by an FPGA according to an embodiment of the present invention.

[0017] Figure 4 It is a calibration channel signal collected by FPGA according to an embodiment of the present invention.

[0018] Figure 5 is a time-frequency diagram of a reference signal and a circuit response signal according to an embodiment of the present invention.

[0019] Figure 6 ] is an amplitude-frequency response result of a reference signal and a circuit response signal according to an embodiment of the present invention.

[0020] Figure 7 1 is a frequency response curve result of the channel to be calibrated according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Figure 1 The block diagram of a very low frequency circuit frequency response parameter calibration system (hereinafter referred to as the "calibration system") is shown. Figure 1 As shown in the figure, the system consists of a very low frequency (VLF) signal acquisition module, an FPGA control module, and a host computer. The VLF signal acquisition module has a three-channel structure, and a bidirectional communication link is established between the FPGA control module and the host computer for system configuration and data transmission. The calibration signal (i.e., the excitation signal) is injected into the input of the circuit to be calibrated and the acquisition module through independent paths, forming a closed-loop measurement structure, ensuring consistent and real-time data comparison.

[0022] The very low frequency circuit to be calibrated is the test object and typically includes two signal processing channels, one for receiving the calibration signal generated by the FPGA control module and the other for outputting the signal data after the circuit to be calibrated responds. Each channel may include modules such as preamplification, filtering, and impedance matching. During the calibration process, both channels simultaneously receive the same standard excitation signal to ensure the synchronization and comparability of the response parameters. The circuit structure of this module is generally complex, and the frequency response characteristics may be affected by factors such as ambient temperature drift and power supply disturbances. Therefore, the system of the present invention requires periodic or real-time response correction.

[0023] The very low frequency (VLF) signal acquisition module is a key measurement component in the system. It features three synchronized acquisition channels, connected to the two output channels of the circuit being calibrated (Channel 1 and Channel 2) and the direct output channel of the calibration signal source generated by the FPGA control module (Channel 3). This module implements high-precision analog-to-digital conversion (ADC) with 16- or 24-bit sampling accuracy, effectively suppressing the noise floor, and offering microsecond-level synchronization between channels to ensure isochronous acquisition and processing of weak signals. The three-channel design offers the advantage of not only capturing the response of the circuit being calibrated but also enabling real-time comparison with the input signal itself (i.e., the stimulus signal), thereby eliminating measurement errors caused by uncertainty at the stimulus end.

[0024] The FPGA control module is responsible for system logic coordination, data preprocessing, and communication scheduling. This module receives data streams from the three-channel acquisition module. During the calibration process, the FPGA controls the frequency switching of the calibration signal according to a preset sequence, organizes the sampling process, and calculates the frequency response function of each channel in real time. Its core processing includes functional modules such as synchronous sampling control, fast Fourier transform (FFT), phase-lock detection, and gain-phase difference calculation. The processing results are transmitted to the host computer via the FPGA, enabling online response evaluation and storage. Furthermore, the FPGA serves as a signal source in this system, and the generated calibration signal is simultaneously output via GPIO to the circuit to be calibrated (channels 1 and 2) and the acquisition module (channel 3).

[0025] The three-channel signals acquired in the time domain (including the output signal of the circuit under calibration and the reference signal) are converted to the frequency domain to extract the signal's frequency components. Using FFT, the injection frequency of the calibration signal (e.g., the fundamental frequency and harmonics of a square wave) can be determined, and the primary frequency components of the output signal of the circuit under test can be isolated. In the frequency domain, FFT directly obtains the signal's amplitude and phase spectra. By extracting the amplitude, the output strength (e.g., voltage amplitude) of the circuit under calibration at a specific frequency is quantified. By calculating the phase, the phase offset of the test signal relative to the reference signal is determined, providing data for subsequent phase difference analysis. Using FFT to locate the signal's fundamental frequency (main frequency), harmonic interference is eliminated, ensuring that subsequent analysis focuses on the target frequency (e.g., the injection frequency of the calibration signal). Phase-locked detection technology synchronizes the test signal with the reference signal (calibration signal), suppressing noise and extracting signal components at the same frequency as the reference signal. The phase-locked loop (PLL) feedback mechanism is adjusted in real time to ensure the system can adapt to dynamic changes in the calibration signal frequency (e.g., phase tracking during frequency sweeps).

[0026] By calculating the gain difference (amplitude ratio) and phase difference (phase offset) between the output signal of the circuit to be calibrated and the reference signal, the frequency response function of the circuit to be calibrated at a specific frequency point can be constructed.

[0027] The host computer serves as the system's human-computer interface, responsible for system configuration and data visualization. Users can use the interface to set parameters such as the calibration frequency range, sampling length, and channel selection, and start or stop the calibration process. After receiving real-time data uploaded by the FPGA, the host computer automatically analyzes the results and generates charts, including gain response curves and phase response curves. The data can also be saved as structured frequency response model files for subsequent error compensation or performance tracking. The host computer can also remotely connect to external databases or calibration signal sources, improving system scalability and manageability.

[0028] The calibration signal input path generated by the FPGA provides a highly stable, frequency-controllable reference signal for the entire system. This signal is split into three paths: one path enters the acquisition module via channel 3, serving as a reference; the other two paths are injected into the two input channels of the circuit being calibrated, driving them to produce corresponding outputs. This three-channel design allows the system to simultaneously acquire and compare input and output signals, eliminating measurement deviations caused by factors such as time delay and amplitude instability, thereby achieving true dynamic calibration.

[0029] Figure 2 The method of calibrating the frequency response parameters of a very low frequency circuit using the calibration system is demonstrated.

[0030] 2.1. The host computer first sets the parameter range for the entire calibration process, including the start and end range of the calibration frequency, the frequency spacing mode (such as logarithmic or linear distribution), the sampling duration for each frequency point, the excitation amplitude, the circuit channel number, etc. Once the settings are complete, the host computer sends a configuration command to the FPGA to set the calibration signal mode parameters.

[0031] 2.2 After receiving instructions from the host computer, the FPGA module controls the signal source to generate a square wave excitation signal at the target frequency according to the set pattern. This excitation signal, which serves as a standard calibration signal, is output through the GPIO port and is divided into three channels: two of which serve as excitation signals and are injected into the first and second channels of the circuit to be calibrated, respectively, to drive them to generate response signals. The third channel is directly input into the third channel of the signal acquisition module and serves as a reference signal for calibration and comparison.

[0032] Considering that GPIO can only output high and low levels, it is necessary to discuss the form of the excitation signal. There are mainly two feasible solutions: Solution 1: Generate a square wave frequency sweep signal with specified parameters. Starting from the lower cutoff frequency, generate a 50% duty cycle square wave signal frequency-by-frequency, either linearly or logarithmically. In this solution, since the square wave signal consists of a fundamental and its harmonics, after obtaining the reference signal and response signal, the fundamental frequency signal must be extracted from the signal spectrum and the signal strength obtained by energy integration. Due to the complexity of the calculation, it often requires processing on a host computer to obtain the calibration result. However, the advantage is that the signal frequency points are discrete and easy to extract, are minimally affected by the transmitter clock accuracy, and can accurately measure the phase-frequency characteristics of the signal to be calibrated. Solution 2: Generate a pseudo-random sequence of a specific order (such as an M sequence) at a specified sampling rate. This solution utilizes the white noise properties of the M sequence. After performing an N-point FFT on an N-order M sequence, its amplitude-frequency characteristic remains constant. Therefore, performing an FFT on the response signal directly yields the amplitude-frequency characteristic of the signal to be calibrated. Due to its simple calculation method, the final calibration result can be calculated directly using the FPGA. Furthermore, the sampling rate and calibration frequency limits can be increased, and calibration time is shortened. However, this method requires very high clock accuracy from the transmitter, and is often only applicable to devices with the same transmitter and receiver. Furthermore, it cannot accurately measure the phase-frequency characteristic. Based on comprehensive considerations, the first signal generation solution (square wave swept frequency signal solution) is recommended.

[0033] 2.3. The circuit being calibrated receives the standard stimulus signal and generates an output response signal based on its own frequency response characteristics. This output signal is fed into the acquisition module via the first and second channels, while the reference signal enters the acquisition module via the third channel. At this point, the FPGA synchronously controls the acquisition module's three sampling channels, initiating data acquisition and completing isochronous sampling, ensuring synchronization of the three data channels in the time domain.

[0034] 2.4. After sampling, the FPGA preprocesses the three-channel data, performing a fast Fourier transform (FFT) or short-time Fourier transform (STFT), followed by amplitude extraction, phase calculation, and frequency identification. The preprocessed data is then uploaded to the host computer for further processing and calculation.

[0035] 2.5. The preprocessed data results are uploaded to the host computer, which further visualizes the sampling results. First, based on the fundamental frequency point identification results, the host computer integrates the energy within a certain bandwidth near the frequency point in the spectrum results of the three sampling channels to obtain signal strength. Then, the signal strength and phase information of the first and second channels are differentially analyzed with the reference signal collected by the third channel to extract the frequency response characteristic parameters of the circuit under test, such as gain, phase offset, and group delay, for the input signal at that frequency. By comparing the first and second channel signals with the reference signal, the host computer constructs a frequency response difference curve for the circuit to be calibrated at that frequency point. This curve reflects the amplitude-frequency and phase-frequency response characteristics of the circuit at the current frequency, providing a basis for subsequent error compensation or performance adjustments.

[0036] 2.6 The above process constitutes a complete calibration step for a single frequency point. The system automatically repeats these steps in a predetermined frequency sweep sequence until the response parameters for all frequency points are extracted. Ultimately, the host computer will generate a complete set of frequency response curves, which can be further fitted to obtain a system response model or derive parameter compensation tables for system compensation, anomaly monitoring, or automatic identification.

[0037] The present invention also provides an embodiment of a host computer. The host computer includes a processor and a memory. The memory is configured to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor is configured to execute the non-transitory computer-readable instructions. When the processor executes the non-transitory computer-readable instructions, steps 2.1 and 2.5 of the calibration method are performed. The memory and processor may be interconnected via a bus system and / or other connection mechanisms.

[0038] For example, a processor can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. The processor can be a general-purpose processor or a special-purpose processor that can control other components in the computer to perform desired functions.

[0039] For example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor may execute the one or more computer program modules to implement various functions of the computer.

[0040] The present invention further provides a readable storage medium for storing a program that, when executed by a host computer, implements steps 2.1 and 2.5 of the calibration method described above. When the software program in the host computer of the present invention is sold or used as a standalone product, it can be stored in a readable storage medium. For details regarding the storage medium, refer to the description of the host computer's memory above and will not be repeated here.

[0041] Application examples: In this embodiment, the FPGA control module generates a linearly swept square wave signal with a frequency range of 100 Hz to 100 kHz. The sweep period is set to 1.0 second to ensure that the entire frequency band is covered within the specified time. The generated square wave signal is output through a GPIO pin and directly sampled through a third sampling channel to serve as a standard reference signal. Figure 3 The figure shows the waveform of the standard reference signal in the time domain. The periodic characteristics that change linearly with time can be clearly observed, reflecting the continuous change process of the square wave frequency from low to high.

[0042] In order to achieve dynamic evaluation of the system frequency response, this embodiment selects a typical first-order RC low-pass filter as the circuit to be calibrated. After the swept square wave signal output by the FPGA passes through the low-pass filter circuit, the signal is modulated by its frequency characteristics, resulting in a response change. The signal processed by the circuit is collected by the first sampling channel and its waveform is as follows: Figure 4 As shown in the figure, it can be clearly seen that the amplitude envelope of the output waveform shows a decaying trend over time, especially in the high frequency band, where the energy of the output signal drops rapidly, which is consistent with the low-pass filter's suppression characteristics for high-frequency signals.

[0043] In order to further analyze the energy distribution of the reference signal and the response signal as it changes with frequency, short-time Fourier transform (STFT) is used to perform time-frequency analysis on the two signals. Figure 5The time-frequency plots of the reference signal and the response signal are shown. As can be seen from the plots, the reference signal exhibits an ideal linear frequency growth trajectory, with its frequency components evenly distributed over time. In contrast, the response signal exhibits a significant decrease in signal energy in the high-frequency region, indicating that the high-frequency components are effectively attenuated after filtering. This result reflects the frequency-selective response characteristics of the circuit under test from a time-frequency perspective.

[0044] Furthermore, for each moment in the time-frequency diagram, its main frequency (i.e., fundamental frequency f) is identified, and a fixed bandwidth (e.g., ±50Hz, total bandwidth 100Hz) region is selected near this frequency, and the energy integral value within this frequency band is calculated as the signal amplitude index A at the current moment. As the frequency sweep process is completed, the amplitude values corresponding to each frequency point in the entire frequency sweep cycle can be aggregated, and the frequency response curves of the reference signal and the response signal can be drawn separately, as shown in Figure 2. Figure 6 As shown in the figure, the reference signal maintains a relatively balanced amplitude distribution across the entire frequency band, while the response signal exhibits a significant attenuation trend in the high-frequency region, further verifying the low-pass filtering characteristics of the RC circuit under test.

[0045] Finally, by taking the difference between the two frequency response curves, we can obtain the amplitude change of the response signal relative to the reference signal at each frequency point. This difference represents the frequency response function A(f) of the circuit to be calibrated. Figure 7 The resulting circuit amplitude-frequency response curve (f, A) is shown. The figure visually demonstrates that the RC circuit's gain approaches 0 dB in the low-frequency region. As the frequency increases, the gain gradually decreases, reaching an attenuation of approximately -25 dB at 100 kHz, exhibiting a typical first-order low-pass response. This result is highly consistent with the theoretical model, verifying that this system extracts the circuit's frequency response characteristics with high accuracy and consistency. The calibration results not only truly reflect the circuit's frequency selectivity but also serve as an important basis for subsequent system response compensation, digital modeling, and error correction. This further demonstrates the effectiveness and practical value of this invention in low-frequency circuit frequency response calibration.

[0046] This invention primarily addresses the need for high-precision extraction and modeling of the frequency response characteristics of analog circuits within the 300 Hz to 100 kHz frequency range. The system utilizes a three-channel synchronous acquisition architecture: two channels acquire the output signal of the circuit to be calibrated, and one channel acquires a reference excitation signal, enabling parallel comparison and closed-loop analysis of the input and output signals. The FPGA control module outputs a linearly swept square wave signal via GPIO, driving the circuit to perform frequency sweeps and synchronously controlling the three-channel sampling and data processing. The system performs time-frequency analysis of the signal based on the short-time Fourier transform (STFT), extracting the amplitude information of the dominant frequency component frequency by frequency and constructing a complete frequency response curve. By comparing the amplitude-frequency characteristics of the reference and response signals, the gain response of the circuit to be calibrated at different frequencies is accurately determined, enabling quantitative modeling and error identification of the frequency response function. The proposed calibration method boasts advantages such as high automation, high recognition accuracy, and strong anti-interference capabilities. It supports continuous testing at multiple frequency points and rapid fitting of the response function, making it suitable for online or offline calibration of various low-frequency analog circuits, such as RC filters, preamplifiers, and sensor front ends. Compared to traditional methods, this system introduces a reference signal channel design, effectively offsetting errors in frequency response measurements caused by unstable excitation sources or system delay drift. FPGA-embedded processing logic also improves overall response extraction and data calculation efficiency, enhancing the system's adaptability and reliability in complex application environments. This system is particularly suitable for applications with strict frequency response requirements, such as geophysical electromagnetic monitoring, power system low-frequency fault analysis, and biomedical signal acquisition. It can also serve as a standardized calibration tool for scientific research experimental platforms or instrument factory testing, demonstrating its broad application prospects and engineering value.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A very low frequency circuit frequency response parameter calibration system, characterized in that: It includes a very low frequency signal acquisition module and an FPGA. The very low frequency signal acquisition module includes three synchronous acquisition channels. The first and second channels of the three synchronous acquisition channels are respectively used to connect to the two output channels of the circuit to be calibrated, and the third channel is connected to the GPIO of the FPGA output calibration signal. The FPGA is configured as: After receiving the configuration instructions from the host computer, the FPGA generates a calibration signal. The calibration signal is divided into three paths: one path enters the very low frequency signal acquisition module as a reference signal for calibration and comparison, and the other two paths are respectively injected into the two input channels of the circuit to be calibrated to drive it to generate corresponding outputs; The FPGA synchronously controls the three synchronous sampling channels of the very low frequency signal acquisition module, starts data acquisition and completes the isochronous sampling task, and ensures the synchronization of the three channels of data in the time domain; After the sampling is completed, the FPGA pre-processes the three-channel data and then uploads the pre-processed data to the host computer for visualization processing.

2. The very low frequency circuit frequency response parameter calibration system according to claim 1, characterized in that: The FPGA preprocesses the three-channel data by first performing a fast Fourier transform or a short-time Fourier transform, and then performing amplitude extraction, phase calculation, and fundamental frequency point recognition operations.

3. The very low frequency circuit frequency response parameter calibration system according to claim 1, characterized in that: The calibration signal is a square wave signal or an m-sequence.

4. A host computer, characterized in that: include: processor; Memory; as well as One or more program modules are stored in the memory and configured to be executed by the processor, the one or more program modules including instructions for performing the following steps: Get the parameter range of the calibration process set by the user; Sending a configuration instruction to the FPGA of the very low frequency circuit frequency response parameter calibration system according to any one of claims 1 to 3, so that the FPGA generates a calibration signal according to a set parameter range, and pre-processes the data collected by the three sampling channels; Obtain the data pre-processed by FPGA and perform visualization.

5. The host computer according to claim 4, characterized in that: The parameter range includes the start and end range of the calibration frequency, the frequency point interval mode, the sampling time of each frequency point and the calibration signal amplitude.

6. The host computer according to claim 4, characterized in that: The visualization processing includes: based on the fundamental frequency point identification result, in the spectrum results of the three synchronous acquisition channels, energy integration is performed in a certain bandwidth near the frequency point to obtain signal strength, and then the signal strength and phase information of the first channel and the second channel are subjected to difference analysis with the reference signal collected by the third channel to extract the frequency response characteristic parameters of the circuit to be calibrated to the input signal at this frequency; by comparing the signals of the first channel and the second channel with the reference signal respectively, a frequency response difference curve of the circuit to be calibrated at this frequency point is constructed.

7. The host computer according to claim 6, characterized in that: After the frequency response parameters of all frequency points are extracted, a set of frequency response curves is formed.

8. A readable storage medium, characterized in that: The readable storage medium stores a program, which, when executed on a host computer, performs the following steps: Get the parameter range of the calibration process set by the user; Sending a configuration instruction to the FPGA of the very low frequency circuit frequency response parameter calibration system according to any one of claims 1 to 3, so that the FPGA generates a calibration signal according to a set parameter range, and pre-processes the data collected by the three sampling channels; Obtain the data pre-processed by FPGA and perform visualization.

9. The readable storage medium according to claim 8, wherein: The parameter range includes the start and end range of the calibration frequency, the frequency point interval mode, the sampling time of each frequency point and the calibration signal amplitude.

10. The readable storage medium according to claim 8, wherein The visualization processing includes: based on the fundamental frequency point identification result, in the spectrum results of the three synchronous acquisition channels, performing energy integration within a certain bandwidth near the frequency point to obtain signal strength, and then performing difference analysis on the signal strength and phase information of the first channel and the second channel with the reference signal collected by the third channel to extract the frequency response characteristic parameters of the circuit to be calibrated for the input signal at the frequency; by comparing the signals of the first channel and the second channel with the reference signal respectively, constructing a frequency response difference curve of the circuit to be calibrated at the frequency point; After the frequency response parameters of all frequency points are extracted, a set of frequency response curves is formed.

Images