Data transmission method and system, chip, electronic equipment and storage medium

Abstract

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

Description

Technical Field

[0001] The present application relates to the field of data transmission technology, and in particular to a data transmission method, system, chip, electronic device and storage medium. Background Art

[0002] As a core component of data encryption, the Hardware Security Module (HSM) in traditional architectures typically rigidly connects the data transmission interface to the AXI (Advanced Extensible Interface) bus to meet standardized communication requirements. However, this design suffers from issues such as insufficient interface flexibility, high bus resource usage, and poor adaptability to different scenarios. When a proprietary interface is required for an application, traditional architectures require redesigning the hardware interface, increasing development costs. Summary of the Invention

[0003] In order to solve the above technical problems, the embodiments of the present application creatively provide a data transmission method, system, chip, electronic device and storage medium.

[0004] According to a first aspect of the present application, a data transmission method is provided, which is applied to a processing module of a data transmission system, the data transmission system also including an encryption / decryption module, the processing module and the encryption / decryption module being connected via an internal bus, the encryption / decryption module including a bus master interface, a bus slave interface, a private interface, a control register, a configuration register, and an encryption / decryption unit, the bus master interface, the bus slave interface, the private interface, and the encryption / decryption unit being all connected to the control register, and the control register being connected to the configuration register, the method comprising:

[0005] When an interrupt request is received, a data transmission instruction is obtained, and data is parsed on the data transmission instruction to obtain a data operation type, an interface type, and data transmission parameters;

[0006] Acquire register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus;

[0007] When the configuration register is configured, the data to be transmitted is obtained through the transmission interface corresponding to the register configuration data, and the data to be transmitted is transmitted corresponding to the data operation type and the data transmission parameters based on the control register and the encryption and decryption unit. The transmission interface is one of the bus master interface, the bus slave interface and the private interface.

[0008] According to an embodiment of the present application, the data transmission system is configured in a data transmission chip, and the data transmission chip further includes a central processing unit, and the central processing unit is connected to the data transmission system via a communication module; accordingly,

[0009] The step of obtaining a data transmission instruction upon receiving an interrupt request includes:

[0010] When an interrupt request is received, obtaining a data transmission instruction from the communication module;

[0011] The interrupt request is sent when the data transmission system receives a data transmission instruction sent by the central processing unit through the communication module.

[0012] According to an embodiment of the present application, the interface types include a bus master interface, a bus slave interface, and a private interface, and the register configuration data includes a write flag bit and a write flag bit; accordingly,

[0013] The obtaining of register configuration data corresponding to the interface type includes:

[0014] In the case where the interface type is a bus slave interface, obtaining register configuration data in which the write flag bit is the first write flag bit and the write flag bit is the first write flag bit;

[0015] In the case where the interface type is a bus master interface, register configuration data is obtained in which the write flag bit is the second write flag bit and the write flag bit is the first write flag bit;

[0016] When the interface type is a private interface, register configuration data in which the write flag is the third write flag and the write flag is the second write flag is obtained.

[0017] According to an embodiment of the present application, the data transmission system further includes a configuration interface, which is connected to the internal bus and the control register; accordingly,

[0018] Configuring the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus includes:

[0019] The register configuration data is transmitted to the control register based on the configuration interface through the internal bus, so that the control register configures the register configuration data and the data transmission parameters to the configuration register.

[0020] According to an embodiment of the present application, obtaining the data to be transmitted through the transmission interface corresponding to the register configuration data includes:

[0021] When the write flag bit of the register configuration data is the first write flag bit and the write flag bit is the first write flag bit, receiving data to be transmitted from the external bus through the bus slave interface;

[0022] When the write flag bit of the register configuration data is the second write flag bit and the write flag bit is the first write flag bit, acquiring the data to be transmitted from the external bus through the bus master interface based on the read address indicated by the data transmission parameter;

[0023] When the write flag of the register configuration data is the third write flag and the write flag is the second write flag, the data to be transmitted is received through the private interface.

[0024] According to an embodiment of the present application, the data transmission system further includes a data handling module, which is connected between the bus slave interface and the control register; accordingly,

[0025] The performing data transmission corresponding to the data operation type and the data transmission parameter on the data to be transmitted based on the control register and the encryption / decryption unit includes:

[0026] When the write flag bit of the register configuration data is the first write flag bit and the write flag bit is the first write flag bit, the data to be transmitted is transmitted to the encryption / decryption unit based on the control register, the encryption / decryption unit is controlled to perform data processing corresponding to the data operation type on the data to be transmitted according to the first total amount of operations indicated by the data transmission parameter, and the processed data to be transmitted is transmitted to the external bus through the bus master interface based on the first write address indicated by the data transmission parameter;

[0027] Among them, transmitting the processed data to be transmitted to the external bus through the bus master interface includes: transmitting the processed data to be transmitted to the data handling module through the control register, so that the data handling module transmits the processed data to be transmitted to the external bus through the bus master interface.

[0028] According to one embodiment of the present application, the method further includes:

[0029] When the write flag bit of the register configuration data is the second write flag bit and the write flag bit is the first write flag bit, the data to be transmitted is transmitted to the control register based on the data handling module, so that the control register controls the encryption and decryption unit to perform data processing corresponding to the data operation type on the data to be transmitted according to the second total amount of operations indicated by the data transmission parameter, and transmits the processed data to be transmitted to the external bus through the bus master interface based on the second write address indicated by the data transmission parameter;

[0030] Among them, transmitting the processed data to be transmitted to the external bus through the bus master interface includes: transmitting the processed data to be transmitted to the data handling module through the control register, so that the data handling module transmits the processed data to be transmitted to the external bus through the bus master interface.

[0031] According to one embodiment of the present application, the method further includes:

[0032] When the write flag of the register configuration data is the third write flag and the write flag is the second write flag, the data to be transmitted is transmitted to the encryption and decryption unit based on the control register, so that the encryption and decryption unit performs data processing corresponding to the data operation type on the data to be transmitted, and transmits the processed data to be transmitted to the private interface through the control register.

[0033] According to an embodiment of the present application, the encryption and decryption unit deploys a symmetric encryption algorithm, and the data operation type includes encryption and decryption; accordingly,

[0034] The encryption and decryption unit performs data processing corresponding to the data operation type on the data to be processed, including:

[0035] The encryption and decryption unit encrypts or decrypts the data to be processed based on the symmetric encryption algorithm.

[0036] According to a second aspect of the present application, a data transmission system is provided, the system comprising a processing module, an internal bus, an encryption / decryption module, and an external bus, the processing module and the encryption / decryption module being connected via the internal bus, the encryption / decryption module comprising a bus master interface, a bus slave interface, a private interface, a control register, a configuration register, and an encryption / decryption unit, the bus master interface, the bus slave interface, the private interface, and the encryption / decryption unit being all connected to the control register, which is connected to the configuration register;

[0037] The processing module is used to obtain a data transmission instruction when an interrupt request is received, and perform data analysis on the data transmission instruction to obtain a data operation type, an interface type and data transmission parameters; obtain register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and the data transmission parameters through an internal bus; when the configuration of the configuration register is completed, obtain the data to be transmitted through the transmission interface corresponding to the register configuration data, and perform data transmission on the data to be transmitted corresponding to the data operation type and the data transmission parameters based on the control register and the encryption and decryption unit, and the transmission interface is one of a bus master interface, a bus slave interface and a private interface.

[0038] According to an embodiment of the present application, the data transmission system further includes a configuration interface connected between the internal bus and the control register;

[0039] Configuring the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus includes: transmitting the register configuration data to the control register based on the configuration interface through the internal bus, so that the control register configures the register configuration data and the data transmission parameters to the configuration register.

[0040] According to one embodiment of the present application, the system further includes:

[0041] a true random number generator, connected to the internal bus, for generating random numbers;

[0042] A public key cryptographic algorithm calculation engine, connected to the internal bus, for executing an asymmetric encryption algorithm;

[0043] The hash unit is connected to the internal bus and is used to execute a hash algorithm.

[0044] According to a third aspect of the present application, a data transmission chip is provided, the chip comprising:

[0045] a central processing unit connected to any of the above-mentioned data transmission systems via a communication module, and configured to, upon receiving a data transmission instruction sent by a user, transmit the data transmission instruction to the data transmission system via the communication module, so that the data transmission system sends an interrupt request to its processing module in response to the data transmission instruction;

[0046] The data transmission system described in any of the above items, the processing module of the data transmission system described in any of the above items is used to obtain data transmission instructions when an interrupt request is received, and perform data analysis on the data transmission instructions to obtain data operation type, interface type and data transmission parameters; obtain register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus; when the configuration of the configuration register is completed, obtain the data to be transmitted through the transmission interface corresponding to the register configuration data, and perform data transmission corresponding to the data operation type and the data transmission parameters on the data to be transmitted based on the control register and the encryption and decryption unit, and the transmission interface is at least one bus interface and one of the private interfaces.

[0047] According to the fourth aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the above-mentioned data transmission methods of the present application.

[0048] According to a fifth aspect of the present application, a computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute any of the above-mentioned data transmission methods of the present application.

[0049] The embodiment of the present application provides a data transmission method, system, chip, electronic device and storage medium, which is applied to a processing module of a data transmission system. When an interrupt request is received, a data transmission instruction is obtained, and data is parsed on the data transmission instruction to obtain a data operation type, an interface type and data transmission parameters; register configuration data corresponding to the interface type is obtained, and the configuration register is configured corresponding to the register configuration data and the data transmission parameters through an internal bus; when the configuration register is configured, the data to be transmitted is obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameters is performed on the data to be transmitted based on the control register and the encryption and decryption unit, wherein the transmission interface is at least one of a bus interface and a private interface. By configuring the configuration register to switch between the private interface and the bus interface, the private interface and the bus are taken into account, the flexibility of data transmission is improved, and the compatibility and scalability of the system are increased.

[0050] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an illustrative and non-limiting manner, in which:

[0052] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0053] Figure 1 Shows a schematic diagram of the composition structure of a traditional hardware security system;

[0054] Figure 2 A schematic diagram showing the structure of a data transmission system according to an embodiment of the present invention is shown;

[0055] Figure 3 A schematic diagram showing the structure of the encryption and decryption module of the data transmission system provided in an embodiment of the present application is shown;

[0056] Figure 4 The following is a schematic diagram showing an implementation flow of a data transmission method provided in an embodiment of the present application;

[0057] Figure 5 A schematic diagram of the structure of a data transmission chip provided in an embodiment of the present application is shown;

[0058] Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0059] In order to make the purpose, features, and advantages of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0060] The technical solution of the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] First, the application scenario of this application is described.

[0062] Figure 1 A schematic diagram of the structure of a traditional hardware security system is shown.

[0063] refer to Figure 1 Traditional hardware security systems (HSMs) are typically designed to connect to the central processing unit (CPU) of their system-on-chip (SOC) via a mailbox communication module. These systems primarily include the CPU, an internal bus (AHB), a true random number generator (TRNG), a public key engine (Public Key Engine), a hashing unit (HASH), an AES (symmetric encryption algorithm), and a data transfer module (DMA). The CPU, TRNG, Public Key Engine, HASH, and AES are all connected to the AHB, while the DMA is connected to the AES and the external bus (AXI BUS).

[0064] The CPU is the control CPU of the HSM, used to schedule the operation of the entire HSM. The TRNG part is a true random number generator, used to generate random numbers. The Public KEY engine is a public key cryptographic algorithm calculation engine used to implement asymmetric encryption algorithms, which can realize encryption and decryption, key exchange, and signature verification functions. HASH is a hash function calculation engine that can implement hash value operations based on the hash algorithm to generate message digests. AES is a symmetric encryption algorithm and a block encryption algorithm that can realize encryption and decryption operations on messages. It encrypts the original text into ciphertext through encryption and restores the ciphertext to the original text through decryption. DMA can realize the function of transferring data from the outside to AES, and then AES will encrypt and decrypt the transferred data.

[0065] Based on the above Figure 1 As can be seen from the description, encryption and decryption in traditional hardware security systems are primarily based on the interaction between DMA, AES, and the AXI bus. DMA is directly connected to the AXI bus, which makes it impossible for traditional hardware security systems to support proprietary interfaces. Therefore, to address the technical problems existing in the prior art, the embodiments of the present application provide a data transmission method, system, chip, electronic device, and storage medium.

[0066] Figure 2 A schematic diagram of the structure of a data transmission system provided in an embodiment of the present application is shown.

[0067] Figure 3 A schematic diagram of the composition structure of the encryption and decryption module of the data transmission system provided in an embodiment of the present application is shown.

[0068] The present invention provides a data transmission system. The processing module of the data transmission system is configured to execute the data transmission method of the present invention. The data transmission system of the present invention, also known as a hardware security system (HSM), is based on improvements to conventional hardware security systems (HSMs). Specifically, the data transmission system of the present invention is primarily achieved by improving the DMA and AES components of conventional HSMs.

[0069] refer to Figure 2 , Figure 2 A simplified diagram of the data transmission system obtained by improving the traditional HSM in the present application is shown. The data transmission system in the embodiment of the present application maintains most of the components consistent with the traditional HSM to retain most of the traditional HSM's functions, including the processing module CPU, TRNG, Public KEY engine and HASH. Only the encryption and decryption module crypto_top replaces the AES and DMA parts, and crypto_top is configured to be connected to both the AXI BUS and the private interface.

[0070] Specifically, refer to Figure 3 , Figure 3 The structure diagram of the encryption and decryption module crypto_top of the data transmission system of an embodiment of the present application is shown. The encryption and decryption module is configured to connect to the processing module via the internal bus AHB, specifically including the bus master interface axi mst, the bus slave interface axi slv, the private interface private interface, the control register cryptoctl, the configuration register crypto cfg, and the encryption and decryption unit aes_top. The bus master interface, bus slave interface, private interface, and encryption and decryption unit are all connected to the control register, which is connected to the configuration register. The bus master interface and bus slave interface are both connected to the AXI BUS.

[0071] Among them, the bus master interface and bus slave interface are interfaces hanging on the axi bus, and the data handling module is used for data handling, which is equivalent to Figure 1 The DMA in the control register is used to control the operation of the entire encryption and decryption module, and the encryption and decryption unit is used to implement encryption and decryption functions, which is equivalent to Figure 1 In the AES part, the configuration register is the configuration register of the encryption and decryption module.

[0072] In this embodiment of the present application, the processing module is configured to execute the data transmission method of the present application, that is, the processing module of the data transmission system is configured to perform the following operations: when an interrupt request is received, the data transmission instruction is obtained, and the data transmission instruction is analyzed to obtain the data operation type, interface type and data transmission parameters; the register configuration data corresponding to the interface type is obtained, and the configuration register is configured to correspond to the register configuration data and the data transmission parameters through the internal bus; when the configuration register is configured, the data to be transmitted is obtained through the transmission interface corresponding to the register configuration data, and the data to be transmitted is transmitted according to the data operation type and the data transmission parameters based on the control register and the encryption and decryption unit, and the transmission interface is one of the bus master interface, the bus slave interface and the private interface.

[0073] refer to Figure 3 In one embodiment of the present application, the encryption and decryption module of the data transmission system further includes a configuration interface (ahb slv), which is connected to an internal bus (AHB BUS) and is used to directly configure the configuration register through the control register. Accordingly, the processing module configures the configuration register corresponding to register configuration data and data transmission parameters via the internal bus, including: transmitting the register configuration data to the control register via the internal bus based on the configuration interface, so that the control register configures the register configuration data and data transmission parameters into the configuration register.

[0074] refer to Figure 3 In one embodiment of the present application, the encryption and decryption module of the data transmission system further includes a data transfer module crypto DMA, which is mainly used for data transfer and is equivalent to Figure 1 DMA in.

[0075] Therefore, the data transmission system of the embodiment of the present application achieves a balance between the bus and the private interface by improving the traditional hardware security system, so that data that needs to be encrypted and decrypted can be transmitted through the AXI bus or through the private interface.

[0076] It should be noted that the specific detailed description of the data transmission method executed by the data transmission system of the present application based on the processing module is similar to the description of the data transmission method of the present application, and has similar beneficial effects. It can be understood through the following description of the data transmission method embodiment and will not be repeated here.

[0077] Figure 4 A schematic diagram of the implementation flow of the data transmission method provided in an embodiment of the present application is shown.

[0078] refer to Figure 4, an embodiment of the present application provides a data transmission method, which is implemented based on the processing module of the above-mentioned data transmission system, and the method includes:

[0079] Operation 101 : upon receiving an interrupt request, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain a data operation type, an interface type, and data transmission parameters.

[0080] In one embodiment of the present application, the data transmission system is configured in a data transmission chip, and the data transmission chip also includes a central processing unit, which is connected to the data transmission system through a communication module; accordingly, when an interrupt request is received, a data transmission instruction is obtained, including: when an interrupt request is received, a data transmission instruction is obtained from the communication module; wherein the interrupt request is sent when the data transmission system receives a data transmission instruction sent by the central processing unit through the communication module.

[0081] Data transmission systems are typically deployed within a chip, connected to the chip's central processing unit (CPU) via a communication module and controlled by the CPU. After the chip boots up and begins operating, its CPU begins running. When data encryption or decryption is required, the CPU receives data transmission instructions.

[0082] When the CPU receives a data transmission instruction, it first calls the data transmission system and sends the instruction to it. Upon receiving the instruction, the data transmission system sends an interrupt request to the processing module to ensure a timely response. Upon receiving the interrupt request, the processing module pauses its ongoing task, retrieves the data transmission instruction from the communication module, and parses the data.

[0083] When data transmission is required, the interface used for data transmission, data transmission parameters, and the data operation type required for data transmission need to be determined. Therefore, when issuing a data transmission instruction, the data operation type, interface type, and data transmission parameters need to be carried simultaneously. When the data transmission instruction is obtained, the data operation type, interface type, and data transmission parameters of this data transmission can be obtained by parsing the data transmission instruction.

[0084] In one embodiment of the present application, data operation types mainly include data encryption, decryption and other operations, interface types mainly include various interfaces supported by the data transmission system, such as bus master interface, bus slave interface and private interface, and data transmission parameters mainly include the total amount of data calculation and data reading and writing addresses, etc.

[0085] Operation 102 : Acquire register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and data transmission parameters via the internal bus.

[0086] The configuration register determines the interface for subsequent data transmission and the read and write addresses for data transmission. For different interface types, the configuration register is pre-configured with the corresponding register configuration data. After parsing the interface type from the data transmission instruction, the corresponding register configuration data is obtained based on the interface type. Then, the register configuration data is assigned to the configuration register, enabling subsequent data transmission using the transmission interface corresponding to the interface type.

[0087] In order to transmit data according to the required data transmission parameters, when the register configuration data is configured into the configuration register, the data transmission parameters are also synchronously configured into the configuration register.

[0088] In one embodiment of the present application, a configuration interface is provided for configuring the configuration register. Configuring the configuration register corresponding to register configuration data and data transmission parameters via an internal bus can be considered as transmitting the register configuration data to a control register via the internal bus based on the configuration interface, so that the control register configures the register configuration data and data transmission parameters to the configuration register. In this way, configuring the configuration register based on a configuration interface that is different from the bus interface achieves isolation between data transmission and data configuration, thereby improving the efficiency of data configuration.

[0089] In one embodiment of the present application, register configuration data is primarily used to determine the input and output data interfaces, and is configured in a configuration register as configuration data for a control register. The control register is a readable and writable register whose reset value is 32'h0 (32-bit hexadecimal number 0, i.e., all bits are 0).

[0090] In one embodiment of the present application, the total amount of operations, the read address, and the write address shown for the data transmission parameters are all configured in the configuration register as configuration data of an independent register.

[0091] Specifically, the total amount of operations is controlled based on the operation register CRYPTO_TRS_SIZE, which is configured in the configuration register as the configuration data of CRYPTO_TRS_SIZE.

[0092] The read address is used to indicate a specific read address for reading input data. It is controlled based on the read register CRYPTO_SRC_ADDR and is configured in the configuration register as configuration data of CRYPTO_SRC_ADDR.

[0093] The write address is used to indicate the specific write address for reading output data (ie, data after data encryption and decryption), which is controlled based on the write register CRYPTO_DST_ADDR and is configured in the configuration register as configuration data of CRYPTO_DST_ADDR.

[0094] Among them, CRYPTO_TRS_SIZE, CRYPTO_SRC_ADDR and CRYPTO_DST_AD DR are all readable and writable registers, and their reset values are all configured as 32'h0.

[0095] Operation 103, when the configuration register is configured, the data to be transmitted is obtained through the transmission interface corresponding to the register configuration data, and the data to be transmitted is transmitted corresponding to the data operation type and data transmission parameters based on the control register and the encryption and decryption unit. The transmission interface is one of the bus master interface, the bus slave interface and the private interface.

[0096] The configuration register is used to set various parameters and conditions during data transmission, such as the interface type and data transmission parameters. Once the configuration register is correctly configured, the encryption and decryption module is ready to perform data transmission operations according to these configurations.

[0097] After the configuration registers are configured, the transmission interface for data transmission of the current encryption / decryption module is determined based on the register configuration data, and the data to be transmitted is obtained based on the determined transmission interface. The transmission interface can be a bus master interface, a bus slave interface, or a private interface, depending on the interface type.

[0098] The control register controls the operation of the entire encryption and decryption module. It can control the flow and transmission of data to be transmitted according to the corresponding configuration of the configuration register. The control register can also control the encryption and decryption unit to perform corresponding operations based on the data operation type. Therefore, after the transmission interface corresponding to the register configuration data obtains the data to be transmitted, it transfers the data to the control register. The control register and the encryption and decryption unit perform data transmission corresponding to the data operation type and data transmission parameters on the data to be transmitted. Among them, data transmission includes data encryption, decryption, and transmission operations.

[0099] Therefore, the embodiment of the present application configures the configuration register to determine the interface for data transmission, thereby achieving a balance between data transmission on the bus and the private interface, so that data can be obtained from the bus based on the bus master-slave interface and can also be transmitted according to the private interface.

[0100] In one embodiment of the present application, the interface types include a bus master interface, a bus slave interface and a private interface, and the register configuration data includes a write flag and a write flag; accordingly, obtaining the register configuration data corresponding to the interface type includes: when the interface type is a bus slave interface, obtaining the register configuration data in which the write flag is the first write flag and the write flag is the first write flag; when the interface type is a bus master interface, obtaining the register configuration data in which the write flag is the second write flag and the write flag is the first write flag; when the interface type is a private interface, obtaining the register configuration data in which the write flag is the third write flag and the write flag is the second write flag.

[0101] For each interface type, the corresponding register configuration data is pre-configured. The register configuration data mainly includes the write flag bit CRYPTO_CTL bit[2:1] and the write flag bit CRYPTO_CTL bit[3]. The write flag bit is used to indicate the input data interface selection, and the write flag bit is used to indicate the output data interface selection. By configuring the write flag bit and the write flag bit corresponding to different input data interfaces and output data interfaces, data transmission under different interface types can be achieved.

[0102] Specifically, depending on the type of system interface, such as a bus master interface, a bus slave interface, or a private interface, the write flag can be configured as a first write flag bit 00 indicating that the input data interface is a bus slave interface, a second write flag bit 01 indicating that the input data interface is a bus master interface, and a third write flag bit 10 indicating that the input data interface is a private interface. Correspondingly, the write flag can be configured as a first write flag bit 0 indicating that the output data interface is a bus master interface and a second write flag bit 1 indicating that the output data interface is a private interface.

[0103] In this way, after the interface type is determined, the corresponding register configuration data can be obtained according to the interface type.

[0104] Among them, the interface type can be the input data interface required for the current data transmission, or it can include both the input data interface and the output data interface. Since the write flag is configured as two types, the interface type can only include the input data interface. In this case, the corresponding write flag is obtained according to the input data interface shown in the interface type, and according to whether the interface type is a bus interface or a private interface, the write flag is directly determined to be the write flag corresponding to the bus interface or the write flag corresponding to the private interface. When the interface type includes both the input data interface and the output data interface, the corresponding write flag and write flag are directly obtained based on the input data interface and the output data interface shown in the interface type.

[0105] In one embodiment of the present application, in the above operation 103, the data to be transmitted is obtained through the transmission interface corresponding to the register configuration data, including: when the write flag bit of the register configuration data is the first write flag bit and the write flag bit is the first write flag bit, receiving the data to be transmitted from the external bus through the bus slave interface; when the write flag bit of the register configuration data is the second write flag bit and the write flag bit is the first write flag bit, obtaining the data to be transmitted from the external bus through the bus master interface based on the read address indicated by the data transmission parameter; when the write flag bit of the register configuration data is the third write flag bit and the write flag bit is the second write flag bit, receiving the data to be transmitted through the private interface.

[0106] Specifically, the bus slave interface, also known as the bus slave device interface, obtains data by waiting for the data to be transmitted automatically. Therefore, after determining that the write flag is the first write flag, the bus slave interface corresponding to the first write flag waits for the external bus to transmit the data to be transmitted.

[0107] The bus master interface, also known as the bus master device interface, has the ability to actively obtain data from the external bus. Therefore, when the write flag is determined to be the second write flag, the bus master interface corresponding to the second flag actively obtains the data to be transmitted from the external bus. However, since it involves an acquisition operation, before obtaining the data to be transmitted, it is also necessary to determine the acquisition address, that is, the read address. When obtaining the data to be transmitted, the bus master interface obtains the data to be transmitted from the external bus based on the determined read address. The read address has been pre-configured in the configuration register. When obtaining the data to be transmitted, it can be read based on the read address configured in the configuration register.

[0108] The private interface can perform agreed behaviors according to actual needs. For example, the read and write control interface of RAM (Random Access Memory) is used as the private interface. When the write flag is determined to be the third write flag corresponding to the private interface, the private interface can be used to directly wait for the data to be transmitted.

[0109] In one embodiment of the present application, the data transmission system further includes a data handling module connected between the bus slave interface and the control register. Accordingly, in the above operation 103, data transmission corresponding to the data operation type and data transmission parameters based on the control register and the encryption / decryption unit for the data to be transmitted includes:

[0110] When the write flag bit of the register configuration data is the first write flag bit and the write flag bit is the first write flag bit, the data to be transmitted is transmitted to the encryption / decryption unit based on the control register, the encryption / decryption unit is controlled to perform data processing corresponding to the data operation type on the data to be transmitted according to the first total amount of operations indicated by the data transmission parameter, and the processed data to be transmitted is transmitted to the external bus through the bus master interface based on the first write address indicated by the data transmission parameter;

[0111] Among them, the processed data to be transmitted is transmitted to the external bus through the bus master interface, including: transmitting the processed data to be transmitted to the data handling module through the control register, so that the data handling module transmits the processed data to be transmitted to the external bus through the bus master interface.

[0112] Specifically, when the write flag is determined to be the first write flag and the write flag is determined to be the first write flag, the data transmission path of this data transmission is determined, that is, the input data interface, the output data interface, and the data transmission path in the encryption and decryption module. Corresponding to the write flag being the first write flag and the write flag being the first write flag, the corresponding input data interface is the bus slave interface and the output data interface is the bus master interface.

[0113] For further reference, Figure 3 In the encryption and decryption module, when the input data interface is a bus slave interface and the output data interface is a bus master interface, the data flow for transmission is: axi slv->crypto_ctl->aes_top->crypto_ctl->crypto DMA ->axi mst. Specifically, the bus slave interface axi slv waits for the data to be transmitted from the external bus, passes it to the encryption and decryption unit aes_top via the control register crypto_ctl. After the encryption and decryption unit aes_top completes encryption and decryption, it returns the data to the control register crypto_ctl. The data then passes through the data handling module crypto DMA and is then returned to the axi bus via the bus master interface axi mst. The total amount of data to be calculated is the first amount of calculations configured by CRYPTO_TRS_SIZE, and the initial address written by axi mst is the first write address configured by CRYPTO_DST_ADDR.

[0114] In one embodiment of the present application, when the write flag bit of the register configuration data is the second write flag bit and the write flag bit is the first write flag bit, the data to be transmitted is transmitted to the control register based on the data handling module, so that the control register controls the encryption and decryption unit to perform data processing corresponding to the data operation type on the data to be transmitted based on the second total amount of operations indicated by the data transmission parameter, and transmits the processed data to be transmitted to the external bus through the bus master interface based on the second write address indicated by the data transmission parameter;

[0115] Among them, the processed data to be transmitted is transmitted to the external bus through the bus master interface, including: transmitting the processed data to be transmitted to the data handling module through the control register, so that the data handling module transmits the processed data to be transmitted to the external bus through the bus master interface.

[0116] Specifically, refer to Figure 3 Based on the bus master interface and bus master interface corresponding to the write flag and write flag, after obtaining the data to be transmitted through the bus master interface, the flow of the data to be transmitted is: axi mst->crypto DMA->crypto_ctl->aes_top->crypto_ctl->crypto DMA->axi mst. In other words, the bus master interface aix mst actively goes to the external bus to request the data to be transmitted. The data passes through the data handling module crypto DMA and the control register crypto_ctl to reach the encryption and decryption unit aes_top. After the encryption and decryption unit completes the encryption and decryption of the transmitted data based on the data operation type, it returns the data to the control register crypto_ctl. After passing through the data handling module crypto DMA, it is sent back to the axi bus (axi bus) through the bus master interface axi mst. Among them, the total amount of data that needs to be calculated is the second total amount of calculation configured by CRYPTO_TRS_SIZE, the initial address written by the bus master interface axi mst is the second write address configured by CRYPTO_DST_ADD R, and the initial address that the bus master interface axi mst takes data is the read address configured by CRYPTO_DST_ADDR.

[0117] In one embodiment of the present application, when the write flag of the register configuration data is the third write flag and the write flag is the second write flag, the data to be transmitted is transmitted to the encryption and decryption unit based on the control register, so that the encryption and decryption unit performs data processing corresponding to the data operation type on the data to be transmitted, and transmits the processed data to be transmitted to the private interface through the control register.

[0118] Specifically, refer to Figure 3If both the write and write flags correspond to the private interface, after receiving data via the private interface, the data flow is: private interface -> crypto_ctl -> aes_top -> crypto_ctl -> private interface. That is, the encryption / decryption module crypto_top waits for data to be transmitted from the private interface. This data is then passed to the encryption / decryption unit aes_top via the crypto_ctl control register. After encryption and decryption are complete, the data is returned to the private interface via the crypto_ctl control register.

[0119] Therefore, the embodiment of the present application realizes active or passive reception of data based on the bus and data transmission, and also realizes data transmission based on the private interface.

[0120] In one embodiment of the present application, the encryption and decryption unit is deployed with a symmetric encryption algorithm, the data operation types include encryption and decryption, and the encryption and decryption unit performs data processing corresponding to the data operation type on the processed data, including: the encryption and decryption unit encrypts or decrypts the processed data based on the symmetric encryption algorithm.

[0121] The encryption and decryption unit is used to encrypt or decrypt the data to be transmitted based on the data operation type. The encryption and decryption unit is deployed with a symmetric encryption algorithm, which encrypts or decrypts the data to be transmitted through the symmetric encryption algorithm.

[0122] Figure 5 A schematic diagram of the structure of a data transmission chip provided in an embodiment of the present application is shown.

[0123] refer to Figure 5Based on the above-mentioned data transmission system and data transmission method, an embodiment of the present application further provides a data transmission chip, which is a SOC chip and includes a central processing unit (SOC CPU) and the above-mentioned data transmission system (HSM). The SOC CPU and the HSM are connected to the data transmission system through a communication module mailbox, and are used to transmit the data transmission instruction to the data transmission system through the communication module when receiving a data transmission instruction sent by the user, so that the data transmission system sends an interrupt request to its processing module in response to the data transmission instruction. The processing module of the data transmission system is used to obtain the data transmission instruction when receiving the interrupt request, and perform data parsing on the data transmission instruction to obtain the data operation type, interface type and data transmission parameters; obtain the register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and data transmission parameters through the internal bus; when the configuration register is completed, obtain the data to be transmitted through the transmission interface corresponding to the register configuration data, and perform data transmission corresponding to the data operation type and data transmission parameters on the data to be transmitted based on the control register and the encryption and decryption unit, and the transmission interface is at least one bus interface and one of the private interfaces.

[0124] It should be noted that the description of the chip in the embodiment of the present application is similar to the description of the above-mentioned method and system embodiments, and has similar beneficial effects as the method embodiments, so it will not be repeated here. Figures 2 to 4 The present invention should be understood by referring to the description of any one of the accompanying drawings.

[0125] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium for executing the data transmission method of the embodiment of the present application.

[0126] Figure 6 FIG. 2 is a schematic block diagram of an electronic device that can be used to implement the embodiments of the present application.

[0127] Electronic device is intended to refer to various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device may also refer to various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are intended to be examples only and are not intended to limit the implementation of the present application described and / or claimed herein.

[0128] like Figure 6As shown, the device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory ROM 602 or a computer program loaded from a storage unit 608 into a random access memory RAM 603. Various programs and data required for the operation of the device 600 can also be stored in the RAM 603. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0129] Various components in device 600 are connected to I / O interface 605, including an input unit 606, such as a keyboard, mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, optical disk, etc.; and a communication unit 609, such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows device 600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0130] The computing unit 601 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 601 performs the various methods and processes described above, such as the data transmission method. For example, in some embodiments, the data transmission method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of the data transmission method described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform the data transmission method in any other appropriate manner (e.g., by means of firmware).

[0131] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0132] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the program code is executed by the processor or controller, the functions / operations specified in the flow charts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0133] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0134] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0135] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user's computer with a desktop synchronization window or a web browser through which a user can interact with embodiments of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0136] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0137] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not a limitation herein.

[0138] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0139] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data transmission method, characterized in that: A processing module applied to a data transmission system, the data transmission system further comprising an encryption and decryption module, the processing module being connected to the encryption and decryption module via the internal bus, the encryption and decryption module comprising a bus master interface, a bus slave interface, a private interface, a control register, a configuration register, and an encryption and decryption unit, the bus master interface, the bus slave interface, the private interface, and the encryption and decryption unit being all connected to the control register, which is connected to the configuration register, the method comprising: When an interrupt request is received, a data transmission instruction is obtained, and data is parsed on the data transmission instruction to obtain a data operation type, an interface type, and data transmission parameters; Acquire register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus; When the configuration register is configured, the data to be transmitted is obtained through the transmission interface corresponding to the register configuration data, and the data to be transmitted is transmitted corresponding to the data operation type and the data transmission parameters based on the control register and the encryption and decryption unit. The transmission interface is one of the bus master interface, the bus slave interface and the private interface.

2. The method according to claim 1, characterized in that The data transmission system is configured in a data transmission chip, and the data transmission chip further includes a central processing unit, and the central processing unit is connected to the data transmission system via a communication module; accordingly, The step of obtaining a data transmission instruction upon receiving an interrupt request includes: When an interrupt request is received, obtaining a data transmission instruction from the communication module; The interrupt request is sent when the data transmission system receives a data transmission instruction sent by the central processing unit through the communication module.

3. The method according to claim 1, characterized in that The interface types include bus master interface, bus slave interface and private interface, and the register configuration data includes a write flag bit and a write flag bit; accordingly, The obtaining of register configuration data corresponding to the interface type includes: In the case where the interface type is a bus slave interface, obtaining register configuration data in which the write flag bit is the first write flag bit and the write flag bit is the first write flag bit; In the case where the interface type is a bus master interface, obtaining register configuration data in which the write flag bit is the second write flag bit and the write flag bit is the first write flag bit; When the interface type is a private interface, register configuration data is obtained in which the write flag is the third write flag and the write flag is the second write flag.

4. The method according to claim 1, wherein The data transmission system further includes a configuration interface, which is connected to the internal bus and the control register; accordingly, Configuring the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus includes: The register configuration data is transmitted to the control register based on the configuration interface through the internal bus, so that the control register configures the register configuration data and the data transmission parameters to the configuration register.

5. The method according to claim 3, characterized in that The acquiring the data to be transmitted through the transmission interface corresponding to the register configuration data includes: When the write flag bit of the register configuration data is the first write flag bit and the write flag bit is the first write flag bit, receiving data to be transmitted from the external bus through the bus slave interface; When the write flag bit of the register configuration data is the second write flag bit and the write flag bit is the first write flag bit, acquiring the data to be transmitted from the external bus through the bus master interface based on the read address indicated by the data transmission parameter; When the write flag of the register configuration data is the third write flag and the write flag is the second write flag, the data to be transmitted is received through the private interface.

6. The method according to claim 5, characterized in that The data transmission system further includes a data handling module connected between the bus slave interface and the control register; accordingly, The performing data transmission corresponding to the data operation type and the data transmission parameter on the data to be transmitted based on the control register and the encryption / decryption unit includes: When the write flag bit of the register configuration data is the first write flag bit and the write flag bit is the first write flag bit, the data to be transmitted is transmitted to the encryption / decryption unit based on the control register, the encryption / decryption unit is controlled to perform data processing corresponding to the data operation type on the data to be transmitted according to the first total amount of operations indicated by the data transmission parameter, and the processed data to be transmitted is transmitted to the external bus through the bus master interface based on the first write address indicated by the data transmission parameter; Among them, transmitting the processed data to be transmitted to the external bus through the bus master interface includes: transmitting the processed data to be transmitted to the data handling module through the control register, so that the data handling module transmits the processed data to be transmitted to the external bus through the bus master interface.

7. The method according to claim 6, characterized in that The method further comprises: When the write flag bit of the register configuration data is the second write flag bit and the write flag bit is the first write flag bit, the data to be transmitted is transmitted to the control register based on the data handling module, so that the control register controls the encryption and decryption unit to perform data processing corresponding to the data operation type on the data to be transmitted according to the second total amount of operations indicated by the data transmission parameter, and transmits the processed data to be transmitted to the external bus through the bus master interface based on the second write address indicated by the data transmission parameter; Among them, transmitting the processed data to be transmitted to the external bus through the bus master interface includes: transmitting the processed data to be transmitted to the data handling module through the control register, so that the data handling module transmits the processed data to be transmitted to the external bus through the bus master interface.

8. The method according to claim 6, characterized in that The method further comprises: When the write flag of the register configuration data is the third write flag and the write flag is the second write flag, the data to be transmitted is transmitted to the encryption and decryption unit based on the control register, so that the encryption and decryption unit performs data processing corresponding to the data operation type on the data to be transmitted, and transmits the processed data to be transmitted to the private interface through the control register.

9. The method according to any one of claims 6 to 8, characterized in that The encryption and decryption unit deploys a symmetric encryption algorithm, and the data operation type includes encryption and decryption; accordingly, The encryption and decryption unit performs data processing corresponding to the data operation type on the data to be processed, including: The encryption and decryption unit encrypts or decrypts the data to be processed based on the symmetric encryption algorithm.

10. A data transmission system, characterized in that: The system includes a processing module, an internal bus, an encryption and decryption module, and an external bus. The processing module and the encryption and decryption module are connected via the internal bus. The encryption and decryption module includes a bus master interface, a bus slave interface, a private interface, a control register, a configuration register, and an encryption and decryption unit. The bus master interface, the bus slave interface, the private interface, and the encryption and decryption unit are all connected to the control register, and the control register is connected to the configuration register. The processing module is used to obtain a data transmission instruction when an interrupt request is received, and perform data analysis on the data transmission instruction to obtain a data operation type, an interface type and data transmission parameters; obtain register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and the data transmission parameters through an internal bus; when the configuration of the configuration register is completed, obtain the data to be transmitted through the transmission interface corresponding to the register configuration data, and perform data transmission on the data to be transmitted corresponding to the data operation type and the data transmission parameters based on the control register and the encryption and decryption unit, and the transmission interface is one of a bus master interface, a bus slave interface and a private interface.

11. The system according to claim 10, wherein: The data transmission system further comprises a configuration interface connected between the internal bus and the control register; Configuring the configuration register corresponding to the register configuration data and the data transmission parameters through the internal bus includes: transmitting the register configuration data to the control register based on the configuration interface through the internal bus, so that the control register configures the register configuration data and the data transmission parameters to the configuration register.

12. The system according to claim 10, wherein: The system further comprises: a true random number generator, connected to the internal bus, for generating random numbers; A public key cryptographic algorithm calculation engine, connected to the internal bus, for executing an asymmetric encryption algorithm; The hash unit is connected to the internal bus and is used to execute a hash algorithm.

13. A data transmission chip, characterized in that: The data transmission chip includes: a central processing unit connected to the data transmission system according to any one of claims 10 to 12 through a communication module, and configured to, upon receiving a data transmission instruction sent by a user, transmit the data transmission instruction to the data transmission system through the communication module, so that the data transmission system sends an interrupt request to its processing module in response to the data transmission instruction; The data transmission system according to any one of claims 10-12, wherein the processing module of the data transmission system according to any one of claims 10-12 is used to obtain a data transmission instruction when an interrupt request is received, and perform data analysis on the data transmission instruction to obtain a data operation type, an interface type and data transmission parameters; obtain register configuration data corresponding to the interface type, and configure the configuration register corresponding to the register configuration data and the data transmission parameters through an internal bus; when the configuration of the configuration register is completed, obtain the data to be transmitted through the transmission interface corresponding to the register configuration data, and perform data transmission corresponding to the data operation type and the data transmission parameters on the data to be transmitted based on the control register and the encryption and decryption unit, and the transmission interface is at least one bus interface and one of a private interface.

14. An electronic device, characterized in that: The data transmission chip according to claim 13 is included, and the processing module of the data transmission chip can execute the method according to any one of claims 1 to 9.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 9.

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