Structure-aware interleaving of digital objects

Abstract

Embodiments of the present disclosure relate to structure-aware interleaving of digital objects. The present disclosure relates to systems, non-transitory computer-readable media, and methods for generating interleaved digital designs according to a visual order of structure graph nodes. In particular, in one or more embodiments, the disclosed system generates, by at least one processor, a structure diagram of a digital design that represents overlapping surfaces of objects in the digital design as nodes and object paths between the overlapping surfaces as edges. Further, the disclosed system assigns, by at least one processor, a visual order to the nodes based on the configuration of the structure graph. Moreover, the disclosed system generates, by at least one processor, an interleaved digital design by sorting overlapping surfaces of the object according to the assigned visual order of the nodes.

Description

Background Art

[0001] In recent years, hardware and software platforms for creating and modifying digital designs have significantly improved. For example, many platforms offer software applications for editing objects in digital designs. For example, some image processing applications can locally reorder the parts of vector objects to create the appearance of depth between the parts of the vector objects. For example, in some cases, some image processing applications reorder the parts of vector objects so that some parts of a first vector object appear above a second vector object, while other parts of the first vector object appear below the second vector object. To create this "intertwined" appearance between a first vector object and a second vector object using conventional systems, a user edits the vector objects by at least manually adding and / or removing parts of the first and second vector objects to create the appearance of depth. This process is tedious and prone to user error. Furthermore, this manual modification of vector objects often results in the destruction of the original geometry of the first and second vector objects. Consequently, applying these effects to create even the most complex designs often requires significant time and resources and is prone to error. Summary of the Invention

[0002] Embodiments of the present disclosure use systems, non-transitory computer-readable media, and methods for interleaving digital objects using structural connectivity analysis of the object's components to provide benefits and / or solve one or more of the aforementioned problems or other problems in the art. In particular, the disclosed system automatically and intelligently interleaves vector objects in a digital design based on a structural analysis of the objects. For example, in one or more embodiments, the disclosed system generates a structural diagram of the digital design that represents the overlapping surfaces of objects in the digital design as nodes. Furthermore, in some embodiments, the disclosed system assigns a visual order to the nodes to specify which overlapping object will be visible at that location in the interleaved digital design. Moreover, in one or more embodiments, the disclosed system generates an interleaved digital design by sorting the overlapping surfaces of the objects according to the assigned visual order of the nodes that cause the objects to be interleaved.

[0003] Additional features and advantages of one or more embodiments of the present disclosure are summarized in the description which follows, and in part may be determined from the description, or may be learned by practice of these example embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The detailed description provides additional specificity and detail for one or more embodiments as briefly described below through use of the accompanying drawings.

[0005] Figure 1An example system environment is shown in which a structure-aware interleaving system operates in accordance with one or more embodiments.

[0006] Figure 2 A process flow for generating a staggered digital design according to a visual order assignment is shown in accordance with one or more embodiments.

[0007] Figure 3A and Figure 3B A diagram illustrating generating an object outline for a digital object in a digital design according to one or more embodiments.

[0008] Figure 4 A process flow for generating a floor plan of an object in a digital design is shown in accordance with one or more embodiments.

[0009] Figure 5 A process flow for removing vertices from a planar graph to generate a structured graph is shown in accordance with one or more embodiments.

[0010] Figure 6 A process flow for assigning a visual order to nodes of a structure graph of a digital design is shown in accordance with one or more embodiments.

[0011] Figures 7A-7C A series of graphical user interfaces are shown illustrating a process of generating an auxiliary interlaced digital design in a graphical user interface according to one or more embodiments.

[0012] Figure 8A and Figure 8B A series of graphical user interfaces illustrating a process flow for generating an interlaced digital design is shown in accordance with one or more embodiments.

[0013] Figure 9 An example schematic diagram of a structure-aware interleaving system is shown in accordance with one or more embodiments.

[0014] Figure 10 Shown is a series of example acts for generating an interleaved digital design based on a block diagram in accordance with one or more embodiments.

[0015] Figure 11 Shown is a series of example acts for generating an interleaved digital design in accordance with one or more embodiments.

[0016] Figure 12 A block diagram of an example computing device for implementing one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0017] This disclosure describes one or more embodiments of a structure-aware interleaving system for interleaving digital design objects based on a structural graph of the object connectivity. Specifically, the structure-aware interleaving system generates a structural graph of the digital design that represents the overlapping surfaces of objects in the digital design as nodes. Furthermore, in some embodiments, the structure-aware interleaving system assigns a visual order to the nodes, thereby specifying which overlapping object will be visible at that location in the interleaved digital design. Furthermore, in one or more embodiments, the structure-aware interleaving system generates the interleaved digital design by sorting the overlapping surfaces of the objects according to the assigned visual order of the nodes that result in the interleaving of the objects.

[0018] As described above, in some embodiments, the structure-aware interleaving system generates a structure graph of a digital design that represents overlapping surfaces of objects in the digital design as nodes. To generate the structure graph, in some embodiments, the structure-aware interleaving system generates a planar graph that represents planes of the digital objects as vertices and represents connections between the vertices as edges. Furthermore, in one or more embodiments, the structure-aware interleaving system identifies vertices where more than one object intersects. Moreover, in one or more embodiments, the structure-aware interleaving system collapses adjacent vertices where more than one object intersects (e.g., vertices that share an edge) into a single vertex. Further, in some embodiments, the structure-aware interleaving system removes vertices that do not represent locations where more than one object intersects to generate the structure graph. Accordingly, in these or other embodiments, the structure graph represents vertices (i.e., nodes) representing overlapping surfaces of the objects and edges connecting the nodes.

[0019] As described above, in some embodiments, the structure-aware interleaving system assigns a visual order to nodes, thereby specifying which overlapping object will be visible at that location in the interleaved digital design. In one or more embodiments, when assigning a visual order to the nodes, the structure-aware interleaving system uses a heuristic that causes adjacent nodes representing overlapping regions of objects to have different objects on top and seeks to achieve interleaving symmetry. In one or more embodiments, the structure-aware interleaving system utilizes any of a variety of algorithms to implement the interleaving of adjacent nodes. For example, in some embodiments, the structure-aware interleaving system uses a greedy algorithm to assign a visual order to each node.

[0020] As described above, in one or more embodiments, the structure-aware interlacing system generates an interlaced digital design by ordering the overlapping surfaces of objects according to an assigned visual order of nodes. Thus, the structure-aware interlacing system generates an interlaced digital design in which objects are interlaced due to varying visual orders of adjacent overlapping surfaces of the objects. Furthermore, in one or more embodiments, the structure-aware interlacing system generates multiple interlacing options by assigning visual orders to nodes in different ways. Indeed, in these or other embodiments, the structure-aware interlacing system displays multiple interlacing options for a user to compare and select.

[0021] As described above, in some embodiments, the structure-aware interlacing system receives user input that specifies or modifies the visual order of objects at a node. In response, the structure-aware interlacing system reorders the assigned visual order of the remaining nodes accordingly. For example, the structure-aware interlacing system receives user input that specifies the visual order of objects at one or more specific regions of overlapping objects in a digital design. Furthermore, in these or other embodiments, the structure-aware interlacing system uses a heuristic that causes adjacent nodes representing overlapping regions of objects to have different objects on top to reorder the remaining overlapping surfaces of the objects accordingly. Thus, in these or other embodiments, the structure-aware interlacing system uses the received user input to generate an auxiliary interlaced digital design.

[0022] Further, in various embodiments, the structure-aware interleaving system interleaves all overlapping positions, interleaves a certain percentage of overlapping positions, or skips positions that do not meet a threshold distance from a previously interleaved position. For example, in some embodiments, the structure-aware interleaving system interleaves every position where objects overlap. In other embodiments, the structure-aware interleaving system only generates a specified percentage of overlapping positions, resulting in an interleaving of objects that gives a different appearance (e.g., a more random interleaving). Further, in one or more embodiments, the structure-aware interleaving system determines which nodes to assign a visual order based on the digital design surface area between the nodes. For example, in these or other embodiments, the structure-aware interleaving system utilizes a threshold area size to determine which nodes to assign a visual order.

[0023] While conventional systems offer various tools for modifying objects in digital designs to achieve interlaced object effects, they also suffer from several drawbacks regarding operational efficiency and flexibility. For example, conventional systems are inefficient for modifying digital design objects because they require extensive user interaction to achieve design effects such as interlaced objects. More specifically, conventional systems require user interaction at each location where objects overlap in order to sort the layers of objects. Therefore, to sort the objects, conventional systems require the use of various user interface tools, menus, and user interactions. The more complex the interlaced effect, the more resources are required to achieve it. Furthermore, when a user wishes to view different interlaced object results, conventional systems require extensive input to implement the interlacing for each unique possible result. This inefficiency is particularly problematic in complex digital designs with many overlapping surfaces between objects.

[0024] Furthermore, in addition to their inefficiency, conventional systems also exhibit operational inflexibility due to the need to manually sort objects at each overlapping surface between them to achieve the overall staggered effect. For example, when staggering objects, conventional systems require input to manually sort the objects at each overlapping surface between them. Even for minimally complex designs, such as those with several overlapping surfaces between two objects or multiple objects, these manual operations quickly become tedious. Achieving a staggered effect in such situations requires a high level of skill and experience. For designs with greater complexity, such as those with many overlapping areas between objects, conventional systems are generally unable to quickly or easily achieve a staggered effect between objects. This inflexibility is even more pronounced when conventional systems generate multiple options for staggering objects. Indeed, the greater the number of overlapping surfaces between objects, the greater the number of possible staggered outcomes between the objects. The inflexibility of conventional systems in generating visualizations of multiple staggered options can be daunting.

[0025] As previously described, the structure-aware interleaving system offers various advantages over conventional systems. For example, by automatically interleaving objects, the structure-aware interleaving system improves efficiency over conventional systems. Specifically, in some embodiments, the structure-aware interleaving system automatically interleaves objects by receiving a single interaction. Thus, the structure-aware interleaving system avoids the need for multiple inputs, such as inputs at each overlapping surface between objects to specify the visual order at each overlapping surface. Furthermore, in some embodiments, the structure-aware interleaving system provides multiple interleaving options with different visual orderings of overlapping surfaces for visualization and selection with minimal interaction (e.g., a single interaction). Accordingly, even for complex designs, the structure-aware interleaving system offers improved efficiency over conventional systems. Furthermore, the structure-aware interleaving system provides an improved graphical user interface for generating interleaved objects. Compared to conventional systems that require users to access and use multiple different graphical user interface tools, menus, and interactions to manually interleave objects, the structure-aware interleaving system provides a graphical user interface and system that provides interleaved objects in response to minimal user interaction. More specifically, the structure-aware interleaving system displays one or more interleaved objects in response to a single interaction (eg, a single button click) within a graphical user interface.

[0026] Moreover, by automatically interleaving objects with minimal interaction, the structure-aware interleaving system provides increased flexibility relative to conventional systems. Specifically, in one or more embodiments, the structure-aware interleaving system quickly and easily interleaves even complex designs with many objects and many overlapping surfaces (e.g., with a single interaction). Further, in one or more embodiments, the structure-aware interleaving system provides multiple interleaving options for visualizing and selecting even complex designs with minimal interaction. Thus, the structure-aware interleaving system provides increased operational flexibility compared to conventional systems. Moreover, in some embodiments, even after selecting an interleaving option between objects from multiple options, the structure-aware interleaving system allows the user to modify the ordering of one or more specific overlapping surfaces between objects and automatically adjusts the remaining overlapping surfaces in the design to maintain the interleaving effect. Thus, the structure-aware interleaving system allows flexible manual adjustments to the interleaved design with minimal interaction while maintaining the aforementioned increased efficiency.

[0027] Additional details about the structure-aware interleaving system will now be provided with reference to the accompanying drawings. For example, Figure 1 1 shows a schematic diagram of an exemplary system 100 in which a structure-aware interleaving system 102 operates. Figure 1 As shown, system 100 includes server(s) 106, network 108, and client device 110. Although Figure 1Although the system 100 is depicted as having a particular number of components, the system 100 can have any number of additional or alternative components (e.g., any number of servers, client devices, or other components communicating with the structure-aware interleaving system 102 via the network 108). Figure 1 A particular arrangement of server(s) 106 , network 108 , and client devices 110 is shown, but various additional arrangements are possible.

[0028] Server(s) 106, network 108, and client device 110 directly or indirectly (e.g., via Figure 12 Furthermore, the server(s) 106 and the client device 110 include one or more various computing devices (including Figure 12 One or more computing devices discussed in more detail).

[0029] As described above, system 100 includes server(s) 106. In one or more embodiments, server(s) 106 generate, store, receive, and / or transmit data including notifications, models, and digital designs. In one or more embodiments, server(s) 106 comprise data servers. In some implementations, server(s) 106 comprise communication servers or web hosting servers. Furthermore, server(s) 106 include digital design system 104, which also includes structure-aware interlacing system 102.

[0030] In one or more embodiments, client device 110 comprises a computing device that accesses, edits, segments, modifies, stores, and / or provides digital content, such as digital designs, for display. For example, client device 110 comprises a smartphone, tablet computer, desktop computer, laptop computer, head-mounted display device, or other electronic device. Client device 110 comprises one or more applications (e.g., digital design editing application 112) that access, edit, segment, modify, store, and / or provide digital content, such as digital designs, for display. For example, in one or more embodiments, digital design editing application 112 comprises a software application installed on client device 110. Additionally or alternatively, digital design editing application 112 comprises a software application hosted on server(s) 106 that is accessible by client device 110 through another application, such as a web browser.

[0031] To provide example implementations, in some embodiments, the structure-aware interlacing system 102 on the server(s) 106 supports the structure-aware interlacing system 102 on the client device 110. In other words, the client device 110 obtains (e.g., downloads) the structure-aware interlacing system 102 from the server(s) 106. Once downloaded, the structure-aware interlacing system 102 on the client device 110 generates an interlaced digital design by ordering overlapping surfaces of an object according to a specified visual order.

[0032] In an alternative embodiment, the structure-aware interlacing system 102 includes a web-hosted application that allows a client device 110 to interact with content and services hosted on the server(s) 106. By way of example, in one or more embodiments, the client device 110 accesses a software application supported by the server(s) 106. In response, the structure-aware interlacing system 102 on the server(s) 106 generates and provides an interlaced digital design. The server(s) 106 then provide the interlaced digital design to the client device 110 for display.

[0033] By way of example, in some cases, the structure-aware interlacing system 102 on the client device 110 generates outlines of objects within the digital design via a software application supported by the server(s) 106. The client device 110 sends the generated outlines to the server(s) 106. In response, the structure-aware interlacing system 102 on the server(s) 106 further generates a construction graph of the digital design, assigns a visual order to nodes of the construction graph, and generates an interlaced digital design by ordering overlapping surfaces of the objects according to the assigned visual order of the nodes.

[0034] Although Figure 1 The structure-aware interleaving system 102 is shown as being implemented for server(s) 106, but different components of the structure-aware interleaving system 102 can be implemented by various devices within the system 100. For example, a different computing device (e.g., client device 110) or a server separate from the server(s) 106 can implement one or more (or all) components of the structure-aware interleaving system 102. In practice, Figure 1 As shown, the client device 110 includes a structure-aware interleaving system 102. Figure 9 Example components of the structure-aware interleaving system 102 are described.

[0035] As described above, in some embodiments, the structure-aware interlacing system 102 interlaces digital design objects by generating a structural diagram of object connectivity and an interlaced digital design based on an assigned visual order of the objects' overlapping locations. For example, Figure 2A process flow for generating an interlaced digital design according to a visual order assignment in accordance with one or more embodiments is shown. Specifically, in some embodiments, structure-aware interlacing system 102 generates a plan view 202 of digital design 200 having a plurality of overlapping objects (i.e., objects 1, 2, and 3). Furthermore, in one or more embodiments, structure-aware interlacing system 102 generates a structure view 206 of the digital design from plan view 202, with structure view 206 having only vertices (i.e., nodes) representing the overlapping surfaces of the objects in digital design 200 and edges connecting these nodes. Further, in one or more embodiments, structure-aware interlacing system 102 generates an interlaced digital design (e.g., interlaced digital design 210) by sorting the overlapping surfaces of the objects according to the assigned visual order of the nodes.

[0036] As described above, in some embodiments, the structure-aware interlacing system 102 generates the plan view 202 of the digital design 200. In practice, the structure-aware interlacing system 102 generates the plan view 202 of the objects in the digital design 200 to include vertices corresponding to the surfaces of the objects and edges connecting the vertices. Figure 2 As shown, plan view 202 includes vertices A, B, C, etc. and edges connecting the vertices. In addition, in some embodiments, structure-aware interlacing system 102 generates overlapping surface vertex groups by determining which vertices correspond to overlapping surfaces of objects in digital design 200. For example, structure-aware interlacing system 102 generates an overlapping surface vertex group that includes each shaded vertex of plan view 202 (i.e., B, E, F, G, H, I, J, M, and S).

[0037] As described above, in one or more embodiments, the structure-aware interleaving system 102 generates a structure graph 206 of the digital design. In these or other embodiments, the structure-aware interleaving system 102 generates the structure graph 206 having only the vertices in the plan view 202 that represent overlapping surfaces of objects in the digital design 200 and the edges connecting these vertices. In one or more embodiments, the remaining vertices in the structure graph are identified as nodes. For example, the structure-aware interleaving system 102 generates the structure graph 206 including nodes A", B, M, and S. To this end, in one or more embodiments, the structure-aware interleaving system 102 performs vertex collapse 204 and vertex removal on the plan view 202.

[0038] As described above, in one or more embodiments, the structure-aware interleaving system 102 performs vertex collapse 204 and vertex removal on the planar graph 202. In these or other embodiments, the structure-aware interleaving system 102 collapses adjacent vertices (e.g., vertices that share an edge) of a group of overlapping surface vertices into aggregated vertices. For example, the structure-aware interleaving system 102 collapses vertices E, F, G, H, I, and J into a single aggregated vertex A. In this example, none of the remaining colored vertices (i.e., vertices that belong to the group of overlapping surface vertices), such as B, M, or S, are adjacent to other vertices in the group, so the structure-aware interleaving system 102 does not collapse them. Additionally, in one or more embodiments, the structure-aware interleaving system 102 removes vertices that are not part of the group of overlapping surface vertices (e.g., A, C, D, K, L, N, O, P, Q, R, T, U).

[0039] Furthermore, in one or more embodiments, the structure-aware interlacing system 102 generates an interlaced digital design (e.g., the interlaced digital design 210) by ordering the overlapping surfaces of the objects according to the assigned visual order of the nodes. For example, in some embodiments, the structure-aware interlacing system 102 performs a visual order assignment 208, wherein the structure-aware interlacing system 102 assigns a visual order to the objects at each node of the structure graph 206. Furthermore, in some embodiments, the structure-aware interlacing system 102 uses a heuristic for visual order assignment 208 that causes adjacent overlapping regions to have different objects on top and seeks to achieve interlaced symmetry.

[0040] Thus, the structure-aware interlacing system 102 generates the interlaced digital design 210 such that the overlapping regions of the objects are ordered according to the visual order assignments for each corresponding node in the structure graph 206. For example, the structure-aware interlacing system 102 orders the objects of the interlaced digital design 210 according to the visual order assignments 208 such that object 3 is first (e.g., on top or in front) at the overlapping regions corresponding to nodes M and S. Similarly, at the overlapping regions corresponding to nodes B and A, the structure-aware interlacing system 102 orders the objects such that object 1 and object 2 are first, respectively.

[0041] As described above, in some embodiments, the structure-aware interlacing system 102 generates a floor plan of an object in a digital design (e.g., a digital design). In some implementations, as part of generating the floor plan, the structure-aware interlacing system 102 generates outlines of the objects within the digital design to determine the boundaries of the objects. For example, Figure 3A and Figure 3BA diagram illustrating object outlines 302, 310 for generating digital objects 300, 304 in a digital design according to one or more embodiments is shown. Specifically, in some implementations, the structure-aware interlacing system 102 generates outlines of objects to determine the boundaries of the objects, regardless of the tool used to create the objects or the effect or style of the objects.

[0042] In particular, Figure 3A The structure-aware interleaving system 102 is shown generating object outlines 302 for relatively simple overlapping objects with various effects. Figure 3A A digital design is shown having two digital objects 300, each having a filled and stroked path. In this and other embodiments, the structure-aware interlacing system 102 generates object outlines 302 to determine the boundaries of the two digital objects 300, regardless of any effects applied to the digital objects 300. Accordingly, in these or other embodiments, the structure-aware interlacing system 102 generates digital object outlines formed by the outermost boundaries of the objects.

[0043] Figure 3B The structure-aware interlacing system 102 is shown generating an object outline for a digital object 304 created using a paintbrush. For example, the structure-aware interlacing system 102 generates an object outline 310 for the digital object 304 via various intermediate steps as shown. For example, in some embodiments, the structure-aware interlacing system 102 determines various internal ribs 306 of the digital object 304. In one or more embodiments, using this series of simplified structures (i.e., the internal ribs 306), the structure-aware interlacing system 102 generates a rib outline 308. Furthermore, in one or more embodiments, the structure-aware interlacing system 102 generates a unified object outline 310 from the rib outlines 308.

[0044] For example, in one or more embodiments, the structure-aware interleaving system 102 determines objects, including path objects and compound path objects, that are defined by geometric shapes but can include various effects, such as strokes, fills, styles, brushes, patterns, images, and various other effects. In one example, to determine or obtain object outlines, the structure-aware interleaving system 102 converts the objects into graphic primitives, such as grids and Bezier-defined shapes with only fill effects applied. In other cases, such as when the structure-aware interleaving system 102 cannot convert the objects into graphic primitives (e.g., grids, meshes, raster brushes, etc.), the structure-aware interleaving system 102 generates bounding boxes and / or other vector representations of the object outlines.

[0045] In some embodiments, once the structure-aware interleaving system 102 converts the objects into primitives, the structure-aware interleaving system 102 merges the primitives into a single object to obtain corresponding boundaries (e.g., object outlines of particular objects). For example, when the structure-aware interleaving system 102 detects regions where objects can be interleaved, the outer boundaries of the objects are used without using any interior details (e.g., by merging the primitives of the objects), thereby reducing the complexity of detecting intersections (e.g., regions) between objects.

[0046] In the above Figure 3B In various embodiments described herein, in which the structure-aware interlacing system 102 adds a particular effect to an object to create a non-vector object (e.g., an image), the structure-aware interlacing system 102 generates ribs (e.g., defined by vectors) for the non-vector object based on properties of the effect (e.g., stroke width). In such embodiments, the ribs are non-overlapping and are combined to obtain an outline of the non-vector object. For example, the ribs are combined to obtain an outline of the entire path and / or object.

[0047] In some embodiments, when combining the components of an object (e.g., ribs, strokes, fills, and other geometric shapes defined by the object), the structure-aware interleaving system 102 utilizes Boolean operations such as merge, union, combine, join, intersect, segment, subtract, trim, offset, and / or other operations. For example, if the object includes a clipping mask, the structure-aware interleaving system 102 merges the clipping mask with the rest of the object (e.g., using a merge operation) so that the structure-aware interleaving system 102 accurately obtains the outline of the object. In various embodiments, the structure-aware interleaving system 102 utilizes a clipping version of a technique that includes use as part of rendering a digital design to selectively enable and disable rendering operations with respect to the digital design. In one example, the structure-aware interleaving system 102 uses clipping and / or clipping masks to define what to render within a specific area.

[0048] Although Figure 3A and Figure 3B Various types of objects are shown that the structure-aware interlacing system 102 uses to generate object outlines and interlaced digital designs with interlaced objects, but in some embodiments, any digital object is used by the structure-aware interlacing system 102. In fact, additional examples of digital objects used by the structure-aware interlacing system 102 are shown in FIG.

[0049] As described above, in some embodiments, the structure-aware interlacing system 102 generates a plan view of an object in a digital design. For example, Figure 4A process flow for generating a floor plan 404 of an object in a digital design 400 is shown, according to one or more embodiments. Specifically, in some embodiments, the structure-aware interlacing system 102 generates a floor plan 402 of the digital design 400. Furthermore, in one or more embodiments, the structure-aware interlacing system 102 uses the floor plan 402 to generate the floor plan 404. Additionally, in one or more embodiments, the structure-aware interlacing system 102 performs vertex collapse 406 on the floor plan 404.

[0050] As described above, in some embodiments, the structure-aware interlacing system 102 generates the floor plan 402 of the digital design 400. For example, the structure-aware interlacing system 102 uses the Figure 3A and Figure 3B The generated object outlines discussed above are used to generate a planar arrangement 402 of three objects in the digital design 400. Additionally, the structure-aware interlacing system 102 generates the planar arrangement to include the planes of the objects and the edges between the planes.

[0051] By way of example, the structure-aware interleaving system 102 generates the planar arrangement 402 to include planes A, B, C, and so on. Furthermore, in these or other embodiments, where two objects intersect, the planes are connected with edges. For example, at plane B where Objects 1 and 2 intersect, plane B is connected to four adjacent planes (e.g., A, C, D, and T), with an edge between plane B and each of these planes. In effect, the structure-aware interleaving system 102 generates an edge between plane B and A, plane B and C, plane B and D, and plane B and T.

[0052] As described above, in one or more embodiments, the structure-aware interleaving system 102 uses the planar arrangement 402 to generate a planar graph 404. For example, in some embodiments, the structure-aware interleaving system 102 generates a planar graph that represents the planes of an object as vertices and the paths of the object between overlapping surfaces as edges. Specifically, in one or more embodiments, the structure-aware interleaving system 102 generates a vertex in the planar graph 404 for each plane of the planar arrangement 402 and preserves the edges connecting the vertices. For example, the structure-aware interleaving system 102 generates a planar graph 404 having vertices A, B, C, and so on, with each adjacent vertex connected by an edge. For example, in the planar graph 404, vertex A is connected to vertex B by one edge, to vertex G by another edge, and to vertex E by a third edge.

[0053] Furthermore, in some embodiments, structure-aware interleaving system 102 generates overlapping surface vertex groups by determining which vertices correspond to overlapping surfaces of the objects in digital design 400. In practice, structure-aware interleaving system 102 generates overlapping surface vertex groups to include all vertices corresponding to overlapping surfaces of the objects. In other words, structure-aware interleaving system 102 generates overlapping surface vertex groups to include vertices corresponding to planes of the objects at the overlapping surfaces of the objects. For example, structure-aware interleaving system 102 generates overlapping surface vertex groups that include each of the shaded vertices (i.e., B, E, F, G, H, I, J, M, and S) of planar layout 404. In this example, the shaded vertices correspond to planes of the same letter at the overlapping surfaces of the objects as shown in planar layout 402.

[0054] In some implementations, the structure-aware interleaving system 102 generates the floor plan 404 from the floor plan 402 using various functions. In one or more embodiments, for each floor plan f i , the structure-aware interleaving system 102 generates the vertex V i Furthermore, in one or more embodiments, the structure-aware interleaving system 102 utilizes edges e in the planar graph 404G to connect adjacent faces. Formally, G = (V, E) is a graph containing edges e = (u, v) (where u≠v), where u and v correspond to adjacent faces in the planar graph. Additionally, in some embodiments, the structure-aware interleaving system 102 generates the planar graph 404 such that the weight w of each edge is e is 0. Furthermore, the structure-aware interleaving system 102 defines two other functions c(v) and Ω(v), which respectively determine the number of overlapping surfaces contributing to the face corresponding to v and the face boundary. Moreover, the colored vertices of the planar graph 404 represent the intersection of more than one object ∑ >1 The vertices of , while the non-colored vertices represent the non-overlapping area ∑1.

[0055] Additionally, in one or more embodiments, the structure-aware interleaving system 102 performs vertex collapse 406 on the planar graph 404. In these or other embodiments, the structure-aware interleaving system 102 collapses adjacent vertices (e.g., vertices that share an edge) of a group of overlapping surface vertices into aggregated vertices. As described above, the structure-aware interleaving system 102 determines the group of overlapping surface vertices by determining which vertices correspond to overlapping surfaces of the object.

[0056] By way of example, structure-aware interleaving system 102 collapses vertices E, F, G, H, I, and J of plan view 404 into a single aggregate vertex A″ as shown at vertex collapse 406. Accordingly, vertex A″ corresponds to a location in digital design 400 where all three objects intersect at the same location. In this example, none of the remaining colored vertices (i.e., vertices belonging to the overlapping surface vertex group), such as B, M, or S, are adjacent to other vertices in the overlapping surface vertex group, and therefore structure-aware interleaving system 102 does not collapse them.

[0057] In some embodiments, the structure-aware interleaving system 102 uses various functions to perform vertex collapse 406. For example, in some implementations, the structure-aware interleaving system 102 performs vertex collapse 406 by merging two vertices u and v. In these or other embodiments, unlike typical vertex collapse, u and v are connected by an edge. This is called edge collapse, but the structure-aware interleaving system 102 performs vertex collapse 406 semantically at the vertex level.

[0058] For example, in one or more embodiments, the structure-aware interleaving system 102 defines a shrink operation as follows: Let G = (V, E) be a graph containing an edge e = (u, v) (where u ≠ v). Furthermore, let f be a function that maps each vertex in V\{u, v} to itself or to a new vertex w. Furthermore, the shrinkage of e results in a new graph G ′ =(V′,E′), where V ′ =(V\{u,v})∪{w},E ′ = E\{e}, and for each x∈V, x is positive if and only if an edge e∈E connects x and G. ′ =f(x)∈V ′ Associated with the corresponding edge e′∈E′. In this and other embodiments, the new graph G ′ is a graph such as the graph of vertex collapse 406 .

[0059] Furthermore, in one or more embodiments, structure-aware interleaving system 102 determines which vertices to merge (e.g., which vertex in a group of overlapping surface vertices to collapse). For example, structure-aware interleaving system 102 divides vertex V into two groups ∑1=u i and ∑ >1 =v i , where c(u i )=1 and c(v i )>1. In addition, in some embodiments, the structure-aware interleaving system 102 detects these groups ∑1 and ∑ >1 In these or other embodiments, the vertices corresponding to these subgroups are vertices (u s ,ud ), so that in (u s ,u d ), such as (u1,u2…u k ), so that belong to the same group. In some embodiments, structure-aware interleaving system 102 semantically merges all adjacent faces that belong to more than one component and faces that belong to a single component. For example, structure-aware interleaving system 102 collapses u and v into w. Therefore, structure-aware interleaving system 102 defines two properties c(w) and Ω(w) as follows. For group ∑1, c(w) = 1.

[0060]

[0061] Ω(w)=Ω(u)+Ω(v)

[0062] In one or more embodiments, the structure-aware interleaving system 102 performs vertex collapse 406. In one or more implementations, any vertex v can belong to ∑1 or ∑ >1 . Starting from u, the structure-aware interleaving system 102 uses a BFS (Breath First Search) traversal to visit all adjacent nodes u*. In some embodiments, if all adjacent nodes in u* belong to the same group as u, the structure-aware interleaving system 102 pushes these adjacent nodes for traversal. Further, in some embodiments, for vertices belonging to other nodes, the structure-aware interleaving system 102 maintains a separate list l. In one or more embodiments, at the end of the traversal, the structure-aware interleaving system 102 applies contraction to the traversed vertices. In addition, the structure-aware interleaving system 102 moves all elements in list l for BFS traversal. In these or other embodiments, the elements belonging to the other group are traversed a second time. In one or more embodiments, the structure-aware interleaving system 102 alternately repeats the process of collecting and contracting the two groups of nodes until the structure-aware interleaving system 102 visits all nodes. Accordingly, in these or other embodiments, the structure-aware interleaving system 102 generates a contracted planar graph with vertex contractions 406 from the planar graph 404.

[0063] In some embodiments, structure-aware interleaving system 102 need not perform vertex collapse. For example, some digital designs may not include adjacent vertices of overlapping surface vertex groups. For example, these digital designs may only include two overlapping objects at any given overlapping location in the digital design. In these or other embodiments, structure-aware interleaving system 102 performs vertex removal on the planar graph without performing vertex collapse.

[0064] As described above, in some embodiments, the structure-aware interleaving system 102 performs vertex removal on a planar graph. For example, Figure 5 A process flow is shown for removing vertices from a planar graph 500 to generate a structure graph 502 in accordance with one or more embodiments. In particular, in one or more embodiments, the structure-aware interleaving system 102 removes vertices from the planar graph that are not part of a set of overlapping surface vertices.

[0065] For example, in one or more embodiments, the structure-aware interleaving system 102 removes vertices from the planar graph 500 to generate the structure graph 502. Specifically, in some embodiments, the structure-aware interleaving system 102 removes vertices that are not part of the overlapping surface vertex group (e.g., uncolored vertices A, C, D, K, L, N, O, P, Q, R, T, U). As a result, the structure-aware interleaving system 102 generates the structure graph 502 having only the vertices of the overlapping surface vertex group and the edges connecting them.

[0066] As described above, the structure-aware interleaving system 102 removes vertices that are not part of the set of overlapping surface vertices. Furthermore, the structure-aware interleaving system 102 adds edges between the remaining nodes (e.g., A", B, M, and S) if they are connected by the vertices removed by the structure-aware interleaving system 102. For example, when the structure-aware interleaving system 102 removes vertex T from the planar graph 500, the structure-aware interleaving system 102 identifies that nodes B and S of the structure graph 502 can be connected via vertex T. Accordingly, when the structure-aware interleaving system 102 removes vertex T, the structure-aware interleaving system 102 also adds an edge between nodes B and S in the structure graph 502.

[0067] In some embodiments, structure-aware interleaving system 102 generates a structure graph 502 of a digital design, wherein overlapping surfaces of objects in the digital design are represented as nodes, and object paths between overlapping surfaces are represented as edges. In practice, structure graph 502 includes nodes A', B, M, and S, and edges connecting these nodes. Specifically, structure graph 502 includes the following four edges: nodes A and B share an edge, nodes A and S share an edge, nodes A and M share an edge, and nodes B and S share an edge.

[0068] For illustrative purposes, a visualization of the original digital design with three overlapping digital objects is included. Figure 5502. In practice, the visualization includes a box around each overlapping surface of the objects represented by a node of the structure diagram 502. In addition, the visualization of the original digital design shows shared edges of the structure diagram 502. For example, the overlapping surfaces represented by nodes B and S are visually connected by the object path of object 1, and the overlapping surfaces represented by nodes S and A" are visually connected by the object path of object 3. Further exemplifying, the overlapping surfaces represented by nodes A" and M are visually connected by two object paths including the object path of object 2 and the object path of object 3. In some embodiments, the structure-aware interleaving system 102 generates a single edge in the structure diagram 502 even when two object paths connect nodes, as in the case of nodes A" and M.

[0069] Furthermore, in one or more embodiments, the structure-aware interleaving system 102 uses a specific operation to remove the above vertices. For example, in one or more embodiments, the structure-aware interleaving system 102 removes all vertices in G′ where c(u)=1. In addition, the structure-aware interleaving system 102 also removes all edges associated with u. Moreover, in some embodiments, via this deletion, the structure-aware interleaving system 102 generates a structure graph 502G. s =(V ″ ,E″), where V ″ =(V ′ -u), E ″ =E ′ -E u +E w . E u is the set of all edges associated with u. For example, the structure-aware interleaving system 102 uses E u =u,v i Define these edges. In addition, in some embodiments, E w Is connected v i In some implementations, the structure-aware interleaving system 102 uses the area of the boundary region of the deleted node u to define the weights of these edges.

[0070] W(E wi )=Ω(u)

[0071] Accordingly, the structure diagram 502 (G s ) represents the connectivity of the overlapping regions of the overlapping objects of the digital design. Therefore, the structure-aware interleaving system 102 generates a structure graph 502 to represent each node corresponding to the merged overlapping regions, and if there is any visual connectivity between two nodes, then the two nodes are adjacent. Moreover, the structure-aware interleaving system 102 uses this property of the structure graph 502 to assign a visual order for interleaving, such as with respect to Figure 6 discussed.

[0072] As described above, in some embodiments, the structure-aware interleaving system 102 assigns a visual order to objects at each node of the structure graph. For example, Figure 6 A process flow for assigning a visual order to nodes of a structure graph 602 of a digital design 600 is shown, according to one or more embodiments. Specifically, in some embodiments, the structure-aware interlacing system 102 generates the structure graph 602 of objects in the digital design 600. Furthermore, in one or more embodiments, the structure-aware interlacing system 102 determines a visual order likelihood 604 for each node of the structure graph 602. Furthermore, in one or more embodiments, the structure-aware interlacing system 102 performs a visual order assignment 606 for the nodes of the structure graph 602. Furthermore, in some embodiments, the structure-aware interlacing system 102 generates an interlaced digital design (e.g., an interlaced image 608) by ordering overlapping surfaces of the objects according to the assigned visual order of the nodes.

[0073] As described above, in some embodiments, the structure-aware interlacing system 102 generates a structure map 602 of an object in the digital design 600. For example, the structure-aware interlacing system 102 uses the same techniques described above with respect to Figure 2-Figure 5 A similar method is used to generate structure graph 602. In addition, in one or more embodiments, structure-aware interleaving system 102 determines a visual order likelihood 604 for each node of structure graph 602. In other words, structure-aware interleaving system 102 determines which objects overlap at each overlapping surface of the objects represented by a node of structure graph 602. In effect, each object at each overlapping surface is a possible option for assigning a visual order at the corresponding node.

[0074] For example, the structure-aware interleaving system 102 determines that any one of the three objects is available for allocation at node A" of the structure graph 602 because all three objects intersect at the overlapping surface corresponding to node A". Furthermore, the structure-aware interleaving system 102 determines that either object 1 or object 2 is available for allocation at node B, object 1 or object 3 is available for allocation at node S, and object 2 or object 3 is available for allocation at node M. Figure 6 , these visual order possibilities are illustrated by shaded boxes adjacent to nodes of the structure graph of the visual order possibilities 604 graph.

[0075] Furthermore, in one or more embodiments, the structure-aware interleaving system 102 performs a visual order assignment 606 for the nodes of the structure graph 602. For example, in some embodiments, the structure-aware interleaving system 102 assigns a visual order to the nodes based on the configuration of the structure graph. More specifically, in some embodiments, the structure-aware interleaving system 102 assigns a visual order to the nodes using a heuristic that causes adjacent overlapping regions of a digital design to have different objects on top and seeks to achieve interleaving symmetry.

[0076] By way of example, in one or more embodiments, the structure-aware interlace system 102 performs visual order assignment 606 by assigning different objects to adjacent nodes as shown in visual order assignment 606. In practice, in these or other embodiments, the structure-aware interlace system 102 assigns object 2 to node A', object 1 to node B, and object 3 to nodes M and S. Thus, the structure-aware interlace system 102 assigns a visual order to each node according to the heuristics described above. For example, the structure-aware interlace system 102 does not assign the same visual order of objects to any two adjacent nodes (i.e., nodes that share an edge).

[0077] By way of further example, in one or more embodiments, the structure-aware interlacing system 102 follows a series of operations to assign a visual order to nodes. For example, in some embodiments, the structure-aware interlacing system 102 determines a first node to begin visual order assignment 606 and assigns a visual order to the first node. Additionally, in one or more embodiments, the structure-aware interlacing system 102 identifies adjacent nodes of the first node for visual order assignment and assigns a visual order to these nodes that is different from the visual order of the first node. In one or more embodiments, the structure-aware interlacing system 102 continues to identify adjacent nodes and assign visual orders to the nodes until all nodes have been assigned a visual order. In some cases, the structure-aware interlacing system 102 will be unable to assign a unique visual order at the nodes based on the heuristics. In these or other embodiments, the structure-aware interlacing system 102 skips nodes to leave the original order in place.

[0078] As described above, in some embodiments, the structure-aware interlace system 102 determines a first node to begin visual order assignment. In some implementations, the structure-aware interlace system 102 determines the first node by identifying the node with the highest number of neighboring nodes or the node with the highest number of possible visual orders (i.e., visual order probabilities) from among the nodes. For example, the structure-aware interlace system 102 uses any of these criteria to determine node A" of the structure graph 602 as the first node. Node A" has the highest number of neighboring nodes because it shares an edge with each of nodes B, M, and S. Additionally, node A" has the highest number of possible visual orders because any one of the three objects can be used for assignment as shown in the graph of visual order probabilities 604. In one or more embodiments, the structure-aware interlace system 102 determines the first node by determining and selecting the node with the lowest number of possible visual orders. Additionally, in some implementations, the structure-aware interlace system 102 uses other criteria to determine the first node.

[0079] As described above, in some embodiments, the structure-aware interlace system 102 assigns a visual order to the first node. By way of example, the structure-aware interlace system 102 assigns object 2 to the first node A″, as shown in the diagram of visual order assignment 606. Specifically, in one or more embodiments, the structure-aware interlace system 102 utilizes various mechanisms to determine which object to assign to each node (i.e., what visual order to assign). For example, in one or more embodiments, the structure-aware interlace system 102 assigns a visual order priority to each object, and uses the visual order priority to assign a visual order to each node. By way of example, the structure-aware interlace system 102 assigns a first visual order priority to object 2, a second visual order priority to object 3, and a third visual order priority to object 1. In these or other embodiments, the structure-aware interlace system 102 assigns the objects at each node according to the priority. In effect, the structure-aware interlace system 102 assigns the object having the first visual order priority (e.g., object 2) to the first node (e.g., assigns object 2 to A″).

[0080] To continue the above description, in one or more embodiments, the structure-aware interlace system 102 then assigns visual orders to nodes adjacent to the first node using the visual order priorities and the above-described heuristics, where the structure-aware interlace system 102 assigns different visual orders to the adjacent nodes. For example, in these or other embodiments, the structure-aware interlace system 102 assigns Object 3 (with the second visual order priority) to nodes M and S, both of which are adjacent to node A″ and therefore cannot be assigned Object 2 (with the first visual order priority). Importantly, nodes M and S are not adjacent to each other (because they do not share an edge), so the structure-aware interlace system 102 assigns Object 3 to both. Further, the structure-aware interlace system 102 assigns Object 1 (with the third visual order priority) to node B, which is adjacent to both nodes A″ (which is assigned Object 2) and S (which is assigned Object 3) and therefore cannot be assigned a dark color or Object 2 according to the heuristics.

[0081] Structure-aware interleaving system 102 uses various algorithms to assign a visual order to the nodes of structure graph 602. In one or more embodiments, structure-aware interleaving system 102 assigns a visual order V to each possible overlapping region of objects in digital design 600. o In these or other embodiments, the block diagram 602 (G s ) represents the overlapping region Ω(v). Furthermore, in these or other embodiments, the structure-aware interlacing system 102 applies a heuristic that, for an interlaced digital design (e.g., interlaced image 608) to be aesthetically pleasing, adjacent overlapping regions should have different objects on top (i.e., in front). Furthermore, in these or other embodiments, the heuristic helps achieve a symmetrical interlacing effect as much as possible.

[0082] In some embodiments, the structure-aware interleaving system 102 maps the problem of interleaving objects to a coloring problem with some additional constraints. In these or other embodiments, the structure-aware interleaving system 102 defines this as a coloring problem and then defines an algorithm for solving the coloring problem. Furthermore, the structure-aware interleaving system 102 uses these results to define an interleaving operation. For example, in one or more embodiments, the structure-aware interleaving system 102 uses the following algorithm:

[0083]

[0084] In some embodiments, the structure-aware interleaving system 102 generates a digital design 600 from each object 1 i (also called interleaving component) assigns a unique local identifier id to start executing the problem mapping. In one or more embodiments, the structure-aware interleaving system 102 uses a bit mask sequence identifier, i.e., idi =2 i Accordingly, in these or other embodiments, the structure-aware interleaving system 102 maps each component to a value equal to id i In addition, the structure-aware interleaving system 102 stores information about the objects that pass through its region Ω at each vertex (i.e., a node of the structure graph). In one or more embodiments, the structure-aware interleaving system 102 stores this information in a single number K(v), where b i Each bit on the vertex represents the component I passing through the vertex boundary i In addition, in some embodiments, the structure-aware interleaving system 102 represents |K(v)| as the set of all components belonging to v. In these or other embodiments, the problem is to assign a color ω(v) to each vertex v that satisfies the following constraint, where u i Represents the adjacent vertices of v:

[0085] ω(v)∈|K(v)|

[0086]

[0087] The graph of visual order possibilities 604 illustrates the possible interleaving components (ie, digitally designed objects) that the structure-aware interleaving system 102 may assign to the vertex.

[0088] As described above, in some embodiments, the structure-aware interleaving system 102 uses an algorithm to solve the color matching problem. For example, in some implementations, the structure-aware interleaving system 102 uses a greedy algorithm for color assignment (ie, assigning a visual order).

[0089] For example, in these or other embodiments, the structure-aware interleaving system 102 starts with the node with the most adjacencies (i.e., the largest number of adjacent nodes) or the largest number of visual order options, as previously described. Furthermore, in these or other embodiments, the structure-aware interleaving system 102 assigns the first object available for assignment to the first node. Furthermore, in some embodiments, the structure-aware interleaving system 102 performs a breadth-first traversal of the structure graph 602 and assigns visual order to adjacent nodes when possible. In practice, this process is detailed in Algorithm 1 above.

[0090] Furthermore, in one or more embodiments, after assigning colors, the structure-aware interleaving system 102 applies a binary operation that can be expressed as follows:

[0091]

[0092] Among them: A keyRepresents one object of a digital design (e.g., object 1, 2, or 3); a vector object A that references a different object (e.g., object 1, 2, or 3) that is an object of the digital design i , changing A in the direction indicated by parameter D (also referred to herein as direction D) key The visual order V. As the above exemplary binary operation As shown, the structure-aware interleaving system 102 does not need to specify a reference vector object A i . More specifically, the structure-aware interlacing system 102 automatically determines the reference vector objects based on the current visual order. In these or other embodiments, the operator used for these operations is Ω(v) interlacing corresponding to ω(v), and the direction D is "send forward". In some implementations, the structure-aware interlacing system 102 applies the interlacing operation to areas that have been assigned a certain color (i.e., visual order). The structure-aware interlacing system 102 displays the result (e.g., interlaced image 608) after applying automatic interlacing to the digital design 600 based on the visual order assignment 606.

[0093] As previously described, in some embodiments, the structure-aware interlacing system 102 generates an interlaced digital design (e.g., interlaced image 608) by ordering the overlapping surfaces of objects in the digital design 600 according to the assigned visual order of the nodes. For example, the structure-aware interlacing system 102 orders the overlapping surfaces of the objects in the digital design 600 according to the visual order assignments 606 of the corresponding nodes.

[0094] For example, structure-aware interlacing system 102 orders the overlapping surfaces corresponding to node A″ of structure diagram 602 according to visual order assignment 606 so that object 2, rather than object 1, in digital design 600 is at the top in interlaced image 608. Furthermore, in interlaced image 608, structure-aware interlacing system 102 orders the overlapping surfaces corresponding to nodes M and S so that object 3 is at the top, and orders the overlapping surfaces corresponding to node B so that object 1 is at the top, respectively, according to visual order assignment 606. Thus, structure-aware interlacing system 102 generates interlaced image 608 from digital design 600. Compared to interlaced image 608, digital design 600 displays objects such that object 1 is always at the top (i.e., in front), object 2 is always below (or behind) object 1 but above (or in front of) object 3, and object 3 is always at the bottom (i.e., behind the other objects).

[0095] As previously described, in some embodiments, the structure-aware interlacing system 102 receives user input specifying the visual order of objects at nodes and reorders the assigned visual order of the remaining nodes to generate an auxiliary interlaced digital design. For example, Figures 7A-7CA process flow for generating an auxiliary interlaced digital design 708 in a graphical user interface is shown, according to one or more embodiments. Specifically, in some embodiments, the structure-aware interlacing system 102 generates a graphical user interface 700 including an automatic interlacing element 702 for receiving user input to modify a digital design 704. Furthermore, in one or more embodiments, the structure-aware interlacing system 102 generates an interlaced digital design (e.g., an interlaced image 706) from the digital design 704. Furthermore, in some embodiments, the structure-aware interlacing system 102 receives the user input (e.g., via the graphical user interface 700 of a user device) and utilizes it to generate the auxiliary interlaced digital design 708.

[0096] As described above, in one or more embodiments, the structure-aware interlacing system 102 generates an interlaced digital design, such as the interlaced image 706, from the digital design 704. Figure 7A As shown, the digital design 704 includes four objects, two of which are in front of (or on top of) two other objects. In fact, the digital design 704 lacks any object interleaving. In one or more embodiments, the structure-aware interleaving system 102 utilizes the above-mentioned Figure 2-Figure 6 Some or all of the methods discussed herein generate the interlaced image 706. For example, the structure-aware interlacing system 102 receives user input via the automatic interlacing element 702. Furthermore, in these or other embodiments, in response to receiving user input via the automatic interlacing element 702, the structure-aware interlacing system 102 generates the interlaced image 706, e.g., Figure 7B In effect, interleaved image 706 shows an interleaved digital design in which structure-aware interleaving system 102 orders overlapping surfaces of objects to have different objects on top of adjacent overlapping surfaces (eg, as previously described, this is related to nodes in a structure diagram).

[0097] As described above, in some embodiments, the structure-aware interlacing system 102 receives user input (e.g., via the graphical user interface 700 of the user device) and utilizes it to generate an auxiliary interlaced digital design 708. For example, Figure 7B The structure-aware interlacing system 102 is shown receiving user input at one or two locations indicated by two rectangles, each of which contains overlapping surfaces of an object. In this example, the structure-aware interlacing system 102 receives user input (e.g., via a user indication such as a mouse click) indicating a user-assigned visual order for one or both of these particular overlapping surfaces of the object that is different from the visual order of the interlaced image 706. In other words, the structure-aware interlacing system 102 receives user input indicating a change in the visual order at the specified overlapping surfaces.

[0098] To further illustrate, the structure-aware interlacing system 102 utilizes user input to generate an auxiliary interlaced digital design 708, such as Figure 7C For example, as shown in the assisted interleaved digital design 708, the structure-aware interleaving system 102 is based on (by Figure 7B In some embodiments, the structure-aware interlacing system 102 generates the auxiliary interlaced digital design 708 using a heuristic that causes adjacent overlapping regions to have different objects on top and seeks to achieve interlaced symmetry to reorder the visual order of the remaining overlapping surfaces relative to the changed overlapping surfaces specified in the user input. In addition, in some embodiments, the structure-aware interlacing system 102 retains the changes in visual order at the two designated overlapping surfaces even if the changes are inconsistent with changes in adjacent overlapping surfaces. For example, although the structure-aware interlacing system 102 uses a heuristic to generate the auxiliary interlaced digital design 708, the structure-aware interlacing system 102 also generates the auxiliary interlaced digital design such that some adjacent overlapping regions have the same object in front due to changes made in response to the user input.

[0099] In this manner, in one or more embodiments, the structure-aware interlacing system 102 generates the auxiliary interlaced digital design 708. In particular, in these or other embodiments, the structure-aware interlacing system 102 generates the auxiliary interlaced digital design 708 by ordering adjacent overlapping surfaces of the object having different objects to have an interlaced appearance. Thus, in these or other embodiments, the structure-aware interlacing system 102 generates the interlaced image 706 and the auxiliary interlaced digital design 708 to respectively interlace the objects, but utilize different object orderings at various overlapping surfaces.

[0100] Moreover, in one or more embodiments, the structure-aware interleaving system 102 changes the visual order of each overlapping region in response to receiving user input. Furthermore, in these or other embodiments, the structure-aware interleaving system 102 uses an algorithm such as Algorithm 2 below (i.e., Assisted Constrained Color Assignment) to change the visual order. For example, in these or other embodiments, the structure-aware interleaving system 102 treats user input to assign a new visual order to a given node as a constrained color assignment for that node / overlapping surface. In other words, the structure-aware interleaving system 102 will not assign any other color to that node. In fact, for the constrained color assignment, the structure-aware interleaving system 102 automatically assigns ω * (v).

[0101]

[0102] As described above, in various embodiments, the structure-aware interleaving system 102 interleaves all overlapping positions, interleaves a certain percentage of overlapping positions, or skips positions that do not meet a threshold distance from a previously interleaved position. For example, in one or more embodiments, the structure-aware interleaving system 102 assigns a visual order to a set percentage of nodes corresponding to overlapping positions of objects in the digital design. Furthermore, in one or more implementations, the structure-aware interleaving system 102 assigns a visual order to some nodes but not others based on a determination of the surface area between the nodes.

[0103] As described above, in some embodiments, the structure-aware interlacing system 102 assigns a visual order to a set percentage of nodes. For example, in these or other embodiments, the structure-aware interlacing system 102 receives user input (e.g., via a user interface of a client device) that sets the percentage of nodes to be assigned a visual order. Furthermore, in some implementations, the structure-aware interlacing system 102 uses an algorithm to assign a visual order to the set percentage of nodes. For example, in these or other embodiments, the structure-aware interlacing system 102 uses Algorithm 2 by using a set percentage k. In these or other embodiments, when k is below a 50% threshold, this promotes "sparse interlacing." In effect, in these or other embodiments, the structure-aware interlacing system 102 utilizes sparse interlacing to give the interlaced digital design a unique appearance (e.g., a more random interlaced appearance or a less interlaced appearance).

[0104] Furthermore, in some embodiments, the structure-aware interleaving system 102 uses various mechanisms to determine which nodes to assign visual order to satisfy a set percentage. In one or more embodiments, the structure-aware interleaving system 102 determines which nodes to assign visual order to by determining the weights of the nodes. In these or other embodiments, a node has a larger weight when the surface area between the node and its adjacent nodes is larger. Accordingly, in these or other embodiments, the structure-aware interleaving system 102 identifies a plurality of top weighted nodes that satisfy the set percentage and assigns visual order to these top weighted nodes, while not assigning visual order to the remaining nodes.

[0105] As described above, in one or more embodiments, the structure-aware interlacing system 102 assigns a visual order to some nodes but not others based on a determination of a digital design surface area between the nodes. For example, in these or other embodiments, the structure-aware interlacing system 102 assigns a visual order to a first node but does not assign a visual order to a second node adjacent to the first node. Specifically, in these or other embodiments, the structure-aware interlacing system 102 determines that the digital design surface area between the first node and the second node fails to meet a threshold surface area size. In practice, in one or more implementations, the structure-aware interlacing system 102 receives a value for the threshold surface area via user input, or the structure-aware interlacing system 102 determines the value using an algorithm.

[0106] Furthermore, in some embodiments, structure-aware interlacing system 102 assigns a visual order to some nodes but not others based on a determination of the relative surface areas between various nodes. Specifically, in these or other embodiments, structure-aware interlacing system 102 determines the surface area of the digital design between several adjacent nodes. In one example, structure-aware interlacing system 102 determines that the surface area between two nodes is significantly smaller than the surface area between other adjacent nodes of the digital design. In these or other embodiments, structure-aware interlacing system 102 does not assign a visual order to one of the two nodes separated by the significantly smaller surface area. In some implementations, structure-aware interlacing system 102 determines the threshold relative surface area size through user input or using an algorithm with a preset threshold. In this way, structure-aware interlacing system 102 maintains an interlaced appearance in the interlaced digital design by skipping nodes that are too close together to be perceived as interlaced.

[0107] As described above, in one or more embodiments, the structure-aware interlacing system 102 generates and provides multiple interlacing options having different visual orderings of overlapping surfaces for visualization and selection with minimal interaction (e.g., a single interaction). More specifically, the structure-aware interlacing system 102 generates multiple alternative interlaced digital designs having different visual orderings by reordering the overlapping surfaces of the objects. For example, in one or more embodiments, the structure-aware interlacing system 102 generates an interlaced digital design having a visual ordering of the overlapping surfaces of the objects to have a staggered appearance. Additionally, in these or other embodiments, the structure-aware interlacing system 102 also generates alternative interlaced digital designs.

[0108] By way of example, the structure-aware interlacing system 102 generates an alternative interlaced digital design by reordering the overlapping surfaces of the objects according to an alternative assigned visual order of the nodes. In practice, in these or other embodiments, the alternative assigned visual order of the nodes generated by the structure-aware interlacing system 102 is different from the visual order of the nodes in the first interlaced digital design. Thus, in some embodiments, the structure-aware interlacing system 102 generates multiple alternative interlaced digital designs for a single original digital design, wherein the alternative interlaced digital designs each exhibit the interlacing of the objects, but in different ways. Furthermore, in some implementations, the structure-aware interlacing system 102 generates many different alternative interlaced digital designs for visualization and selection. In practice, for more complex digital designs (e.g., digital designs with many overlapping objects and / or digital designs with many overlapping surfaces between objects), the structure-aware interlacing system 102 generates many different interlaced digital design possibilities (i.e., interlacing options).

[0109] As described above, in one or more embodiments, the structure-aware interlacing system 102 generates an interlaced digital design with interlaced objects from any digital design. For example, Figure 8A and Figure 8B 1. A process flow for generating an interlaced digital design in a graphical user interface according to one or more embodiments is shown. For example, the structure-aware interlacing system 102 receives user input via the automatic interlacing element 802 of the graphical user interface 800 to generate an interlaced digital design 806 from a corresponding original digital design 804.

[0110] Use the above Figure 2 In one or more of the various embodiments described in FIG. 7 , the structure-aware interlacing system 102 generates an interlaced digital design 806 using minimal user input (e.g., a single user interaction). For example, in one or more embodiments, the structure-aware interlacing system 102 displays the original digital design 804 in the graphical user interface 800. Furthermore, in these or other embodiments, the structure-aware interlacing system 102 receives user input via the automatic interlacing element 802. For example, the user input can be a single user interaction with the automatic interlacing element 802. Furthermore, in response to receiving the user input, the structure-aware interlacing system 102 performs the operations described above with respect to the interlacing process. Figure 2 - One or more embodiments described in FIG. 7 to generate Figure 8B The staggered digital design 806 is shown. In fact, Figure 8B As shown, the structure-aware interlacing system 102 displays two objects of the interlaced digital design 806 in the graphical user interface 800 with an interlaced appearance.

[0111] Accordingly, the structure-aware interleaving system 102 uses Figure 2FIG7 illustrates various embodiments for generating an interlaced digital design with multiple objects in an interlaced appearance. In practice, structure-aware interlacing system 102 enables rapid and accurate interlacing of objects in a digital design by utilizing one or more of the aforementioned embodiments. For example, structure-aware interlacing system 102 generates interlaced digital design 806 such that objects are interlaced at each of seven overlapping locations between two objects using a single user interaction. Accordingly, structure-aware interlacing system 102 efficiently and flexibly generates interlaced digital designs with minimal user interaction.

[0112] Steering Figure 9 , additional details will now be provided regarding the various components and capabilities of the structure-aware interleaving system 102. In particular, Figure 9 An example schematic diagram of a computing device 900 (e.g., server(s) 106 and / or client device 110) implementing a structure-aware interleaving system 102 for components 900-910 according to one or more embodiments of the present disclosure is shown. Figure 9 As shown, the structure-aware interleaving system 102 includes an object outline manager 902 , a floor plan structure map manager 904 , a visual order manager 906 , an interleaved digital design manager 908 , and a data storage device 910 .

[0113] In some embodiments, the object outline manager 902 accesses one or more digital design documents. For example, the object outline manager 902 accesses the digital design document(s) and generates outlines of objects within the digital design to determine the boundaries of the objects. In particular, in some embodiments, the object outline manager 902 generates object outlines with the boundaries of the objects so that the object outlines can be further used by additional components of the structure-aware interlacing system 102, such as the floor plan structure diagram manager 904.

[0114] In one or more embodiments, the floor plan and structure graph manager 904 generates a floor plan and a structure graph based on the object boundaries within the digital design. For example, the floor plan and structure graph manager 904 receives object outlines and generates a floor plan 404 that represents overlapping surfaces of objects in the digital design as vertices and object paths between overlapping surfaces as edges. Furthermore, in one or more implementations, the floor plan and structure graph manager 904 performs operations on the floor plan 404. In particular, in some embodiments, the floor plan and structure graph manager 904 performs vertex collapse 406 and / or vertex removal to generate the structure graph 502 from the floor plan 404. Accordingly, in these or other embodiments, the floor plan and structure graph manager 904 generates the structure graph 502 that represents overlapping surfaces of objects in the digital design as nodes and object paths between overlapping surfaces as edges.

[0115] In some embodiments, the visual order manager 906 assigns a visual order to the nodes of the structure diagram 502. For example, the visual order manager 906 receives the structure diagram 502 from the floor plan structure diagram manager 904 and assigns a visual order to the nodes of the structure diagram 502. In practice, in these or other embodiments, the visual order manager 906 assigns a visual order to the nodes of the structure diagram using a heuristic that causes adjacent overlapping regions to have different objects on top and seeks to achieve staggered symmetry. Furthermore, in one or more embodiments, the visual order manager 906 identifies a first node and assigns a first visual order to the first node, and then assigns a different visual order to nodes adjacent to the first node.

[0116] In one or more embodiments, the interlaced digital design manager 908 receives a structural diagram having assigned visual orders to the nodes and generates an interlaced digital design (e.g., the interlaced image 608). For example, the interlaced digital design manager 908 generates the interlaced image 608 by ordering the overlapping surfaces of the objects according to the assigned visual order of the nodes. Additionally, the interlaced digital design manager 908 generates an alternative interlaced digital design by reordering the overlapping surfaces of the objects according to an alternative assigned visual order of the nodes of the structural diagram 502.

[0117] The data storage device 910 stores data sets, documents, and graphics (plans and structure drawings). For example, the data storage device 910 stores digital design documents and stores corresponding structures such as object outlines, plan drawings and structure drawings, the visual order assigned to the structure drawings, and the interleaved digital design of the digital design.

[0118] Each of the components 902-910 of the structure-aware interleaving system 102 may include software, hardware, or both. For example, the components 902-910 may include one or more instructions stored on a computer-readable storage medium and executable by a processor of one or more computing devices (such as a client device or a server device). When executed by one or more processors, the computer-executable instructions of the structure-aware interleaving system 102 may cause the computing device(s) to perform the methods described herein. Alternatively, the components 902-910 may include hardware, such as a dedicated processing device that performs a certain function or group of functions. Alternatively, the components 902-910 of the structure-aware interleaving system 102 may include a combination of computer-executable instructions and hardware.

[0119] Further, the components 902-910 of the structure-aware interlacing system 102 may be implemented, for example, as one or more operating systems, one or more stand-alone applications, one or more modules of an application, one or more plug-ins, one or more library functions or functions that can be called by other applications, and / or a cloud computing model. Thus, the components 902-910 of the structure-aware interlacing system 102 may be implemented as stand-alone applications, such as desktop applications or mobile applications. Further, the components 902-910 of the structure-aware interlacing system 102 may be implemented as one or more web-based applications hosted on a remote server. Alternatively or in addition, the components 902-910 of the structure-aware interlacing system 102 may be implemented in a set of mobile device applications or "apps". For example, in one or more embodiments, the structure-aware interlacing system 102 may include or operate in conjunction with a digital software application, such as ADOBE ADOBE ADOBE MOBILE, PROTEUS, XD、ADOBE MOBILE、ADOBE ADOBE STANDARD、ADOBE DOCUMENT ADOBE CREATIVE CLOUD, ADOBE EXPRESS. The aforementioned are trademarks or registered trademarks of Adobe Systems Incorporated in the United States and / or other countries.

[0120] Figures 1-9 , corresponding text and examples provide various systems, methods, and non-transitory computer-readable media for generating a modified interlaced digital design by generating a structure graph and assigning a visual order to the nodes of the structure graph. In addition to the foregoing, embodiments may also be described in terms of flowcharts including actions for achieving a particular result. For example, Figure 10 and Figure 11 A flow diagram illustrating an example sequence of actions in accordance with one or more embodiments is shown.

[0121] Although Figure 10 and Figure 11 Actions according to some embodiments are shown, but alternative embodiments may omit, add, reorder, and / or modify Figure 10 and Figure 11 Any action shown. Figure 10 and Figure 11Alternatively, the non-transitory computer readable medium may include instructions that, when executed by one or more processors, cause the computing device to perform Figure 10 and Figure 11 In another embodiment, the system may perform Figure 10 and Figure 11 Additionally, actions described herein may be repeated or performed in parallel with each other, or with different instances of the same or other similar actions.

[0122] Figure 10 A series of example acts 1000 for generating an interlaced digital design by generating a structure graph and assigning a visual order to nodes of the structure graph based on a configuration of the structure graph is shown. The series of acts 1000 may include: an act 1002 of generating the interlaced digital design by ordering overlapping surfaces of objects according to the assigned visual order of the nodes; an act 1004 of generating a structure graph of the digital design, the structure graph representing overlapping surfaces of objects in the digital design as nodes and representing object paths between the overlapping surfaces as edges; and an act 1006 of assigning a visual order to the nodes based on the configuration of the structure graph.

[0123] For example, in one or more embodiments, the series of actions 1000 includes: generating, by at least one processor, a structural graph of the digital design, the structural graph representing overlapping surfaces of objects in the digital design as nodes and representing object paths between overlapping surfaces as edges; assigning, by at least one processor, a visual order to the nodes based on a configuration of the structural graph; and generating, by at least one processor, an interleaved digital design by sorting the overlapping surfaces of the objects according to the assigned visual order of the nodes.

[0124] In one or more embodiments, generating a structural diagram of the digital design representing overlapping surfaces of an object in the digital design includes generating a plan view of the object in the digital design. Furthermore, in some embodiments, the series of actions 1000 may include generating overlapping surface vertex groups by determining a plurality of vertices corresponding to the overlapping surfaces of the object in the digital design.

[0125] Furthermore, in some embodiments, the series of actions 1000 includes removing one or more vertices that are not in the overlapping surface vertex group from the plan view. Further, in some embodiments, the series of actions 1000 may include generating a clustered vertex by: determining adjacent vertices corresponding to the overlapping surfaces of the object; and clustering the adjacent vertices to generate a clustered vertex.

[0126] In some embodiments, the series of actions 1000 may include: generating an alternative assigned visual order for the nodes; and generating an alternative staggered digital design by reordering the overlapping surfaces of the objects according to the alternative assigned visual order for the nodes. Furthermore, in some embodiments, the series of actions 1000 may include generating the auxiliary staggered digital design by: receiving, via a graphical user interface of a client device, a user-assigned visual order for designated overlapping surfaces of the objects; and reordering the remaining overlapping surfaces of the objects according to the user-assigned visual order for the designated overlapping surfaces of the objects.

[0127] Additionally, in some embodiments, assigning a visual order to the nodes based on the configuration of the structure graph includes assigning a first visual order to the first node and not assigning any visual order to a second node adjacent to the first node. Further, in some embodiments, not assigning any visual order to the second node adjacent to the first node includes determining that a surface area of the digital design between the first node and the second node fails to satisfy a threshold surface area size.

[0128] In one or more embodiments, assigning a visual order to nodes based on a configuration of the structure graph includes: assigning a first visual order to a first node; assigning a second visual order to a second node adjacent to the first node; and assigning a third visual order to a third node adjacent to the first node and the second node.

[0129] Moreover, in some embodiments, assigning a visual order to the nodes based on the configuration of the structure graph includes utilizing a heuristic that causes adjacent overlapping regions to have different objects on top and seeks to achieve staggered symmetry. Additionally, in some implementations, assigning a visual order to the nodes includes assigning different visual orders to adjacent nodes.

[0130] Figure 11 A series of example actions 1100 is shown for generating a modified staggered digital design by generating outlines of objects within the digital design to determine the boundaries of the objects; generating a structure graph of the digital design based on the boundaries of the objects; and assigning a visual order to the nodes of the structure graph. The series of actions 1100 may include: an action 1102 of generating the staggered digital design by sorting overlapping surfaces of the objects according to the assigned visual order of the nodes; an action 1104 of generating outlines of the objects within the digital design to determine the boundaries of the objects; an action 1106 of generating a structure graph of the digital design based on the boundaries of the objects, the structure graph representing overlapping surfaces of the objects in the digital design as nodes and object paths between overlapping surfaces as edges; and an action 1108 of assigning a visual order to the nodes of the structure graph using a heuristic that causes adjacent overlapping regions to have different objects on top and seeks to achieve staggered symmetry.

[0131] Furthermore, in some embodiments, the series of actions 1100 may include: generating outlines of objects within the digital design to determine boundaries of the objects; generating a structural graph of the digital design based on the boundaries of the objects, the structural graph representing overlapping surfaces of the objects in the digital design as nodes and representing object paths between overlapping surfaces as edges; assigning a visual order to the nodes of the structural graph using a heuristic method that causes adjacent overlapping areas to have different objects on top and seeks to achieve staggered symmetry, and generating a staggered digital design by sorting the overlapping surfaces of the objects according to the assigned visual order of the nodes.

[0132] Further, in some embodiments, assigning a visual order to the nodes includes: assigning a first visual order to the first node; and assigning a second visual order to a second node adjacent to the first node. In one or more embodiments, the series of actions 1100 may include determining the first node by identifying a node having at least one of a highest number of adjacent nodes or a highest possible number of visual orders from among the nodes.

[0133] Furthermore, in some embodiments, the series of actions 1100 may include determining a second node adjacent to the first node by identifying, from among the nodes, that the second node shares an edge with the first node in the structure graph. Furthermore, in some implementations, the series of actions 1100 may include assigning a first visual order priority to a first object among the objects in the digital design; and assigning a second visual order priority to a second object among the objects in the digital design.

[0134] Further, in some embodiments, assigning the first visual order to the first node includes assigning a first visual order priority to the first node. In some implementations, assigning the visual order to the nodes includes assigning the visual order to a set percentage of the nodes.

[0135] For example, embodiments of the present disclosure may include or utilize a special-purpose or general-purpose computer that includes computer hardware (such as one or more processors and system memory), as discussed in more detail below. Implementations within the scope of the present disclosure also include physical media and other computer-readable media for carrying or storing computer-executable instructions and / or data structures. In particular, one or more processes described herein may be implemented at least in part as instructions embodied in a non-transitory computer-readable medium and executable by one or more computing devices (e.g., any media content access device described herein). Generally speaking, a processor (e.g., a microprocessor) receives instructions from a non-transitory computer-readable medium (e.g., a memory, etc.) and executes these instructions, thereby performing one or more processes, including one or more processes described herein.

[0136] Computer-readable media can be any available medium that can be accessed by a general-purpose or special-purpose computer system. A computer-readable medium that stores computer-executable instructions is a non-transitory computer-readable storage medium (device). A computer-readable medium that carries computer-executable instructions is a transmission medium. Thus, by way of example and not limitation, embodiments of the present disclosure may include at least two distinct types of computer-readable media: a non-transitory computer-readable storage medium (device) and a transmission medium.

[0137] Non-transitory computer-readable storage media (devices) include RAM (random access memory), ROM (read-only memory), EEPROM (electrically erasable programmable ROM), CD-ROM, solid state drive (SSD) (e.g., based on RAM), flash memory, phase change memory (PCM), other types of memory, other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired program code means in the form of computer-executable instructions or data structures and can be accessed by a general or special purpose computer.

[0138] "Network" is defined as one or more data links that can transmit electronic data between computer systems and / or modules and / or other electronic devices. When information is transmitted or provided to a computer via a network or another communication connection (hardwired, wireless, or a combination of hardwired or wireless), the computer appropriately views the connection as a transmission medium. Transmission media may include networks and / or data links that can be used to carry desired program code means in the form of computer-executable instructions or data structures and that can be accessed by general-purpose or special-purpose computers. Combinations of the above should also be included within the scope of computer-readable media.

[0139] Furthermore, upon reaching various computer system components, program code means in the form of computer-executable instructions or data structures can be automatically transferred from the transmission medium to the non-transitory computer-readable storage medium (device) (or vice versa). For example, computer-executable instructions or data structures received over a network or data link can be buffered in RAM within a network interface module (e.g., a NIC (network interface module)) and then ultimately transferred to the computer system RAM and / or non-volatile computer storage medium (device) at the computer system. Thus, it should be understood that non-transitory computer-readable storage media (devices) can be included in computer system components that also (or even primarily) utilize transmission media.

[0140] Computer executable instructions include instructions and data, for example, when executed by a processor, the instructions and data cause a general-purpose computer, a special-purpose computer or a special-purpose processing device to perform a certain function or function group. In some embodiments, computer executable instructions are executed on a general-purpose computer to convert the general-purpose computer into a special-purpose computer that implements each element of the present disclosure. For example, computer executable instructions can be binary intermediate format instructions (such as assembly language), or even source code. Although the subject matter has been described in a language dedicated to structural features and / or method actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the above-mentioned features or actions. More specifically, the described features and actions are disclosed as example forms of implementing the claims.

[0141] Those skilled in the art will appreciate that the present disclosure can be practiced in a network computing environment with many types of computer system configurations, including personal computers, desktop computers, laptop computers, message processors, handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs (personal computers), minicomputers, mainframe computers, mobile phones, PDAs (Personal Digital Assistants), tablet computers, pagers, routers, switches, and the like. The present disclosure can also be practiced in a distributed system environment in which local computer systems and remote computer systems that are linked (by hardwired data links, wireless data links, or a combination of hardwired data links and wireless data links) over a network all perform tasks. In a distributed system environment, program modules can be located in both local and remote storage devices.

[0142] Embodiments of the present disclosure may also be implemented in a cloud computing environment. In this specification, "cloud computing" is defined as a model for enabling on-demand network access to a shared pool of configurable computing resources. For example, cloud computing can be employed in a market to provide ubiquitous and convenient on-demand access to a shared pool of configurable computing resources. This shared pool of configurable computing resources can be rapidly provisioned via virtualization, released with minimal management effort or service provider interaction, and then scaled accordingly.

[0143] For example, a cloud computing model can be comprised of various characteristics, such as on-demand self-service, broad network access, resource pooling, rapid elasticity, and measured services. For example, a cloud computing model can also expose various service models, such as Software as a Service (SaaS), Platform as a Service (PaaS), and Infrastructure as a Service (IaaS). A cloud computing model can also be deployed using different deployment models, such as private cloud, community cloud, public cloud, and hybrid cloud. Throughout this specification and claims, a "cloud computing environment" is an environment that employs cloud computing.

[0144] Figure 12 A block diagram of an exemplary computing device 1200 (e.g., server(s) 106 and / or client device 110) that may be configured to perform one or more of the above-described processes is shown. It will be understood that server(s) 106 and / or client device 110 may include one or more computing devices, such as computing device 1200. Figure 12 As shown, computing device 1200 may include a processor 1202, memory 1204, storage device 1206, I / O interface 1208, and communication interface 1210, which may be communicatively coupled via a communication infrastructure 1212. Figure 12 An exemplary computing device 1200 is shown in FIG. Figure 12 The components shown are not intended to be limiting. In other embodiments, additional or alternative components may be used. Further, in some embodiments, the computing device 1200 may include more than Figure 12 Fewer components are shown. Figure 12 Components of computing device 1200 are shown.

[0145] In particular embodiments, processor 1202 includes hardware for executing instructions, such as instructions that comprise a computer program. By way of example and not limitation, to execute instructions, processor 1202 may retrieve (or fetch) instructions from internal registers, internal caches, memory 1204, or storage device 1206, and decode and execute them. In particular embodiments, processor 1202 may include one or more internal caches for data, instructions, or addresses. By way of example and not limitation, processor 1202 may include one or more instruction caches, one or more data caches, and one or more translation lookaside buffers (TLBs). The instructions in the instruction caches may be copies of the instructions in memory 1204 or storage device 1206.

[0146] Memory 1204 may be used to store data, metadata, and programs for execution by the processor(s). Memory 1204 may include one or more volatile and non-volatile memories, such as random access memory (RAM), read-only memory (ROM), solid-state disk (SSD), flash memory, phase-change memory (PCM), or other types of data storage devices. Memory 1204 may be internal memory or distributed memory.

[0147] Storage device 1206 includes a storage device for storing data or instructions. By way of example and not limitation, storage device 1206 may include the non-transitory storage media described above. Storage device 1206 may include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, storage device 1206 may include removable or non-removable (or fixed) media. Storage device 1206 may be internal or external to computing device 1200. In certain embodiments, storage device 1206 is a non-volatile solid-state memory. In other embodiments, storage device 1206 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0148] The I / O interface 1208 allows a user to provide input to the computing device 1200, receive output from the computing device 1200, and otherwise transmit data to and receive data from the computing device 1200. The I / O interface 1208 may include a mouse, a keypad or keyboard, a touch screen, a camera, an optical scanner, a network interface, a modem, other known I / O devices, or a combination of these I / O interfaces. The I / O interface 1208 may include one or more devices for presenting output to the user, including but not limited to a graphics engine, a display (e.g., a display screen), one or more output drivers (e.g., a display driver), one or more audio speakers, and one or more audio drivers. In some embodiments, the I / O interface 1208 is configured to provide graphical data to the display for presentation to the user. The graphical data may represent one or more graphical user interfaces and / or any other graphical content that may serve a particular embodiment.

[0149] The communication interface 1210 may include hardware, software, or both. In any case, the communication interface 1210 may provide one or more interfaces for communication (e.g., packet-based communication) between the computing device 1200 and one or more other computing devices or networks. By way of example and not limitation, the communication interface 1210 may include a network interface controller (NIC) or network adapter for communicating with an Ethernet or other wired network, or a wireless NIC (WNIC) or wireless adapter for communicating with a wireless network (such as Wi-Fi).

[0150] Additionally or alternatively, the communication interface 1210 can facilitate communication with one or more portions of an ad hoc network, a personal area network (PAN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), or the Internet, or a combination of two or more of these. One or more portions of one or more of these networks can be wired or wireless. As an example, the communication interface 1210 can facilitate communication with a wireless PAN (WPAN) (e.g., a Bluetooth WPAN), a WI-FI network, a WI-MAX network, a cellular telephone network (e.g., a Global System for Mobile Communications (GSM) network), or other suitable wireless networks, or a combination thereof.

[0151] Additionally, communication interface 1210 may facilitate communications in various communication protocols. Examples of communication protocols that may be used include, but are not limited to, data transmission media, communication equipment, Transmission Control Protocol (TCP), Internet Protocol (IP), File Transfer Protocol (FTP), remote login, Hypertext Transfer Protocol (HTTP), Hypertext Transfer Protocol Secure (HTTPS), Session Initiation Protocol (SIP), Simple Object Access Protocol (SOAP), Extensible Markup Language (XML) and its variants, Simple Mail Transfer Protocol (SMTP), Real-Time Transport Protocol (RTP), User Datagram Protocol (UDP), Global System for Mobile Communications (GSM) technology, Code Division Multiple Access (CDMA) technology, Time Division Multiple Access (TDMA) technology, Short Message Service (SMS), Multimedia Message Service (MMS), Radio Frequency (RF) technology, and the like. frequency (RF) signaling technology, Long Term Evolution (LTE) technology, wireless communication technology, in-band and out-of-band signaling technology, and other suitable communication networks and technologies.

[0152] The communication infrastructure 1212 may include hardware, software, or both that couples components of the computing device 1200 to each other. By way of example and not limitation, the communication infrastructure 1212 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a front-side bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, a Wireless Broadband Interconnect, a low-pin-count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association local (VLB) bus, or another suitable bus or combination thereof.

[0153] In the foregoing description, the present invention has been described with reference to specific exemplary embodiments thereof. Various embodiments and aspects of the present invention have been described with reference to the details discussed herein, and the accompanying drawings illustrate various embodiments. The above description and the accompanying drawings are illustrative of the present invention and should not be construed as limiting the present invention. Numerous specific details have been described to provide a thorough understanding of the various embodiments of the present invention.

[0154] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. The described embodiments are to be considered in all respects only as illustrative and not restrictive. For example, the methods described herein may be performed using fewer or more steps / actions, or these steps / actions may be performed in a different order. In addition, the steps / actions described herein may be repeated or performed in parallel with each other, or repeated or performed in parallel with different instances of the same or similar steps / actions. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description. All changes within the meaning and scope of the equivalents of the claims are included within the scope of the claims.

Claims

1. A computer-implemented method comprising: generating, by at least one processor, a structural graph of a digital design, the structural graph representing overlapping surfaces of objects in the digital design as nodes and object paths between the overlapping surfaces as edges; assigning, by the at least one processor, a visual order to the nodes based on a configuration of the structure graph; as well as An interlaced digital design is generated by the at least one processor by ordering the overlapping surfaces of the object according to the assigned visual order of the nodes.

2. The computer-implemented method of claim 1 , wherein generating the structural diagram of the digital design representing overlapping surfaces of objects in the digital design comprises: A plan view of the object in the digital design is generated.

3. The computer-implemented method of claim 2 , further comprising: An overlapping surface vertex group is generated by determining a plurality of vertices corresponding to the overlapping surfaces of the object in the digital design.

4. The computer-implemented method of claim 3 , further comprising: One or more vertices that are not in the set of overlapping surface vertices are removed from the planar graph.

5. The computer-implemented method of claim 2 , further comprising generating the aggregated vertices by: determining adjacent vertices corresponding to the overlapping surfaces of the object; and The adjacent vertices are aggregated to generate the aggregated vertex.

6. The computer-implemented method of claim 1 , further comprising: generating an alternative assigned visual order of the nodes; as well as An alternative staggered digital design is generated by reordering overlapping surfaces of the object according to the alternative assigned visual order of the nodes.

7. The computer-implemented method of claim 1 , further comprising generating an auxiliary interleaved digital design by: receiving, via a graphical user interface of a client device, a user-assigned visual order of designated overlapping surfaces of the objects; and The remaining overlapping surfaces of the objects are reordered according to the user-assigned visual order of the designated overlapping surfaces of the objects.

8. A system comprising: one or more storage devices; as well as One or more processors coupled to the one or more memory devices, the one or more processors configured to cause the system to: generating an outline of an object within the digital design to determine a boundary of the object; generating a structural graph of the digital design based on the boundary of the object, the structural graph representing overlapping surfaces of objects in the digital design as nodes and object paths between the overlapping surfaces as edges; assigning a visual order to the nodes of the structure graph using a heuristic that causes adjacent overlapping regions to have different objects on top and seeks to achieve staggered symmetry; as well as An interlaced digital design is generated by ordering the overlapping surfaces of the objects according to the assigned visual order of the nodes.

9. The system of claim 8, wherein assigning the visual order to the nodes comprises: assigning a first visual order to the first node; as well as A second visual order is assigned to a second node adjacent to the first node.

10. The system of claim 9, wherein the one or more processors are further configured to: The first node is determined by identifying a node from among the nodes that has at least one of a highest number of neighboring nodes or a highest number of possible visual orders.

11. The system of claim 10, wherein the one or more processors are further configured to: The second node adjacent to the first node is determined by identifying, from among the nodes, that the second node shares an edge with the first node in the structure graph.

12. The system of claim 9, wherein the one or more processors are further configured to: assigning a first visual order priority to a first object among the objects within the digital design; and A second visual order priority is assigned to a second object among the objects in the digital design.

13. The system of claim 12, wherein assigning the first visual order to the first node comprises: The first visual order priority is assigned to the first node.

14. The system of claim 8, wherein assigning the visual order to the nodes comprises: Assign the visual order to a set percentage of nodes.

15. A non-transitory computer-readable medium storing executable instructions that, when executed by a processing device, cause the processing device to perform operations comprising: generating a structural graph of a digital design, the structural graph representing overlapping surfaces of objects in the digital design as nodes and object paths between the overlapping surfaces as edges; assigning a visual order to the nodes based on a configuration of the structure graph; as well as An interlaced digital design is generated by ordering the overlapping surfaces of the objects according to the assigned visual order of the nodes.

16. The non-transitory computer-readable medium of claim 15, wherein assigning the visual order to the nodes based on the configuration of the structure graph comprises: A first visual order is assigned to a first node and no visual order is assigned to a second node adjacent to the first node.

17. The non-transitory computer-readable medium of claim 16, wherein not assigning any visual order to the second node adjacent to the first node comprises: It is determined that a surface area of the digital design between the first node and the second node fails to satisfy a threshold surface area size.

18. The non-transitory computer-readable medium of claim 15, wherein assigning the visual order to the nodes based on the configuration of the structure graph comprises: assigning a first visual order to the first node; assigning a second visual order to a second node adjacent to the first node; as well as A third visual order is assigned to a third node adjacent to the first node and the second node.

19. The non-transitory computer-readable medium of claim 15, wherein assigning the visual order to the nodes based on the configuration of the structure graph comprises: A heuristic is used that causes adjacent overlapping regions to have different objects on top and seeks to achieve staggered symmetry.

20. The non-transitory computer-readable medium of claim 15, wherein assigning the visual order to the nodes comprises: Assign different visual orders to adjacent nodes.

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