Module state verification system based on circuit hierarchical design
Through the module state verification system based on circuit-level design, by comparing the sub-design information defined by the target module instance and design library, the problem of inefficient module status verification is solved, and rapid and comprehensive verification and differential item display is achieved, which improves verification efficiency and convenience.
Patent Information
- Application Number
- CN202510634864.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-16
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, module status verification cannot be carried out quickly and comprehensively, especially in the design of complex circuit systems, modification of module instances cannot be determined through module symbol comparison verification, resulting in inefficient verification.
A module state verification system based on circuit hierarchical design is adopted. By obtaining the sub-design information defined by the target module example and the design library, the port, component and connection relationship are compared, the sub-design consistency verification results are generated, and the differences are displayed in a preset display manner.
It realizes fast and comprehensive module status verification, improves verification efficiency and convenience, can intuitively display differences, and improves the application efficiency of sub-design consistency verification.
Smart Images
Figure CN120449779A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of circuit design verification, and in particular to a module state verification system based on circuit hierarchical design. Background Art
[0002] Currently, when designing the principles of complex circuit systems, a hierarchical design method is usually adopted to more intuitively represent the relationship between modules at different levels.
[0003] However, as design complexity continues to rise, the number of modules, circuit structure, and port signal definitions are becoming increasingly complex. The status verification and management of complex modules in hierarchical design have become key issues affecting the quality and reliability of circuit design.
[0004] In the prior art, usually only the module instance and the module symbols defined in the corresponding design library are compared and verified to ensure the reliability of the module symbols of the module instance. However, during the design phase, the designer may modify the module symbols, sub-designs, etc. of the module instance. Since the modifications made by the designer may involve the sub-design of the module instance, it is impossible to determine the modified location by using module symbol comparison and verification. In the existing method, the modification content can usually only be determined through manual inspection and comparison, resulting in the inability to quickly and comprehensively verify the status of the module instance.
[0005] Therefore, how to improve the efficiency and comprehensiveness of module status verification has become an urgent problem to be solved. Summary of the Invention
[0006] In view of the above technical problems, the technical solution adopted by the present invention is:
[0007] A module status verification system based on circuit hierarchical design, the system comprising: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented:
[0008] S101, obtaining first sub-design information of a target module instance and second sub-design information defined in a design library corresponding to the target module instance, wherein the first sub-design information includes port information corresponding to M1 first ports, component information corresponding to N1 first components, and P1 first connection relationships; the second sub-design information includes port information corresponding to M2 second ports, component information corresponding to N2 second components, and P2 second connection relationships, and M1, M2, N1, N2, P1, and P2 are all positive integers.
[0009] S102: Compare and verify the first sub-design information and the second sub-design information to obtain a sub-design consistency verification result, wherein the sub-design consistency verification result includes a plurality of difference items and a comparison result corresponding to each difference item, and each difference item is determined by port information, component information, a first connection relationship, and a second connection relationship.
[0010] S103: Display the sub-design consistency verification result in a preset display mode.
[0011] The present invention has significant advantages over the prior art. By utilizing the above technical solution, the module status verification system based on circuit hierarchical design provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following beneficial effects:
[0012] The present invention compares the first sub-design information of the target module instance with the second sub-design information defined in the design library corresponding to the target module instance to obtain the sub-design consistency verification result, which can quickly verify the differences at the sub-design level, improve the efficiency and comprehensiveness of the module status verification, and through the comparison results of each difference item in the sub-design consistency verification result, the difference items with differences can be intuitively displayed, thereby improving the convenience of verification and analysis of the target module instance, and thereby improving the application efficiency of the sub-design consistency verification result. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 A schematic diagram of a flow chart of a computer program being executed by a processor in a module status verification system based on circuit hierarchical design provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.
[0016] This embodiment provides a module status verification system based on circuit hierarchical design. Figure 1, which is a flow chart of a computer program executed by a processor in a module status verification system based on circuit hierarchical design provided by an embodiment of the present invention. The system includes: a processor and a memory storing the computer program. When the computer program is executed by the processor, the following steps are implemented:
[0017] S101, obtaining first sub-design information of a target module instance and second sub-design information defined in a design library corresponding to the target module instance, wherein the first sub-design information includes port information corresponding to M1 first ports, component information corresponding to N1 first components, and P1 first connection relationships; the second sub-design information includes port information corresponding to M2 second ports, component information corresponding to N2 second components, and P2 second connection relationships, where M1, M2, N1, N2, P1, and P2 are all positive integers;
[0018] S102: Compare and verify the first sub-design information and the second sub-design information to obtain a sub-design consistency verification result, wherein the sub-design consistency verification result includes a plurality of difference items and a comparison result corresponding to each difference item, where each difference item is determined by port information, component information, a first connection relationship, and a second connection relationship;
[0019] S103: Display the sub-design consistency verification result in a preset display mode.
[0020] Among them, the target module instance can be selected by the implementer from the various module instances in the circuit design, or it can be determined by traversing the various module instances in the circuit design in hierarchical order. Usually, the target module instance can correspond to at least one sub-design drawing, and all ports are extracted from all sub-design drawings corresponding to the target module instance as the first port, and the port information of each first port is obtained. Similarly, all components are extracted from all sub-design drawings corresponding to the target module instance as the first component, and the component information of each first component is obtained.
[0021] If the target module instance is instantiated from the design library definition, then the target module instance corresponds to a design library definition. Similarly, the design library definition can also correspond to several sub-design drawings. All ports are extracted from all sub-design drawings corresponding to the design library definition as second ports, and the port information of each second port is obtained. All components are extracted from all sub-design drawings corresponding to the design library definition as second components, and the component information of each second component is obtained.
[0022] The first connection relationship may include the connection relationship between the first port and the first element in the sub-design diagram of the target module instance, and the connection relationship between the first element and the first element. The second connection relationship may include the connection relationship between the second port and the second element in the sub-design diagram defined by the design library, and the connection relationship between the second element and the second element.
[0023] The difference items may specifically represent the objects used for comparison, and the comparison results may include consistency and inconsistency.
[0024] Specifically, when comparing and verifying the first sub-design information and the second sub-design information, each first connection relationship in the first sub-design information is traversed. If the current first connection relationship has a corresponding second connection relationship in the second sub-design information, the comparison result of the difference item corresponding to the current first connection relationship is determined to be consistent. Otherwise, the comparison result of the difference item corresponding to the current first connection relationship is determined to be inconsistent. A single second connection relationship can only correspond to one first connection relationship. If each first connection relationship in the first sub-design information has been traversed and there is still a second connection relationship that does not correspond to a first connection relationship, the comparison result of the difference item corresponding to each second connection relationship that does not correspond to a first connection relationship is determined to be inconsistent.
[0025] Traverse each first port in the first sub-design information. If the second sub-design information does not have a second port corresponding to the current first port, the comparison result of the difference item corresponding to the port information of the current first port is inconsistent. If the second sub-design information has a second port corresponding to the current first port, compare the port information of the current first port with the port information of the second port corresponding to the first port. If the comparison is consistent, determine that the comparison result of the difference item corresponding to the port information of the current first port is consistent. If the comparison is inconsistent, determine that the comparison result of the difference item corresponding to the port information of the current first port is inconsistent. If each first port in the first sub-design information has been traversed and there is still a second port that does not correspond to the first port, determine that the comparison result of the difference item corresponding to the port information of each second port that does not correspond to the first port is inconsistent.
[0026] Similarly, traverse each first component in the first sub-design information. If the second sub-design information does not contain a second component corresponding to the current first component, the comparison result of the difference item corresponding to the component information of the current first component is inconsistent. If the second sub-design information contains a second component corresponding to the current first component, compare the component information of the current first component with the component information of the second component corresponding to the first component. If the comparison is consistent, determine that the comparison result of the difference item corresponding to the component information of the current first component is consistent. If the comparison is inconsistent, determine that the comparison result of the difference item corresponding to the component information of the current first component is inconsistent. If each first component in the first sub-design information has been traversed and there is still a second component that does not correspond to the first component, determine that the comparison result of the difference item corresponding to the component information of each second component that does not correspond to the first component is inconsistent.
[0027] The correspondence between the first port and the second port may refer to that the first port and the second port have the same port name, and the correspondence between the first element and the second element may refer to that the first element and the second element have the same element name.
[0028] It should be noted that if the current target module instance contains a lower-level module instance, then after the comparison and verification of the current target module instance is completed, the lower-level module instance contained in the current target module instance is used as the target module instance. If the current target module instance contains multiple lower-level module instances, the target module instance is determined from the lower-level module instances contained in the current target module instance in a traversal manner.
[0029] In one embodiment, when the comparison results corresponding to all difference items are consistent, the sub-design consistency verification result is verification passed; otherwise, the sub-design consistency verification result is verification failed. The sub-design consistency verification result can be directly displayed as a verification result in a preset display method in the user interaction interface.
[0030] In one embodiment, ports or components corresponding to the difference items with inconsistent comparison results may be color-coded in the sub-design drawing, so that the implementer can quickly locate the difference items with inconsistent comparison results in the sub-design drawing.
[0031] In a specific embodiment, the port information includes at least a port type and a port location, and the component information includes at least a component type, a component attribute, and a component location;
[0032] Accordingly, each difference item is determined by the port type and port position, component type, component attribute, component position, first connection relationship and second connection relationship.
[0033] In order to improve the precision of the difference item comparison, the port information can be divided into port type and port position for comparison, and the component information can be divided into component type, component attribute and component position for comparison.
[0034] The port type may include an output port type and an input port type, and the port position may refer to the coordinate information of the port in the sub-design drawing.
[0035] Component type can be used to distinguish different components, component attributes can include package type, manufacturer, operating temperature, source, etc., and component position can refer to the coordinate information of the component in the sub-design drawing.
[0036] In one embodiment, the component attributes may be further divided into a plurality of difference items for comparison, so that the implementer can more quickly determine the difference items with inconsistent comparison results.
[0037] In one embodiment, the implementer can filter the difference items, for example, all the difference items and their corresponding check boxes are displayed to the implementer in the user interaction interface. The implementer selects the difference items to be filtered by clicking the check boxes. The difference items to be filtered will no longer be compared and will not affect the sub-design consistency verification results.
[0038] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:
[0039] S201, obtaining module instance symbol information corresponding to the target module instance and design symbol information defined in a design library corresponding to the target module instance;
[0040] S202, determining a hierarchical synchronization verification result according to the module instance symbol information and the port information corresponding to the M1 first ports;
[0041] S203, determining a symbol consistency verification result based on the module instance symbol information and the design symbol information;
[0042] Accordingly, displaying the sub-design consistency verification result in a preset display mode includes:
[0043] The sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result are displayed in the preset display mode.
[0044] The module instance symbol information includes K1 first symbol ports, and the design symbol information includes K2 second symbol ports, where K1 and K2 are both positive integers.
[0045] Specifically, the hierarchical synchronization verification result is determined based on the module instance symbol information and the port information corresponding to the M1 first ports. This may refer to comparing each first symbol port with the port name of each first port. If each first symbol port has a corresponding first port, the hierarchical synchronization verification result is determined to be consistent. Otherwise, the hierarchical synchronization verification result is determined to be inconsistent. It should be noted that a single first symbol port can correspond to multiple first ports.
[0046] Determining the symbol consistency verification result based on the module instance symbol information and the design symbol information may refer to comparing K1 first symbol ports and K2 second symbol ports. If K1≠K2, the symbol consistency verification result is determined to be inconsistent. If K1=K2, the port names of each first symbol port and each second symbol port are compared. If each first symbol port has a unique corresponding second symbol port, the symbol consistency verification result is determined to be consistent. Otherwise, the symbol consistency verification result is determined to be inconsistent.
[0047] In a specific embodiment, displaying the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result in the preset display mode includes:
[0048] When the verification report is generated in a difference display mode, the verification report is formed and displayed based on the difference items corresponding to the inconsistent comparison results;
[0049] When the verification report is generated in a full display mode, the verification report is formed and displayed by all the difference items and the corresponding comparison results.
[0050] Among them, the module status verification results can be displayed in the form of a verification report. The difference display method can mean that only the difference items with inconsistent comparison results are displayed in the verification report. The full display method can mean that all difference items and the comparison results of each difference item are displayed in the verification report.
[0051] Specifically, the verification report generation method can be selected by the implementer from the difference display method and the full display method according to actual needs.
[0052] In a specific embodiment, displaying the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result in the preset display mode includes:
[0053] If the symbol consistency verification result is consistent, setting the first preset signal light to the first preset color; otherwise, setting the first preset signal light to the second preset color;
[0054] If the hierarchical synchronization verification result is consistent, the second preset signal light is set to the first preset color; otherwise, the second preset signal light is set to the second preset color;
[0055] If the sub-design consistency verification result is consistent, the third preset signal light is set to the first preset color; otherwise, the third preset signal light is set to the second preset color.
[0056] The first preset signal light, the second preset signal light and the third preset signal light may be displayed on a user interaction interface, and the user interaction interface may be used to display the module status verification result to the implementer.
[0057] As an example, the first preset color may be green, and the second preset color may be red.
[0058] It should be noted that the target module instance may be created by the implementer himself in the design rather than instantiated from the design library. The module instance symbol information and sub-design information of such target module instance cannot be compared and verified with the design library definition. Therefore, the first preset signal light and the third preset signal light corresponding to such target module instance can be set to the third preset color. As an example, the third preset color can be gray.
[0059] In a specific embodiment, the displaying of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result in the preset display mode further includes:
[0060] If the sub-design consistency verification result is inconsistent, the difference item corresponding to the inconsistent comparison result is displayed.
[0061] Among them, a trigger condition can be set for displaying the difference items corresponding to the inconsistent comparison results. For example, the trigger condition may be that the implementer performs a first preset operation. After the trigger condition is met, the difference items with inconsistent comparison results can be displayed in the user interaction interface. The first preset operation may refer to double-clicking the sub-design consistency verification result in the user interaction interface, clicking the difference item button, etc. The display of specific difference items can be set by the implementer according to usage habits.
[0062] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:
[0063] S301, obtaining third sub-design information and reference symbol information corresponding to a reference module instance;
[0064] S302, determining a first reference verification result according to the first sub-design information and the third sub-design information;
[0065] S303: Determine a second reference verification result according to the module instance symbol information and the reference symbol information.
[0066] Among them, the reference module instance can be selected by the implementer for comparison and verification between module instances. It is usually applied to the comparison between multiple module instances instantiated from the same design library definition, so that the differences between different module instances can be located through difference items.
[0067] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:
[0068] S204 , when at least one of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result is inconsistent and an update command is received, updating the target module instance with the design library definition corresponding to the target module instance.
[0069] The update command may be issued by the implementer by performing a second preset operation on the user interaction interface. The second preset operation may refer to selecting an update button on the target module instance displayed in the user interaction interface.
[0070] In a specific embodiment, when the computer program is executed by a processor, the following steps are further implemented:
[0071] S204 , when at least one of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result is inconsistent and a replacement command is received, replacing the target module instance with the selected module instance.
[0072] When at least one of the sub-design consistency verification results, the hierarchy synchronization verification results, and the symbol consistency verification results is inconsistent and a replacement command is received, the target module instance is replaced with the module instance selected by the implementer. Similarly, the replacement command can be issued by the implementer by performing a third preset operation on the user interaction interface.
[0073] In a specific embodiment, when a module instance is created, the module file corresponding to the module instance is stored in the cache;
[0074] When the computer program is executed by a processor, the following steps are also implemented:
[0075] If a cache clearing instruction is received, the module files in the cache that do not correspond to module instances are deleted from the cache.
[0076] Among them, during the design process, when a module instance is created, the module file corresponding to the module instance is stored in the cache. Even after the module instance is deleted, the module file corresponding to the module instance is still stored in the cache. In order to improve the cache utilization, this embodiment receives a cache clearing instruction issued by the implementer. After receiving the cache clearing instruction, the module file in the cache that does not correspond to the module instance is deleted from the cache.
[0077] In this embodiment, the first sub-design information of the target module instance and the second sub-design information defined in the design library corresponding to the target module instance are compared to obtain the sub-design consistency verification result, which can quickly verify the differences at the sub-design level, improve the efficiency and comprehensiveness of the module status verification, and through the comparison results of each difference item in the sub-design consistency verification result, the difference items with differences can be intuitively displayed, thereby improving the convenience of verification and analysis of the target module instance, and thereby improving the application efficiency of the sub-design consistency verification result.
[0078] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.
Claims
1. A module status verification system based on circuit hierarchical design, characterized in that: The system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: S101, obtaining first sub-design information of a target module instance and second sub-design information defined in a design library corresponding to the target module instance, wherein the first sub-design information includes port information corresponding to M1 first ports, component information corresponding to N1 first components, and P1 first connection relationships; the second sub-design information includes port information corresponding to M2 second ports, component information corresponding to N2 second components, and P2 second connection relationships, where M1, M2, N1, N2, P1, and P2 are all positive integers; S102: Compare and verify the first sub-design information and the second sub-design information to obtain a sub-design consistency verification result, wherein the sub-design consistency verification result includes a plurality of difference items and a comparison result corresponding to each difference item, where each difference item is determined by port information, component information, a first connection relationship, and a second connection relationship; S103: Display the sub-design consistency verification result in a preset display mode.
2. The module status verification system based on circuit hierarchical design according to claim 1, characterized in that: The port information includes at least the port type and port location, and the component information includes at least the component type, component attributes and component location; Accordingly, each difference item is determined by the port type, port position, component type, component attribute, component position, first connection relationship and second connection relationship.
3. The module status verification system based on circuit hierarchical design according to claim 1, characterized in that: When the computer program is executed by a processor, the following steps are also implemented: S201, obtaining module instance symbol information corresponding to the target module instance and design symbol information defined in a design library corresponding to the target module instance; S202, determining a hierarchical synchronization verification result according to the module instance symbol information and the port information corresponding to the M1 first ports; S203, determining a symbol consistency verification result based on the module instance symbol information and the design symbol information; Accordingly, displaying the sub-design consistency verification result in a preset display mode includes: The sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result are displayed in the preset display mode.
4. The module status verification system based on circuit hierarchical design according to claim 3, characterized in that: The displaying of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result in the preset display mode includes: When the verification report is generated in a difference display mode, the verification report is formed and displayed based on the difference items corresponding to the inconsistent comparison results; When the verification report is generated in a full display mode, the verification report is formed and displayed by all the difference items and the corresponding comparison results.
5. The module status verification system based on circuit hierarchical design according to claim 3, characterized in that: The displaying of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result in the preset display mode includes: If the symbol consistency verification result is consistent, setting the first preset signal light to the first preset color; otherwise, setting the first preset signal light to the second preset color; If the hierarchical synchronization verification result is consistent, the second preset signal light is set to the first preset color; otherwise, the second preset signal light is set to the second preset color; If the sub-design consistency verification result is consistent, the third preset signal light is set to the first preset color; otherwise, the third preset signal light is set to the second preset color.
6. The module status verification system based on circuit hierarchical design according to claim 5, characterized in that: The displaying of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result in the preset display mode further includes: If the sub-design consistency verification result is inconsistent, the difference item corresponding to the inconsistent comparison result is displayed.
7. The module status verification system based on circuit hierarchical design according to claim 3, characterized in that: When the computer program is executed by a processor, the following steps are also implemented: S301, obtaining third sub-design information and reference symbol information corresponding to a reference module instance; S302, determining a first reference verification result according to the first sub-design information and the third sub-design information; S303: Determine a second reference verification result according to the module instance symbol information and the reference symbol information.
8. The module status verification system based on circuit hierarchical design according to claim 3, characterized in that: When the computer program is executed by a processor, the following steps are also implemented: S204 , when at least one of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result is inconsistent and an update command is received, updating the target module instance with the design library definition corresponding to the target module instance.
9. The module status verification system based on circuit hierarchical design according to claim 3, characterized in that: When the computer program is executed by a processor, the following steps are also implemented: S204 , when at least one of the sub-design consistency verification result, the hierarchical synchronization verification result, and the symbol consistency verification result is inconsistent and a replacement command is received, replacing the target module instance with the selected module instance.
10. The module status verification system based on circuit hierarchical design according to claim 1, characterized in that: When a module instance is created, the module file corresponding to the module instance is stored in the cache; When the computer program is executed by a processor, the following steps are also implemented: If a cache clearing instruction is received, the module files in the cache that do not correspond to module instances are deleted from the cache.