Load capacitance optimization method and system based on dichotomy and dynamic variable control

Abstract

The present invention relates to a load capacitance optimization method and system based on dichotomy and dynamic variable control. The method comprises: when performing load capacitance reduction processing on each load capacitance violation signal line, extracting the basic characteristics of the load capacitance of the load capacitance violation signal line, and determining the load capacitance formation characteristics of the load capacitance violation signal line based on the extracted basic characteristics of the load capacitance, selecting a buffer insertion state corresponding to the load capacitance formation characteristics based on the load capacitance formation characteristics of the current load capacitance violation signal line, and performing buffer insertion processing on the current load capacitance violation signal line based on the selected buffer insertion state. The present invention can accurately locate the formation state of large load capacitance, and perform buffer insertion layout according to the formation state of large load capacitance, while reducing the load capacitance, avoiding the risks of timing violations, wiring congestion and excessive power consumption.

Description

Technical Field

[0001] The present invention relates to a load capacitance optimization method and system, in particular to a load capacitance optimization method and system based on dichotomy and dynamic variable control, specifically to an integrated circuit load capacitance optimization method and system based on dichotomy and dynamic variable control. Background Art

[0002] In digital integrated circuits, load capacitance generally includes line parasitic capacitance and the input capacitance of the driven element. Specifically, the load capacitance is the sum of the line parasitic capacitance and the gate input pin capacitance. When the driver transmits a signal to the driven element, the load capacitance must be charged. When the load capacitance is too large, the charging time increases, leading to transition time violations and critical path timing violations. Furthermore, signal lines with high parasitic capacitance are more sensitive to noise, which can easily lead to signal integrity issues.

[0003] As integrated circuit process nodes continue to shrink, interconnect density has increased dramatically, reducing metal line spacing and leading to a significant increase in parasitic capacitance. From 90nm to 7nm, the average parasitic capacitance per unit length of interconnect has increased from 0.1fF / μm to around 0.5fF / μm, making the problem of high load capacitance increasingly prominent.

[0004] The problem of large load capacitance mentioned above can be solved by using large drive units. However, in actual integrated circuits, the use of large drive units has many disadvantages. Specifically: First, continuous high current output will cause voltage drop and electromigration problems, reducing the reliability of the integrated circuit, especially the impact on advanced processes; second, large current can easily interfere with nearby signal lines, causing signal distortion and affecting the normal function of the integrated circuit; third, mobile electronic devices have an increasingly urgent demand for low power consumption. The use of large drive units will lead to increased power consumption of mobile electronic devices, which is not allowed.

[0005] From the above description, it can be seen that the optimization of load capacitance is one of the key challenges for the timing convergence and power consumption control of integrated circuits, and it has very important practical significance. How to effectively optimize the load capacitance of integrated circuits is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a load capacitance optimization method and system based on dichotomy and dynamic variable control, which can accurately locate the formation state of large load capacitance and insert buffer layout according to the formation state of large load capacitance, while reducing the load capacitance, avoiding the risks of timing violations, wiring congestion and excessive power consumption, and improving the effective efficiency of load capacitance.

[0007] According to the technical solution provided by the present invention, a load capacitance optimization method based on dichotomy and dynamic variable control includes:

[0008] A target integrated circuit for load capacitance optimization is provided, and a load capacitance optimization process is performed on the target integrated circuit, wherein the load capacitance optimization process includes:

[0009] Screening and determining all load capacitance violation signal lines in the target integrated circuit that are in a large load capacitance state, and performing load capacitance reduction processing on each load capacitance violation signal line, wherein:

[0010] When performing load capacitance reduction processing on each load capacitance violation signal line, it includes:

[0011] extracting a basic load capacitance characteristic of the load capacitance violation signal line, and determining a load capacitance formation characteristic of the load capacitance violation signal line based on the extracted basic load capacitance characteristic, so as to determine a main cause of the current large load capacitance state of the load capacitance violation signal line by using the load capacitance formation characteristic;

[0012] selecting, based on a load capacitance formation characteristic of a current load capacitance violating signal line, a buffer insertion state corresponding to the load capacitance formation characteristic, and performing a buffer insertion process on the current load capacitance violating signal line based on the selected buffer insertion state, so as to reduce the load capacitance of the current load capacitance violating signal line after the buffer insertion process, wherein, when performing the buffer insertion process, at least a binary method is employed to insert a required buffer into the load capacitance violating signal line;

[0013] The target integrated circuit after the load capacitance optimization process is evaluated. When the evaluation confirms that there are still load capacitance violation signal lines in a large load capacitance state, the above-mentioned load capacitance optimization process is repeated until the evaluation confirms that there are no load capacitance violation signal lines in a large load capacitance state.

[0014] Extract the load capacitance of the signal line with load capacitance violation. The basic characteristics of the load capacitance include the signal transition time under the ideal timing state. 、The line parasitic capacitance of the current load capacitance violation signal line , the gate input pin capacitance information of the fan-out unit corresponding to the current load capacitance violation signal line And the maximum output current of the output pin of the driver unit corresponding to the current load capacitance violation signal line ;

[0015] After extracting the basic characteristics of the load capacitance of the load capacitance violation signal line, the dynamic variable value of the current load capacitance violation signal line is calculated, and the load capacitance formation characteristics of the current load capacitance violation signal line are determined according to the calculated dynamic variable, wherein,

[0016] The load capacitance formation feature includes a long wire length feature representing a main cause of wire length or a high fan-out feature representing a main cause of fan-out.

[0017] When calculating the dynamic variables of the load capacitance violation signal line, we have:

[0018]

[0019] in, is a dynamic variable, is the operating voltage of the target integrated circuit, is the average capacitance of the gate input pin corresponding to the current load capacitance violation signal line;

[0020] The calculated dynamic variable value is compared with the fan-out value of the current load capacitance violation signal line. When the fan-out value of the load capacitance violation signal line is greater than the calculated dynamic variable, the generated load capacitance formation feature is determined as a high fan-out feature; otherwise, the generated load capacitance formation feature is determined as a long line length feature.

[0021] When the load capacitance formation characteristic is determined to be a high fan-out characteristic, the buffer insertion state is configured as a reduced fan-out buffer insertion, wherein,

[0022] When the buffer insertion state is configured as fan-down buffer insertion and the buffer insertion process is performed using a binary method, the inserted buffer should reduce the fan-out value corresponding to the current load capacitance violation signal line by half.

[0023] When the load capacitance forming characteristic is determined to be a long line length characteristic, the buffer insertion state is configured as a reduced line length buffer insertion, wherein,

[0024] When the buffer insertion state is configured as line length reduction buffer insertion and the buffer insertion process is performed using a binary method, the inserted buffer should reduce the line length corresponding to the current load capacitance violation signal line by half.

[0025] When performing load capacitance reduction processing on each load capacitance violation signal line, it also includes routing optimization processing of the current load capacitance violation signal line, wherein,

[0026] After performing buffer insertion processing on the load capacitance violation signal line, a signal line to be optimized is generated, and then a routing optimization processing is performed on the signal line to be optimized, wherein:

[0027] When performing routing optimization, it includes:

[0028] Configuring routing optimization rules, wherein the configured routing rules at least include prohibiting top metal routing, signal line width, and / or signal line spacing;

[0029] Based on the configured routing optimization rules, the signal line to be optimized for routing is routed. When the routing of the signal line to be optimized for routing fails, the above-mentioned signal line spacing is adjusted until the routing of the signal line to be optimized reaches a successful state.

[0030] When configuring routing optimization rules, first increase the signal line spacing of the signal lines to be optimized, where:

[0031] When the routing of the signal line to be optimized fails, the signal line spacing corresponding to the signal line to be optimized is gradually reduced until the routing of the signal line to be optimized reaches a successful state.

[0032] The target integrated circuit is at least in an automatic placement and routing completion state;

[0033] Screening for load capacitance violation signal lines with large load capacitance within the target integrated circuit includes:

[0034] Obtaining the line parasitic capacitance and the corresponding gate input pin capacitance corresponding to each signal line in the target integrated circuit, and adding the line parasitic capacitance and the gate input pin capacitance of each signal line to generate the load capacitance of the current signal line;

[0035] The load capacitance of each signal line is compared with a load capacitance threshold. When the load capacitance of the signal line is greater than the load capacitance threshold, the current signal line is in a large load capacitance state, and the current signal line is regarded as a load capacitance violation signal line.

[0036] When obtaining the parasitic capacitance of each signal line, include:

[0037] Extracting parasitic parameters of the target integrated circuit to obtain a standard parasitic parameter exchange format file that characterizes the parasitic parameter state of the target integrated circuit;

[0038] Determine the line parasitic capacitance corresponding to each signal line based on the standard parasitic parameter exchange format file;

[0039] When obtaining the gate input pin capacitance of each signal line, include:

[0040] Query the timing library file of the target integrated circuit to obtain the gate input pin capacitance of the current signal line.

[0041] A load capacitance optimization system based on dichotomy and dynamic variable control includes a load capacitance optimization device, wherein the load capacitance optimization device optimizes any target integrated circuit to be load capacitance optimized using the above-mentioned load capacitance optimization method.

[0042] The advantages of the present invention are as follows: for a target integrated circuit, load capacitance violation signal lines in a large load capacitance state are screened and determined, and then load capacitance reduction processing is performed on the load capacitance violation signal lines, wherein, during the load capacitance reduction processing, the basic load capacitance characteristics of the load capacitance violation signal lines are first extracted to determine the load capacitance formation characteristics, and then the buffer insertion state is selected according to the load capacitance formation state, and the corresponding buffer insertion processing is performed, that is, the formation state of the large load capacitance can be accurately located through the load capacitance formation characteristics, and the buffer insertion layout is performed using a binary method according to the formation state of the large load capacitance, thereby minimizing the number of buffer insertions and accurately locating the insertion position, while reducing the load capacitance, avoiding the risks of timing violations, wiring congestion and excessive power consumption, and improving the load capacitance optimization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a flow chart of an embodiment of the load capacitance optimization method of the present invention.

[0044] Figure 2 This is a schematic diagram of an embodiment of the present invention after performing buffer insertion processing.

[0045] Figure 3 This is a schematic diagram of another embodiment after the buffer insertion process is performed in the present invention.

[0046] Figure 4 A schematic diagram of an embodiment of the routing of a signal line with load capacitance violation is shown.

[0047] Figure 5 For the present invention Figure 4 A schematic diagram of an embodiment of the wiring after routing optimization processing is performed.

[0048] Figure 6 for Figure 5 Schematic diagram of an embodiment of the parasitic capacitance of the signal line in FIG. DETAILED DESCRIPTION

[0049] From the above description, it can be seen that when large load capacitance appears, the load capacitance needs to be optimized and the corresponding load capacitance is reduced through optimization. At present, the conventional means in the industry to reduce load capacitance is to insert buffers to reduce the line length and fan-out value of the signal line, but there are obvious limitations: First, there is no quantitative control mechanism. When using tool commands to insert buffers in batches, the tool cannot accurately judge the main contradiction causing large load capacitance, whether to prioritize breaking long lines or reducing fan-out, resulting in low optimization efficiency; second, the strategy is rigid. The number and position of buffer insertions rely on experience or tool default rules. There is a lack of mathematical convergence model, which easily leads to substandard optimization of large load capacitance and requires multiple iterations, affecting the design cycle. In addition, doing so easily leads to the insertion of excessive buffers, with the risk of timing violations, routing congestion and excessive power consumption.

[0050] It should be noted that the tools and tool commands mentioned above are generally commonly used tools for integrated circuit design, or commonly used tools and corresponding tool commands used for integrated circuit optimization. The tools and tool commands are well known to people in this technical field and will not be repeated here.

[0051] In recent years, some studies have proposed methods for calculating the number and location of buffer insertions. For example, in the application with publication number CN 117151018 A, the applicant proposed inserting buffers along each signal path connecting the load gate to amplify the signal, optimize the logic gate delay of the driving gate and the interconnection wire delay to solve the timing problem caused by large load capacitance, and proposed an algorithm model to obtain the optimal solution for the number and location of inserted buffers. However, it inserts buffers according to each load gate in sequence. For signal lines with large load capacitance, it lacks the judgment on the main contradiction between long line length and high fan-out, and cannot accurately quantify the judgment of the main contradiction. Therefore, it can be seen that it cannot solve the global load distribution problem in the mixed scenario of high fan-out network and long line length. Therefore, the technical solution adopted in the application still cannot meet the optimization requirements for large load capacitance.

[0052] In order to accurately locate the formation state of large load capacitance and insert and layout buffers according to the formation state of large load capacitance, while reducing load capacitance, avoiding the risks of timing violations, wiring congestion, and excessive power consumption, and improving the optimization efficiency of large load capacitance, the present invention provides a load capacitance optimization method based on dichotomy and dynamic variable control. Specifically, the load capacitance optimization method includes:

[0053] A target integrated circuit for load capacitance optimization is provided, and a load capacitance optimization process is performed on the target integrated circuit, wherein the load capacitance optimization process includes:

[0054] Screening and determining all load capacitance violation signal lines in the target integrated circuit that are in a large load capacitance state, and performing load capacitance reduction processing on each load capacitance violation signal line, wherein:

[0055] When performing load capacitance reduction processing on each load capacitance violation signal line, it includes:

[0056] extracting a basic load capacitance characteristic of the load capacitance violation signal line, and determining a load capacitance formation characteristic of the load capacitance violation signal line based on the extracted basic load capacitance characteristic, so as to determine a main cause of the current large load capacitance state of the load capacitance violation signal line by using the load capacitance formation characteristic;

[0057] selecting, based on a load capacitance formation characteristic of a current load capacitance violating signal line, a buffer insertion state corresponding to the load capacitance formation characteristic, and performing a buffer insertion process on the current load capacitance violating signal line based on the selected buffer insertion state, so as to reduce the load capacitance of the current load capacitance violating signal line after the buffer insertion process, wherein, when performing the buffer insertion process, at least a binary method is employed to insert a required buffer into the load capacitance violating signal line;

[0058] The target integrated circuit after the load capacitance optimization process is evaluated. When the evaluation confirms that there are still load capacitance violation signal lines in a large load capacitance state, the above-mentioned load capacitance optimization process is repeated until the evaluation confirms that there are no load capacitance violation signal lines in a large load capacitance state.

[0059] Figure 1 A flow chart of the load capacitance optimization of the present invention is shown in the figure. As can be seen from the figure, when performing load capacitance optimization, a target integrated circuit should be provided. Specifically, the target integrated circuit is the integrated circuit to be load capacitance optimized, that is, the object of the load capacitance optimization of the present invention is the signal line in the target integrated circuit that is in a large load capacitance state. In specific implementation, the signal line in the large load capacitance state is called a load capacitance violation signal line. When performing load capacitance optimization on the target integrated circuit, all load capacitance violation signal lines in the target integrated circuit should be screened and determined. Thereafter, a load capacitance reduction process is performed on each load capacitance violation signal line. The load capacitance reduction process can reduce the load capacitance corresponding to each load capacitance violation signal line, so as to achieve the purpose of load capacitance optimization.

[0060] Depend on Figure 1 As can be seen from the above description, when optimizing the load capacitance of a target integrated circuit, it is necessary to first screen and determine the load capacitance violation signal lines in the target integrated circuit that are in a large load capacitance state. When screening and determining the load capacitance violation signal lines, there are:

[0061] In one embodiment of the present invention, the target integrated circuit is at least in an automatic placement and routing completion state;

[0062] Screening for load capacitance violation signal lines with large load capacitance within the target integrated circuit includes:

[0063] Obtaining the line parasitic capacitance and the corresponding gate input pin capacitance corresponding to each signal line in the target integrated circuit, and adding the line parasitic capacitance and the gate input pin capacitance of each signal line to generate the load capacitance of the current signal line;

[0064] The load capacitance of each signal line is compared with a load capacitance threshold. When the load capacitance of the signal line is greater than the load capacitance threshold, the current signal line is in a large load capacitance state, and the current signal line is regarded as a load capacitance violation signal line.

[0065] It should be noted that in order to screen and determine the load capacitance violation signal lines within the target integrated circuit, the target integrated circuit should at least be in the automatic layout and routing completion state, that is, the target integrated circuit should first be automatically layout and routing processed, and only then can the target integrated circuit be screened and determined for the load capacitance violation signal lines, as well as subsequent load capacitance optimization. Among them, the method of automatically layout and routing the integrated circuit is consistent with the existing technology, that is, the existing technology can be used to determine whether the target integrated circuit is in the automatic layout and routing completion state.

[0066] From the above description of the load capacitance violation signal line, it can be seen that in order to screen and determine the load capacitance violation signal line, the line parasitic capacitance and gate input pin capacitance corresponding to each signal line in the target integrated circuit should be obtained first, wherein the correspondence between the line parasitic capacitance, gate input pin capacitance of each signal line and the signal line is consistent with the prior art. From the meaning of the load capacitance, it can be seen that the line parasitic capacitance of each signal line and the capacitance value corresponding to the gate input pin capacitance are added to obtain the load capacitance of the current signal line. Therefore, it can be seen that the load capacitance of the signal line refers to the load capacitance value corresponding to the signal line.

[0067] In one embodiment of the present invention, obtaining the line parasitic capacitance of each signal line includes:

[0068] Extracting parasitic parameters of the target integrated circuit to obtain a standard parasitic parameter exchange format file that characterizes the parasitic parameter state of the target integrated circuit;

[0069] Determine the line parasitic capacitance corresponding to each signal line based on the standard parasitic parameter exchange format file;

[0070] When obtaining the gate input pin capacitance of each signal line, include:

[0071] Query the timing library file of the target integrated circuit to obtain the gate input pin capacitance of the current signal line.

[0072] Specifically, existing technical means can be used to extract the parasitic parameters of the target integrated circuit, and then a standard parasitic parameter exchange format file can be obtained. Generally, the standard parasitic parameter exchange format file is an SPEF file, wherein the storage in the SPEF has a fixed format, such as storing the name and number of each signal line in the "*NAME_MAP" list, and then listing the parasitic capacitance value in the format of "*D_NET *number parasitic capacitance value". Therefore, the line parasitic capacitance of each signal line can be obtained through regular matching, wherein regular matching is to perform a matching query through the name and / or number corresponding to each signal line.

[0073] To obtain the gate input capacitance of each signal line, use the gate input capacitance query module within the layout and routing tool environment. Using layout and routing tool commands and TCL scripts, you can retrieve the fan-out unit and driver unit, as well as the corresponding input and output pins, for each signal line. A LIB query key is constructed to query the pin capacitance of the fan-out unit's gate input pins and the maximum output current of the driver unit's output pins. As a timing library file, LIBs describe pin capacitance and output current in a fixed format. Within the cell (cell name) list, each input pin's sublist contains capacitance information, and each output pin's sublist contains output_current information. Therefore, through regular expression matching, you can obtain the corresponding pin capacitance of each fan-out unit's gate input pin and the maximum output current of the driver unit's output pin. For the same signal line, summing the pin capacitances of all fan-out units will yield the corresponding gate input capacitance.

[0074] As can be seen from the above description, the corresponding line parasitic capacitance and gate input pin capacitance can be obtained by the above method. Thereafter, the line parasitic capacitance and the gate input pin capacitance are added to determine the load capacitance of the signal line. When obtaining the load capacitance, the load capacitance of each signal line is compared with the load capacitance threshold. When the load capacitance of the signal line is greater than the load capacitance threshold, the current signal line is in a large load capacitance state, and the current signal line is used as a load capacitance violation signal line. Specifically, the load capacitance threshold is the threshold for determining whether the signal line is in a large load capacitance state. The load capacitance threshold can be determined according to the type of the target integrated circuit and the requirements for load capacitance optimization. The setting method of the load capacitance threshold can be consistent with the existing technology and will not be repeated here.

[0075] It should be understood that after using the above method to screen and determine the load capacitance violation signal lines in a large load capacitance state, the name and / or number of the load capacitance violation signal lines in the target integrated circuit can be determined, thereby accurately controlling the load capacitance reduction processing of each load capacitance violation signal line in the subsequent process.

[0076] To more clearly illustrate the process of screening and determining signal lines with load capacitance violations, the following uses the placement and routing tool IC Compiler II as an example to illustrate the method and process of screening and determining signal lines with load capacitance violations.

[0077] Specifically, it is assumed that the design of the target integrated circuit has sufficient wiring resources, layout and routing have been completed, parasitic parameters have been extracted and the SPEF file has been generated. It is assumed that the interconnection line to be optimized is a digital signal and optimization operations such as inserting a buffer can be performed. Thereafter, the following steps can be used to complete the screening and determination. Specifically,

[0078] Construct a parasitic capacitance query module, a gate input pin capacitance query module, a maximum drive current query module and a sorting module. Among them, the gate input pin capacitance query module and the maximum drive current query module need to be run in the layout and routing tool environment, so TCL scripts are used, and the parasitic capacitance query module and the sorting module use Perl scripts. The method of using TCL scripts to construct the gate input pin capacitance query module and the maximum drive current query module is consistent with the existing technology. In addition, the method of using Perl scripts to construct the parasitic capacitance query module and the sorting module is also consistent with the existing technology. The specific construction method and process will not be repeated here.

[0079] Using a Perl script to build a parasitic capacitance query module, and when performing a parasitic capacitance query, the following steps are performed: Get the signal line name and corresponding number in the "*NAME_MAP" list, and store them in the hash %map for future use, @datanew = split( / s+ / ,$net), $map{$datanew[0]} = $datanew[1]. Then use the regular expression if ($net=~m / ^\*D_NET / ) to find the line parasitic capacitance of each signal line, and store the signal line name and parasitic capacitance value as a key-value pair in the hash %para, that is, $name = $map{$datanew[1]}, $para{$name} = $datanew[2].

[0080] In the place-and-route tool environment, use the gate input pin capacitance query module to perform gate input pin capacitance interpolation. Specifically, use the foreach net $nets loop to query the gate input pin capacitance corresponding to each signal line. Use the commands get_pins [all_connected -leaf $net] -filter {direction==in} and get_attr[get_cells -of_objects $pin]ref_name to obtain the cell name and input pin name. Construct a LIB query key and then use the regular expression regexp {capacitance\s*:\s*([0-9.eE+-]+)\s*;?} $line ->$cell_cap to extract the gate input pin capacitance.

[0081] In the place-and-route tool environment, the maximum drive current query module is similar to the gate input pin capacitance query module. Specifically, the get_pins [all_connected -leaf $net] -filter {direction==out} and get_attr [get_cells -of_objects $pin]ref_name commands can be used to obtain the driver unit name and its output pin name. Based on the existing LIB query key, the maximum drive current can be extracted by using the regular expression {output_current\s*:\s*([0-9.eE+-]+)\s*;?} $line ->$output_current based on the driver unit name.

[0082] Based on the parasitic capacitance and gate input capacitance obtained from the query above, we add them together: $total_cap = $para_cap + $cell_cap. We then store the signal line name and total_cap value as a key-value pair in the hash %total: $total{$name} = $total_cap. We then use the sorting module to sort the signal line names in descending order by load capacitance: @keys = sort{$total{$b} <=> $outdata{$a}} keys %total. Finally, we print out the signal line names and their corresponding load capacitances, filtering out signal lines whose load capacitance exceeds the load capacitance threshold. This results in all signal lines with load capacitance violations.

[0083] In specific implementation, load capacitance reduction processing should be performed on each load capacitance violation signal line. After the load capacitance reduction processing is performed once on all load capacitance violation signal lines, the above-mentioned load capacitance optimization processing is performed. It can be seen that when performing the load capacitance optimization processing, it includes at least performing one or more load capacitance reduction processings, and the number of times the load capacitance reduction processing is performed is consistent with the number of load capacitance violation signal lines determined by screening.

[0084] For each load capacitance violation signal line, in order to determine the root cause of the current load capacitance violation signal line being in a large load capacitance state, the basic characteristics of the load capacitance of the load capacitance violation signal line should be extracted. Thereafter, the load capacitance formation characteristics are determined based on the extracted basic characteristics of the load capacitance, so as to use the load capacitance formation characteristics to determine the main cause of the current load capacitance violation signal line being in a large load capacitance state. From the above description, it can be seen that determining the main cause of the formation of the load capacitance violation signal specifically refers to whether it is a large load capacitance state caused by a long line length or a large load capacitance state caused by a high fan-out.

[0085] In one embodiment of the present invention, the basic characteristics of the load capacitance of the load capacitance violation signal line are extracted, including the signal transition time under the ideal timing state. 、The line parasitic capacitance of the current load capacitance violation signal line , the gate input pin capacitance information of the fan-out unit corresponding to the current load capacitance violation signal line And the maximum output current of the output pin of the driver unit corresponding to the current load capacitance violation signal line ;

[0086] After extracting the basic characteristics of the load capacitance of the load capacitance violation signal line, the dynamic variable value of the current load capacitance violation signal line is calculated, and the load capacitance formation characteristics of the current load capacitance violation signal line are determined according to the calculated dynamic variable value, wherein,

[0087] The load capacitance formation feature includes a long wire length feature representing a main cause of wire length or a high fan-out feature representing a main cause of fan-out.

[0088] Specifically, the basic characteristics of the load capacitance may include at least the signal transition time under the ideal timing state. , Line parasitic capacitance , Gate input pin capacitance information and the maximum output current From the above description, we can see that when screening and determining the load capacitance violation signal line, the corresponding line parasitic capacitance can be extracted at the same time. , Gate input pin capacitance information and maximum output current , the specific extraction method and process can refer to the above description, the maximum output current This is the maximum output current corresponding to the output pin of the drive unit mentioned above. Signal transition time under ideal timing conditions , which can generally be set in the constraint file. Therefore, the signal transition time under the ideal timing state can be directly extracted through the standard design constraint file. .

[0089] Gate input pin capacitance information That is, the gate input pin capacitance value corresponding to the load capacitance violation signal line. As can be seen from the above description, it can be composed of one or more pin capacitors. The gate input pin capacitance information The pin capacitance included in the circuit can be referred to the above description and will not be repeated here.

[0090] The standard design constraint file is the .sdc file. The standard design constraint file is a standardized file used uniformly in the integrated circuit design industry to describe the timing, area and / or power consumption constraints of logic synthesis and physical layout and routing. Specifically, the signal transition time under the ideal timing state corresponding to each signal line can be directly obtained in the standard design constraint file. , specifically extract the signal transition time under the ideal timing state The method can be consistent with the existing technology.

[0091] In order to determine the load capacitance formation characteristics of the load capacitance violation signal line, the dynamic variable value of the load capacitance violation signal line should be calculated using the load capacitance basic characteristics. Thereafter, the load capacitance formation characteristics can be determined based on the calculated dynamic variable value. From the above description, it can be seen that the load capacitance formation characteristics include a long line length characteristic that characterizes the main cause of line length or a high fan-out characteristic that characterizes the main cause of fan-out. When the load capacitance formation characteristic is a long line length characteristic, it indicates a large load capacitance mainly caused by the long line length. When the load capacitance formation characteristic is a high fan-out characteristic, it indicates a large load capacitance mainly caused by the high fan-out.

[0092] In one embodiment of the present invention, when calculating the dynamic variable of the load capacitance violation signal line, the following is obtained:

[0093]

[0094] in, is the dynamic variable value, is the operating voltage of the target integrated circuit, is the average capacitance of the gate input pin corresponding to the current load capacitance violation signal line;

[0095] The calculated dynamic variable value is compared with the fan-out value of the current load capacitance violation signal line. When the fan-out value of the load capacitance violation signal line is greater than the calculated dynamic variable value, the generated load capacitance formation feature is determined as a high fan-out feature; otherwise, the generated load capacitance formation feature is determined as a long line length feature.

[0096] Specifically, after the basic characteristics of the load capacitance are extracted, the dynamic variable value can be calculated using the above method. The dynamic variable value is the dynamic variable value calculated using the above method. When calculating dynamic variables, the average gate input capacitance value corresponding to the current load capacitance violation signal line is , the pin capacitance corresponding to the load capacitance violation signal line can be calculated by arithmetic average, such as the gate input pin capacitance information mentioned above. Calculate the corresponding average gate input pin capacitance If there is only one fan-out unit, the corresponding gate input pin capacitance average value is This is the gate input pin capacitance information within the load capacitance violation signal line When there are multiple fan-out units, the corresponding gate input pin capacitance average value is calculated using the algorithm average method. .

[0097] It can be seen from the method of calculating the dynamic variable value in the above manner that the calculated dynamic variable value can represent the maximum fan-out value of the current load capacitance violation signal under the ideal timing state. Therefore, after the dynamic variable value is calculated, the dynamic variable value can be compared with the fan-out value of the load capacitance violation signal line. Here, the fan-out value of the load capacitance violation signal line refers to the actual fan-out value of the load capacitance violation signal line. The fan-out value of the load capacitance violation signal line can be extracted through existing technical means.

[0098] In specific implementation, when the fan-out value of the load capacitance violation signal line is greater than the calculated dynamic variable value, the generated load capacitance formation characteristic is determined as a high fan-out characteristic; otherwise, the generated load capacitance formation characteristic is determined as a long line length characteristic, thereby realizing the determination of the load capacitance formation characteristic of the load capacitance violation signal line.

[0099] From the above description, it can be seen that if the load capacitance violation signal line has only one fan-out unit, then the above corresponding gate input pin capacitance average value is This is the gate input pin capacitance information within the load capacitance violation signal line , the calculated dynamic variable value k is 1. At this time, the calculated dynamic variable value is equal to the fan-out value of the load capacitance violation signal, that is, the fan-out value of the load capacitance violation signal line is not greater than the dynamic variable value, and the generated load capacitance formation feature should be a long line length feature.

[0100] In order to improve the efficiency and reliability of load capacitance optimization, after determining the load capacitance formation characteristics of the load capacitance violation signal line, a buffer insertion state corresponding to the load capacitance formation characteristics should be selected. Thereafter, buffer insertion processing is performed on the current load capacitance violation signal line based on the selected buffer insertion state, so as to reduce the load capacitance of the current load capacitance violation signal line after the buffer insertion processing. It can be seen that when optimizing the load capacitance, the present invention does not simply perform buffer insertion. When the performed buffer insertion processing corresponds to the load capacitance formation characteristics, the load capacitance of the current load capacitance violation signal line can be quickly and effectively reduced.

[0101] It should be understood that the signal line type in the target integrated circuit can be a digital signal line or an analog signal line. Since the analog signal line is destroyed into a digital signal after being inserted into the buffer, the signal line with optimized load capacitance in the present invention belongs to a digital signal line, that is, the load capacitance violation signal line is a digital signal line. At this time, the line length and fan-out value of the signal line can be reduced by inserting a buffer, thereby reducing the corresponding load capacitance.

[0102] It is understandable that when a small number of buffers are inserted into the load capacitance violation signal line, the signal transition time and line delay can be reduced, which is beneficial to timing; when excessive buffers are inserted, the path delay will be increased due to the delay of the buffer itself, which is not conducive to timing, and excessive buffers require a large amount of layout and wiring resources, which may not be able to be wound through during winding. Therefore, the difficulty of inserting buffers lies in using the least number to achieve the best effect; in order to achieve a better buffer insertion effect, it is necessary to make an estimate of the parasitic capacitance of the line after rewinding when inserting the buffer, and this process requires a lot of computing power and time, and after actual wiring, the estimated result may not be accurate. Therefore, buffer insertion using estimation and other methods is difficult to achieve the expected effect.

[0103] In order to achieve a better buffer insertion effect, the present invention adopts a binary search method to insert the required buffer into the load capacitance violation signal line. Specifically, the advantage of using the binary search method is that its divide-and-conquer nature has exponential optimization efficiency and can be quickly and dynamically adjusted based on feedback, thereby significantly improving the effect of reducing the large load capacitance of the load capacitance violation signal line after the buffer insertion process.

[0104] In one embodiment of the present invention, when the load capacitance formation characteristic is determined to be a long line length characteristic, the buffer insertion state is configured as a reduced line length buffer insertion, wherein:

[0105] When the buffer insertion state is configured as line length reduction buffer insertion and the buffer insertion process is performed using a binary method, the inserted buffer should reduce the line length corresponding to the current load capacitance violation signal line by half.

[0106] Specifically, when the load capacitance formation characteristic is a long line length characteristic, as can be seen from the above description, the line length of the load capacitance violation signal line should be interrupted. In this case, the buffer insertion state should be line length reduction buffer insertion. Here, line length reduction buffer insertion specifically means that after the buffer is inserted, the line length of the load capacitance violation signal line is interrupted, that is, the line length of the load capacitance violation signal line is reduced. When the buffer insertion process is performed using the binary method, the inserted buffer should reduce the line length corresponding to the current load capacitance violation signal line by half.

[0107] Figure 2 An embodiment of reducing the load capacitance of a load capacitance violation signal line is shown in FIG. Figure 2 In the figure, STD1 and STD2 are two standard cells, the signal line connecting the standard cell STD1 and the standard cell STD2 is a load capacitance violation signal line, and the corresponding load capacitance formation feature is a long line length feature, that is, Figure 2 The signal line with medium load capacitance violation is mainly in a large load capacitance due to the long line length. At this time, a buffer should be inserted when performing the buffer insertion process by binary division. Figure 2 BUF1 in the middle is a buffer inserted when the buffer insertion process is performed using the binary method. At this time, the length of the signal line directly connecting the standard cell STD1 and the standard cell STD2 can be halved, that is, the buffer BUF1 is placed at the 1 / 2 position of the corresponding signal line.

[0108] In one embodiment of the present invention, when the load capacitance formation characteristic is determined to be a high fan-out characteristic, the buffer insertion state is configured as a reduced fan-out buffer insertion, wherein:

[0109] When the buffer insertion state is configured as fan-down buffer insertion and the buffer insertion process is performed using a binary method, the inserted buffer should reduce the fan-out value corresponding to the current load capacitance violation signal line by half.

[0110] Specifically, when the load capacitance formation characteristic is a high fan-out characteristic, as can be seen from the above description, the fan-out of the load capacitance violation signal line should be reduced first. In this case, the buffer insertion state should be fan-out reduction buffer insertion. Here, fan-out reduction buffer insertion specifically means that the fan-out of the load capacitance violation signal line can be reduced after the buffer is inserted. When the buffer insertion process is performed using the binary method, the inserted buffer should reduce the fan-out corresponding to the current load capacitance violation signal line by half.

[0111] Figure 3 An embodiment of reducing the load capacitance of a load capacitance violation signal line is shown in FIG. Figure 3 Among them, STD3 is the driver unit, STD4~STD11 are 8 fan-out units, Figure 3 Buffers BUF3 to BUF7 are buffers inserted when performing fan-down buffer insertion, wherein Iteration1 is an embodiment of performing a first optimization process on the target integrated circuit to perform fan-down buffer insertion, wherein the inserted buffers BUF3, BUF4 and buffers BUF5, BUF6 can reduce the fan-out value of the load capacitance violation signal line in the initial state by half.

[0112] From the above description, it can be seen that through the above-mentioned dynamic variable control, the load capacitance formation characteristics of the load capacitance violation signal line can be determined. After determining the load capacitance formation characteristics of the load capacitance violation signal line, the binary method can be used to determine the position and number of the corresponding buffers, so that the buffers can be accurately placed on the signal line, thereby improving the efficiency and reliability of load capacitance optimization of the target integrated circuit, thereby effectively solving the global load distribution in the mixed scenario of high fan-out network and long line.

[0113] It should be noted that, through the dynamic variable control set above, it is possible to flexibly switch between interrupting long lines and reducing fan-out, and it can be applied to different process sizes. For example, under advanced process nodes, the magnitude of the line parasitic capacitance far exceeds the gate input pin capacitance. Through dynamic variable control, it can be determined that the load capacitance formation characteristic is a long line length characteristic. In this case, it is preferred to interrupt the long signal line; under traditional process nodes, the load capacitance mainly comes from the input pin capacitance of the driven gate. Through dynamic variable control, it can be determined that the load capacitance formation characteristic is a high fan-out characteristic. In this case, it is preferred to reduce the fan-out value.

[0114] It should be noted that during each load capacitance optimization, the line length reduction buffer insertion or fan-out reduction buffer insertion is performed only once for each load capacitance violation signal line. After the load capacitance reduction process is performed on all load capacitance violation signal lines, the load capacitance optimization process for the target integrated circuit is completed. It is understandable that after performing a load capacitance optimization process, load capacitance violation signal lines may still exist. Therefore, it is necessary to evaluate the target integrated circuit after performing a load capacitance optimization process. The purpose of this evaluation is mainly to determine whether load capacitance violation signal lines still exist in the target integrated circuit.

[0115] In specific implementations, when evaluating a target integrated circuit, the aforementioned screening method for identifying load capacitance violation signal lines can be employed. Specifically, parasitic parameter extraction and other processing are required for the target integrated circuit after load capacitance optimization processing has been performed. For details, reference can be made to the above description, so as to determine whether load capacitance violation signal lines exist. It should be understood that if the evaluation determines that load capacitance violation signal lines still exist, load capacitance optimization processing should be performed again. The load capacitance optimization processing performed can be consistent with the aforementioned method, and reference can be made to the above description for details.

[0116] As can be seen from the above description, when optimizing the load capacitance of a target integrated circuit, the process of load capacitance optimization processing-evaluation-load capacitance optimization processing-evaluation is generally repeated. When the evaluation determines that there are no load capacitance violation signal lines, the load capacitance optimization of the target integrated circuit is considered to be completed, that is, the purpose / goal of the final load capacitance optimization is achieved.

[0117] Figure 2 In one embodiment, the corresponding load capacitance violation signal line undergoes two load capacitance reduction processes, that is, the corresponding load capacitance violation signal line undergoes two load capacitance optimization processes. Figure 2 In the figure, Iteration1 is the buffer insertion process performed during the first load capacitance optimization process, and Iteration2 is the buffer insertion process performed during the second load capacitance optimization process. It can be understood that during the second load capacitance optimization, the signal line between the buffer BUF1 and the standard unit STD2 is a load capacitance violation signal line, and the corresponding load capacitance formation feature is a long line length feature. The position where the buffer BUF2 is inserted is the 1 / 2 position of the corresponding signal line connecting the buffer BUF1 and the standard unit STD2.

[0118] Figure 3 In the embodiment, the corresponding load capacitance violation signal line is subjected to two load capacitance reduction processes, that is, the corresponding load capacitance violation signal line undergoes two load capacitance optimization processes. Figure 3 In the figure, Iteration 1 represents the buffer insertion process performed during the first load capacitance optimization, and Iteration 2 represents the buffer insertion process performed during the second load capacitance optimization. The inserted buffer BUF7 is placed halfway between the violating signal lines during the second optimization, halving the length of the violating signal lines. As can be seen from the figure, the first load capacitance is characterized by high fan-out, while the second load capacitance is characterized by long line length.

[0119] Figure 3 In the embodiment shown in , when buffers BUF3 to BUF7 are not inserted, the fan-out value corresponding to the corresponding load capacitance violation signal line should be 8. After the first buffer insertion process, the corresponding fan-out value becomes 4; after buffer BUF7 is inserted, the corresponding fan-out value becomes 3.

[0120] When more load capacitance optimization processes are required, the specific buffer insertion methods and processes can be referred to Figure 2 、 Figure 3 As well as the corresponding explanations above, no further examples will be given here.

[0121] In one embodiment of the present invention, when performing load capacitance reduction processing on each load capacitance violation signal line, it also includes routing optimization processing on the current load capacitance violation signal line, wherein:

[0122] After performing buffer insertion processing on the load capacitance violation signal line, a signal line to be optimized is generated, and then a routing optimization processing is performed on the signal line to be optimized, wherein:

[0123] When performing routing optimization, it includes:

[0124] Configuring routing optimization rules, wherein the configured routing rules at least include prohibiting top metal routing, signal line width, and / or signal line spacing;

[0125] Based on the configured routing optimization rules, the signal line to be optimized for routing is routed. When the routing of the signal line to be optimized for routing fails, the above-mentioned signal line spacing is adjusted until the routing of the signal line to be optimized reaches a successful state.

[0126] From the above description, it can be seen that for each load capacitance violation signal line, after the above load capacitance reduction process, the load capacitance corresponding to the load capacitance violation signal line can be reduced. In order to further reduce the corresponding load capacitance state, routing optimization processing can also be performed, wherein the routing optimization processing should be performed on all signal lines formed after the buffer insertion processing of the load capacitance as an example signal line, as mentioned above. Figure 2 In the example, after the first load capacitance optimization process, the load capacitance violation signal line is changed from one signal line to two signal lines, and the two signal lines are separated by the buffer BUF1. At this time, the objects of routing optimization process are the two signal lines separated by the buffer BUF1, which also form the signal lines to be optimized. For other situations, please refer to the description here.

[0127] It can be seen from the above description that when a load capacitance reduction process is performed on each load capacitance violation signal line, it at least includes a buffer insertion process and a routing optimization process performed in sequence. When performing routing optimization, routing optimization rules should be configured. Specifically, the configured routing rules at least include prohibiting top-layer metal routing, signal line width and / or signal line spacing. Among them, prohibiting top-layer metal routing specifically means that when performing routing optimization, the corresponding signal line should be prohibited from being wired from the top-layer metal, so as to significantly reduce the sidewall capacitance; signal line width specifically refers to the width of the signal line, such as the signal line width can be set to a single minimum line width; signal line spacing specifically refers to the distance between the signal line and other signal lines. When designing an integrated circuit, the minimum line width and the minimum spacing should generally be determined in advance. Therefore, the signal line width and signal line spacing within the routing optimization rules can be configured as needed.

[0128] In specific implementation, when configuring routing optimization rules, first increase the signal line spacing of the signal lines to be optimized. For example, the signal line spacing can be set to a multiple of the minimum line spacing, such as 2 times the minimum line spacing. It should be noted that the top metal thickness is large and the resistance is small, but the parasitic capacitance is large. After the buffer is inserted, the signal line length can be considered short, and the line delay is dominated by the parasitic capacitance. In this case, by avoiding top metal routing and increasing the line spacing, the parasitic capacitance can be optimized, thereby reducing line delay and signal interference.

[0129] Figure 4 The figure shows an embodiment of the existing signal line routing. Figure 4 and Figure 5 An embodiment with 4 winding layers is shown in FIG. Figure 4 and Figure 5 In the figure, M4 is the top winding layer, and M3~M1 are the winding layers below the top winding layer. Figure 4 and Figure 5 In the diagram, VIA1~VIA3 are the holes between the winding layers. Figure 4 An embodiment of setting signal routing on the top winding layer is shown in FIG. Figure 5 FIG2 shows an embodiment in which a signal routing is not provided on the top winding layer. As can be seen from the above description, Figure 5 The routing optimization processing in can reduce line delay and minimize signal interference. Figure 6 Shown in Figure 5 An embodiment of the parasitic capacitance corresponding to the wiring.

[0130] It should be noted that after configuring the routing optimization rules, you can perform routing in the load capacitance optimization tool, wherein the routing specifically refers to configuring the signal line according to the routing optimization rules to form at least Figure 5 In a similar connection state, after starting the routing, the routing results can be captured in the load capacitance optimization tool. If the routing results contain the words "failure" or "error", the routing fails. It can be seen that after configuring the routing optimization rules, the routing can be started and the routing results can be captured directly in the load capacitance optimization tool.

[0131] In one embodiment of the present invention, when the winding of the signal line to be optimized for routing fails, the signal line spacing corresponding to the signal line to be optimized for routing is gradually reduced until the winding of the signal line to be optimized for routing reaches a successful winding state. As can be seen from the above description, when configuring the routing optimization rules, the signal line spacing is set to multiple times the minimum line spacing. At this time, the signal line spacing is gradually reduced. For example, when the signal line spacing configured by the routing optimization rules is 3 times the minimum line spacing, after the winding fails, the signal line spacing can be reduced to 2 times the minimum line spacing or single minimum line spacing, and then the winding is started again, and the winding results are captured until the winding success state is reached. This can further reduce the load capacitance and line delay, and reduce signal interference.

[0132] It should be understood that when performing routing optimization, other signal lines of the target integrated circuit should not be affected. For example, the modified_nets_only mode of the route_eco command can be used to avoid generating new signal line violations.

[0133] From the above description, a load capacitance optimization system based on dichotomy and dynamic variable control can be obtained. In one embodiment of the present invention, it includes a load capacitance optimization device, wherein for any target integrated circuit to be load capacitance optimized, the load capacitance optimization device uses the above-mentioned load capacitance optimization method to optimize it.

[0134] Specifically, the load capacitance optimization device can be a computer terminal that can meet the needs of integrated circuit design or load capacitance optimization tools. The type of load capacitance optimization device can be selected according to needs, and it shall be based on whether it can execute the above-mentioned load capacitance optimization method for the target integrated circuit. The specific implementation of the load capacitance optimization method can refer to the above description, which will not be repeated here.

Claims

1. A load capacitance optimization method based on dichotomy and dynamic variable control, characterized in that: The load capacitance optimization method comprises: A target integrated circuit for which load capacitance optimization is to be performed is provided, and a load capacitance optimization process is performed on the target integrated circuit, wherein the load capacitance optimization process is performed, including: Screening and determining all load capacitance violation signal lines in the target integrated circuit that are in a large load capacitance state, and performing load capacitance reduction processing on each load capacitance violation signal line, wherein: When performing load capacitance reduction processing on each load capacitance violation signal line, it includes: extracting a basic load capacitance characteristic of the load capacitance violation signal line, and determining a load capacitance formation characteristic of the load capacitance violation signal line based on the extracted basic load capacitance characteristic, so as to determine a main cause of the current large load capacitance state of the load capacitance violation signal line by using the load capacitance formation characteristic; Extract the load capacitance of the signal line with load capacitance violation. The basic characteristics of the load capacitance include the signal transition time under the ideal timing state. 、The line parasitic capacitance of the current load capacitance violation signal line , the gate input pin capacitance information of the fan-out unit corresponding to the current load capacitance violation signal line And the maximum output current of the output pin of the driver unit corresponding to the current load capacitance violation signal line ; selecting, based on a load capacitance formation characteristic of a current load capacitance violating signal line, a buffer insertion state corresponding to the load capacitance formation characteristic, and performing a buffer insertion process on the current load capacitance violating signal line based on the selected buffer insertion state, so as to reduce the load capacitance of the current load capacitance violating signal line after the buffer insertion process, wherein, when performing the buffer insertion process, at least a binary method is employed to insert a required buffer into the load capacitance violating signal line; The target integrated circuit after the load capacitance optimization process is evaluated. When the evaluation confirms that there are still load capacitance violation signal lines in a large load capacitance state, the above-mentioned load capacitance optimization process is repeated until the evaluation confirms that there are no load capacitance violation signal lines in a large load capacitance state.

2. The load capacitance optimization method based on dichotomy and dynamic variable control according to claim 1 is characterized in that: After extracting the basic characteristics of the load capacitance of the load capacitance violation signal line, the dynamic variable value of the current load capacitance violation signal line is calculated, and the load capacitance formation characteristics of the current load capacitance violation signal line are determined according to the calculated dynamic variable, wherein, The load capacitance formation feature includes a long wire length feature representing a main cause of wire length or a high fan-out feature representing a main cause of fan-out.

3. The load capacitance optimization method based on dichotomy and dynamic variable control according to claim 2, wherein: When calculating the dynamic variables of the load capacitance violation signal line, we have: in, is a dynamic variable, is the operating voltage of the target integrated circuit, is the average capacitance of the gate input pin corresponding to the current load capacitance violation signal line; The calculated dynamic variable value is compared with the fan-out value of the current load capacitance violation signal line. When the fan-out value of the load capacitance violation signal line is greater than the calculated dynamic variable, the generated load capacitance formation feature is determined as a high fan-out feature; otherwise, the generated load capacitance formation feature is determined as a long line length feature.

4. The load capacitance optimization method based on dichotomy and dynamic variable control according to claim 3 is characterized in that: When the load capacitance formation characteristic is determined to be a high fan-out characteristic, the buffer insertion state is configured as a reduced fan-out buffer insertion, wherein, When the buffer insertion state is configured as fan-down buffer insertion and the buffer insertion process is performed using a binary method, the inserted buffer should reduce the fan-out value corresponding to the current load capacitance violation signal line by half.

5. The load capacitance optimization method based on dichotomy and dynamic variable control according to claim 3 is characterized in that: When the load capacitance forming characteristic is determined to be a long line length characteristic, the buffer insertion state is configured as a reduced line length buffer insertion, wherein, When the buffer insertion state is configured as line length reduction buffer insertion and the buffer insertion process is performed using a binary method, the inserted buffer should reduce the line length corresponding to the current load capacitance violation signal line by half.

6. The load capacitance optimization method based on dichotomy and dynamic variable control according to any one of claims 1 to 5, characterized in that: When performing load capacitance reduction processing on each load capacitance violation signal line, it also includes routing optimization processing of the current load capacitance violation signal line, wherein, After performing buffer insertion processing on the load capacitance violation signal line, a signal line to be optimized is generated, and then a routing optimization processing is performed on the signal line to be optimized, wherein: When performing routing optimization, it includes: Configuring routing optimization rules, wherein the configured routing rules at least include prohibiting top metal routing, signal line width, and / or signal line spacing; Based on the configured routing optimization rules, the signal line to be optimized for routing is routed. When the routing of the signal line to be optimized for routing fails, the above-mentioned signal line spacing is adjusted until the routing of the signal line to be optimized reaches a successful state.

7. The load capacitance optimization method based on dichotomy and dynamic variable control according to claim 6, wherein: When configuring routing optimization rules, first increase the signal line spacing of the signal lines to be optimized, where: When the routing of the signal line to be optimized fails, the signal line spacing corresponding to the signal line to be optimized is gradually reduced until the routing of the signal line to be optimized reaches a successful state.

8. The load capacitance optimization method based on dichotomy and dynamic variable control according to any one of claims 1 to 5, characterized in that: The target integrated circuit is at least in an automatic placement and routing completion state; Screening for load capacitance violation signal lines with large load capacitance within the target integrated circuit includes: Obtaining the line parasitic capacitance and the corresponding gate input pin capacitance corresponding to each signal line in the target integrated circuit, and adding the line parasitic capacitance and the gate input pin capacitance of each signal line to generate the load capacitance of the current signal line; The load capacitance of each signal line is compared with a load capacitance threshold. When the load capacitance of the signal line is greater than the load capacitance threshold, the current signal line is in a large load capacitance state, and the current signal line is regarded as a load capacitance violation signal line.

9. The load capacitance optimization method based on dichotomy and dynamic variable control according to claim 8, wherein: When obtaining the parasitic capacitance of each signal line, include: Extracting parasitic parameters of the target integrated circuit to obtain a standard parasitic parameter exchange format file that characterizes the parasitic parameter state of the target integrated circuit; Determine the line parasitic capacitance corresponding to each signal line based on the standard parasitic parameter exchange format file; When obtaining the gate input pin capacitance of each signal line, include: Query the timing library file of the target integrated circuit to obtain the gate input pin capacitance of the current signal line.

10. A load capacitance optimization system based on dichotomy and dynamic variable control, characterized in that: The invention comprises a load capacitance optimization device, wherein for any target integrated circuit to be load capacitance optimized, the load capacitance optimization device optimizes the target integrated circuit by using the load capacitance optimization method of any one of claims 1 to 9.

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