Method, system, article of manufacture and apparatus for updating trim value of device

Abstract

The invention relates to a method, a system, an article of manufacture and an apparatus for updating a trim value for a device. An example apparatus (100) includes instructions and programmable circuitry configurable to instantiate and / or execute the instructions to authenticate a request to update a first trim value (406) to a second trim value (408), where the first trim value (406) is stored in a memory (110). The example apparatus (100) also includes instructions to store the second trim value (406) to the memory (110) while the first trim value (406) remains stored in the memory (110) in response to authentication of the request.

Description

Technical Field

[0001] The present description relates generally to electrical components and, more particularly, to methods, systems, articles of manufacture, and apparatus for updating trim values of a device. Background Art

[0002] Electronic devices may be deployed in various environments to facilitate system operations related to radio frequency (RF) power transmission, RF reception, oscillator frequency control, and the like. Summary of the Invention

[0003] An example device includes instructions and programmable circuitry configured to instantiate and / or execute the instructions to authenticate a request to update a first trimming value to a second trimming value stored in a memory. The example device also includes instructions to, in response to authenticating the request, store the second trimming value in the memory while the first trimming value remains stored in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example apparatus including a peripheral device that uses a trim value, wherein a data structure integrator operates to update the trim value of the apparatus.

[0005] Figure 2 yes Figure 1 A block diagram of an example implementation of a data structure integrator.

[0006] Figure 3 It means by Figure 1 A block diagram of an example trimmed data structure authentication performed by a data structure integrator.

[0007] Figure 4 yes Figure 1 A block diagram of the nonvolatile memory structure with additional details.

[0008] Figure 5A and 5B is representative of an exemplary programmable circuit system that can be run, instantiated, and / or executed to implement Figure 1 The data structures of the integrator circuitry 106 may include example machine-readable instructions and / or a flow chart of example operations.

[0009] Figure 6 is structured to run, instantiate, and / or execute Figure 5A and 5B Example machine readable instructions and / or perform example operations to implement Figure 1 106 is a block diagram of an example processing platform for programmable circuitry.

[0010] The use of the same reference numbers or other reference designators in the drawings indicates the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0011] The figures are not necessarily drawn to scale. Generally, like reference numerals in the figures and throughout this specification refer to like or similar parts. Although the figures illustrate regions with distinct lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, the boundaries and / or lines may be unobservable, intermingled, and / or irregular.

[0012] Devices produced by a manufacturer and deployed into an operating environment (e.g., sometimes referred to as "the field") are expected to operate consistently and reliably. In some examples, devices are laboratory tested at or near the end of the manufacturing and / or assembly process to set operating parameters, referred to herein as "trim values." Depending on the type of device, the corresponding trim values exhibit different effects on the device. For example, a radio frequency (RF) transmitter in a power amplifier device may have a first trim value (e.g., a transmit trim value) that sets a specific RF power level during operation, and an RF receiver in the power amplifier device may have a second trim value (e.g., a receiver trim value) that sets a specific receive sensitivity during operation. In some examples, a resistor / capacitor (RC) oscillator device exhibits a specific operating frequency based on the trim values, but examples include any other type of device having one or more trim values to assist in operating characteristics.

[0013] End users and / or original equipment manufacturers (OEMs) of devices may expect specific trim values to be operational in a particular operating environment upon receipt and deployment. Consequently, OEMs design circuits, system-on-chip (SoC) components, and / or systems to perform consistently with end-use application specifications that rely on static trim values established by the manufacturer. However, in some instances, OEM applications may change, potentially requiring the acquisition (e.g., purchase) of replacement devices that operate in accordance with the changed environment or the design of costly workarounds for the end-use application. In some instances, OEM applications change based on environmental changes (e.g., temperature changes, proximity placement changes, etc.) that have occurred since the device was initially installed in the operating environment. To illustrate, if a power amplifier is in a first position at a first time, the transmitter power level established by the first trim value may be appropriate for the end-user application. However, if the power amplifier is relocated to a second position at a second time, the transmitter power level may be too high or too low, thereby resulting in transmission errors and / or transmission performance that no longer meets quality of service (QoS) expectations. To remedy the changed environment of a field device (eg, a power amplifier), it may be necessary to request a new power amplifier from the manufacturer with alternative trim values appropriate for the new (eg, second) location.

[0014] The subject matter of device trimming is discussed in U.S. Patent Application Publication No. 2023 / 0138906 Al, filed on December 30, 2021, and U.S. Application No. 18 / 345,449, filed on June 30, 2023. The entire contents of U.S. Patent Application Publication No. 2023 / 0138906 Al and U.S. Application No. 18 / 345,449 are incorporated herein by reference.

[0015] Known devices do not include mechanisms and / or techniques for trimming and updating the device after it is powered on in the field. For example, after the device is manufactured, one or more test programs store trim values in the device's memory (e.g., flash memory). During the device's startup process (e.g., a cold boot) or after a device reset condition, the memory is locked, making the trim data unreadable, modifiable, and / or erasable by applications. Furthermore, the locations corresponding to the registers in which the trim values are set are not disclosed to the device's end user, OEM, and / or reference manual. Consequently, after the device is installed in the field, the OEM remains unaware of any trim changes to the device.

[0016] Examples described herein enable over-the-air (OTA) updates of trim values (e.g., firmware over-the-air (FOTA) updates) by OEMs while a device is operational and / or otherwise installed in the field. Examples described herein enable OEMs to perform trim updates (e.g., updates to trim values and / or updates to trim data structures containing trim values for one or more peripheral devices) in a manner that is secure through authentication and achieves reliability by testing the updated trim values before the device is used. As further described herein, the performance, functionality, and / or efficiency of a peripheral device can be improved after updating the trim values associated with the peripheral device. After updating the trim values in a device, the device can better adapt to the environment, situation, or network parameters.

[0017] Figure 1 is a block diagram of an example apparatus 100 including one or more peripheral devices that utilize trimmed values. Figure 1 In the illustrated example, device 100 includes processor circuitry 102, read only memory (ROM) 104 storing boot code, and data structure integrator circuitry 106 to facilitate updating trim values of device 100 and / or its peripherals, as described in further detail below. Figure 1 The illustrated example also includes radio circuitry 108, non-volatile memory 110 (e.g., flash memory) having a primary portion 110A and a non-primary portion 110B, random access memory (RAM) 112 (e.g., static RAM (SRAM)), and accelerator circuitry 114. In some examples, accelerator circuitry 114 includes an Advanced Encryption Standard (AES) accelerator to perform encryption and / or decryption operations. In some examples, accelerator circuitry 114 includes a Secure Hash Algorithm (SHA) accelerator for performing hash operations. In some examples, accelerator circuitry 114 includes true random number generator (TRNG) circuitry. Figure 1 The illustrated example of also includes one or more peripherals 116, such as an example power management unit (PMU) 118, an example oscillator 120, and an example analog-to-digital converter (ADC) 122. Figure 1The illustrated example includes three peripherals, but the examples disclosed herein are not limited thereto. Any number of peripherals may include, but are not limited to, power amplifiers, low noise amplifiers, DC to DC (DCDC) converters, oscillators, ADCs, Internet of Things (IoT) devices, digital to analog (DAC) converters, operational amplifiers (OpAmp), etc. Each example peripheral 116 includes corresponding registers that store trim values that direct and / or otherwise indicate the operation of the peripheral 116. The example PMU 118 includes a PMU register 118A, the example oscillator 120 includes an oscillator register 120A, and the example ADC 122 includes an ADC register 122A. Although Figure 1 The illustrated example includes three example peripheral devices, but the examples described herein are not limited thereto. For example, Figure 1 The illustrated example apparatus 100 may be a system on a chip (SoC) or platform having any number of peripheral devices thereon.

[0018] In operation, Figure 1 An example device 100 can be deployed in an environment to perform one or more objectives utilizing peripherals 116. In some instances, the device 100 can be located in a first location having a first environmental characteristic, such as a first temperature or a first distance from one or more other devices. In some instances, the device 100 can be stationary, but the first environmental characteristic changes in a manner that causes a degradation in performance of one or more objectives that the device is designed to meet. For example, the second environmental characteristic can include a second temperature greater than the first temperature that causes a degradation in performance of the device due to a temperature extreme exceeding one or more thresholds for the device and / or its components. In some instances, if Figure 1 If the device 100 is located at a second distance away from the participating devices communicating via the example radio circuit system 108 at the second time, the relatively larger distance may result in a larger number of communication errors (e.g., the second location at the second distance may be in a noisy environment).

[0019] To mitigate the negative effects caused by changing conditions of the example device 100, the examples described herein employ the data structure integrator circuitry 106 to facilitate the ability to set alternative trim values on the device while the device is in the field. For example, in response to elevated temperature characteristics, the data structure integrator circuitry 106 enables the trim values of the example PMU 118 to be reduced in an effort to avoid a thermal runaway condition. In some examples, in response to increased communication errors, the example data structure integrator circuitry 106 enables the frequency setting of the example oscillator 120 to be reduced to reduce the communication bit rate.

[0020] Figure 2 It is used to update the trim value Figure 1A block diagram of an example implementation of the data structure integrator circuit system 106 is shown. Figure 2 The data structure integrator circuitry 106 may be instantiated (e.g., created as an instance, generated for any length of time, realized, implemented, etc.) by programmable circuitry, such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, Figure 2 The data structure integrator circuitry 106 may be instantiated (e.g., instantiated, generated for any length of time, realized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) structured and / or configured to perform operations corresponding to the first instruction in response to executing the second instruction. In some examples, the CPU 102 may be configurable to perform some or all of the functionality attributed to the data structure integrator circuitry 106 in the present disclosure. Thus, Figure 2 Some or all of the circuitry may be instantiated at the same or different times. Figure 2 Some or all of the circuitry of may be instantiated, for example, in one or more threads that execute concurrently on hardware and / or serially on hardware. Furthermore, in some instances, Figure 2 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0021] Figure 2 is a block diagram of an example data structure integrator circuitry 106. Figure 2 In the illustrated example, data structure integrator circuitry 106 includes example update detection circuitry 202, example memory management circuitry 204, example authentication circuitry 206, and example trim value verification circuitry 208. In some examples, update detection circuitry 202 is instantiated by programmable circuitry that executes update detection instructions and / or is configured to perform, for example, a process represented as Figure 5A and 5B In some examples, memory management circuitry 204 is instantiated by programmable circuitry that executes memory management instructions and / or is configured to perform operations such as those of the flowchart of FIG. Figure 5A and 5B In some examples, the authentication circuit system 206 is instantiated by a programmable circuit system that executes authentication instructions and / or is configured to perform, for example, the operations represented by Figure 5A and 5BIn some examples, the trim value verification circuitry 208 is instantiated by a programmable circuitry that executes trim value verification instructions and / or is configured to perform operations such as those represented by the flowchart of Figure 5A and 5B Those operations of the flowchart and other operations.

[0022] In some examples, data structure integrator circuitry 106 includes means for detecting updates, means for managing memory, means for authentication, and means for verifying trimmed values. For example, means for detecting updates may be implemented by update detection circuitry 202, means for managing memory may be implemented by memory management circuitry 204, means for authentication may be implemented by authentication circuitry 206, and means for verifying trimmed values may be implemented by trimmed value verification circuitry 208. In some examples, update detection circuitry 202, memory management circuitry 204, authentication circuitry 206, and trimmed value verification circuitry 208 may be implemented by, for example, Figure 6 The foregoing circuitry may be instantiated by a programmable circuitry such as the example programmable circuitry 612 of FIG. Additionally or alternatively, the foregoing circuitry may be instantiated by any other combination of hardware, software, and / or firmware. For example, the foregoing circuitry may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) that are configured and / or structured to execute some or all machine-readable instructions and / or to perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0023] In operation, Figure 2 The example update detection circuitry 202 monitors for the occurrence of a request to update a trim value of the device 100. In some examples, the update detection circuitry 202 is communicatively connected to the example radio circuitry 108 and parses incoming information associated with the trim update request. In some examples, the trim update request is received by the radio circuitry 108 (e.g., Bluetooth Low Energy (BLE)) as a data packet having header information, wherein one or more tags indicate a trim value change request. Thus, the example update detection circuitry 202 parses the packet header for a particular tag associated with the trim update request.

[0024] When the update detection circuitry 202 detects a trim update request and / or a request to update a trim value (e.g., to update and / or otherwise overwrite a first trim value to a second trim value, overwrite a second trim value with a third trim value, etc.), the example memory management circuitry 204 may store the new trim value and / or a new trim data structure in the example RAM 112. However, the received trim value and / or new trim data structure is not yet stored in the non-volatile memory 110 and / or is not otherwise permitted to change (e.g., overwrite) any current trim values because the newly received trim data structure has not yet been reviewed (e.g., authenticated and / or tested to contain secure and / or otherwise functional trim values). The examples described herein will involve receiving a trim data structure containing any number of trim values for a corresponding peripheral device, but examples are not limited thereto. The example authentication circuitry 206 may be configurable to perform one or more security checks on the received trim data structure (e.g., or on the trim values received individually). As described in further detail below, the security check may include, but is not limited to, decrypting the digital signature of the data structure to generate a decrypted signature value that is compared to the hash digest. If the authentication circuitry 206 performs the comparison and determines a mismatch, the data structure is rejected from further use and / or consideration by the authentication circuitry 206. However, if the authentication circuitry 206 performs the comparison and determines a match, the example memory management circuitry 204 stores the trimmed data structure in the non-volatile memory 110. As described in further detail below, the memory management circuitry 204 may store the authenticated trimmed data structure in the non-primary portion 110B (sometimes referred to herein as an auxiliary memory sector), while the primary portion 110A (sometimes referred to herein as a primary memory sector) is generally reserved for user applications.

[0025] Although the newly received trim data structure may be successfully authenticated by the example authentication circuitry 206, the example trim value verification circuitry 208 may be configurable to determine whether one or more of the trim values within the newly received trim data structure are safe and / or otherwise suitable for use by one or more peripheral devices 116. In some examples, one or more of the newly received trim values are tested with one or more of the corresponding peripheral devices 116. For example, if the peripheral device is a power amplifier (PA) or a low noise amplifier (LNA), the trim value verification circuitry 208 may instantiate one or more RF loopback tests. The results of the RF loopback tests may then be compared to one or more thresholds. In some examples, if the peripheral device is an ADC with new trim values corresponding to the ADC resolution, the example trim value verification circuitry 208 may perform an ADC conversion (e.g., as part of a linearity test) using the new trim values to confirm whether the ADC's output value is updated and / or otherwise corrected. In some examples, if the peripheral device is a clock module (CKM), the trim value verification circuitry 208 tests the new trim values to verify that they will adjust the clock frequency by, for example, using a time-to-digital converter (TDC) (e.g., an on-chip TDC with an SoC). In other words, the example trim value verification circuitry 208 performs any number of tests using newly received trim values to verify that such values are tested to meet one or more target metrics and that such values do not corrupt and / or otherwise disrupt the correct operation of one or more peripheral devices to be reconfigured with the new trim values, which overwrite existing trim values that may be in one or more registers.

[0026] If the example trim value validation circuitry 208 determines that the trim value test failed, the received trim data structure (or trim value) is denied further consideration and / or use by the device 100 and / or the peripherals 116 of the device 100. In other words, the use of a trim value and / or trim data structure that does not satisfy one or more trim value tests is prohibited. Rather than using the newly received trim data structure and / or the trim value therein, the failed test causes the previous trim value to remain in effect for the device 100 (e.g., disabling device use of the second trim value and enabling device use of the first (e.g., original or previous) trim value). In some examples, the failed test is reported back to the OEM. However, if the example trim value validation circuitry 208 determines that the trim value test succeeded, the example data structure integrator circuitry 202 may be configurable to authorize use of the trim value and cause the device 100 to reboot and use the newly received trim value stored in non-volatile memory. In other words, a tested trim value that satisfies one or more target metrics (e.g., operating thresholds of one or more peripheral devices) causes the tested trim value (e.g., the newly received trim value) to be authorized for future use, while the previous trim value is deactivated and / or otherwise prohibited from use by the peripheral device. While the new trim value is now stored in memory and implemented and / or otherwise applied to the corresponding peripheral device, at least one immediately previous version of the trim value and / or trim data structure is also stored in the memory. For example, in the event of a rollback, the previous version of one or more trim values and / or the previous trim data structure remains stored in the memory and can be activated.

[0027] Figure 3 is a block diagram of a trimmed data structure authentication operation 300. Figure 3 In the illustrated example, trim data structure authentication operations 300 include digital signature generation operations 302 performed on original and / or additional candidate trim data structures prior to transmission to one or more devices 100, and digital signature verification operations 304 performed on the signed trim data structures. The example digital signature generation operations 302 include original and / or additional candidate trim data structures 306 to be sent and / or otherwise distributed to one or more peripheral devices 116 of a device 100. The candidate trim data structures 306 are not yet ready for distribution by a trusted party, such as the OEM and / or manufacturer of the device 100. The candidate trim data structures 306 are hashed using a hashing algorithm 308 to generate a first hash digest 310. The first hash digest 310 is signed and / or otherwise encrypted using a private key 312 to generate a digital signature 314 that is paired with the candidate trim data structure to generate a signed trim data structure 318. As described in further detail below, the private key 312 is paired with a corresponding public key 316.

[0028] In response to the authentication circuitry 206 detecting that the signed trimmed data structure 318 has been received by the device 100, the data structure integrator 106 calls the example accelerator circuitry 114 to perform a hash using the hash algorithm 308 to generate a second hash digest 320. Additionally, the accelerator circuitry 114 decrypts the digital signature using the public key 316 to generate a decrypted digital signature 322. The authentication circuitry 206 further calls the accelerator circuitry 114 to compare the second hash digest 320 with the decrypted digital signature 322 to determine a match (324). If the match is successful, the signed trimmed data structure 318 received by the device 100 is then considered secure and / or otherwise not tampered with. Alternatively, if the match is unsuccessful, the received signed trimmed data structure 318 is not trusted, and the example authentication circuitry 206 prevents any further use and / or processing of the signed trimmed data structure 318 received by the device 100.

[0029] Figure 4 corresponds to Figure 1 A block diagram of the nonvolatile memory 110 is provided for additional details. Figure 4 In the illustrated example of nonvolatile memory 110, nonvolatile memory 110 includes an example primary portion 110A and an example non-primary portion 110B. Example non-primary portion 110B includes a first sector 402 and a second sector 404. The example first sector includes a primary trimming data structure 406 (or primary trimming values), which may have been stored on memory 110 during manufacture of device 100. The example second sector includes a secondary trimming data structure 408 (or new / subsequent trimming values) requested for use by the device at a second time after the time of manufacture of device 100.

[0030] In operation, the initial trim values are set by the manufacturer of the device 100 prior to distribution to an end user, such as an OEM. The initial trim values are stored in the first sector 402 as a master trim data structure 406. However, in some instances, the master trim data structure 406 may initially be stored in the second sector 404, as described in further detail below. When the device 100 is powered on or experiences a reset condition, the example boot code 104 copies the trim values from one of the first sector 402 or the second sector 404 to corresponding registers of one or more peripheral devices 116 of the device 100. In some instances, the disclosed techniques may not significantly increase the size of the boot code stored in the ROM 104 because the data structure integrator circuitry 106 can call and utilize the built-in self-test routine.

[0031] In the event that the apparatus 100 receives a replacement (e.g., new) trim data structure to be used by one or more peripheral devices, and in the event that the received trim data structure and / or update request is successfully authenticated, the memory management circuitry 204 stores the trim data structure in the non-volatile memory 110 in a manner that also retains at least one previous version of the trim data structure. Generally, while new trim data structures are authenticated and tested to confirm that they will function in a manner consistent with performance expectations, there is the possibility that a previous version of the trim value may be helpful in the event that one or more anomalies are discovered associated with the new trim value. Thus, the examples described herein maintain at least one previous version of the trim value that can be retrieved later in the event that the updated trim value does not perform as expected. Additionally, while Figure 4 The illustrated example includes a first sector 402 and a second sector 404 of example memory 110, but the examples described herein are not limited thereto. For example, if desired, any number of sectors may be used in a manner that allows more than one previous version of a trimmed value to be retained for future use. For example, if memory 110 has three or more sectors, a second request to update the second trimmed value to a third trimmed value would allow two or more previous trimmed values (or trimmed data structures) to be stored in memory 110 if a recalculation is needed and / or otherwise requested. As described herein, the techniques of this disclosure may allow a trimmed value to be updated more than once or twice.

[0032] In response to memory management circuitry 204 detecting a trim data structure storage request, memory management circuitry 204 determines whether an empty sector is available. For example, if the detected trim data structure storage request occurs after newly manufactured device 100 is placed into operation, the initial trim data structure is already stored in one of the two sectors, leaving the other sector empty. If so, memory management circuitry 204 stores the newly received data structure in the empty sector. However, if both first sector 402 and second sector 404 are populated with at least one previously stored instance of the trim data structure, memory management circuitry 204 obtains a time and date metric (e.g., a timestamp, a storage timestamp, etc.) from the data structures stored in first sector 402 and second sector 404. Memory management circuitry 204 compares the timestamps (e.g., a storage timestamp comparison) to determine which is the oldest data structure and selects the corresponding sector to store the newly received trim data structure therein. In other words, the examples described herein alternate and / or otherwise cycle sector storage operations based on the earliest trim data, which is sometimes referred to as ping-pong storage operations. Figure 4 The example memory 110 having first and second sectors is sometimes referred to herein as a ping-pong memory.

[0033] Although Figure 1 An example manner of implementing the data structure integrator circuitry 106 is described in Figure 1 One or more of the elements, processes and / or devices described in the can be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. Figure 1 The example update detection circuitry 202, the example memory management circuitry 204, the example authentication circuitry 206, the example trim value verification circuitry 208, and / or more generally, the example data structure integrator circuitry 106, may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the example update detection circuitry 202, the example memory management circuitry 204, the example authentication circuitry 206, the example trim value verification circuitry 208, and / or more generally, the example data structure integrator circuitry 106 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), and / or a field programmable logic device (FPLD) such as an FPGA. Further, Figure 1 The integrator circuitry 106 may include one or more components, processes, and / or devices as Figure 1 The present invention may be in addition to or instead of those elements, processes and / or devices described in the specification, and / or may include more than one of any or all of the described elements, processes and devices.

[0034] Figure 5A and 5B A flowchart is shown in FIG, which represents an example of a method that can be executed by a programmable circuit system to implement and / or instantiate Figure 1 Example machine-readable instructions for the data structures of the integrator circuitry 106 and / or representations executable by the programmable circuitry to implement and / or instantiate Figure 1 The machine-readable instructions may be one or more executable programs or portions of one or more executable programs for execution by programmable circuitry, such as described below in conjunction with Figure 6 Programmable circuitry 612 is shown in the example processor platform 600 depicted. In some examples, machine-readable instructions cause operations, tasks, etc. to be performed and / or executed in an automated manner in the real world. As used herein, "automatically" means without human intervention.

[0035] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray Discs, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuitry residing in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than programmable circuitry. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between the server and the endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Furthermore, although reference is made to Figure 5A and 5BThe flowchart illustrated in the describes an example procedure, but many other methods of implementing the example data structure integrator circuitry 106 may alternatively be used. For example, the order of execution of the blocks of the flowchart may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0036] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as part of instructions, code, a representation of code, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, on edge devices, etc.) on a network or collection of networks. The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, etc., in order to render the machine-readable instructions directly readable, interpretable, and / or executable by a computing device and / or another machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, wherein the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form, for example, the programs described herein.

[0037] In another example, the machine-readable instructions may be stored in a state in which they can be read by a programmable circuit system, but may require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API) (e.g., a patch update API instantiated by boot code in ROM), etc., in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding program may need to be configured (e.g., to store settings, input data, record network addresses, etc.) before they can be fully or partially executed. Therefore, as used herein, machine-readable, computer-readable, and / or machine-readable media may contain instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or programs.

[0038] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0039] As mentioned above, Figure 5A and 5BThe example operations of may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, as a temporary buffer, and / or as a cache of information). As used herein, the terms "non-transitory computer-readable storage" and "non-transitory machine-readable storage" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but to exclude propagating signals and to exclude transmission media. Examples of non-transitory computer-readable storage and / or non-transitory machine-readable storage include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, that may or may not be configured with computer-readable instructions, machine-readable instructions, etc., and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0040] Figure 5A is a flow chart representing example machine-readable instructions and / or example operations 500 that may be executed, instantiated, and / or performed by programmable circuitry to update trim values for a device. Figure 5A The example machine-readable instructions and / or example operations 500 begin at block 502, where the memory management circuitry 204 stores an initial trimmed data structure in the first sector 402 of the memory 110. As described above, after the device 100 is manufactured, the initial data structure is stored on the device 100 for field use. Additionally, the memory management circuitry 204 stores or causes the trimmed values from the initial data structure to be stored in registers of one or more peripheral devices 116 of the device 100 (block 504). In some examples, the device 100 is moved to an operating environment so that the one or more peripheral devices 116 can perform corresponding tasks.

[0041] During field operation, the example CPU 102 executes any number of applications (block 506), and the example update detection circuitry 202 determines whether a trim update request has been initiated, triggered, and / or otherwise occurred (block 508). If not, control returns to block 506 and monitoring for such triggers continues. However, in response to the update detection circuitry 202 determining and / or otherwise detecting a trigger that a trim update has been requested (block 508), the memory management circuitry 204 stores the new trim data structure in the RAM 112 (block 510). Because the newly received trim data structure has not yet been authenticated, the authentication circuitry 206 performs one or more security checks described above (block 512). If the authentication circuitry 206 determines that the security check failed (block 514), the newly received trim data structure is rejected (block 516). However, if authentication circuitry 206 determines that the security check is successful (block 514), memory management circuitry 204 stores the new trim data structure in a sector of memory 110 that is either empty or contains the oldest version of the previous trim data structure (block 518). As described above, in some examples, memory management circuitry 204 may store the newly received and successfully authenticated trim data structure in first sector 402 if the first sector contains the oldest version of the previous trim data structure, or in second sector 404 if the second sector contains the oldest version. Additionally, in some examples, more than two sectors may be available for trim data structure storage, which may facilitate the ability to have a large number of previous trim data structures stored on memory.

[0042] The example trim value validation circuitry 208 performs one or more security tests using one or more of the trim values from the newly received trim data structure (block 520). If the tested trim value fails the security check (block 522) (e.g., does not meet one or more thresholds), the trim data structure is rejected (block 516). In such cases, the previous version of the trim data structure and the trim values therein are maintained for use with the device 100. However, if one or more of the tested trim values meet the one or more security checks (block 522), the example data structure integrator 106 restarts the device 100 to populate the peripheral device trim registers with the trim values from the newly received trim data structure (block 524). Thus, the trim value validation circuitry 208 can ensure the authenticity and integrity of the newly received trim data, rather than blindly copying the new trim data.

[0043] Figure 5B is a flow chart representing example machine-readable instructions and / or example operations 550 that may be executed, instantiated, and / or performed by programmable circuitry to store a received trimmed data structure in memory 110 after such trimmed data structure has been successfully authenticated. Figure 5B In the illustrated example, memory management circuitry 204 monitors for the occurrence of a trim data structure storage request (block 552). If memory management circuitry 204 determines and / or otherwise detects that one of the memory sectors is empty (block 554), the trim data structure is stored in the previously empty sector (block 556). However, if none of the sectors of memory 110 are empty, memory management circuitry 204 obtains time and date information (e.g., timestamps) from data structures in all available sectors of memory 110 (block 558). Based on the sector in memory 110 containing the earliest associated timestamp, memory management circuitry 204 overwrites the contents of that sector with the newly received trim data structure (block 560). Control then returns to block 552 to continue monitoring for storage requests.

[0044] Figure 6 is structured to execute and / or instantiate Figure 5A and 5B Example machine-readable instructions and / or example operations to implement Figure 1 The data structure of the integrator circuit system 106 is a block diagram of an example programmable circuit system platform 600. The programmable circuit system platform 600 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smartphone, an iPad, etc.). TM tablet), internet appliance, gaming console, set-top box, headset (e.g., augmented reality (AR) headset, virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0045] The programmable circuitry platform 600 of the illustrated example includes programmable circuitry 612. The programmable circuitry 612 of the illustrated example is hardware. For example, the programmable circuitry 612 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuitry 612 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuitry 612 implements the update detection circuitry 202, the memory management circuitry 204, the authentication circuitry 206, the trim value verification circuitry, and the data structure integrator 106.

[0046] The programmable circuit system 612 of the illustrated example includes a local memory 613 (e.g., cache, registers, etc.). The programmable circuit system 612 of the illustrated example communicates with main memory 614, 616 via a bus 618, the main memory including volatile memory 614 and non-volatile memory 616. The volatile memory 614 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory 616. The non-volatile memory 616 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 614, 616 of the illustrated example is controlled by a memory controller 617. In some examples, the memory controller 617 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 614, 616.

[0047] The programmable circuitry platform 600 of the illustrated example also includes an interface circuitry 620. The interface circuitry 620 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0048] In the illustrated example, one or more input devices 622 are connected to the interface circuitry 620. The input devices 622 allow a user (e.g., a human user, a machine user, etc.) to enter data and / or commands into the programmable circuitry 612. The input devices 622 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isochronous device, and / or a speech recognition system.

[0049] One or more output devices 624 are also connected to the interface circuitry 620 of the illustrated example. The output devices 624 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switch (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 620 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry such as a GPU.

[0050] The interface circuitry 620 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any type of computing device) over a network 626. Communication may occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a non-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0051] The programmable circuitry platform 600 of the illustrated example also includes one or more mass storage disks or devices 628 to store firmware, software, and / or data. Examples of such mass storage disks or devices 628 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0052] Available through Figure 5A and 5B The machine-readable instructions 632 implemented by the machine-readable instructions may be stored in the mass storage device 628, in the volatile memory 614, in the non-volatile memory 616, and / or on at least one non-transitory computer-readable storage medium, such as a removable CD or DVD.

[0053] In some instances, Figure 6 The programmable circuit system 612 can be in one or more packages. In some examples, the XPU can be composed of Figure 6 The programmable circuitry 612 is implemented in accordance with the present invention, which may be in one or more packages.

[0054] "Comprise" and "include" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within any type of claim recitation, additional elements, items, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, the phrase "at least" when used as a transitional term, such as in the preamble of a claim, is open-ended in the same manner as the terms "comprise" and "comprising" are open-ended.

[0055] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude the plural. As used herein, the term "a" or "an" object refers to one or more of the objects described. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0056] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the Earth. A first part is above a second part if at least one portion of the second part is between the Earth and the first part. Similarly, as used herein, a first part is "below" a second part when the first part is closer to the Earth than the second part. As mentioned above, a first part can be above or below a second part, with one or more of the following conditions: with other parts in between, without other parts in between, with the first and second parts in contact, or with the first and second parts not in direct contact with each other.

[0057] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any manner located on another part (e.g., located on, situated on, disposed on, or formed on, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intermediate parts positioned therebetween.

[0058] As used herein, unless otherwise specified, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and / or relative movement between those elements. Thus, connection references do not necessarily imply that two elements are directly connected and / or are in fixed relation to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0059] As used herein, "substantially" and "approximately" modify the subject matter / values thereof to recognize the potential for variations that occur in real-world applications. For example, as will be understood by one of ordinary skill in the art, "substantially" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections. For example, unless otherwise specified herein, "substantially" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%.

[0060] As used herein, "substantially real time" means occurring in a near instantaneous manner, recognizing that there may be real-world delays in computing time, transmission, etc. Thus, unless otherwise specified, "substantially real time" means real time + / - 1 second.

[0061] As used herein, the phrase "communication," including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals and / or one-time events.

[0062] As used herein, "programmable circuitry" is defined to include: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are structured to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform specific functions and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU), which can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction to configure and / or structure the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations and / or functions; and / or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and orchestration technology (e.g., an application programming interface (API) that can assign computing tasks to any one(s) of the multiple types of programmable circuitry that is suitable and available to perform the computing tasks).

[0063] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0064] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, for example: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. In addition, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0065] As used herein, the term "coupled" may encompass any connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0066] Numerical identifiers such as "first," "second," "third," etc., are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers used in the detailed description are not necessarily consistent with the identifiers used in the claims.

[0067] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0068] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between or terminations of a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0069] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, for example, by an end user and / or a third party, to form the described structure.

[0070] The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being outside the integrated circuit may be included in the integrated circuit, and / or some features described as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0071] Modifications of the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

[0072] Disclosed herein are example methods, apparatuses, systems, and articles of manufacture for updating trim values for a device. Other examples and combinations thereof include at least the following:

[0073] Example 1 includes a device comprising instructions and programmable circuitry, the programmable circuitry configurable to instantiate and / or execute the instructions to: authenticate a request to update a first trimming value to a second trimming value, wherein the first trimming value is stored in a memory; and in response to authenticating the request, store the second trimming value in the memory while the first trimming value remains stored in the memory.

[0074] Example 2 includes the device of example 1, wherein the request is a first request, the programmable circuitry is further configured to authenticate a second request to update the second trimming value to a third trimming value, and in response to authenticating the second request, store the third trimming value to the memory while the second trimming value remains stored in the memory.

[0075] Example 3 includes the device of example 2, wherein the programmable circuitry is further configurable to overwrite the first trim value with the third trim value.

[0076] Example 4 includes the device of example 1, wherein the programmable circuitry is further configurable to test the second trim value on the device.

[0077] Example 5 includes the apparatus of example 4, wherein the programmable circuitry is further configurable to authorize use of the second trim value in response to the test satisfying a target metric.

[0078] Example 6 includes the device of example 4, wherein the programmable circuitry is further configurable to, in response to the test satisfying a target metric, store the second trim value in one of the first sector of the memory or the second sector of the memory.

[0079] Example 7 includes the device of example 1, wherein the programmable circuitry is further configurable to determine which of a first sector of the memory or a second sector of the memory includes the first trim value.

[0080] Example 8 includes the device of example 7, wherein the programmable circuitry is further configurable to rewrite one of the first sector or the second sector based on a storage timestamp comparison.

[0081] Example 9 includes the apparatus of example 8, wherein the programmable circuitry is further configurable to overwrite one of the first sector or the second sector that corresponds to the respective earliest stored timestamp.

[0082] Example 10 includes the device of example 1, wherein the first trim value is generated at a first time during manufacture of the device.

[0083] Example 11 includes the device of example 10, wherein the programmable circuitry is further configurable to receive the second trim value at a second time after the device is installed.

[0084] Example 12 includes the device of example 11, wherein the programmable circuitry is further configurable to activate the second trimming value for use by the device and deactivate the first trimming value from use by the device.

[0085] Example 13 includes the device of example 1, wherein the device comprises at least one of a power amplifier, a low noise amplifier, a direct current to direct current (DCDC) converter, an oscillator, or an analog-to-digital converter (ADC).

[0086] Example 14 includes a non-transitory computer-readable medium comprising machine-readable instructions that, when executed, cause processor circuitry to: at least authenticate a first request corresponding to replacing a first trimming value with a second trimming value, wherein the first trimming value is stored in a memory; and in response to authentication of the first request, store the second trimming value to the memory and maintain the first trimming value in the memory.

[0087] Example 15 includes the non-transitory computer-readable medium of example 14, wherein the machine-readable instructions cause the processor circuitry to: authenticate a second request corresponding to replacing the second trimming value with a third trimming value; and in response to authentication of the second request, store the third trimming value to the memory and maintain the second trimming value in the memory.

[0088] Example 16 includes the non-transitory computer-readable medium of example 15, wherein the machine-readable instructions cause the processor circuitry to overwrite the first trimming value with the third trimming value.

[0089] Example 17 includes the non-transitory computer-readable medium of example 15, wherein the machine-readable instructions cause the processor circuitry to test the second trim value on a device.

[0090] Example 18 includes the non-transitory computer-readable medium of example 17, wherein the machine-readable instructions cause the processor circuitry to authorize use of the second trim value in response to the test satisfying one or more target metrics.

[0091] Example 19 includes the non-transitory computer-readable medium of example 17, wherein the machine-readable instructions cause the processor circuitry to: store the second trim value in one of a first sector of the memory or a second sector of the memory in response to the test satisfying one or more target metrics, the first and second sectors of the memory forming a ping-pong memory.

[0092] Example 20 includes the non-transitory computer-readable medium of example 15, wherein the machine-readable instructions cause the processor circuitry to determine which of a first sector of the memory or a second sector of the memory includes the first trim value.

[0093] Example 21 includes the non-transitory computer-readable medium of example 20, wherein the machine-readable instructions cause the processor circuitry to rewrite one of the first sector or the second sector of the memory based on a storage timestamp comparison.

[0094] Example 22 includes the non-transitory computer-readable medium of example 21, wherein the machine-readable instructions cause the processor circuitry to: rewrite the one of the first sector or the second sector that corresponds to the respective earliest stored timestamp.

[0095] Example 23 includes the non-transitory computer-readable medium of example 15, wherein the machine-readable instructions cause the processor circuitry to enable device use of the second trimming value and disable device use of the first trimming value.

[0096] Example 24 includes a method comprising: authenticating a request to update a first trimming value to a second trimming value, wherein the first trimming value is stored in a memory; and responsive to verification of the request, storing the second trimming value to the memory while the first trimming value remains stored in the memory.

[0097] Example 25 includes the method of example 24, further comprising: authenticating a second request to update the second trimming value to a third trimming value; and in response to authenticating the second request, storing the third trimming value to the memory while the second trimming value remains stored in the memory.

[0098] Example 26 includes the method of example 25, further comprising overwriting the first trimming value with the third trimming value.

[0099] Example 27 includes the method of example 24, further comprising testing a device based on the second trim value.

[0100] Example 28 includes the method of example 27, further comprising authorizing use of the second trimming value by the device in response to the testing satisfying one or more target metrics.

[0101] Example 29 includes the method of Example 27, further comprising storing the second trimming value in one of the first sector of the memory or the second sector of the memory in response to the testing satisfying one or more target metrics.

[0102] Example 30 includes the method of example 24, further comprising determining which of a first sector of the memory or a second sector of the memory includes the first trim value.

[0103] Example 31 includes the method of example 30, further comprising rewriting one of the first sector or the second sector based on a storage timestamp comparison.

[0104] Example 32 includes the method of example 31, further comprising overwriting the one of the first sector or the second sector corresponding to the respective earliest stored timestamp value.

[0105] As will be appreciated from the foregoing, example systems, devices, articles, and methods have been described that enable peripheral device operation to be updated and / or customized in the field, particularly when initial field environmental conditions have (e.g., unexpectedly) changed after the initial installation or deployment of the peripheral device. For example, a transmitter's RF power output value may have an appropriate trim value at the first time after the initial deployment of a system-on-chip (SoC) containing one or more power amplifiers, but when the SoC is subsequently located in an alternate location, such RF power output value may no longer result in acceptable performance of the power amplifier. Thus, the examples described herein facilitate a manner for updating the trim values of peripheral devices so that acceptable (e.g., within-threshold operational metrics) peripheral device operation can occur. In some instances, if an RF transmitter has a trim value that is too high, power is wasted and the corresponding RF receiver may become saturated. Thus, the described systems, devices, articles, and methods improve the efficiency of using a device by facilitating power-saving trim settings for one or more peripheral devices of the device after they have been deployed in the field. The described systems, devices, articles, and methods accordingly relate to one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.

Claims

1. A device comprising: instruction; as well as Programmable circuitry configurable to instantiate and / or execute the instructions to: authenticating a request to update a first trimming value to a second trimming value, wherein the first trimming value is stored in a memory; as well as In response to authenticating the request, the second trimming value is stored to the memory while the first trimming value remains stored in the memory.

2. The apparatus of claim 1 , wherein the request is a first request, and the programmable circuitry is further configurable to: authenticating a second request to update the second trimming value to a third trimming value; and In response to authenticating the second request, the third trimming value is stored to the memory while the second trimming value remains stored in the memory. 3 . The apparatus of claim 2 , wherein the programmable circuitry is further configurable to overwrite the first trimming value with the third trimming value.

4. The device of claim 1, wherein the programmable circuitry is further configurable to test the second trim value on the device. 5 . The apparatus of claim 4 , wherein the programmable circuitry is further configurable to authorize use of the second trim value in response to the test meeting a target metric.

6. The apparatus of claim 4, wherein the programmable circuitry is further configurable to, in response to the test satisfying a target metric, store the second trim value in one of the first sector of the memory or the second sector of the memory.

7. The device of claim 1, wherein the programmable circuitry is further configurable to determine which of a first sector of the memory or a second sector of the memory contains the first trim value.

8. The device of claim 7, wherein the programmable circuitry is further configurable to rewrite one of the first sector or the second sector based on a storage timestamp comparison.

9. The apparatus of claim 8, wherein the programmable circuitry is further configurable to overwrite the one of the first sector or the second sector that corresponds to the respective earliest stored timestamp.

10. The device of claim 1, wherein the first trim value is generated at a first time during manufacture of the device.

11. The device of claim 10, wherein the programmable circuitry is further configurable to receive the second trim value at a second time after the device is installed.

12. The apparatus of claim 11 , wherein the programmable circuitry is further configurable to: activating the second trim value for use by the apparatus; and The first trimming value is deactivated from use by the device.

13. The device of claim 1, wherein the device comprises at least one of a power amplifier, a low noise amplifier, a direct current to direct current (DCDC) converter, an oscillator, or an analog-to-digital converter (ADC).

14. A non-transitory computer-readable medium comprising machine-readable instructions that, when executed, cause a processor circuit system to at least: The authentication corresponds to a first request to replace a first trimming value with a second trimming value, wherein the first trimming value is stored in a memory; and In response to authenticating the first request: storing the second trimming value in the memory; and The first trim value is maintained in the memory.

15. The non-transitory computer-readable medium of claim 14, wherein the machine-readable instructions cause the processor circuitry to: authenticating a second request corresponding to replacing the second trimming value with a third trimming value; and In response to the authentication of the second request: storing the third trimming value in the memory; and The second trim value is maintained in the memory.

16. The non-transitory computer-readable medium of claim 15, wherein the machine-readable instructions cause the processor circuitry to overwrite the first trimming value with the third trimming value.

17. The non-transitory computer-readable medium of claim 15, wherein the machine-readable instructions cause the processor circuitry to test the second trim value on a device.

18. The non-transitory computer-readable medium of claim 17, wherein the machine-readable instructions cause the processor circuitry to authorize use of the second trim value in response to the test satisfying one or more target metrics.

19. The non-transitory computer-readable medium of claim 17, wherein the machine-readable instructions cause the processor circuitry to store the second trim value in one of a first sector of the memory or a second sector of the memory in response to the test satisfying one or more target metrics, the first and second sectors of the memory forming a ping-pong memory.

20. A method comprising: authenticating a request to update a first trimming value to a second trimming value, wherein the first trimming value is stored in a memory; as well as In response to authenticating the request, the second trimming value is stored to the memory while the first trimming value remains stored in the memory.

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