Pulse event coding method and system based on multistage addressing

Abstract

The invention relates to the field of pulse neural network coding and application thereof, in particular to a pulse event coding method and system based on multistage addressing. According to the method, pulse sparsity is utilized, meanwhile, a synaptic partition concept is introduced, all synapses corresponding to neurons are divided into partitions with the same size, then address coding is carried out on the synaptic partitions, secondary address coding is carried out on the synapses in each synaptic partition, a synaptic partition address and a synaptic address are mapped by adopting two stages of memories, and the synaptic partition address and the synaptic address are mapped by adopting two stages of memories. The bit width of the synaptic index in pulse event coding is reduced, the total storage is finally reduced, and compared with the original scheme, the total storage overhead is reduced by more than 95%. According to the invention, pulse event coding is carried out by adopting a multi-level addressing technology, the coding efficiency is high, and the expandability is strong; when the circuit is applied to a pulse neural network circuit or a chip, the area and the power consumption of the circuit can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to pulse neural network coding and its application field, and in particular to a pulse event coding method and system based on multi-level addressing. Background Art

[0002] Spiking neural network (SNN) has the characteristics of bionics and low power consumption. Neurons transmit information through binary spikes, and synapses perform calculations through binary spikes. Neuron models such as Figure 1 However, the effective pulses ("1" pulses) in SNNs are extremely sparse. For example, in the VGG model (Visual Geometry Group Network), the proportion of "1" pulses is less than 20%. This means that a large number of invalid "0" pulses are transmitted between neurons and participate in synaptic calculations, significantly reducing computational efficiency in the circuit and increasing power consumption.

[0003] In response to the above situation, an existing advanced solution is to use pulse event coding technology to encode, transmit and calculate only valid "1" pulses. The core idea is that if a neuron outputs a valid pulse, it is represented as a neuron index and the index is transmitted to the next level neuron; if the neuron outputs an invalid pulse, it is not encoded or transmitted. After the next level neuron receives the event package, it finds the corresponding synapse based on the previous level neuron index and performs calculations. The main problem faced by this technical solution is that valid pulses require multiple bits to represent, which may result in large communication bandwidth and storage capacity overhead. When designing neuron memory, in order to ensure compatibility under various sparsities, the design capacity usually needs to be greater than or equal to the maximum case in actual application. Compared with the binary coding scheme, the storage overhead required by the pulse event coding technology is extremely large. Summary of the Invention

[0004] To address the aforementioned problems and shortcomings, and to address the inability of existing spiking neural network coding techniques to effectively balance computational efficiency and storage overhead, the present invention proposes a method and system for pulse event coding based on multi-level addressing. The present invention employs multi-level addressing technology for pulse event coding, thereby reducing storage overhead and improving coding efficiency.

[0005] A pulse event encoding method based on multi-level addressing, specifically:

[0006] All synapses corresponding to a neuron are divided into continuous partitions of equal size, and each synaptic partition is address-coded in sequence; the synapses within each synaptic partition are also address-coded in sequence.

[0007] The first-level memory is an address memory, whose address space corresponds to the number of synaptic partitions, and the number of bits storing address data meets the address index requirements of the second-level memory; the data stored at each address is used to index the event memory address corresponding to the first event in the synaptic partition.

[0008] The secondary memory is an event memory, and the address space is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition.

[0009] If the neuron outputs a valid pulse 1, it is represented as a neuron index in the form of the first-level memory address + the second-level memory address; if the neuron outputs an invalid pulse 0, it is not encoded or transmitted; after the next-level neuron receives the event packet, it finds the corresponding synapse based on the previous-level neuron index and performs calculations.

[0010] Furthermore, the primary memory is implemented using static random access memory SRAM, or a functional circuit.

[0011] A pulse event coding system based on multi-level addressing, its structure is as follows Figure 2 As shown, it includes a neuron synapse partition encoding module, a primary memory, a secondary memory, and an address and event index module.

[0012] The neuron synapse partition coding module is used to divide all synapses corresponding to a neuron into continuous partitions of equal size, and perform address coding on the synapse partitions in sequence, and perform address coding on the synapses in the partitions in sequence.

[0013] The primary memory is used to store the event memory address corresponding to the first event in the synaptic partition, and its address space corresponds to the number of synaptic partitions. The number of bits of the stored address data meets the secondary memory address index requirement.

[0014] The secondary memory is used to store the synaptic event index in each synaptic partition. The address space of the secondary memory is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; each address stores an event packet, the data of which is the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition.

[0015] The address and event index module is used to perform multi-level addressing of the neuron's pulse events and determine the pulse event coding; if the neuron outputs a valid pulse 1, it is represented as a neuron index in the form of the first-level memory address + the second-level memory address; if the neuron outputs an invalid pulse 0, it is not encoded or transmitted.

[0016] Furthermore, the above-mentioned pulse event coding system based on multi-level addressing corresponding to a neuron is extended to the entire pulse neural network circuit or chip to perform synaptic calculations, so as to give a good balance between computing efficiency and storage overhead.

[0017] In summary, compared to the prior art, the present invention utilizes pulse sparsity and introduces the concept of synaptic partitioning, dividing all synapses corresponding to neurons into partitions of equal size. The synaptic partitions are then address-encoded, and the synapses within each synaptic partition are then secondarily address-encoded. By using a two-level memory to map the synaptic partition address and synaptic address, the bit width of the synaptic index in the pulse event encoding is reduced, ultimately reducing the total storage overhead by over 95% compared to the prior art. The present invention employs multi-level addressing technology for pulse event encoding, resulting in high encoding efficiency and strong scalability. Furthermore, when applied to pulse neural network circuits or chips, the circuit area and power consumption can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the spiking neural network neuron model;

[0019] Figure 2 is a system block diagram of the present invention;

[0020] Figure 3 Memory overhead for example event;

[0021] Figure 4 The embodiment is based on a pulse event encoding scheme of multi-level addressing. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the method and process of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] A pulse event coding system based on multi-level addressing, such as Figure 2 As shown, it includes a neuron synapse partition encoding module, a primary memory, a secondary memory, and an address and event index module;

[0024] The neuron synapse partition coding module is used to divide all synapses corresponding to a neuron into continuous partitions of equal size, and perform address coding on the synapse partitions in sequence, such as Figure 2-1 01; address the synapses in the partition in sequence, as shown in Figure 2-1 As shown in 02.

[0025] The primary memory is used to store the event memory address corresponding to the first event in the synaptic partition. Its address space corresponds to the number of synaptic partitions, and the number of bits of the stored address data meets the secondary memory address index requirements, such as Figure 2-1 As shown in 03.

[0026] The secondary memory is used to store the synaptic event index in each synaptic partition. The address space of the secondary memory is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition, such as Figure 2-1 04 shown.

[0027] The address and event index module is used to perform multi-level addressing of the neuron's pulse events and determine the pulse event coding; the pulse event coding is completed through the address index from the first-level memory to the second-level memory, and then through the second-level memory to the event index of the synapse; if the neuron outputs a valid pulse 1, it is represented as the neuron index and the index is transmitted to the next-level neuron; if the neuron outputs an invalid pulse 0, it is not encoded or transmitted.

[0028] For this embodiment, assuming that a neuron has 64K synapses, the maximum memory size is used, that is, all pulses with sparsity of 0 can be stored. The storage overhead of the binary encoding scheme is 64Kb. However, using the existing pulse event encoding scheme, 17 bits are required to represent a single pulse (1 bit time synchronization + 16 bits synaptic index), and the neuron storage overhead is 1088Kb, which is 16 times higher than the binary encoding scheme. The total storage overhead is serious, such as Figure 3 shown.

[0029] By using the technical solution of the present invention, the 64K synapses of a neuron in the above example are divided into 256 continuous synaptic partitions of equal size. Figure 4 : The partition address is encoded as 0x000~0x100. Each synapse partition contains 256 consecutive synapses, and the synapse address is encoded as 0x000~0x100.

[0030] The corresponding primary memory address space is designed to be 256, corresponding to the number of synaptic partitions. Each address stores 12 bits of data (assuming the effective pulse ratio is less than 1 / 16, and the event memory size is designed to be 4K). This data is used to index the event memory (i.e., secondary memory) address corresponding to the first event in the synaptic partition. This embodiment is based on the design of a spiking neural network circuit and is implemented using static random access memory (SRAM).

[0031] The corresponding secondary memory address space is designed to be 4K, corresponding to the event memory size in the above calculation. Each address stores an event packet, which contains 9-bit data (1-bit synaptic partition switching signal + 8-bit synaptic index), which is used to index the first synaptic event in the corresponding synaptic partition.

[0032] The pulse event of a neuron is indexed from the address of the primary memory to the secondary memory, and then indexed from the secondary memory to the synapse event, completing the pulse-neuron mapping, such as Figure 2-1 05 and Figure 4 As shown in the figure; if the neuron outputs a valid pulse 1, it is represented as the neuron index and transmitted to the next level neuron; if the neuron outputs an invalid pulse 0, it is not encoded or transmitted; after the next level neuron receives the event packet, it finds the corresponding synapse according to the previous level neuron index and performs calculations.

[0033] After adopting the technical solution of the present invention, the primary memory is 3Kb, the secondary memory is 36Kb, and the final total memory overhead is reduced to 39Kb, which is more than 96% lower than the total storage overhead of 1088Kb of the existing technical solution. For a spiking neural network circuit system containing multiple neurons, by using the technical solution of the present invention, the pulse event encoding method of the above single neuron can be extended to the entire spiking neural network circuit system, which will achieve significant area and power consumption benefits.

[0034] As can be seen from the above examples, the present invention utilizes spike sparsity and introduces the concept of synaptic partitioning, dividing all synapses corresponding to a neuron into equally sized partitions. The synaptic partitions are then address-encoded, and the synapses within each partition are then subjected to secondary address encoding. By using a two-level memory to map synaptic partition addresses to synaptic addresses, the bit width of the synaptic index in the spike event encoding is significantly reduced, ultimately reducing total memory usage. Compared to the prior art, the present invention reduces total memory overhead by over 95%, and features high encoding efficiency and strong scalability. When applied to spiking neural network circuits or chips, the present invention can significantly reduce circuit area and power consumption.

Claims

1. A pulse event encoding method based on multi-level addressing, characterized in that: Specifically: All synapses corresponding to a neuron are divided into continuous partitions of equal size, and each synaptic partition is address-coded in sequence; the synapses within each synaptic partition are also address-coded in sequence; The primary memory is an address memory, whose address space corresponds to the number of synaptic partitions, and the number of bits storing address data meets the address index requirements of the secondary memory; the data stored at each address is used to index the event memory address corresponding to the first event in the synaptic partition; The secondary memory is an event memory, and the address space is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, then the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirements in each synaptic partition; Each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition; If the neuron outputs a valid pulse of 1, it is represented as the neuron index in the form of the first-level memory address + the second-level memory address; If a neuron outputs an invalid pulse 0, it will not be encoded or transmitted; after the next-level neuron receives the event packet, it will find the corresponding synapse based on the index of the previous-level neuron and perform calculations.

2. The pulse event encoding method based on multi-level addressing as claimed in claim 1, characterized in that: The primary memory is implemented using static random access memory SRAM.

3. The pulse event encoding method based on multi-level addressing as claimed in claim 1, characterized in that: The primary memory is implemented using a functional circuit.

4. A pulse event coding system based on multi-level addressing, characterized in that: It includes a neuron synapse partition encoding module, a primary memory, a secondary memory, and an address and event index module; The neuron synapse partition coding module is used to divide all synapses corresponding to a neuron into continuous partitions of equal size, and perform address coding on the synapse partitions in sequence, and perform address coding on the synapses within the partitions in sequence; The primary memory is used to store the event memory address corresponding to the first event in the synaptic partition, the address space of which corresponds to the number of synaptic partitions, and the number of bits of the stored address data meets the secondary memory address index requirement; The secondary memory is used to store the synaptic event index in each synaptic partition. The address space of the secondary memory is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; Each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition; The address and event index module is used to perform multi-level addressing on the pulse events of neurons and determine the pulse event codes; If the neuron outputs a valid pulse of 1, it is represented as the neuron index in the form of the first-level memory address + the second-level memory address; If a neuron outputs an invalid pulse 0, it is not encoded or transmitted.

5. The pulse event coding system based on multi-level addressing as claimed in claim 4, characterized in that: The pulse event coding system based on multi-level addressing corresponding to a neuron is extended to the entire pulse neural network circuit or chip to perform synaptic calculations, so as to strike a good balance between computing efficiency and storage overhead.

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