Digital model generation using neural networks

Abstract

The invention discloses digital model generation using neural networks. Apparatuses, systems, and techniques are provided for generating a digital model. In at least one embodiment, a neural network is used to generate a motion of a first portion of an object based on a motion of a second portion of the object and audio corresponding to the motion of the second portion of the object. For example, a neural network may use audio information to generate motion of facial and body features of a digital model.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training a neural network according to the various new techniques described herein. Background Art

[0002] Training and using neural networks to generate images and / or avatars based on audio and / or text input can be challenging because the generated avatars must depict complex and nuanced expressions. For example, the neural networks must generate models that can represent both verbal and non-verbal forms of expressive communication. Furthermore, training such neural networks can be challenging because they require significant computational resources, such as processing and memory. Therefore, there is a need for improved neural networks for generating avatars, as well as improved methods for training these neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A system for generating one or more 3D objects from one or more audio and / or text inputs according to at least one embodiment is shown;

[0004] Figure 2 An example of a data collection pipeline for training a neural network to generate one or more 3D objects in accordance with at least one embodiment is shown;

[0005] Figure 3 An example of a training architecture for a neural network that generates one or more 3D objects using a conditional diffusion model in accordance with at least one embodiment is shown;

[0006] Figure 4 An example of a conditional diffusion model with a crisscross attention mechanism according to at least one embodiment is shown;

[0007] Figure 5 An example of a detailed diffusion model architecture for generating one or more 3D objects based on at least one portion, an audio and / or text input is shown in accordance with at least one embodiment;

[0008] Figure 6 is a flow chart illustrating a method of generating updated posture information according to at least one embodiment;

[0009] Figure 7 An example of a processor according to at least one embodiment is shown;

[0010] Figure 8 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment;

[0011] Figure 9A illustrates logic according to at least one embodiment;

[0012] Figure 9B illustrates logic according to at least one embodiment;

[0013] Figure 10 illustrates the training and deployment of a neural network according to at least one embodiment;

[0014] Figure 11 An example data center system is shown in accordance with at least one embodiment;

[0015] Figure 12A An example of an autonomous vehicle according to at least one embodiment is shown;

[0016] Figure 12B According to at least one embodiment, Figure 12A Examples of camera positions and fields of view for autonomous vehicles;

[0017] Figure 12C According to at least one embodiment Figure 12A A block diagram of an example system architecture for an autonomous vehicle;

[0018] Figure 12D is a diagram illustrating a method for one or more cloud-based servers and Figure 12A A diagram of a system for communicating between autonomous vehicles;

[0019] Figure 13 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 14 is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 15 A computer system according to at least one embodiment is shown;

[0022] Figure 16 A computer system according to at least one embodiment is shown;

[0023] Figure 17A A computer system according to at least one embodiment is shown;

[0024] Figure 17B A computer system according to at least one embodiment is shown;

[0025] Figure 17C A computer system according to at least one embodiment is shown;

[0026] Figure 17DA computer system according to at least one embodiment is shown;

[0027] Figure 17E and Figure 17F illustrates a shared programming model according to at least one embodiment;

[0028] Figure 18 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Figures 19A to 19B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0030] FIG. 20A to FIG. 20B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Figure 21 A computer system according to at least one embodiment is shown;

[0032] Figure 22A A parallel processor according to at least one embodiment is shown;

[0033] Figure 22B shows a partition unit according to at least one embodiment;

[0034] Figure 22C illustrates a processing cluster according to at least one embodiment;

[0035] Figure 22D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 23 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Figure 24 A graphics processor according to at least one embodiment is shown;

[0038] Figure 25 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Figure 26 A deep learning application processor according to at least one embodiment is shown;

[0040] Figure 27 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0041] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Figure 30 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 31 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Figure 32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Figures 33A to 33B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0047] Figure 34 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0048] Figure 35 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0049] Figure 36 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0050] Figure 37 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0051] Figure 38 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0052] Figure 39 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0053] Figure 40 includes an example illustration of a high-level computational pipeline for processing imaging data in accordance with at least one embodiment;

[0054] Figure 41A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0055] Figure 41B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0056] Figure 42AA data flow diagram illustrating a process for training a machine learning model according to at least one embodiment;

[0057] Figure 42B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment; and

[0058] Figure 43 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0059] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0060] In at least one embodiment, a data collection pipeline (e.g., Figure 2 The pipeline 200 is used to generate one or more training datasets by collecting and processing existing videos depicting people speaking. In at least one embodiment, the pipeline includes processing audio and text information, where audio is first extracted and then sent to a pre-trained automatic speech recognition (ASR) system to obtain a text sequence. In at least one embodiment, the text sequence is sent to an existing emotion classifier and character recognition model so that one or more users can use the emotion and character labels to generate one or more 3D objects in a user interface. In at least one embodiment, facial recognition and body joint recognition are used to generate a set of predefined facial points and a set of joint tensor maps. In at least one embodiment, a pre-trained model such as OpenPose2 is used to recognize body joint poses and facial points (e.g., facial expressions of eyes and mouth). In at least one embodiment, 2D body poses are converted to 3D using various 2D to 3D deep learning models described herein. In at least one embodiment, a pre-trained heatmap generation model (such as HRNet) is used to annotate heatmap information of image and / or video frame data depicting people and / or other objects.

[0061] In at least one embodiment, a 3D avatar (e.g., an object and / or body) is generated to model motion that expresses emotional content (e.g., body language) corresponding to textual and / or audio content for digital applications. In at least one embodiment, the motion of one or more objects, bodies, or parts of bodies or objects is modeled because the motion corresponds to the sounds that express or convey communication, which is important for forming the expression of the content. In at least one embodiment, the motion of one or more objects, bodies, or parts of bodies or objects is modeled to express non-verbal forms of communication, such as body language, which complement audio communication and are important for forming a complete understanding of the information and emotional content. In at least one embodiment, one or more 3D avatars are generated to accurately model communication forms (e.g., audio and non-audio expression forms), such as by modeling variations in form, motion, and / or expression corresponding to different languages, cultures, audio streams, emotional content expressed, and / or external environmental factors. In at least one embodiment, the avatar is modeled as one or more 3D body poses that include motion associated with one or more audio streams that express information and / or emotional content. In at least one embodiment, the 3D avatar is modeled as one or more 3D body gestures comprising motions converted from one or more text strings into one or more 3D body gesture streams that convey informational and / or emotional content.

[0062] In at least one embodiment, one or more neural networks are configured to capture motion distributions, such as distributions of motion information indicating motion of one or more joints of a human body, and convert the motion into one or more tensor graphs. In at least one embodiment, one or more neural networks are configured to receive audio (e.g., an audio stream) comprising one or more spoken languages and identify emotions and / or information content from the audio. In at least one embodiment, one or more processors utilize the neural network to receive one or more text prompts and / or audio inputs and generate a 3D avatar and / or image corresponding to the one or more text and / or voice inputs. In at least one embodiment, the neural network generates an animation of a three-dimensional (3D) model of an object (e.g., a 3D avatar of a human or non-human figure) based on the audio input. In at least one embodiment, the 3D model displays motion consistent with human body language corresponding to the audio input (e.g., motion of a limb, arm, hand, or torso), as well as motion of other body parts (e.g., facial expressions). In at least one embodiment, for example, one or more audio inputs may express emotions, and the motion of the 3D model generated by the one or more neural networks may depend on the emotional content of the audio input. In at least one embodiment, one or more neural networks may generate a 3D object that depicts one or more motions of a first portion of the object based at least in part on one or more motions of a second portion of the object and audio corresponding to the one or more motions of the second portion of the object.

[0063] In at least one embodiment, software executed by one or more processors enables training of one or more neural networks using input data including audio, text, heatmaps, tensor maps, image data, video data, any combination thereof, or any other input data described herein. In at least one embodiment, the encoding portion of the neural network identifies features corresponding to the motion of an object associated with one or more audio and / or text inputs and is trained to identify expressive features corresponding to the motion of the object from both the audio and text. In at least one embodiment, the software executed by one or more processors enables the decoding portion of the neural network to be trained to associate features with corresponding keywords from a text prompt (e.g., by associating features of an emotional motion such as surprise with words and / or sounds expressing surprise) by decoding the features identified by the decoder portion. In at least one embodiment, the training enables the neural network to associate specific features of the emotional motion with one or more words, sounds, or motions of one or more objects, such that the words, sounds, or motions can be associated with different motions of an object expressing emotional content.

[0064] In at least one embodiment, a processor includes circuitry for generating, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, a processor includes circuitry for generating, using one or more neural networks, one or more movements of the first portion of the object based at least in part on one or more movements of the second portion of the object and audio corresponding to the one or more movements of the second portion of the object, wherein the audio is based at least in part on one or more textual instructions from one or more users, the textual instructions including content to be expressed as audio and / or motion expressions. In at least one embodiment, a neural network generates 3D images of the same object (e.g., an avatar of a human) in different contexts, wherein the same object is in a different pose, state, or position in each of the images.

[0065] In at least one embodiment, one or more layers of a neural network are trained to identify features of emotions or information content expressions represented in different images and how one or more textual cues correspond to the features. In at least one embodiment, the neural network includes a layer that receives training data, the training data including audio, text, images, and / or video frames corresponding to one or more subjects (e.g., video frames including images and audio of a person speaking) and learns to identify which features of the subjects correspond to expressions of emotions or information content. In at least one embodiment, a self-attention layer that receives a feature map (e.g., a data structure including features identified in one or more input images) generates a new (e.g., updated) feature map that includes weights assigned to features common to identical or repeated features in the input images (e.g., assigning more weight to common features and no weight or reduced weight to other features). In at least one embodiment, for example, in a series of images of a cat meowing, the self-attention layer generates a feature map representing the identified features, the feature map including higher weights for features that identify the movement of the cat's mouth, head, and / or body when meowing.

[0066] In at least one embodiment, the generated feature map including the identified features and weight values is provided as input to another layer of a neural network that identifies image features corresponding to text prompts. In at least one embodiment, the layer receives a feature map (for each input image) and a text prompt corresponding to each feature map (e.g., a feature map corresponding to a man saying "hello world" and making a hand-waving gesture corresponds to a text prompt "man speaking hello world in English"), and then outputs a 3D object that includes feature representations of the feature map corresponding to the features of the text prompt. In at least one embodiment, the layer includes a cross-attention layer that receives the feature map and the text prompt from the self-attention layer as input, and then outputs a data structure that includes representations of the 3D object features and corresponding features representing the text content (e.g., facial expressions and / or actions that convey the emotion or information content associated with the data structure). In at least one embodiment, after generating the data structure, a decoder can be used to decode the features in the data structure to generate an image (in response to receiving the text prompt).

[0067] Figure 1 A system 100 for generating one or more 3D objects from one or more audio and / or text inputs is shown in accordance with at least one embodiment. In at least one embodiment, the system 100 illustrates generating one or more motions of a first portion of an object based at least in part on one or more motions of a second portion of the object and audio corresponding to the one or more motions of the second portion of the object. In at least one embodiment, the system 100 includes one or more inputs, such as text 102 and / or audio 104. In at least one embodiment, the text 102 and / or audio 104 are input to a generative model 106 to obtain an output 108. In at least one embodiment, the output 108 includes one or more 3D objects, such as a character model and / or a representation of a person.

[0068] In at least one embodiment, one or more neural networks use audio 104 and / or text 102 as input to generate a 3D object (e.g., a character model, a representation of a person). In at least one embodiment, text 102 includes a text data string representing utterances (e.g., words and / or sentences) to be spoken by the generated avatar. In at least one embodiment, audio 104 includes speech audio data. In at least one embodiment, a neural network is used to generate a 3D character model based on the text 102 and / or audio 104 input, the model displaying a representation of emotion (e.g., fear, optimism, awe, etc.), personality (e.g., conscientiousness, extroversion, agreeableness, etc.), and / or information content (e.g., facial expressions) corresponding to the audio 104 and / or text 102 input. In at least one embodiment, the neural network uses information contained in the audio 104 and / or text 102 to generate one or more 3D objects that depict and / or express audible speech. In at least one embodiment, a neural network uses information contained in audio 104 and / or text 102 to generate non-audible body language corresponding to one or more informational contents of text 102 , and / or one or more emotional content expressions of audio 104 .

[0069] In at least one embodiment, text 102 is input to a generative model 106. In at least one embodiment, generative model 106 processes text 102 to generate one or more 3D avatars, which can be represented as voices representing one or more aspects of the input text. In at least one embodiment, generative model 106 processes text 102 by providing the text data to one or more speech synthesizers (such as text-to-speech neural networks), which generate audio representing speech data corresponding to the input text. In at least one embodiment, the synthesized audio representing speech can be specified to represent one or more forms of expression, such as speech associated with one or more cultures, emotions, languages, dialects, any combination thereof, and / or any other form of expression. In at least one embodiment, the synthesized speech can be a replica of human speech. In at least one embodiment, the speech can be selected from a set of voice options, and / or the speech data can be provided by one or more users and / or obtained from another source. In at least one embodiment, a microphone can be used to capture the speech of one or more users to generate speech reference data for processing text 102 into speech. In at least one embodiment, previously recorded speech of one or more users may be used as reference data. In at least one embodiment, the reference data may be stored in a memory (e.g., Figures 13 to 21The reference data is stored in an associated memory for access by the generative model 106 during processing of the text 102 into speech. In at least one embodiment, the reference data includes the results of an analysis of speech data, audio features, or audio frequency data representing speech from one or more cultures, people, emotions, any combination thereof, and / or any other characteristics of the reference data described herein.

[0070] In at least one embodiment, the audio 104 includes speech data obtained from one or more audio devices. In at least one embodiment, the audio device includes an audio recording, an analog, a radio, a video, a sound broadcast, speech, music, sound waves, any combination thereof, and / or any other audio device described herein. In at least one embodiment, the audio 104 is input to a generative model 106. In at least one embodiment, the generative model 106 processes the audio 104 to generate an output 108 including one or more 3D objects that express emotional content corresponding to the audio 104. In at least one embodiment, the audio 104 is obtained from one or more users, such as when the user speaks into an audio capture device (such as a microphone).

[0071] In at least one embodiment, the generative model 106 generates a 3D object depicting the motion of one or more parts of the 3D object based at least in part on audio corresponding to the motion of one or more parts of the object (e.g., mouth movement to depict speech and / or hand movement to express gestures). In at least one embodiment, the motion is used to determine one or more communication intentions of other motions of other parts (e.g., limbs) of the object (e.g., hands, arms, etc.). In at least one embodiment, the generative model 106 coordinates the motion (e.g., body language depicted in one or more tensor graphs) with audio and / or text input to generate one or more animations of the 3D object. In at least one embodiment, the generative model 106 includes one or more neural networks. In at least one embodiment, the generative model 106 includes one or more diffusion neural networks that take as input audio such as speech, text strings, and / or a set of 3D joint tensor graphs and depth information.

[0072] In at least one embodiment, audio data containing or representing speech (such as audio 104) can be provided as input to one or more diffuse or generative models, such as a trained neural network of generative model 106. In at least one embodiment, the neural network can be trained to generate two-dimensional or three-dimensional representations of objects, images, and / or videos that speak the speech contained in the corresponding audio data. In at least one embodiment, for a given image or video frame to be generated, generative model 106 infers the shape of the mouth of a person speaking a language corresponding to one or more audio segments. In at least one embodiment, for a given image or video frame to be generated, generative model 106 infers the shape of the mouth of a person speaking a language corresponding to one or more text strings. In at least one embodiment, generative model 106 infers a 3D pose of a full human form that gestures or moves in a manner corresponding to the spoken language and emotional expressions using body parts (e.g., body language) corresponding to the one or more audio segments and / or text strings. In at least one embodiment, generative model 106 receives previously generated facial animations output from one or more other neural networks as conditional input. In at least one embodiment, the facial animation includes a video representing a general model of a speaker with the mouth shape, as well as other posture, style, and / or movement aspects that can be inferred by one or more neural networks. In at least one embodiment, the obtained facial animation model can include any number or type of features that can be used for speech animation, such as features associated with the mouth, eyes, cheeks, etc., but can exclude unnecessary features such as hair, skin texture, color, clothing, etc. In at least one embodiment, the facial animation model includes features that allow for accurate speech animation and enables the neural network to generate a video of a specific person speaking the speech based at least in part on the animation. In at least one embodiment, the facial animation model includes features that are similar to features of the user depicted in the reference image.

[0073] Figure 2An example of a data collection pipeline 200 ("pipeline 200") for training a neural network to generate one or more 3D objects is shown, according to at least one embodiment. In at least one embodiment, pipeline 200 includes video 202. In at least one embodiment, video 202 is video information obtained from one or more video and / or image capture devices. In at least one embodiment, video 202 is processed in multiple pipelines to obtain audio data, text, emotional content, classification, and / or one or more images or a series of image frames, character pose and joint tensor maps, and / or diffusion model output and heat maps. For example, in at least one embodiment, HRNet 220 can use video 202 to generate one or more heat maps 222. In at least one embodiment, video 202 can be used to generate frames 214 for OpenPose 216 to generate one or more joint tensors 218. In at least one embodiment, video 202 can be used to generate audio 204 for ASR model 206 to generate text 208, and classifier 212 can determine and use emotion 210 based on text 208.

[0074] In at least one embodiment, the output of one or more data collection pipelines is input to one or more neural networks and / or machine learning models, such as Audio2Pose 224. In at least one embodiment, one or more neural networks and / or machine learning models, such as Audio2Pose 224, are used to generate one or more 3D objects. In at least one embodiment, the output 226 is a 3D avatar representing a humanoid model speaking one or more languages, the speech conveying informational and emotional content corresponding to one or more text and / or audio inputs, and gesturing one or more actions corresponding to the audio or text, as well as one or more other actions of the object.

[0075] In at least one embodiment, the video 202 includes video frames of various dimensions (e.g., 2D, 3D, 4D, or higher), one or more series of image frames, and audio data corresponding to one or more motions, actions, and / or content of the video data. In at least one embodiment, the video 202 includes one or more frames depicting one or more human figures. In at least one embodiment, the video 202 includes frames depicting people and / or objects speaking in one or more languages. In at least one embodiment, the video 202 includes digitally generated animation paired with speech audio. In at least one embodiment, the speech audio is recorded, synthesized, or otherwise digitally generated, and / or expressed from one or more speakers. In at least one embodiment, the video 202 is processed to extract or otherwise isolate one or more audio streams. In at least one embodiment, the isolated audio stream is audio 204 (e.g., Figure 1Audio 104, Figure 3 Various elements of the audio condition 302, Figure 4 Audio 408A, 408B and 408C and / or Figure 6 In at least one embodiment, the video 202 is processed for input into one or more speech recognition models, such as an ASR model 206. In at least one embodiment, the video 202 is processed to be segmented based on corresponding audio and / or one or more series of image frames.

[0076] In at least one embodiment, video 202 includes one or more image sequences synthesized by a neural network using correlated noise images and text input. In at least one embodiment, the correlated text input is Figure 1 102 of text. In at least one embodiment, a correlated noise image refers to an image that contains noise based on noise from another image. In at least one embodiment, for example, in at least one embodiment, the second correlated noise image has additive noise, where the additive noise is obtained from the first correlated noise image. In at least one embodiment, the first image has noise added based on a Gaussian distribution of noise or some other distribution, and the second image has the same noise added to it, rather than having noise generated independently of the distribution.

[0077] In at least one embodiment, the video data obtained by pipeline 200 comprises the output of one or more neural networks during training. In at least one embodiment, video 202 is generated by transforming a series of correlated noisy images into a corresponding series of denoised video frames. In at least one embodiment, the series of correlated noisy images includes noise based on earlier frames in the sequence. In at least one embodiment, the noise includes additive noise or deviations from the noise in the earlier frames. In at least one embodiment, the correlated noisy images depict one or more objects before noise is added. In at least one embodiment, the correlated noisy images include only or primarily noise. In at least one embodiment, denoising the correlated noisy images results in the generation of a corresponding sequence of video frames. In at least one embodiment, the denoising is subject to one or more conditions, such as conditions associated with the object, object location, object style, lighting effects, speed, direction, etc. In at least one embodiment, the constraints are indicated by textual or visual input. In at least one embodiment, one or more of the factors are also or alternatively included in the input to the system, for example by being depicted in the correlated noisy images before noise is added, or in a separate image. In at least one embodiment, video 202 data is output from one or more video image synthesizers, such as Figure 12C shown.

[0078] In at least one embodiment, audio 204 includes one or more sounds corresponding to one or more expressions. In at least one embodiment, audio 204 includes speech data corresponding to one or more movements of a second portion of one or more objects. In at least one embodiment, audio 204 includes information or emotional content represented by sound and / or speech in one or more frames of video 202. In at least one embodiment, audio 204 includes synthesized and other digitally generated sounds, including speech. In at least one embodiment, a neural network recognizes one or more features of the video data as audio signals. In at least one embodiment, one or more components of the neural network recognize one or more audio streams corresponding to time ranges or time periods. In at least one embodiment, audio 204 includes speech corresponding to one or more movements of a second portion of one or more objects.

[0079] In at least one embodiment, the audio 204 includes music, a personal digital assistant, navigation instructions, news, radio, video sound streams, television, movies, streaming music, telephone audio, hands-free call transmissions, signal streams detectable within the range of human hearing, signal streams not detectable within the range of human hearing, signals of varying frequencies, impact sounds, machine-generated sounds, naturally occurring noises (such as wind, rain, or waves), synthetic noise, white, gray, green, brown, or speckled noise, any combination thereof, or any other sounds described herein.

[0080] In at least one embodiment, natural language processing (such as using a transducer model) identifies tokens from an audio recording and / or text input. In at least one embodiment, the processor performs language processing of one or more audio and / or text inputs using a diffusion model comprising one or more layers. In at least one embodiment, the diffusion model is used in conjunction with other types of speech recognition models (such as ASR model 206). In at least one embodiment, language processing includes processing and analyzing language data (such as Figure 1 In at least one embodiment, the text is obtained by processing the audio to identify text strings. In at least one embodiment, the language processing includes segmenting one or more text inputs and identifying tags for the segments. In at least one embodiment, the processing of the text input uses a neural network (e.g., a diffusion model, an ASR model, etc.) in communication with a processor to generate one or more images, image sequences, and / or 3D objects based at least in part on the processed text and / or audio input.

[0081] In at least one embodiment, the ASR model 206 includes one or more speech recognition models, or recognizes text from audio and / or video data. In at least one embodiment, one or more machine learning models are enabled to generate text from an audio signal. In at least one embodiment, the model includes one or more components for identifying features corresponding to one or more time periods of an audio stream. In at least one embodiment, one or more machine neural networks are enabled to generate text from an audio input. In at least one embodiment, the identified features include one or more text strings corresponding to one or more time periods of the audio stream. In at least one embodiment, the one or more components refer to one or more components of a neural network and / or machine learning model. In at least one embodiment, a component refers to a numerical embedding, a numerical encoding, a latent space representation, an encoder, a decoder, one or more layers of a neural network, one or more artificial neurons in a neural network, a transformer, a convolution, any combination thereof, or a combination thereof Figures 9A to 43 In at least one embodiment, the latent space portion is Figure 5 506. In at least one embodiment, the portion includes code and / or data for computing outputs, such as text 208, to be passed to a subsequent model or neural network. In at least one embodiment, the outputs are computed based on inputs to the portion, such as audio 204 and / or video 202.

[0082] In at least one embodiment, the ASR model 206 processes one or more inputs (such as video 202) to recognize text data. In at least one embodiment, the recognized text data includes one or more text strings, letters, words, sentences, paragraphs, pages, phrases, information content, emotional content, any combination thereof, or any other form of text described herein. In at least one embodiment, the text recognized by the ASR model 206 is processed into text 208. In at least one embodiment, audio 204 is received as input data and processed by the ASR model 206 to recognize text 208. In at least one embodiment, the recognized text data is further processed so that it can be received as input by one or more subsequent models. In at least one embodiment, the text data recognized and processed by the ASR model 206 is passed as input data to emotion 210. In at least one embodiment, one or more neural networks, machine learning models, or portions thereof perform pattern recognition on an audio stream. In at least one embodiment, the audio stream includes audio 204.

[0083] In at least one embodiment, the ASR model 206 and / or one or more components thereof generate attention weights to indicate the importance of one or more features in generating text corresponding to one or more time segments of an audio stream. In at least one embodiment, the generation of attention weights refers to the assignment, representation, modeling, and / or processing of an embedding vector for an audio signal. In at least one embodiment, the embedding vector for the audio signal includes Q, and / or K, and / or V values determined during the embedding calculation. In at least one embodiment, the generation of attention weights is based at least in part on calculations using sine and / or cosine functions performed at different frequencies on the audio signal sequence. In at least one embodiment, the attention weights indicate the importance of one or more portions of the audio stream signal relative to another portion of the audio signal. In at least one embodiment, the encoding process for generating text features from the audio signal uses information from other audio signal portions. In at least one embodiment, such information includes contextual information developed from multiple audio signal portions. In at least one embodiment, the contextual information is used to converge the training cycle.

[0084] In at least one embodiment, the ASR model 206 includes an attention-enhanced convolutional part. In at least one embodiment, the convolutional part is a part of the attention-enhanced deep convolutional network. In at least one embodiment, attention and / or self-attention and / or multi-head attention and / or cross-attention are implemented in one or more of the encoder, decoder and / or transformer to generate text from the audio signal. In at least one embodiment, the ASR model 206 includes a self-attention part. In at least one embodiment, the multi-attention part refers to the part of the ASR model 206 that implements multi-head attention. In at least one embodiment, the cross-attention part refers to the part of the ASR model 206 that implements cross-attention. In at least one embodiment, the multi-attention part is Figure 4 Cross-attention 406A, cross-attention 406B, and cross-attention 406C. In at least one embodiment, one or more components of the ASR model 206 are implemented as a deep convolutional network enhanced with attention to generate text from an audio signal, where the enhanced deep convolutional network consists of a convolutional component and / or a self-attention component. In at least one embodiment, a decoder operates as a transformer as part of the ASR model 206. In at least one embodiment, the decoder portion performs decoding of encoded features. In at least one embodiment, the decoder is used to generate text from the encoding.

[0085] In at least one embodiment, the pre-trained WAV2VEC model uses attention-enhanced convolutional network modules implemented in ASR-related applications, including automatic speech recognition, conversational / multi-speaker ASR, far-field speech processing, speaker and language identification, spoken language understanding, low-resource / multi-language, language processing, spoken document retrieval, speech-to-speech translation, text-to-speech systems, speech summarization, new applications of automatic speech recognition, audio-visual / multimodal speech processing, and / or emotion recognition from speech.

[0086] In at least one embodiment, emotion 210 includes one or more models for extracting emotional content from audio and / or text input. In at least one embodiment, emotion 210 includes one or more neural networks trained to recognize emotions in speech data. In at least one embodiment, emotions include inflection, syntax, words, pauses, rhythm changes, a sequence of words known to convey specific emotional content, punctuation, grammar, or any other audible emotional expression found in speech. In at least one embodiment, emotion 210 includes one or more neural networks trained to recognize features, characters, or tokens in text data that convey emotional content. In at least one embodiment, classifier 212 includes one or more neural networks trained to classify features of text and / or audio data. In at least one embodiment, classifier 212 uses sentiment analysis, a big-5 character classification model to process one or more text and / or audio streams. In at least one embodiment, the text 208 is processed by the emotion 210 and classifier 212 models to identify and tag emotions and character features in the text data for use in subsequent steps to generate one or more 3D objects that depict body language movements corresponding to the emotions and character features.

[0087] In at least one embodiment, frames 214 comprise two-dimensional (2D) images corresponding to one or more frames of video 202. In at least one embodiment, video 202 is processed to separate individual image frames corresponding to one or more time periods. In at least one embodiment, the images depict one or more speakers speaking one or more languages and gesturing one or more actions corresponding to one or more forms of communication. In at least one embodiment, the images depict the positions (e.g., postures) of one or more people, objects, and / or avatars as a freeze-frame capture of a series of movements. In at least one embodiment, the movements comprise one or more movements of an arm or other part (e.g., a limb) of a subject. In at least one embodiment, the movements comprise movement of one or more parts of a subject's face. In at least one embodiment, the movements comprise body language of one or more subjects, the body language corresponding to one or more audio signals and / or one or more text strings. In at least one embodiment, the image data captures the positions of one or more joints in a subject, positioned relative to each other joint in a manner that conveys emotion or informational content.

[0088] In at least one embodiment, OpenPose 216 includes one or more machine learning models for performing multi-person 2D pose estimation. In at least one embodiment, OpenPose 216 obtains image data and processes the image data to identify and / or detect the position of one or more figures, objects, and people in the image. In at least one embodiment, OpenPose 216 detects body position, joint position, limb movement, foot, hand, and facial key points, etc. In at least one embodiment, OpenPose 216 includes one or more machine learning models that are trained to associate one or more body parts with individuals depicted in the image data. In at least one embodiment, OpenPose 216 detects one or more body parts and / or other key points of 2D and / or 3D figures depicted in the image based at least in part on an annotated publicly available dataset. In at least one embodiment, OpenPose 216 is software such as OpenPose, PoseNet, MediaPipe, etc.

[0089] In at least one embodiment, joint tensor 218 comprises a tensor map output by openpose 216. In at least one embodiment, the tensor map represents one or more images or a series of images, mapping the motion of keypoints of one or more objects in the images. In at least one embodiment, a 2D pose image is converted into a 3D pose image using one or more deep learning models. In at least one embodiment, joint tensor 218 is a 2D image converted into a 3D pose tensor map using the deep learning model. In at least one embodiment, HRnet 220 comprises a deep learning model for performing visual recognition tasks for high-resolution representation learning in one or more neural networks. In at least one embodiment, HRnet 220 comprises one or more convolutional neural networks for performing tasks such as semantic segmentation, object detection, and / or image classification. In at least one embodiment, HRnet 220 acquires video 202 and processes the data to generate one or more annotated heatmaps. In at least one embodiment, for each frame of video data, HRnet 220 generates heatmap information for each object depicted in each frame. In at least one embodiment, heat map 222 includes a set of image frames depicting heat map data for each object depicted in input data of video 202. In at least one embodiment, the objects include human figures.

[0090] In at least one embodiment, the Audio2Pose model 224 includes one or more neural networks for generating one or more motions of a first portion of the object based at least in part on one or more motions of a second portion of the object and audio corresponding to the one or more motions of the second portion of the object. In at least one embodiment, one or more conditional diffusion models are used to perform the body pose estimation task to generate one or more 3D body language streams corresponding to one or more audio streams and / or one or more text strings and conditioned at least in part on image frames corresponding to the audio and / or text.

[0091] Figure 3 A system 300 for training a neural network using a conditional diffusion model to generate one or more 3D objects is shown in accordance with at least one embodiment. Figure 1 The system 100 is described Figure 3. In at least one embodiment. In at least one embodiment, the conditional diffusion 330 includes one or more conditional diffusion models 334 and one or more conditional hybrid networks 332 for generating one or more body pose estimates. In at least one embodiment, the body pose estimate includes one or more graphs depicting a set of joints of an object. In at least one embodiment, the body pose estimate includes one or more frames depicting the positions of parts of the object corresponding to a movement. In at least one embodiment, the movement is a body language stream, or other similar physical form that conveys information or emotional content. In at least one embodiment, the body pose estimate is conditioned on the audio condition 302 and the heat map condition 328. In at least one embodiment, one or more conditioned body pose estimates are generated and output by the conditional diffusion 330. In at least one embodiment, the conditioned body pose estimate is depicted in one or more image frames that are attached to or otherwise correspond to one or more audio conditions, so that the generated body language stream can be used downstream by one or more other neural networks and / or models, such as Figure 4 Conditioned pose tensor 412, Figure 2 The audio2pose model 224 and Figure 1 Generative model 106.

[0092] In at least one embodiment, the audio condition 302 includes a quantized model for describing emotions 316 and / or characters 314, a text encoder 304, a step size encoder / embedder 310, and a duration predictor 318. In at least one embodiment, the audio condition 302 includes one or more decoders for decoding the encoded and / or embedded portions generated by the embedder 310. In at least one embodiment, the embedder 310 is a decoder that is configured to decode the encoded and / or embedded portions generated by the embedder 310. Figure 2 The encoder of the ASR model 206. In at least one embodiment, the duration 318 is predicted in the logarithmic domain using the duration extracted from the MFA. In at least one embodiment, the output of the duration 318 is stabilized and optimized to minimize the value of any loss function applied to one or more models.

[0093] In at least one embodiment, one or more text inputs 308 are obtained and encoded into speech by a text encoder 304. In at least one embodiment, the output of the text encoder 304 is used by one or more neural network models to generate audio information corresponding to the speech. In at least one embodiment, the generated audio information is used by subsequent models such as Figure 2In at least one embodiment, pre-trained context and / or classification models (such as emotion 316, character 314, and / or duration 318) may be applied to provide additional context for the speech information generated by the text encoder 304. In at least one embodiment, emotion 316 is Figure 2 The sentiment 210, characters 314 and duration 318 are Figure 2 Part of the classifier 212.

[0094] In at least one embodiment, the text encoder 304 identifies contextual information from phoneme sequences, syllable sequences, sentence fragments, and / or subwords, and then provides the contextual information to the duration 318 and one or more decoders. In at least one embodiment, the text encoder 304 includes one or more neural networks trained to obtain phoneme, syllable, and / or subword data from text input. In at least one embodiment, the text encoder 304 includes a recurrent neural network trained to solve sequence-to-sequence problems. In at least one embodiment, the text encoder 304 includes a pre-network (pre-net) that receives one or more inputs and converts the input text and / or speech into hidden representations for use by one or more transformers. In at least one embodiment, the input is passed from the pre-network to a fully connected (FC) layer via a ReLU activation. In at least one embodiment, the fully connected layer includes one or more neural networks, where each neuron of the neural network applies a linear transformation to the input data using a weight matrix. In at least one embodiment, the text encoder 304 includes N (e.g., 10) residual blocks with dilated convolutions and one or more LSTM (long short-term memory) layers. In at least one embodiment, the residual block comprises one or more cross-connected blocks that learn a residual function corresponding to the layer input. In at least one embodiment, the dilated convolution comprises dilating one or more kernels by inserting holes between kernel elements according to a dilation rate parameter. In at least one embodiment, the kernel is a fixed-size matrix that is convolved on one or more inputs or feature maps to identify information. In at least one embodiment, the dilation of the convolution is predefined from bottom to top (e.g., [1, 2, 4, 1, 2, 4, 1, 2, 4, 1]) and the kernel size is 4, where the ReLU activation function is followed by layer normalization.

[0095] In at least one embodiment, LR 320 includes a length adjuster that controls the length mismatch between phoneme and spectral sequences in the speech output encoded by text encoder 304. In at least one embodiment, text encoder 304 outputs the encoded speech to the length adjuster to match the length of the phoneme, syllable, subword, and / or mel-spectrogram sequences. In at least one embodiment, LR 320 requires alignment information to extend the phoneme sequence and control the speed of the speech encoded by text encoder 304. In at least one embodiment, Montreal Forced Alignment (MFA) is used. In at least one embodiment, attention-based alignment is used.

[0096] In at least one embodiment, the diffusion model 306 includes a decoder and / or a stride encoder. In at least one embodiment, the decoder is configured to predict noise based on a latent space variable conditioned on a phoneme embedding and a diffusion stride embedding. In at least one embodiment, the noise includes Gaussian noise, salt and pepper noise, poison noise, impulse noise, speckle noise, any combination thereof, and / or any other noise described herein. In at least one embodiment, the decoder obtains output from the stride encoder to inform the diffusion time step, so that each diffusion time step has a different output value. In at least one embodiment, the diffusion stride embedding is a sinusoidal embedding with a 128-dimensional encoding vector for each time step. In at least one embodiment, the stride encoder is constructed using two FC layers and / or swish activation. In at least one embodiment, the decoder consists of a stack of 12 residual blocks with different convolutional layers (e.g., Conv1D, tanh, sigmoid, and 1x1) and a 512-dimensional residual channel. In at least one embodiment, the embedded input, the output of LR 320, and the output of text encoder 304 are added to the processing flow of diffusion model 306 after passing through the convolutional layers. In at least one embodiment, the kernel size of the convolutional layer (such as Conv1D) is 3, and there is no dilation. In at least one embodiment, the output from the residual block is processed by the post-net layer and output as output 322. In at least one embodiment, output 322 includes speech data representing the content of human voice communication corresponding to one or more text inputs.

[0097] In at least one embodiment, the audio2face module 324 includes one or more neural networks that are used to generate one or more animated 3D facial models. In at least one embodiment, the audio2face module 324 receives as input speech audio data output as output 322 from the audio conditions 302. In at least one embodiment, the audio2face module 324 generates an animated 3D facial model that speaks the output 322. In at least one embodiment, the audio2face module 324 includes one or more pre-trained deep neural networks. In at least one embodiment, the output of the audio2face module 324 includes a 3D vertex character mesh depicting facial animation.

[0098] In at least one embodiment, heatmap conditioning 328 includes obtaining one or more 3D joint tensor maps and converting the iterative distortion of the joint vector coordinates into a Gaussian distribution. In at least one embodiment, the denoising process is conditioned on a joint-wise heatmap generated by a 2D joint detector. In at least one embodiment, the denoising process is conditioned using an embedding transformer and / or a pose transformer. In at least one embodiment, the 2D joint detector is Figure 2 HRnet 220. In at least one embodiment, the heat map conditions 328 include Figure 4 In at least one embodiment, the heatmap condition 328 accounts for the independent multinomial distribution of detections in the 64×64 grid (e.g., Figure 2 The output dimension of each heat map of HRNet 220 is , and n samples with replacement are drawn for each joint. In at least one embodiment, the sampled 2D poses are normalized so that the generated heat map covers the interval [-1, 1] in both image directions.

[0099] In at least one embodiment, the conditional diffusion 330 adjusts the output of the diffusion model 334 by integrating one or more conditions into the diffusion pattern using an embedding transformer as described in the heat map condition 328. In at least one embodiment, the embedding transformer embeds the vector and position information of each sampled joint into a channel and projects the information onto the output tensor by summing the feasible positions for a joint. In at least one embodiment, the embedding transformer sends the vectors of all joints to a traditional transformer architecture with a multi-head self-attention (MHSA) and a feed-forward network (FFN) module. In at least one embodiment, the MHSA module is Figure 4In at least one embodiment, the heatmap condition 328 conditions the joint tensor input by considering information of individual joints as well as global information between all joint tensor pairs.

[0100] In at least one embodiment, the conditional hybrid network 334 combines all three conditions using a combining network such as a transformer. In at least one embodiment, the conditional hybrid network 334 utilizes cross-attention so that each condition can be independently integrated with the 3D object generation flow to select only the parts of the condition that are important for generating the 3D object.

[0101] In at least one embodiment, conditional diffusion 330 comprises a conditional diffusion model that receives a set of well-formed joint tensors Figure X 0, and output a set of diffuse joint tensor maps X T , thereby perturbing the tensors for each joint in the output. In at least one embodiment, each step of the diffusion process during training and each step of the reconstruction during inference is regulated by preset constraint values to constrain the target body posture, the position of each joint, and / or the relationship between each joint. In at least one embodiment, the generated 3D object depicts the emotion and character corresponding to the audio and / or text communication target. In at least one embodiment, the audio condition 302 includes a text-to-speech diffusion model 306. In at least one embodiment, the diffusion model 306 is Figure 5 One or more parts of the diffusion process described in the latent space 506.

[0102] Figure 4 An example of a conditional mixture network 400 with a cross-attention mechanism according to at least one embodiment is shown. In at least one embodiment, the conditional mixture network 400 comprises a simplified conditional mixture network that includes one or more diffusion models. In at least one embodiment, the conditional mixture network 400 is Figure 2 Conditional hybrid network 332. In at least one embodiment, conditional hybrid network 400 depicts Figure 3In at least one embodiment, only audio conditioning data is retained and facial or heatmap based information is ignored, thereby generalizing one or more neural network models and making them scalable in situations where predefined conditions are incomplete. In at least one embodiment, the conditional hybrid network 400 is used to generate one or more motions of a first portion of an object based at least in part on one or more motions of a second portion of the object and audio corresponding to the one or more motions of the second portion of the object. In at least one embodiment, the 3D object depicts a realistic and accurate 3D human pose that expresses body language. In at least one embodiment, the 3D object approximates a complete posterior distribution of a human form.

[0103] In at least one embodiment, the blurring caused by information loss when projecting 2D data onto the 3D image plane is compensated for by adjusting one or more diffusion models on the 2D detections. In at least one embodiment, the conditional hybrid network 400 includes iteratively distorting one or more vectors containing 3D joint coordinates into a Gaussian distribution N(0, I). In at least one embodiment, an embedding transformer (such as Figure 3 heatmap condition 328) to be embedded in a 2D joint detector (such as Figure 2 The denoising process is conditioned on the joint-by-joint heatmap generated by HRNet 220.

[0104] In at least one embodiment, the conditional hybrid network 400 includes a forward process that iteratively adds Gaussian noise of a predefined mean and variance to the original data to distort the data. In at least one embodiment, the forward process is a Markov chain. In at least one embodiment, the conditional hybrid network 400 includes an inverse process performed by one or more neural networks on progressively degraded versions. In at least one embodiment, one or more diffusions of the process are performed by the following Algorithm 1:

[0105] Algorithm 1: DDPM training algorithm for human pose estimation

[0106] 1. Given: x text (input text sentence), x image (2D image / frame, optional), x face (2D face / frame, optional), y (body language in human pose), ε HRNet (HRNet), ε embed (embedded transformer), ε ViT Pre-trained visual image transformer for encoding and representing facial frames, ε y Trainable Human Pose Embedding Network (to Low-Dimensional Projection)

[0107] 2. Text-to-speech from text to audio via pre-trained TTS models

[0108] 3. Encoding and labeling through pre-trained HRNet model

[0109] 4. Encoding facial frames using a pre-trained visual image transformer model

[0110] 5. Low-dimensional projection based on trainable human pose embedding network

[0111] 6. Random sampling time t

[0112] 7. Gaussian noise

[0113] 8. Adding noise information for diffusion

[0114] 9. Go forward, given y0 and three conditions

[0115] 10.

[0116] Where: x text (input text sentence), x image (2D image / frame), x face (2D face / frame), y (body language in human pose), ε HRNet (HRNet),ε embed (embedded converter), ε ViT (a pre-trained visual image transformer for encoding and representing facial frames), and / or ε y (Trainable Human Pose Embedding Network to Low-Dimensional Projections).

[0117] In at least one embodiment, Algorithm 1 provides a one-step stream training process for training one or more neural networks to generate one or more motions of a first portion of an object based at least in part on one or more motions of a second portion of the object and audio corresponding to the one or more motions of the second portion of the object.

[0118] In at least one embodiment, the diffused pose tensor 402 includes one or more well-formed poses based on at least a portion of a human body position depicted in the image data. In at least one embodiment, the target human pose tensor expresses body language and / or other forms of emotional content and is projected into a low-dimensional tensor to accelerate the diffusion and reconstruction process.

[0119] In at least one embodiment, conditions 404A, 404B, and 404C respectively include three preconditions of the central diffusion network, namely, the audio tensor, the heat map tensor, and the facial information tensor. In at least one embodiment, each of conditions 404A, 404B, and 404C is interpolated by a trainable conditional mixture network to integrate the given conditions, thereby guiding the diffusion and reconstruction process of the human body posture. In at least one embodiment, the trainable network is Figure 3 Conditional hybrid network 330.

[0120] In at least one embodiment, cross-attention 406A, cross-attention 406B, and cross-attention 406C comprise independently trainable U-Nets with cross-attention, where the conditions act as memories (e.g., keys and values in the cross-attention). In at least one embodiment, the audio 408A, audio 408B, and audio 408C outputs of cross-attention 406A, cross-attention 406B, and cross-attention 406C are stitched together at stitching 410 to output a conditioned pose tensor 412. In at least one embodiment, the conditioned pose tensor 412 comprises one or more well-formed poses depicting joint vectors and points of a humanoid conditioned based on conditions 404A, 404B, and 404C.

[0121] Figure 5 FIG2 is an example of a diffusion model architecture 500 for generating one or more 3D objects based on at least one part, audio, and / or text input, in accordance with at least one embodiment. In at least one embodiment, diffusion model 502 includes an image space 516, a latent space 506, and conditions 508, wherein image space 516 includes a pose input 504 and a model output 514, latent space 506 includes one or more diffusions processed using one or more denoising U-Nets 512, and conditions 508 include one or more conditional hybrid networks 510.

[0122] In at least one embodiment, the denoising U-Net 512 includes one or more neural networks for performing semantic level segmentation of images with depth information. In at least one embodiment, the denoising U-net includes one or more cross-attention layers (QKV), a concatenation step, a skip connection, and a denoising step. In at least one embodiment, the denoising U-Net 512 is Figure 4 In at least one embodiment, the cross attention layer is combined with Figure 2 The ASR model 206 depicts the cross attention layer. In at least one embodiment, the skip connection and denoising steps are combined Figure 3The steps described in the conditional hybrid network 334 are as follows.

[0123] In at least one embodiment, a well-formed pose, such as pose input 504, is obtained from image space 516 as input to latent space 506. In at least one embodiment, latent space 506 is a combination of Figure 3 In at least one embodiment, the gesture input 504 includes a well-formed stream of gestures that are independent of each other. In at least one embodiment, the gesture input 504 is time-sensitive, wherein one or more autoregressive models are used to account for temporal dependency information. In at least one embodiment, the autoregressive models include Figure 3 Diffusion model 334, Figure 2 at least a portion of the audio2pose model 224 and Figure 1 One or more of the parts of the generative model 106 .

[0124] In at least one embodiment, input gesture 504 is combined with Figure 3 The diffusion pattern 330 describes one or more well-formed gestures, and / or Figure 4 conditioned pose tensor 412. In at least one embodiment, the image space 516 comprises one or more generated 2D or 3D images, 2D or 3D video frames, or other spaces comprising image and / or video data as described herein. In at least one embodiment, one or more cross-attention layers receive input conditions as memories and / or keys and pass potential representations of the images and / or generated poses as one or more queries.

[0125] In at least one embodiment, the condition 508 includes one or more conditional hybrid networks 510. In at least one embodiment, the condition 508 is Figure 3 In at least one embodiment, the conditional hybrid network 510 performs at least a portion of the diffusion process, acts as a time-sensitive conditional memory, and manages the multimodal conditions of audio, text, emotion labels, and feature scores used to generate one or more 3D objects depicting spoken language and body language. In at least one embodiment, the conditional hybrid network 510 is Figure 3 Conditional hybrid network 332.

[0126] In at least one embodiment, the diffusion model 502 includes one or more autoregressive diffusion models that generate diffusion data over multiple time steps in a diffusion process. In at least one embodiment, the diffusion process includes iteratively applying a series of diffusion steps, wherein in each diffusion step, the diffusion model 502 adjusts the generation of the immediately following data point on the previously generated data point. In at least one embodiment, the diffusion model 502 generates a 3D object pose (such as a human pose frame point) condition based at least in part on a previous human pose frame point. In at least one embodiment, the diffusion model 502 uses a transformer-based architecture. In at least one embodiment, the diffusion model 502 processes previously generated data points (e.g., human pose frame points) and predicts a conditional distribution of the immediately following data point given the conditional data. In at least one embodiment, the diffusion model 502 uses masked self-attention and / or masked convolution to ensure that the 3D object generated as a result of the diffusion process follows a causal ordering principle.

[0127] In at least one embodiment, the diffusion model 502 is trained to maximize the likelihood of generating high-quality ground-truth data given a set of conditions. In at least one embodiment, the training involves iteratively estimating the posterior distribution over the missing information at each diffusion step. In at least one embodiment, the training is complete once the diffusion model 502 can iteratively generate the missing portion of the data by sampling from the conditional distribution predicted by the autoregressive model with pre-given time-sensitive conditions. In at least one embodiment, the conditions are a combination of Figures 1 to 4 Audio, text, sentiment tags, and feature tags for descriptions.

[0128] Figure 6 is a flow chart illustrating a method 600 for generating updated posture information according to at least one embodiment. In at least one embodiment, the method 600 includes, at block 602, accessing input information. For example, in at least one embodiment, the input information includes Figure 1 The audio 104 and / or text 102 of the first portion of the object are used as input to one or more neural networks for generating one or more movements of the first portion of the object based at least in part on the one or more movements of the second portion of the object and audio corresponding to the one or more movements of the second portion of the object.

[0129] In at least one embodiment, each block of the method 600 described herein comprises a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, in at least one embodiment, various functions can be implemented by a processor executing instructions stored in a memory. In at least one embodiment, the method 600 can also be embodied as computer-usable instructions stored on a computer storage medium. In at least one embodiment, the method 600 can be provided by a standalone application, a service, or a hosted service (standalone or in combination with another hosted service), or a plug-in to another product, to name a few. Furthermore, in at least one embodiment, by way of example, reference is made to Figure 1 Method 600 is described with reference to system 100. In at least one embodiment, these methods may additionally or alternatively be performed by any one system or any combination of systems, including but not limited to those described herein.

[0130] In at least one embodiment, method 600 includes, at block 604, adjusting one or more audio and / or text inputs corresponding to one or more 3D object generation streams. In at least one embodiment, for example, Figure 3 The audio condition 302, heat map condition 328 and conditional diffusion 330 regulate one or more inputs and outputs corresponding to a first part and a second part, the first part including one or more limbs of the object (e.g., arms, legs, etc.) and the second part including one or more parts of the object's face.

[0131] In at least one embodiment, method 600 includes, at block 606, generating one or more poses of one or more 3D objects. In at least one embodiment, for example, Figure 1 The generative model 106 includes one or more circuits for using one or more neural networks to generate one or more movements of a first portion of an object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, the one or more neural networks include a second portion for generating the one or more movements of the second portion of the object based at least in part on the audio, and a first portion for generating the one or more movements of the first portion of the object. In at least one embodiment, the one or more movements of the second portion indicate body language of the one or more objects. In at least one embodiment, the 3D object includes an avatar of a person. In at least one embodiment, after block 606, method 600 may terminate.

[0132] Figure 7 FIG2 shows an example of a processor 700 according to at least one embodiment. In at least one embodiment, the processor 705 performs one or more processes, such as referring to FIG2 . Figures 1 to 6 The process of generating one or more second masks to modify one or more second portions of the neural network based at least in part on one or more first masks of one or more first portions of the neural network, wherein the one or more second portions of the neural network are dependent on the one or more first portions of the neural network. In at least one embodiment, the processor 705 performs operations to identify dependencies between the one or more first portions of the neural network and the one or more second portions of the neural network; identify neuron dimensions of the one or more first masks; and identify neuron dimensions of the one or more second masks using the neuron dimensions of the one or more first masks.

[0133] In at least one embodiment, processor 705 includes one or more processors, such as a processor in conjunction with Figures 17A to 29 processor described. In at least one embodiment, the processor 700 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor 705 includes one or more software programs 710, input modules 720, propagation modules 730, relationship modules 740, dependency modules 750, and / or pruning modules 760. In at least one embodiment, the software programs 710, input modules 720, propagation modules 730, relationship modules 740, dependency modules 750, pruning modules 760, and / or code generation modules 770 are or are part of one or more other processors. In at least one embodiment, the software programs 710, input modules 720, propagation modules 730, relationship modules 740, dependency modules 750, pruning modules 760, and / or code generation modules 770 are distributed among multiple processors that communicate via a bus, a network, by writing to a shared memory, or any suitable communication process, for example, with reference to FIG. Figures 17A to 29 Describe the process.

[0134] In at least one embodiment, software program 710 includes one or more software programs (e.g., functions, kernels, etc.) for generating and / or modifying one or more portions of one or more neural networks, such as Figures 1 to 6 shown.

[0135] In at least one embodiment, input module 720 includes circuitry that enables one or more input masks and / or tensors to be accessed, e.g., Figures 1 to 6 shown.

[0136] In at least one embodiment, propagation module 730 includes circuitry that causes one or more changes in a first portion of a neural network to propagate to one or more other portions of the neural network, e.g., Figures 1 to 6 shown.

[0137] In at least one embodiment, relationship module 740 includes circuitry that causes one or more relationships between portions of a neural network to be indicated, e.g., as Figures 1 to 6 shown.

[0138] In at least one embodiment, dependency module 750 includes circuitry that enables dependencies of one or more masks of a neural network to be identified, e.g., Figures 1 to 6 shown.

[0139] In at least one embodiment, pruning module 760 includes circuitry that causes one or more neurons of one or more neural networks to be pruned, e.g., Figures 1 to 6 shown.

[0140] In at least one embodiment, the code generation module 770 includes circuitry that causes one or more neurons of one or more neural networks to generate code, e.g., Figures 1 to 6 shown.

[0141] Figure 8 A driver and / or runtime 800 is shown according to at least one embodiment, which includes one or more libraries to provide one or more application programming interfaces (APIs). In at least one embodiment, the software program 802 is a software module. In at least one embodiment, the software program 802 includes Figures 1 to 7 In at least one embodiment, the software program 802 includes one or more software modules. In at least one embodiment, the one or more software modules are as follows: Figure 8802. In at least one embodiment, the one or more APIs 810 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, the one or more APIs 810 are distributed or otherwise provided as part of one or more libraries 806, runtimes 804, drivers 804, and / or any other software and / or executable code groups further described herein. In at least one embodiment, the one or more APIs 810 perform one or more computing operations in response to a call from a software program 802. In at least one embodiment, the software program 802 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets (such as APIs 810 or API functions 812) for execution. In at least one embodiment, the functionality provided by the one or more APIs 810 includes software functions 812, such as software functions that can be used to accelerate one or more portions of the software program 802 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, the software program is a compiler. Figures 1 to 7 Further non-exclusively shown in.

[0142] In at least one embodiment, the API 810 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 810 described herein are implemented as one or more circuits to perform the following operations in conjunction with Figures 1 to 8 In at least one embodiment, one or more software programs 802 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the following combined Figures 1 to 7 One or more techniques further described.

[0143] In at least one embodiment, a software program 802, such as a user-implemented software program, utilizes one or more application programming interfaces (APIs) 810 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, the one or more APIs 810 provide a set of callable functions 812, referred to herein as APIs, API functions, and / or functions, that each perform one or more computational operations, such as computational operations related to parallel computing. For example, in one embodiment, the one or more APIs 810 provide functions 812 to enable an image generator 816 to use Figures 1 to 8The systems, methods, and other components disclosed in the disclosure generate multiple images that include the same object in different backgrounds.

[0144] In at least one embodiment, one or more software programs 802 interact or otherwise communicate with one or more APIs 810 to perform one or more computing operations using one or more PPUs (such as GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations that are accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 802 interact with the one or more APIs 810 to facilitate parallel computing using remote or local interfaces.

[0145] In at least one embodiment, the interface is software instructions that, when executed, provide access to one or more functions 812 provided by the one or more APIs 810. In at least one embodiment, the software programs 802 use native interfaces when a software developer compiles the one or more software programs 802 in conjunction with one or more libraries 806 that include or otherwise provide access to the one or more APIs 810. In at least one embodiment, the one or more software programs 802 are statically compiled in conjunction with precompiled libraries 806 or uncompiled source code that includes instructions to implement the one or more APIs 810. In at least one embodiment, the one or more software programs 802 are dynamically compiled and linked to the one or more precompiled libraries 806 that include the one or more APIs 810 using a linker.

[0146] In at least one embodiment, a software program 802 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 806 including one or more APIs 810 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 806 including the one or more APIs 810 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 806 including the one or more APIs 810 are executed by any other computing host that provides the one or more APIs 810 to the one or more software programs 802.

[0147] In at least one embodiment, a processor executing or using one or more software programs 802 calls, uses, executes, or otherwise implements one or more APIs 810 to allocate or otherwise manage memory to be used by the software programs 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 to allocate and otherwise manage memory to be used by one or more portions of the software programs 802 for acceleration using one or more PPUs (such as GPUs or any other accelerators or processors described further herein). These software programs 802 can be executed by one or more processors using functions 812, which in one embodiment are provided by one or more APIs 810, based at least in part on the latency of an interconnect coupling the one or more processors.

[0148] In at least one embodiment, API 810 is an API that facilitates parallel computing. In at least one embodiment, API 810 is any other API described further herein. In at least one embodiment, API 810 is provided by a driver and / or runtime 804. In at least one embodiment, API 810 is provided by a CUDA user-mode driver. In at least one embodiment, API 810 is provided by a CUDA runtime. In at least one embodiment, driver 804 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 812 of API 810 during the loading and execution of one or more portions of software program 802. In at least one embodiment, runtime 804 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 812 of API 810 during the execution of software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 implemented or otherwise provided by a driver and / or runtime 804 to perform combined arithmetic operations by the one or more software programs 802 during execution by one or more PPUs, such as a GPU.

[0149] In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to perform combined arithmetic operations for one or more PPUs (such as GPUs). In at least one embodiment, the one or more APIs 810 provide combined arithmetic operations through the driver and / or runtime 804, as described above. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve one or more blocks of memory 814 for one or more PPUs (such as GPUs). In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve blocks of memory. In at least one embodiment, the one or more APIs 810 are used to perform operations as described below in conjunction with any Figures 1 to 8 The combinatorial arithmetic operations described.

[0150] In at least one embodiment, to improve the usability of the software program 802 and / or optimize one or more portions of the software program 802 to be accelerated by one or more PPUs (such as GPUs), in at least one embodiment, one or more APIs 810 provide one or more API functions 812 to perform the operations described above and in conjunction with the operations described below. Figures 1 to 8 Further described is a scheduling system that can be used or usable by one or more computing devices. In at least one embodiment, exemplary block diagram 800 depicts a processor that includes one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 800 depicts a system that includes one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses the API to cause a scheduler to select a thread selection mechanism and / or otherwise perform the operations described herein. In at least one embodiment, exemplary block diagram 800 shows that the API calls one or more modules (e.g., modules 803-806) to generate one or more objects in two or more different images based at least in part on one or more instructions from one or more users, the one or more instructions indicating the content of at least one of the two or more different images other than the one or more objects.

[0151] In at least one embodiment, a processor uses the exemplary API to schedule one or more instructions to be executed by one or more processors based at least in part on the latency of one or more interconnects coupled to the one or more processors. Figures 9A to 43 The components, methods and / or systems described herein are as follows Figures 1 to 8 Further non-exclusively shown.

[0152] Those skilled in the art will appreciate from this disclosure that certain embodiments may be able to achieve certain advantages, including some or all of the following advantages: Improved computing fields and job scheduler systems for distributing jobs across a cluster of nodes. Thus, according to the embodiments disclosed above, one or more processors use one or more neural networks to recognize a subject of one or more inputs, where the input can be text, an image, or a combination of text and an image, and generate one or more output images that include the subject of the input as a foreground image and one or more background elements described by one or more cues.

[0153] logic

[0154] Figure 9A Logic 915 is shown according to at least one embodiment, such as described elsewhere herein, which can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is reasoning and / or training logic. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic used to provide the functions or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU)).

[0155] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0156] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 901 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 901 is internal or external to a processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0157] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 905 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 905 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0158] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 905 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 905 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip or off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0159] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0160] In at least one embodiment, logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values from a layer or neuron within a neural network) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, the activations stored in activation storage 920 are generated based on linear algebra and / or matrix-based math performed by ALU 910 in response to executing instructions or other code, with weight values stored in code and / or data storage 905 and / or code and / or data storage 901 used as operands, as well as other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip storage.

[0161] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 910 may be included within an execution unit of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0162] In at least one embodiment, activation storage 920 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 920 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0163] In at least one embodiment, Figure 9A The logic 915 shown in FIG may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9A The illustrated logic 915 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0164] In at least one embodiment, utilizing Figure 9A At least one component shown or described is implemented in conjunction with Figures 1 to 8 In at least one embodiment, Figure 9A At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 9A At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8The driver and / or runtime 800 describes at least one aspect.

[0165] Figure 9B Logic 915 is shown in accordance with at least one embodiment. In at least one embodiment, logic 915 is inference and / or training logic. In at least one embodiment, logic 915 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B The logic 915 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9B The logic 915 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown in FIG, code and / or data storage 901 and code and / or data storage 905 are each associated with dedicated computing resources, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, computing hardware 902 and computing hardware 906 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results being stored in activation storage 920.

[0166] In at least one embodiment, each of the code and / or data stores 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 901 / 902 of the code and / or data store 901 and computing hardware 902 are provided as inputs to the next storage / computation pair 905 / 906 of the code and / or data store 905 and computing hardware 906, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0167] In at least one embodiment, utilizing Figure 9B At least one component shown or described is implemented in conjunction with Figures 1 to 8 In at least one embodiment, Figure 9B At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 9B At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0168] Neural network training and deployment

[0169] Figure 10The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0170] In at least one embodiment, untrained neural network 1006 is trained using supervised learning, where training dataset 1002 includes inputs paired with expected outputs for the inputs, or where training dataset 1002 includes inputs with known outputs and the outputs of neural network 1006 are manually graded. In at least one embodiment, untrained neural network 1006 is trained in a supervised manner, processing inputs from training dataset 1002 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 1006. In at least one embodiment, training framework 1004 adjusts the weights that control untrained neural network 1006. In at least one embodiment, training framework 1004 includes tools for monitoring the degree to which untrained neural network 1006 converges toward a model (such as trained neural network 1008) suitable for generating correct answers (such as results 1014) based on input data (such as new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0171] In at least one embodiment, untrained neural network 1006 is trained using unsupervised learning, wherein untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1006 can learn groupings within training dataset 1002 and can determine how individual inputs relate to untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1008 that can perform operations useful for reducing the dimensionality of new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1012 that deviate from the normal pattern of new dataset 1012.

[0172] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to new datasets 1012 without forgetting the knowledge that was infused into the trained neural network 1008 during initial training.

[0173] In at least one embodiment, the training framework 1004 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0174] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0175] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or their variants.

[0176] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variants thereof.

[0177] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0178] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0179] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0180] In at least one embodiment, utilizing Figure 10 At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 10 At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 10 At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0181] Data Center

[0182] Figure 11 An example data center 1100 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0183] In at least one embodiment, Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources ("node CRs") 1116(1)-1116(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1116(1)-1116(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1116(1)-1116(N) may be a server having one or more of the above-mentioned computing resources.

[0184] In at least one embodiment, the grouped computing resources 1114 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in a number of racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0185] In at least one embodiment, resource coordinator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may comprise a software design infrastructure ("SDI") management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may comprise hardware, software, or some combination thereof.

[0186] In at least one embodiment, Figure 11 As shown, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, the framework layer 1120 may include a framework that supports software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1128 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1122 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 1100. In at least one embodiment, the configuration manager 1124 may be capable of configuring different layers, such as the software layer 1130 and the framework layer 1120 including Spark and a distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, the resource manager 1126 may be capable of managing the mapping or allocation of clustered or grouped computing resources to support the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 at the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0187] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least portions of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0188] In at least one embodiment, the one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least portions of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0189] In at least one embodiment, any of configuration manager 1124, resource manager 1126, and resource coordinator 1112 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1100 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0190] In at least one embodiment, data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, the resources described above with respect to data center 1100 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks using weight parameters calculated using one or more training techniques described herein.

[0191] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0192] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in data center 1100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0193] In at least one embodiment, utilizing Figure 11 At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 11 At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 11 At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0194] autonomous vehicles

[0195] Figure 12AAn example of an autonomous vehicle 1200 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1200 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0196] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of the standards). In at least one embodiment, the vehicle 1200 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0197] In at least one embodiment, the vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1250 may be connected to a drive train of the vehicle 1200, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 1200. In at least one embodiment, the propulsion system 1250 may be controlled in response to a signal received from a throttle / accelerator 1252.

[0198] In at least one embodiment, when propulsion system 1250 is operating (e.g., when vehicle 1200 is in motion), a steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive signals from steering actuator 1256. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1246 may be used to operate vehicle brakes in response to signals received from brake actuator 1248 and / or brake sensors.

[0199] In at least one embodiment, one or more controllers 1236, which may include but are not limited to one or more system on a chip ("SoC") ( Figure 12A ) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, one or more controllers 1236 can send signals to operate vehicle brakes via brake actuator 1248, operate steering system 1254 via one or more steering actuators 1256, and operate propulsion system 1250 via one or more throttle / accelerator 1252. In at least one embodiment, one or more controllers 1236 can include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1200. In at least one embodiment, one or more controllers 1236 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0200] In at least one embodiment, the one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1258 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 12A Not shown), mid-range camera ( Figure 12A ), one or more speed sensors 1244 (e.g., for measuring the speed of the vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of a brake sensor system 1246), and / or other sensor types.

[0201] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from a dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1234, an audible annunciator, a speaker, and / or via other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 12A ), location data (e.g., the location of the vehicle 1200, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1236, etc. For example, in at least one embodiment, the HMI display 1234 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0202] In at least one embodiment, the vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, the network interface 1224 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1226 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, and the like protocols).

[0203] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in vehicle 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0204] In at least one embodiment, utilizing Figure 12A At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 12A At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 12A At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0205] Figure 12B According to at least one embodiment, Figure 12A 1200. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1200.

[0206] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1200. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a transparent pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0207] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0208] In at least one embodiment, the one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1200 (e.g., reflected light from the dashboard reflecting in the windshield mirror), which may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, the one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0209] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1200 can be used for surround vision to help identify the path ahead and obstacles, as well as to assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1236 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0210] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 12B Only one wide-angle camera 1270 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1200. In at least one embodiment, any number of remote cameras 1298 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1298 can also be used for object detection and classification and basic object tracking.

[0211] In at least one embodiment, any number of stereo cameras 1268 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1200's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1200 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to or in place of those described herein.

[0212] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1200 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1274 (e.g., Figure 12B The four surround cameras shown (four surround cameras) can be positioned on the vehicle 1200. In at least one embodiment, the one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0213] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1200 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0214] In at least one embodiment, utilizing Figure 12B At least one component shown or described is implemented in conjunction with Figures 1 to 8 In at least one embodiment, Figure 12B At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 12B At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0215] Figure 12C is a diagram illustrating a method according to at least one embodiment Figure 12A A block diagram of an example system architecture for an autonomous vehicle 1200 is provided. In at least one embodiment, Figure 12C Each of the components, features, and systems of vehicle 1200 is shown as being connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN can be a network internal to vehicle 1200 that assists in controlling various features and functions of vehicle 1200, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, bus 1202 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1202 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1202 can be an ASIL B compliant CAN bus.

[0216] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1202, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1202 may communicate with any component of vehicle 1200, and two or more buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1200) and can be connected to a common bus, such as a CAN bus.

[0217] In at least one embodiment, the vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Figure 12A In at least one embodiment, the controller 1236 can be used for a variety of functions. In at least one embodiment, the controller 1236 can be coupled to any of the various other components and systems of the vehicle 1200 and can be used to control the vehicle 1200, the artificial intelligence of the vehicle 1200, the infotainment and / or other functions of the vehicle 1200.

[0218] In at least one embodiment, the vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit ("CPU(s)") 1206, a graphics processing unit ("GPU(s")) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1204 may be used to control the vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1204 may be combined in a system (e.g., a system of the vehicle 1200) along with a high-definition ("HD") map 1222 that may be downloaded from one or more servers (e.g., a system of the vehicle 1200) via a network interface 1224. Figure 12C ) to obtain map refreshes and / or updates.

[0219] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1206 may be active at any given time.

[0220] In at least one embodiment, one or more CPUs 1206 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0221] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may utilize an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may utilize one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0222] In at least one embodiment, one or more GPUs 1208 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1208 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0223] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0224] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1208 to directly access one or more CPU 1206 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, two of the one or more CPUs 1206 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1206 and the one or more GPUs 1208, thereby simplifying programming the one or more GPUs 1208 and porting applications to the one or more GPUs 1208.

[0225] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that can track the frequency with which one or more GPUs 1208 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0226] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1206 and one or more GPUs 1208. In at least one embodiment, one or more caches 1212 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0227] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks of one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0228] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and often significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0229] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer can target any function to one or more DLAs or one or more GPUs 1208. For example, in at least one embodiment, a designer can centralize CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0230] In at least one embodiment, one or more accelerators 1214 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1238, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0231] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0232] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1206. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0233] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0234] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0235] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that are accessible to both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using the APB). In at least one embodiment, the on-chip computer vision network may include an interface that ensures that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface can provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface can comply with the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61508 standard, although other standards and protocols can be used.

[0236] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0237] In at least one embodiment, one or more accelerators 1214 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithmic domain that requires predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1200, the PVA may be designed to run classic computer vision algorithms because it can be efficient at object detection and integer math operations.

[0238] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0239] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0240] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1266 associated with vehicle 1200 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0241] In at least one embodiment, one or more SoCs 1204 may include one or more data stores 1216 (e.g., memory). In at least one embodiment, one or more data stores 1216 may be on-chip memory of one or more SoCs 1204 that may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data stores 1216 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, one or more data stores 1216 may include one or more L2 or L3 caches.

[0242] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1204 thermal and temperature sensors, and / or manage one or more SoCs 1204 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1204 into a lower power state and / or place the vehicle 1200 into a driver's safe parking mode (e.g., bringing the vehicle 1200 to a safe stop).

[0243] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that can function as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0244] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0245] In at least one embodiment, one or more processors 1210 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0246] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1204, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0247] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0248] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1208 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1208 to improve performance and responsiveness.

[0249] In at least one embodiment, one or more of the SoCs 1204 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0250] In at least one embodiment, one or more of the SoCs 1204 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1204 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via an Ethernet channel), data from the bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1204 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1206 from routine data management tasks.

[0251] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data stores 1216, can provide a fast, efficient platform for level 3-5 autonomous vehicles.

[0252] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0253] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0254] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1208.

[0255] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0256] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0257] In at least one embodiment, the vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1218 may include, for example, an X86 processor. The one or more CPUs 1218 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or an infotainment system on a chip ("infotainment SoC") 1230. In at least one embodiment, the SoC 1204 includes one or more interconnects, and the interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0258] In at least one embodiment, the vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1220 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1200 (e.g., sensor data).

[0259] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1200). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1200.

[0260] In at least one embodiment, the network interface 1224 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, the network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0261] In at least one embodiment, the vehicle 1200 may further include one or more data stores 1228, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1204) storage. In at least one embodiment, the one or more data stores 1228 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0262] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0263] In at least one embodiment, the vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, the one or more RADAR sensors 1260 may be used by the vehicle 1200 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1260 may use a CAN bus and / or bus 1202 (e.g., for transmitting data generated by the one or more RADAR sensors 1260) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1260 are pulsed Doppler RADAR sensors.

[0264] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between static objects and moving objects and can be used by the ADAS system 1238 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surroundings of the vehicle 1200 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1200 .

[0265] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0266] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262, which may be positioned at the front, rear, and / or side of the vehicle 1200, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 may operate at an ASIL B functional safety level.

[0267] In at least one embodiment, the vehicle 1200 can include one or more LIDAR sensors 1264. In at least one embodiment, the one or more LIDAR sensors 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1264 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1200 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0268] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support 100 Mbps Ethernet connectivity. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1264 may comprise small devices that can be embedded in the front, rear, sides, and / or corners of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1264 may be configured for a horizontal field of view between 45 and 135 degrees.

[0269] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0270] In at least one embodiment, the vehicle 1200 may also include one or more IMU sensors 1266. In at least one embodiment, the one or more IMU sensors 1266 may be located at the center of the rear axle of the vehicle 1200. In at least one embodiment, the one or more IMU sensors 1266 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1266 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1266 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0271] In at least one embodiment, the one or more IMU sensors 1266 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the one or more IMU sensors 1266 can enable the vehicle 1200 to estimate its heading by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1266, without the need for input from a magnetic sensor. In at least one embodiment, the one or more IMU sensors 1266 and the one or more GNSS sensors 1258 can be combined in a single integrated unit.

[0272] In at least one embodiment, the vehicle 1200 can include one or more microphones 1296 positioned within and / or around the vehicle 1200. In at least one embodiment, the one or more microphones 1296 can be used for emergency vehicle detection and identification.

[0273] In at least one embodiment, the vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long range cameras 1298, one or more mid range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1200. In at least one embodiment, the type of camera used depends on the vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1200. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the various embodiments of the present invention. Figure 12A and Figure 12B Each camera is described in more detail.

[0274] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, one or more vibration sensors 1242 may measure vibration of a component (e.g., an axle) of vehicle 1200. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0275] In at least one embodiment, the vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0276] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1200 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0277] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1224 and / or one or more wireless antennas 1226. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1200 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of vehicle 1200, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0278] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0279] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0280] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1200 crosses a lane marking. In at least one embodiment, the LDW system is deactivated when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1200 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1200.

[0281] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0282] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1200 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0283] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1200 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0284] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0285] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1204.

[0286] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0287] In at least one embodiment, the output of the ADAS system 1238 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0288] In at least one embodiment, the vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1200. For example, the infotainment SoC 1230 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1200, such as information from the ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0289] In at least one embodiment, the infotainment SoC 1230 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 can communicate with other devices, systems, and / or components of the vehicle 1200 via the bus 1202. In at least one embodiment, the infotainment SoC 1230 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1236 (e.g., the vehicle's 1200 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1230 can place the vehicle 1200 in a driver-to-safety parking mode, as described herein.

[0290] In at least one embodiment, the vehicle 1200 may further include an instrument panel 1232 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1232 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the instrument panel 1232. In at least one embodiment, the instrument panel 1232 may be included as part of the infotainment SoC 1230, or vice versa.

[0291] In at least one embodiment, utilizing Figure 12C At least one component shown or described is implemented in conjunction with Figures 1 to 8 In at least one embodiment, Figure 12C At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 12C At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0292] Figure 12D In accordance with at least one embodiment, one or more cloud-based servers and Figure 12AFIG2 is a diagram of a system for communicating between autonomous vehicles 1200. In at least one embodiment, the system may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but is not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected using a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0293] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that depicts an unexpected or altered road condition, such as a recently begun road project. In at least one embodiment, one or more servers 1278 may transmit an updated neural network 1292 and / or map information 1294 to the vehicle via one or more networks 1290, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to the map information 1294 may include, but not limited to, updates to the HD map 1222, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292 and / or map information 1294 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0294] In at least one embodiment, one or more servers 1278 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model can be used by one or more servers 1278 to remotely monitor the vehicle.

[0295] In at least one embodiment, one or more servers 1278 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1278 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 can include the deep learning infrastructure of a data center using CPU power.

[0296] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1200, such as an image sequence and / or objects that the vehicle 1200 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1200, and if the results do not match and the deep learning infrastructure concludes that the AI in the vehicle 1200 is malfunctioning, the one or more servers 1278 may send a signal to the vehicle 1200 instructing the vehicle's 1200 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0297] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. Figure 9A and / or Figure 9B Provides details about the hardware structure 915.

[0298] In at least one embodiment, utilizing Figure 12D At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 12D At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 12D At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0299] Computer system

[0300] Figure 1313 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1300 may include, but is not limited to, components such as processor 1302 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1300 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0301] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0302] In at least one embodiment, computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1300 is a single-processor desktop or server system, but in another embodiment, computer system 1300 may be a multi-processor system. In at least one embodiment, processor 1302 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310, which may transmit data signals between processor 1302 and other components in computer system 1300.

[0303] In at least one embodiment, processor 1302 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1306 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0304] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1302. In at least one embodiment, the processor 1302 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general-purpose processor and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1302. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0305] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0306] In at least one embodiment, the system logic chip can be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 can direct data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via a high-bandwidth memory path 1318 , and the graphics / video card 1312 may be coupled to the MCH 1316 via an accelerated graphics port (“AGP”) interconnect 1314 .

[0307] In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to couple MCH 1316 to I / O controller hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub ("flash BIOS") 1328, a wireless transceiver 1326, a data store 1324, a legacy I / O controller 1323 including a user input and keyboard interface 1325, a serial expansion port 1327 (such as a universal serial bus ("USB") port), and a network controller 1334. In at least one embodiment, data store 1324 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0308] In at least one embodiment, Figure 13 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 13 An exemplary SoC may be shown. In at least one embodiment, Figure 13 The devices shown in FIG1300 can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using a Compute Express Link (CXL) interconnect.

[0309] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0310] In at least one embodiment, utilizing Figure 13 At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 13At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 13 At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0311] Figure 14 1 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0312] In at least one embodiment, the electronic device 1400 may include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 14 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 14 An exemplary SoC may be shown. In at least one embodiment, Figure 14 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0313] In at least one embodiment, Figure 14 It may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an express chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0314] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components described herein. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1436, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1462, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1462 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452 and the WWAN unit 1456 may be implemented as a next generation form factor ("NGFF").

[0315] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BDetails are provided regarding logic 915. In at least one embodiment, logic 915 may be used in electronic device 1400 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0316] In at least one embodiment, utilizing Figure 14 At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 14 At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 14 At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0317] Figure 15 A computer system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0318] In at least one embodiment, computer system 1500 includes, but is not limited to, at least one central processing unit ("CPU") 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1522 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1500.

[0319] In at least one embodiment, computer system 1500 includes, but is not limited to, input device 1508, parallel processing system 1512, and display device 1506, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0320] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0321] In at least one embodiment, utilizing Figure 15 At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 15 At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 15At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0322] Figure 16 A computer system 1600 is shown according to at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, a computer 1610 and a USB drive 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0323] In at least one embodiment, the USB disk 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1630 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1630 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0324] In at least one embodiment, USB interface 1640 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 can include any number and type of logic that enables processing unit 1630 to interface with a device (e.g., computer 1610) via USB connector 1640.

[0325] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0326] In at least one embodiment, utilizing Figure 16 At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 16 At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 16 At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0327] Figure 17AAn exemplary architecture is shown in which a plurality of GPUs 1710(1)-1710(N) are communicatively coupled to a plurality of multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values of which may vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 1710(1)-1710(N) include: Figure 20A and Figure 20B , one or more graphics cores (also referred to simply as "cores") 2000 disclosed in

[0065] . In at least one embodiment, one or more graphics cores 2000 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where in this context, a slice may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0328] Furthermore, in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729(1)-1729(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 may be connected via high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 17A All communications between the various system components shown in .

[0329] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to processor memory 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memory 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N), respectively. In at least one embodiment, memory interconnects 1726 and 1750 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1701(1)-1701(M) and GPU memory 1720 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1701 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0330] As described herein, although each multi-core processor 1705 and GPU 1710 can be physically coupled to a specific memory 1701, 1720, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1701(1)-1701(M) can each include 64GB of system memory address space, and GPU memories 1720(1)-1720(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values of N and M are possible.

[0331] In at least one embodiment, utilizing Figure 17A At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 17A At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 17A At least one component performs Figure 1 Generative model 106, Figure 2ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0332] Figure 17B Additional details are shown for the interconnection between the multi-core processor 1707 and the graphics acceleration module 1746 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip with the processor 1707.

[0333] In at least one embodiment, the processor 1707 includes a plurality of cores 1760A-1760D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by each group of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which may include Figure 17A Processor memory 1701(1)-1701(M) in.

[0334] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1762A-1762D, 1756, and system memory 1714 via inter-core communication over a coherence bus 1764. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1764 to snoop cache accesses.

[0335] In at least one embodiment, proxy circuitry 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in a cache coherence protocol as a peer of cores 1760A-1760D. In particular, in at least one embodiment, interface 1735 provides connectivity to proxy circuitry 1725 via high-speed link 1740, and interface 1737 connects graphics acceleration module 1746 to high-speed link 1740.

[0336] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746 include, for example, a combination of Figure 20A and Figure 20B The one or more graphics cores 2000 discussed. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731(1)-1731(N), or the graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a common package, circuit card, or chip.

[0337] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1738 may store commands and data for efficient access by the graphics processing engines 1731(1)-1731(N). In at least one embodiment, a fetch unit 1744 may be used to keep data stored in the cache 1738 and graphics memory 1733(1)-1733(M) consistent with the core caches 1762A-1762D, 1756, and system memory 1714. As previously described, this can be implemented on behalf of cache 1738 and memory 1733(1)-1733(M) via proxy circuit 1725 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0338] In at least one embodiment, a set of registers 1745 stores context data for threads executed by graphics processing engines 1731(1)-1731(N), and context management circuitry 1748 manages thread contexts. For example, context management circuitry 1748 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1748 can store current register values to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0339] In at least one embodiment, the MMU 1739 converts virtual / effective addresses from the graphics processing engine 1731 into real / physical addresses in the system memory 1714. In at least one embodiment, the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 can be dedicated to a single application executing on the processor 1707, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1731 (1)-1731 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0340] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge to the system for the graphics acceleration module 1746 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1731(1)-1731(N).

[0341] In at least one embodiment, because the hardware resources of graphics processing engines 1731(1)-1731(N) are explicitly mapped into the real address space seen by host processor 1707, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1736 is the physical separation of graphics processing engines 1731(1)-1731(N) so that they appear to the system as independent units.

[0342] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each graphics processing engine 1731(1)-1731(N), respectively, with N=M. In at least one embodiment, graphics memories 1733(1)-1733(M) store instructions and data being processed by each graphics processing engine 1731(1)-1731(N). In at least one embodiment, graphics memories 1733(1)-1733(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0343] In at least one embodiment, to reduce data traffic on high-speed link 1740, biasing techniques may be used to ensure that the data stored in graphics memory 1733(1)-1733(M) is the data most frequently used by graphics processing engines 1731(1)-1731(N), and preferably is not used (at least not frequently) by cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 1731(1)-1731(N)) in caches 1762A-1762D, 1756, and system memory 1714.

[0344] In at least one embodiment, utilizing Figure 17B At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 17B At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 17B At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0345] Figure 17C Another exemplary embodiment is shown in which an accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, the graphics processing engines 1731(1)-1731(N) communicate directly with the accelerator integrated circuit 1736 via interface 1737 and interface 1735 (again, which can be any form of bus or interface protocol) over a high-speed link 1740. In at least one embodiment, the accelerator integrated circuit 1736 can perform operations related to Figure 17BThe operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1764 and caches 1762A-1762D, 1756. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0346] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731(1)-1731(N), thereby providing virtualization within a VM / partition.

[0347] In at least one embodiment, graphics processing engines 1731(1)-1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1731(1)-1731(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0348] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731(1)-1731(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1731(1)-1731(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0349] In at least one embodiment, utilizing Figure 17C At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 17CAt least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 17C At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0350] Figure 17D An exemplary accelerator integrated slice 1790 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1736. In at least one embodiment, the application is an effective address space 1782 in system memory 1714, which stores a process element 1783. In at least one embodiment, the process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on the processor 1707. In at least one embodiment, the process element 1783 contains the process state of the corresponding application 1780. In at least one embodiment, the work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of the application.

[0351] In at least one embodiment, the graphics acceleration module 1746 and / or the individual graphics processing engines 1731(1)-1731(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0352] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either a graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when a graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0353] In at least one embodiment, in operation, a WD fetch unit 1791 in the accelerator integrated slice 1790 fetches a next WD 1784, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, data from the WD 1784 can be stored in registers 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page walk circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuitry 1747 can process interrupt events 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, effective addresses 1793 generated by the graphics processing engines 1731(1)-1731(N) are converted to real addresses by the MMU 1739.

[0354] In at least one embodiment, registers 1745 are replicated for each graphics processing engine 1731(1)-1731(N) and / or graphics acceleration module 1746 and can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1790. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0355] Table 1 – Registers initialized by the hypervisor

[0356]

[0357]

[0358] Example registers that may be initialized by the operating system are shown in Table 2.

[0359] Table 2 – Registers initialized by the operating system

[0360]

[0361] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1731(1)-1731(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0362] In at least one embodiment, utilizing Figure 17D At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 17D At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 17D At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0363] Figure 17E 1796 virtualizes the graphics acceleration module engine for the operating system 1795.

[0364] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models where the graphics acceleration module 1746 is shared by multiple processes and partitions, namely, time-sliced sharing and graphics-directed sharing.

[0365] In at least one embodiment, in this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism, (2) the graphics acceleration module 1746 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) the graphics acceleration module 1746 must ensure fairness between processes when operating in a directed shared programming model.

[0366] In at least one embodiment, the application 1780 is required to make an operating system 1795 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1746.

[0367] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 (not shown) and the graphics acceleration module 1746 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1796 may selectively apply the current AMR value before placing the AMR into the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the effective address of an area in the application's effective address space 1782 for the graphics acceleration module 1746 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0368] Upon receiving the system call, the operating system 1795 can verify that the application 1780 has been registered and granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 calls the hypervisor 1796 using the information shown in Table 3.

[0369] Table 3 – OS to Hypervisor call parameters

[0370]

[0371] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1796 verifies that operating system 1795 has registered and been granted permission to use graphics acceleration module 1746. Then, in at least one embodiment, hypervisor 1796 places process element 1783 into a linked list of process elements of the corresponding type of graphics acceleration module 1746. In at least one embodiment, the process element may include the information shown in Table 4.

[0372] Table 4 – Process element information

[0373]

[0374] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1790 registers 1745 .

[0375] In at least one embodiment, utilizing Figure 17E At least one component shown or described is implemented in combination Figures 1 to 8In at least one embodiment, Figure 17E At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 17E At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0376] like Figure 17F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1701(1)-1701(N) and GPU memory 1720(1)-1720(N). In this implementation, operations executed on GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access processor memory 1701(1)-1701(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701(1), a second portion is allocated to second processor memory 1701(N), a third portion is allocated to GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1701 and GPU memory 1720, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0377] In at least one embodiment, bias / coherency management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherency between the caches of one or more host processors (e.g., 1705) and GPU 1710 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. In at least one embodiment, while Figure 17F Multiple instances of bias / coherence management circuits 1794A- 1794E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1705 and / or within an accelerator integrated circuit 1736 .

[0378] One embodiment allows GPU memory 1720 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1720 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1705 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1720 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1710. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0379] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1720, with or without a bias cache in GPU 1710 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0380] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1720 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1710 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1720. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1705 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1710. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0381] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1705 bias to GPU bias, but not for the reverse migration.

[0382] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1705. In at least one embodiment, to access these pages, processor 1705 may request access from GPU 1710, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1705 and GPU 1710, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1705, and vice versa.

[0383] One or more hardware structures 915 are used to execute one or more embodiments. Figure 9A and / or Figure 9B Details regarding one or more hardware structures 915 are provided.

[0384] In at least one embodiment, utilizing Figure 17FAt least one component shown or described is implemented in conjunction with Figures 1 to 8 In at least one embodiment, Figure 17F At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 17F At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0385] Figure 18 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0386] Figure 18 1800 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I 2 S / I 2IC controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industry Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0387] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in integrated circuit 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0388] Figures 19A-19B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0389] In at least one embodiment, utilizing Figure 18 A-18B shows or describes at least one component to achieve the combination Figures 1 to 8 In at least one embodiment, Figure 18 At least one component of A-18B is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 18 At least one component of the A-18B performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0390] Figures 19A-19B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 19A An exemplary graphics processor 1910 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 19B An additional exemplary graphics processor 1940 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 19A The graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 can be Figure 18 A variant of the graphics processor 1810.

[0391] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D through 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1915A-1915N use the primitives and vertex data generated by the vertex processor 1905 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0392] In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide virtual to physical address mapping for graphics processor 1910 (including for vertex processor 1905 and / or fragment processors 1915A-1915N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B may synchronize with other MMUs within the system, including with Figure 18 One or more MMUs associated with one or more application processors 1805, graphics processor 1815, and / or video processor 1820 enable each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable graphics processor 1910 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0393] In at least one embodiment, graphics processor 1940 includes the following: Figure 19B One or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F through 1955N-1 and 1955N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0394] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BDetails are provided regarding logic 915. In at least one embodiment, logic 915 may be used in graphics processors 1910 and / or 1940 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0395] In at least one embodiment, utilizing Figures 19A-19B At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figures 19A-19B At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figures 19A-19B At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0396] Figures 20A-20B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figures 20A-20B Shown and combined Figures 20A-20B The components described are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or another type of processor. In at least one embodiment, Figure 20A Shows that can be included in Figure 18 Graphics core 2000 within graphics processor 1810, and in at least one embodiment, may be such as Figure 19B Unified shader cores 1955A-1955N are shown. Figure 20BA highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 2030 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, graphics processing unit 2030 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1800 includes graphics core 2000, e.g., to form an integrated circuit and / or to form a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0397] In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020 (e.g., including L1, L2, L3, last-level cache, or other caches), which are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A-2001N, or partitions of each core, and a graphics processor may include multiple instances of graphics core 2000. In at least one embodiment, each slice 2001A-2001N refers to graphics core 2000. In at least one embodiment, slices 2001A-2001N have sub-slices that are part of slices 2001A-2001N. In at least one embodiment, slices 2001A-2001N may be independent of other slices or dependent on other slices. In at least one embodiment, the slices 2001A-2001N may include support logic including a local instruction cache 2004A-2004N, a thread scheduler (sequencer) 2006A-2006N, a thread dispatcher 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, the slices 2001A-2001N may include a set of additional function units (AFUs 2012A-2012N), floating point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016A-2016N), address calculation units (ACUs 2013A-2013N), double-precision floating point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A-2017N). In at least one embodiment, the MPUs 2017A-2017N are referred to as a matrix engine.

[0398] In at least one embodiment, each slice 2001A-2001N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large data set workloads. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 2001A-2001N include 16 vector engines, which are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed through matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of a processor. In at least one embodiment, graphics core 2000 includes one or more matrix engines for computing matrix operations, for example, when computing tensor operations.

[0399] In at least one embodiment, one or more slices 2001A-2001N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice in slices 2001A-2001N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0400] In at least one embodiment, one or more slices 2001A-2001N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0401] In at least one embodiment, one or more slices 2001A-2001N are linked to L2 cache and memory structures, link connectors, high bandwidth memory (HBM) (e.g., HBM2e, HDMI3) stacks, and media engines. In at least one embodiment, one or more slices 2001A-2001N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2001A-2001N have one or more L1 caches. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 2001A-2001N include memory structures, such as an L2 cache.

[0402] In at least one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017A-2017N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2012A-2012N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0403] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in graphics core 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0404] In at least one embodiment, the graphics core 2000 includes an interconnect and link fabric sublayer attached to switches and GPU-GPU bridges that enable multiple graphics processors 2000 (e.g., eight) to interconnect with each other without glue by having load / store units (LSUs), data transfer units, and synchronization semantics across the multiple graphics processors 2000. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0405] In at least one embodiment, graphics core 2000 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where the individual dies can be connected via an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 2000 includes a compute tile, a memory tile (e.g., where the memory tile can be exclusively accessed by different tiles or different chipsets (such as a Rambo tile)), a base tile, a foundation tile, an HMB tile, a link tile, and an EMIB tile, where all of the tiles are packaged together in graphics core 2000 as part of a GPU. In at least one embodiment, graphics core 2000 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have eight graphics cores 2000 and an L1 cache; and a foundation tile can have host interfaces for PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the blocks are connected via fine-pitch 36-micron microbumps (e.g., copper pillars) with face-to-face (F2F) chip-on-chip bonding. In at least one embodiment, graphics core 2000 includes a memory structure (the memory structure includes memory) and is a block accessible by multiple blocks. In at least one embodiment, graphics core 2000 stores its own hardware context in memory, accesses its own hardware context in memory, or loads its own hardware context into memory, where the hardware context is a set of data loaded from registers before a process resumes, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0406] In at least one embodiment, graphics core 2000 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or vice versa.

[0407] In at least one embodiment, graphics core 2000 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, block data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0408] In at least one embodiment, the graphics core 2000 executes an API that abstracts the graphics core 2000's hardware and accesses libraries with instructions to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0409] In at least one embodiment, utilizing Figure 20A At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 20A At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 20A At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0410] Figure 20BA GPGPU 2030 is shown in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 2030 can be directly linked to other instances of GPGPU 2030 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 for connecting to a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interface 2032 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 may be used as a higher level cache for cache memory within compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H include slices or are referred to as "slices." In at least one embodiment, GPGPU 2030 is part of a SoC, such as integrated circuit 1800 ( Figure 18 ).

[0411] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled to compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0412] In at least one embodiment, computing clusters 2036A-2036H each include a set of graphics cores, such as Figure 20AThe graphics core 2000 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0413] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2036A-2036H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to a GPU link 2040, which enables direct connections to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via a network device accessible via host interface 2032. In at least one embodiment, GPU link 2040 may be configured to enable connection to a host processor in addition to or in lieu of host interface 2032 .

[0414] In at least one embodiment, GPGPU 2030 can be configured to train a neural network. In at least one embodiment, GPGPU 2030 can be used within an inference platform. In at least one embodiment, when using GPGPU 2030 for inference, GPGPU 2030 can include fewer compute clusters 2036A-2036H than when using GPGPU 2030 for training a neural network. In at least one embodiment, the memory technology associated with memories 2044A-2044B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0415] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in GPGPU 2030 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0416] In at least one embodiment, utilizing Figure 20B At least one component shown or described is implemented in combination Figures 1 to 8 In at least one embodiment, Figure 20B At least one component of the system is configured to generate, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. In at least one embodiment, Figure 20B At least one component performs Figure 1 Generative model 106, Figure 2 ASR model 206, HRNet 220, OpenPose 216, classifier 212 and / or Audio2Pose model 224, Figure 3 Audio condition 302, heat map condition 328 and / or condition diffusion 330, Figure 4 Conditional hybrid network 400, Figure 5 Diffusion model architecture 500, Figure 6 Method 600, Figure 7 Processor 700, and / or Figure 8 The driver and / or runtime 800 describes at least one aspect.

[0417] Figure 212 is a block diagram illustrating a computing system 2100 according to at least one embodiment. In at least one embodiment, computing system 2100 includes a processing subsystem 2101 having one or more processors 2102 ...

Claims

1. A processor, comprising: One or more circuits for generating, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object. 2 . The processor of claim 1 , wherein the first portion of the object comprises one or more limbs of the object and the second portion of the object comprises one or more features of the subject's face.

3. The processor of claim 1 , wherein the one or more neural networks comprises a second portion for generating the one or more motions of the second portion of the object based at least in part on the audio, and a first portion for generating the one or more motions of the first portion of the object.

4. The processor of claim 1 , wherein the one or more neural networks are used to generate a heat map indicating a posture of the object and the one or more motions of the second portion of the object. 5 . The processor of claim 1 , wherein the one or more movements of the second portion are indicative of body language of the subject.

6. The processor of claim 1, wherein the object is an avatar of one or more parts of a human being.

7. The processor of claim 1, wherein the audio comprises one or more speech utterances, and the one or more movements of the second portion of the object correspond to the one or more speech utterances.

8. A system comprising: One or more processors for generating, using one or more neural networks, one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object.

9. The system of claim 8, wherein the first portion of the subject comprises one or more limbs of the subject and the second portion of the subject comprises one or more features of the subject's face.

10. The system of claim 8, wherein the one or more neural networks include a second portion for generating the one or more motions of the second portion of the object based at least in part on the audio, and a first portion for generating the one or more motions of the first portion of the object.

11. The system of claim 8, wherein the one or more neural networks are used to generate a heat map indicating a posture of the object and the one or more motions of the second portion of the object.

12. The system of claim 8, wherein the one or more movements of the second portion are indicative of body language of the subject.

13. The system of claim 8, wherein the object is an avatar of one or more parts of a human being.

14. The system of claim 8, wherein the audio comprises one or more speech utterances, and the one or more movements of the second portion of the object correspond to the one or more speech utterances.

15. A method comprising: One or more neural networks are used to generate one or more movements of a first portion of the object based at least in part on one or more movements of a second portion of the object and audio corresponding to the one or more movements of the second portion of the object.

16. The method of claim 15, wherein the first portion of the subject comprises one or more limbs of the subject and the second portion of the subject comprises one or more features of the subject's face.

17. The method of claim 15, wherein the one or more neural networks include a second portion for generating the one or more motions of the second portion of the object based at least in part on the audio, and a first portion for generating the one or more motions of the first portion of the object.

18. The method of claim 15, wherein the one or more neural networks are used to generate a heat map indicating a posture of the object and one or more motions of the second portion of the object.

19. The method of claim 15, wherein the one or more movements of the second portion are indicative of body language of the subject.

20. The method of claim 15, wherein the object is an avatar of one or more parts of a human being.

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