Display driving system and applicable driving chip and time sequence control chip thereof

Abstract

The invention provides a display driving system and a driving chip and a time sequence control chip suitable for the display driving system. The display driving system comprises the time sequence control chip, a first driving chip and a second driving chip. Wherein the data line of the first driving chip and the data line of the second driving chip are in point-to-point connection with the time sequence control chip. When the second driving chip enters the unlocking state, the time sequence control chip transmits at least one synchronizing signal to the first driving chip and the second driving chip. After the first driving chip receives at least one synchronization signal, the first driving chip reads a picture control information signal provided by the time sequence control chip in an unscrambled mode.

Description

Technical Field

[0001] The present invention relates to a display driving system and its applicable driving chip and timing control chip; in particular, to a display driving system and its applicable driving chip and timing control chip that avoid scrambling coding misjudgment during synchronization under a point-to-point connection architecture. Background Art

[0002] In the driving circuit of a display device, a timing control chip (TCON) is often used to control several driver chips. In order to simplify the circuit complexity between the timing control chip and the driver chips, a point-to-point connection architecture is used in the prior art to configure the circuit.

[0003] In a point-to-point connection architecture, when transmitting the same or highly repetitive images, the signals between multiple driver chips may interfere with each other and / or resonate, generating noise. Therefore, point-to-point drive technology uses scrambling technology to scramble the signals provided to the driver chips, ensuring that each driver chip has a different waveform during signal transmission. This prevents resonant interference or electromagnetic interference between the signals between the driver chips.

[0004] Because point-to-point drive technology typically uses differential signals as the data transmission medium and lacks a clock signal, when a data signal error occurs, the driver chip with the error must be unlocked. The timing control chip then re-sends a relock signal to resynchronize the differential signal to avoid image anomalies.

[0005] However, if the timing control chip enters a resynchronization process, such as retransmitting synchronization signals such as the tracking training signal (TS), link stability signal (LSP), and / or unscrambled picture control information (CTRL-F), it is possible that the unlocked driver chip will be reset to a non-scrambled state, while the unlocked driver chip will still maintain the scrambled state. In this case, the unlocked driver chip will decode the unscrambled synchronization signal using the scrambled code, resulting in decoding errors and causing abnormal display images on the display device.

[0006] As can be seen from the above, in the point-to-point transmission architecture using scrambling technology, the existing technology still has many problems that need to be overcome and solved. Summary of the Invention

[0007] One of the purposes of the present invention is to synchronize a timing control chip and a controlled driver chip in a point-to-point connection architecture in scrambling technology.

[0008] One of the purposes of the present invention is to avoid signal interpretation problems between an unlocked driver chip and a non-unlocked driver chip during synchronization between a timing control chip and a controlled driver chip.

[0009] A preferred embodiment of the present invention provides a display driver system. The display driver system includes a timing control chip, a first driver chip, and a second driver chip. The data line of the first driver chip and the data line of the second driver chip are connected point-to-point to the timing control chip. When the second driver chip enters an unlocked state, the timing control chip transmits at least one synchronization signal to the first and second driver chips. After the first driver chip receives the at least one synchronization signal, the first driver chip reads the image control information signal provided by the timing control chip in an unscrambled manner.

[0010] In one embodiment, the at least one synchronization signal includes a lock training signal.

[0011] In one embodiment, the at least one synchronization signal includes a connection stability information signal.

[0012] In one embodiment, when the second driver chip enters the unlocked state, the second driver chip transmits unlocking information to the timing control chip via the status line path.

[0013] In one embodiment, the status line path connects the status line of the first driver chip and the status line of the second driver chip in series, and the series connection position of the first driver chip is before the second driver chip.

[0014] In one embodiment, when the second driver chip enters the unlocked state, the second driver chip transmits unlocking information to the first driver chip via the status line; and after the first driver chip receives the unlocking information, the first driver chip disables scrambling coding.

[0015] In one embodiment, when the second driver chip enters the unlocked state, the second driver chip transmits unlocking information to the first driver chip via the status line; and after the first driver chip receives the unlocking information, the first driver chip enters the unlocked state.

[0016] A preferred embodiment of the present invention is a driver chip for a display driver system. The driver chip is configured such that: a data line of the driver chip is point-to-point connected to a timing control chip; and upon receiving at least one synchronization signal from the timing control chip, the driver chip reads an image control information signal provided by the timing control chip in an unscrambled manner.

[0017] In one embodiment, the driver chip is further configured to transmit unlocking information to at least one other driver chip located in series before the driver chip on a radial path of the status line when the driver chip enters the unlocking state.

[0018] In one embodiment, the driver chip is further configured to: after the driver chip receives unlocking information from the status line of the driver chip, the driver chip turns off the scrambling code.

[0019] In one embodiment, the driving chip is further configured to: after the driving chip receives unlocking information from the status line of the driving chip, the driving chip enters the unlocking state.

[0020] A preferred embodiment of the present invention provides a display driver system. The display driver system includes a timing control chip, a first driver chip, and a second driver chip. The data lines of the first driver chip and the second driver chip are connected point-to-point to the timing control chip. When the second driver chip enters an unlocked state, before the timing control chip enters a synchronization process, the timing control chip causes the first driver chip to enter an unlocked state.

[0021] In one embodiment, before the timing control chip enters the synchronization process, the timing control chip transmits an error signal to the first driver chip to cause the first driver chip to enter an unlocked state.

[0022] A preferred embodiment of the present invention is a timing control chip for a display driver system. The timing control chip is configured such that: the timing control chip is connected to data lines of multiple driver chips via a point-to-point connection; when at least one of the multiple driver chips enters an unlocked state, the timing control chip enters a synchronization process; and before the synchronization process, the timing control chip causes each of the multiple driver chips to enter an unlocked state.

[0023] In one embodiment, the timing control chip is further configured to: before the synchronization process, transmit an error signal to each of the plurality of driver chips to cause each of the plurality of driver chips to enter an unlocked state.

[0024] The aforementioned display driver system and its applicable driver chips and timing control chips ensure that, when at least one driver chip is unlocked due to a transmission error, the picture control information signal provided by the timing control chip will not be misconfigured due to differences in the driver chip's scrambling settings. This ensures stable synchronization between the timing control chip and the controlled driver chip in a point-to-point connection architecture within scrambling technology, and avoids signal misinterpretation issues caused by differences in scrambling settings between unlocked and unlocked driver chips during synchronization between the timing control chip and the controlled driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings presented in this application are intended to help describe various embodiments of the present invention. However, to simplify the drawings and / or highlight the intended content, existing structures and / or elements in the drawings may be depicted in a simplified schematic manner or omitted. Furthermore, the number of elements in the drawings may be singular or plural. The drawings presented in this application are intended only to illustrate these embodiments and are not intended to limit them.

[0026] Figure 1 FIG. 1 is a connection diagram of a display driving system in the first embodiment of the present invention.

[0027] Figure 2A This is a flow chart of disabling scrambling after the driver chip receives the synchronization signal in the first embodiment of the present invention.

[0028] Figure 2B This is a timing diagram of the driver chip turning off scrambling after receiving the synchronization signal in the first embodiment of the present invention.

[0029] Figure 2C This is a flow chart of disabling scrambling after the driver chip is synchronized in the first embodiment of the present invention.

[0030] Figure 2D This is a timing diagram of disabling scrambling after the driver chip is synchronized in the first embodiment of the present invention.

[0031] Figure 3 This is a timing diagram of a synchronization signal including a lock training signal and / or a connection stability information signal in a first embodiment of the present invention.

[0032] Figure 4A FIG. 1 is a schematic diagram showing the connection of serial state lines of a display driving system in the first embodiment of the present invention.

[0033] Figure 4B and Figure 4C FIG. 1 is a signal timing diagram after the state lines are connected in series, compared with the prior art according to the first embodiment of the present invention.

[0034] Figure 5 FIG. 1 is a schematic diagram showing the connection of parallel state lines of a display driving system in the first embodiment of the present invention.

[0035] Figure 6 FIG. 1 is a connection diagram of a display driving system in a second embodiment of the present invention.

[0036] Figure 7A This is a flow chart of the timing control chip unlocking the driving chip in the second embodiment of the present invention.

[0037] Figure 7B This is a timing diagram of the timing control chip unlocking the driving chip in the second embodiment of the present invention. Description of main component symbols:

[0038] 100 display driver system

[0039] 110 timing control chip

[0040] 110-TX Settings

[0041] 120 driver chip

[0042] 120-RX Settings

[0043] 121 first driver chip

[0044] 122 second driver chip

[0045] 123 third driver chip

[0046] 200 display drive system

[0047] 210 timing control chip

[0048] 221 first driver chip

[0049] 222 second driver chip

[0050] BCCF, BCC1, BCC2, BCC3, BCC4, BCCB status lines

[0051] State line path of BCC-S concatenation

[0052] BCC-P parallel state line path

[0053] D1, D2, D3 data lines

[0054] L1, L2 paths

[0055] R101, R102, R103, R103', R104, R105, R106 steps

[0056] R201, R202, R203, R203', R204, R205, R206 steps

[0057] R301, R302, R303, R304, R305, R306 steps

[0058] Steps T101, T102, T103, T104

[0059] Steps T201, T202, T203, T204, T205 DETAILED DESCRIPTION

[0060] Any reference to elements using names such as "first" and "second" in this article does not generally limit the number or order of these elements. On the contrary, these names are used as a convenient way to distinguish two or more elements or element instances in this article. Therefore, it should be understood that the names "first", "second" and the like in the claims do not necessarily correspond to the same names in the written description. In addition, it should be understood that the reference to the first and second elements does not mean that only two elements can be used or that the first element must be before the second element. As used herein, "comprising", "including", "having", "containing" and the like are all open terms, that is, they mean including but not limited to.

[0061] The term "coupled" is used herein to refer to direct or indirect electrical coupling between two structures. For example, in an example of indirect electrical coupling, one structure may be coupled to another structure via a passive element such as a resistor, capacitor, or inductor.

[0062] In this disclosure, the words "exemplary" and "for example" are used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. The terms "approximately" and "substantially," as used herein with respect to a specified value or characteristic, are intended to mean within a certain value (e.g., 10%) of the specified value or characteristic.

[0063] Please refer to Figure 1 , Figure 1 A display driver system 100 according to a first embodiment of the present invention is described. Display driver system 100 includes a timing control chip 110, a first driver chip 121, and a second driver chip 122. Data lines D1 of the first driver chip 121 and data lines D2 of the second driver chip 122 are connected point-to-point to the timing control chip 110. It should be noted that for simplicity, only the first driver chip 121 and the second driver chip 122 are shown; however, the timing control chip 110 can control more than two driver chips.

[0064] According to the first embodiment, the present invention provides a driver chip 120 suitable for the display driver system 100. The driver chip 120 is configured as follows: the data line of the driver chip is point-to-point connected to the timing control chip (see Figure 1); and when the driver chip 120 receives at least one synchronization signal from the timing control chip 110, the driver chip 120 reads the picture control information signal provided by the timing control chip 110 in an unscrambled manner. The scrambling of the driver chip 120 can be turned on or off by firmware or hardware within the driver chip 120. For example, in terms of hardware, a switch or a toggle for the scrambling function can be set in the driver chip 120 to switch between scrambling and non-scrambling. On the other hand, in terms of firmware, the decoding method for the received picture control information signal can be determined by the system settings within the driver chip 120 (for example, the driver chip 120 can have a scrambling function block, and the scrambling function block can be controlled according to instructions (for example, the picture control information CTRL-F)). However, the means for turning on or off scrambling of the driver chip 120 in the present invention is not limited to this.

[0065] In the first embodiment, the driver chip 120 reads the picture control information signal provided by the timing control chip 110 in an unscrambled manner, and there are multiple setting methods. Figure 2A and Figure 2B , Figure 2A and Figure 2B One of the setting methods of the driver chip 120 (120-RX, 110-TX) is described below. Figure 2A As shown, take the unlocking of the driver chip 120 as an example (please refer to Figure 2A After the driver chip 120 is configured (e.g., path L1), data (DATA) transmission will begin in step R101. However, if the driver chip 120 enters an unlocked state (ULS) (step R103) due to a data error (Fail) or any other factor (step R102), the driver chip 120 will provide unlock information (ULI) to the timing control chip 110 and disable scrambling (step R104). Upon receiving the unlock information (ULI) from the driver chip 120 (step T102), the timing control chip 110 will initiate a synchronization process and provide at least one synchronization signal (SYS) (steps R105, T103) to resynchronize the unlocked driver chip 120 and ensure accurate control. It should be noted that the timing control chip 110 can be coupled to multiple driver chips 120 simultaneously, and the unlock information (ULI) may be provided by at least one of the multiple driver chips 120. After synchronization is completed, the timing control chip 110 will provide an unscrambled picture control information signal (CTRL-F) to configure the driver chip 120 (steps R106, T104). Since the driver chip 120 has disabled scrambling, it can correctly interpret the picture control information signal (CTRL-F) for subsequent configuration and subsequent data transmission (steps R101, T101).

[0066] On the other hand, take the example of the driver chip 120 not being unlocked (see Figure 2A In the middle path L2, when the driver chip 120 normally receives the data signal (DATA), if it receives at least one synchronization signal (SYS) from the timing control chip 110 (step R103', T103), the driver chip 120 will disable scrambling (step R104) and then continue the synchronization process (step R105). After the synchronization process is completed, when the driver chip 120 receives the unscrambled picture control information signal (CTRL-F) provided by the timing control chip 110 (step R106, T104), because the driver chip 120 has disabled scrambling, it can correctly interpret the picture control information signal (CTRL-F) for subsequent settings and subsequent data transmission (steps R101, T101).

[0067] More specifically, taking the first driver chip 121 and the second driver chip 122 in the display driver system 100 as an example, please refer to Figure 2B . In the reception (122-RX) of the second driver chip 122, the chip is unlocked due to an error (Fail), and the scrambling (122-SCR) of the second driver chip 122 will be turned off. When the timing control chip 110 receives the unlocking information of the second driver chip 122, it will transmit at least one synchronization signal (SYS) to the first driver chip 121 and the second driver chip 122. When the first driver chip 121 receives at least one synchronization signal (SYS), the scrambling (121-SCR) of the first driver chip 121 will be turned off, and the screen control information signal (CTRL-F) provided by the timing control chip 110 will be read in an unscrambled manner. It should be noted that in this step, the screen control information signal (CTRL-F) refers to the first screen control information signal (CTRL-F) received after the synchronization process. Specifically, the picture control information signal (CTRL-F) can be provided by the timing control chip 110 to the first driver chip 121 and the second driver chip 122 during the data transmission process. The first driver chip 121 and the second driver chip 122 can determine the settings when receiving data based on the picture control information signal (CTRL-F). Furthermore, after the first driver chip 121 and the second driver chip 122 synchronize with the timing control chip 110 and receive the picture control information signal (CTRL-F), the scrambling function (121-SCR) of the first driver chip 121 and the scrambling function (122-SCR) of the second driver chip 122 can be determined to be enabled or disabled based on the subsequently transmitted picture control information signal (CTRL-F).

[0068] In the first embodiment, please refer to Figure 2C and Figure 2D , Figure 2C and Figure 2DOne of the configuration methods of the driver chip 120 is described below. Figure 2C As shown, the unlocking setting of the driver chip 120 (please refer to Figure 2C Middle path L1) and Figure 2A However, take the example of the driver chip 120 not being unlocked (see Figure 2C When the driver chip 120 receives the data signal (DATA) normally, if it receives at least one synchronization signal from the timing control chip 110 (steps R203', T103), the driver chip 120 will perform a synchronization process (step R204). After the synchronization process is completed, the driver chip 120 will disable scrambling (step R205) and then continue to receive the unscrambled image control information signal from the timing control chip 110 (step R206). Because the driver chip 120 has disabled scrambling, it can correctly interpret the image control information signal for subsequent settings.

[0069] More specifically, taking the first driver chip 121 and the second driver chip 122 in the display driver system 100 as an example, please refer to Figure 2D . In the reception (122-RX) of the second driver chip 122, the lock is unlocked due to an error (Fail), and the scrambling (122-SCR) of the second driver chip 122 will be turned off. When the timing control chip 110 receives the information that the second driver chip 122 is unlocked, it will transmit at least one synchronization signal (SYS) to the first driver chip 121 and the second driver chip 122. After the first driver chip 121 and the second driver chip 122 receive at least one synchronization signal (SYS), the first driver chip 121 and the second driver chip 122 will be synchronized with the timing control chip 110. After the synchronization is completed, the scrambling (121-SCR) of the first driver chip 121 will be turned off, and the picture control information signal (CTRL-F) provided by the timing control chip 110 will be read in an unscrambled manner. Figure 2B Similar to the figure, the scrambling ( 121 -SCR) of the first driving chip 121 and the scrambling ( 122 -SCR) of the second driving chip 122 can be determined to be turned on or off according to the image control information signal (CTRL-F).

[0070] It should be noted that Figures 2A to 2D The process and signal contents shown are only for illustrating the present invention and are not intended to limit the present invention. The synchronization signals between the timing control chip 110 and the first driver chip 121 and the second driver chip 122 may vary according to the point-to-point connection interface. For example, referring to Figure 3Among the outputs (110-TX) of the timing control chip 110, at least one synchronization signal (SYS) may include a lock training signal (TS) and / or a link stability signal (LSP). The driver chip 120 may first establish synchronization with the timing control chip 110 using the lock training signal (TS) and then determine the synchronization status using the link stability signal (LSP), but the present invention is not limited thereto.

[0071] In the first embodiment, the unlocking information of the first driver chip 121 and / or the second driver chip 122 can be provided to the timing control chip 110 via the status line path. Taking the serial status line path (BCC-S) as an example, please refer to Figure 4A The timing control chip 110, the first driver chip 121, the second driver chip 122, and the third driver chip 123 can be connected in series via status lines (BCC1, BCC2, BCC3, BCC4). The first driver chip 121 is connected in series before the second driver chip 122, and the third driver chip 123 is connected in series after the second driver chip 122.

[0072] For the signal timing diagram between the status lines (BCC1, BCC2, BCC3, BCC4) and the first driver chip 121, the second driver chip 122 and the third driver chip 123, please refer to Figure 4B and Figure 4C . Figure 4B It is explained that in the prior art, the scrambling state of the first driver chip 121 is an uncertain state. Figure 4BAs shown, when a signal transmission failure (failure) occurs from the second driver chip 122, resulting in unlocking, the signal line (BCC2) from the second driver chip 122 to the third driver chip 123 is transitioned to the unlock level (e.g., from a digital "1" to a digital "0"). Furthermore, the signal line (BCCB) from the third driver chip 123 to the timing control chip 110 is also transitioned to the unlock level, thereby providing a status signal (the unlock level) to the timing control chip 110, causing the timing control chip 110 to enter the synchronization process. The third driver chip 123 is also forced to enter the unlock state due to the transition of the signal line (BCCB) to the unlock level. In the unlocked state, scrambling is disabled for the second and third driver chips 122 and 123. Therefore, the second and third driver chips 122 and 123 do not experience errors when receiving the unscrambled picture control information signal (CTRL-F) transmitted by the timing control chip 110. However, in the prior art, because the first driver chip 121 is connected in series before the second driver chip 122, the signal line (BCC1) is not switched to the unlocked state. Therefore, the first driver chip 121 does not enter the unlocked state and directly disables scrambling. Consequently, in the prior art, the scrambling state of the first driver chip 121 is uncertain (on / off).

[0073] In contrast, according to Figures 2A to 2D The setting method described, such as Figure 4C As shown, the first driver chip 121 can forcibly turn off scrambling when receiving the synchronization signal (SYS) or before receiving the picture control information signal (CTRL-F) after synchronization is completed. Therefore, in the present invention, under the architecture of the serial status line, regardless of the unlocking position, the first driver chip 121, the second driver chip 122, and the third driver chip 123 can all use an unscrambled method to read the picture control information signal (CTRL-F) provided by the timing control chip 110 for subsequent settings. This avoids the problem of signal interpretation errors caused by different scrambling settings between the unlocked driver chip and the unlocked driver chip during synchronization between the timing control chip and the controlled driver chip.

[0074] However, the state line of the present invention can also be a parallel structure. Taking the parallel state line path (BCC-P) as an example, please refer to Figure 5, the status lines of the first driver chip 121 and the second driver chip 122 can be connected in parallel and coupled to the timing control chip 110. When one of the first driver chip 121 and the second driver chip 122 is unlocked, the unlocking information on the status line path (BCC-P) will be set to the unlocking level. The timing control chip 110 can determine whether to enter the synchronization process based on the unlocking information. Similar to the series architecture, when, for example, the second driver chip 122 is unlocked, the first driver chip 121 can be turned off for scrambling through the synchronization signal (SYS) of the timing control chip 110. This avoids the problem of signal reading errors caused by different scrambling settings between the unlocked driver chip and the driver chip that has not yet been unlocked. It should be noted that Figure 5 The driver chips shown are exemplary, and the present invention does not limit the number of driver chips in the parallel state line path.

[0075] In one embodiment, when the second driver chip 122 enters the unlocked state, it can transmit unlock information to the first driver chip 121 via the status line paths (BCC-S, BCC-P). After receiving the unlock information, the first driver chip 121 disables scrambling or enters the unlocked state. Taking the serial status line path (BCC-S) as an example, when the second driver chip 122 enters the unlocked state, the status line (BCC2) is set to the unlock level. At this point, the second driver chip 122 can provide the unlock information to the first driver chip 121 via the status line (BCC1). It should be noted that in this embodiment, the second driver chip 122 can provide the unlock information to the first driver chip 121 via a bidirectional status line configured for both reception and transmission. Therefore, this embodiment can be used with either serial or parallel status line paths (BCC-S, BCC-P). Furthermore, the serial status line path (BCC-S) is not limited to the serial connection between the first driver chip 121 and the second driver chip 122. For example, after the second driver chip 122 is unlocked, the unlocking information can be provided to the first driver chip 121 and / or the third driver chip 123 via the status line path (i.e., the unlocking information is provided forward or backward). Taking the series connection as an example, the first driver chip 121 that receives the unlocking information from the second driver chip 122 can turn off the scrambling code or enter the unlocked state to read the picture control information signal (CTRL-F) provided by the timing control chip 110 in an unscrambled manner in unison with the second driver chip 122 and the third driver chip 123 for subsequent settings. This avoids the problem of signal reading errors caused by different scrambling settings between the unlocked driver chip and the driver chip that has not yet been unlocked during synchronization between the timing control chip and the controlled driver chip.

[0076] Please refer to Figure 6 , Figure 6The second specific embodiment of the present invention is a display driving system 200. The display driving system 200 includes a timing control chip 210, a first driving chip 221 and a second driving chip 222. The data line D1 of the first driving chip 221 and the data line D2 of the second driving chip 222 are point-to-point connected to the timing control chip 210. When the second driving chip 222 enters the unlocked state to allow the timing control chip 210 to enter the synchronization process, the timing control chip 210 causes the first driving chip 221 to enter the unlocked state. Multiple driving chips 221-222 and the timing control chip 210 can provide the unlocked state to the timing control chip 210 through the status line path (BCC-S). It should be noted that, Figure 6 The serial state line path (BCC-S) shown is only an example. As in the first embodiment, the state line path of the display driving system 200 may also be a parallel structure.

[0077] According to the second embodiment, the timing control chip 210 of the display driving system 200 is configured as follows: the timing control chip 210 is connected to the data lines D1 and D2 of the plurality of driving chips 221-222 via point-to-point communication (see Figure 6 , the number of driver chips may be more than two). When at least one of the multiple driver chips 221-222 enters the unlocked state, the timing control chip enters the synchronization process. Before the synchronization process, the timing control chip causes each of the multiple driver chips to enter the unlocked state.

[0078] Specifically, before the synchronization process, the timing control chip 210 makes each of the plurality of driving chips 221-222 enter the unlocked state, which can be set in a variety of ways. For example, please refer to Figure 7A and Figure 7B When one of the multiple driver chips 221-222 is unlocked due to an error (for example, the second driver chip 222 is unlocked), the second driver chip 222 transmits the unlocking information to the timing control chip 210 through the status line. When the timing control chip 210 receives the unlocking information, it can transmit an unlocking control signal (UCS) to all driver chips controlled by the timing control chip 210. The unlocking control signal (UCS) can be transmitted through the status line, for example, so that the driver chip enters the unlocking state after receiving the unlocking control signal (UCS) and turns off scrambling. After all the controlled driver chips are set to the unlocking state, the timing control chip 210 can perform a synchronization process and provide a screen control information signal (CTRL-F) to reset the settings of all the controlled driver chips.

[0079] On the other hand, when one of the multiple driver chips 221-222 is unlocked due to an error (for example, the second driver chip 222 is unlocked), the second driver chip 222 transmits the unlocking information to the timing control chip 210 via the status line. When the timing control chip 210 receives the unlocking information, it can transmit an erroneous data signal (ES) to all driver chips controlled by the timing control chip 210. When the driver chip receives the erroneous data signal (ES), it will automatically enter the unlocking state and turn off scrambling. After all the controlled driver chips are set to the unlocking state, the timing control chip 210 can perform a synchronization process and provide a screen control information signal (CTRL-F) to reset the settings of all the controlled driver chips.

[0080] By using the display drive system 200 and the applicable timing control chip 210, when the driver chips 221 and 222 are unlocked due to a transmission error, the timing control chip 210 can cause all controlled driver chips to enter the unlocked state before synchronization and image control are performed. Therefore, the image control information signal provided by the timing control chip 210 will not cause control setting errors due to different scrambling settings of the driver chips. This achieves stable synchronization between the timing control chip and the controlled driver chips under the point-to-point connection architecture in the scrambling technology, and avoids the problem of signal interpretation errors caused by different scrambling settings between the unlocked driver chip and the unlocked driver chip during synchronization between the timing control chip and the controlled driver chip.

[0081] The previous description of the present invention is provided to enable one skilled in the art to make or practice the present invention. Various modifications to the present invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations or the various embodiments may be combined or implemented separately without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features of the present invention.

Claims

1. A display driving system, characterized in that: Include: A timing control chip; a first driver chip; and a second driver chip; The data line of the first driver chip and the data line of the second driver chip are point-to-point connected to the timing control chip; When the second driver chip enters the unlocked state, the timing control chip transmits at least one synchronization signal to the first driver chip and the second driver chip; After the first driving chip receives the at least one synchronization signal, the first driving chip reads a picture control information signal provided by the timing control chip in a non-scrambled manner.

2. The display driving system according to claim 1, wherein: The at least one synchronization signal includes a lock training signal.

3. The display driving system according to claim 1, wherein: The at least one synchronization signal includes a connection stability information signal.

4. The display driving system according to claim 1, wherein: When the second driving chip enters the unlocking state, the second driving chip transmits unlocking information to the timing control chip via a status line path.

5. The display driving system according to claim 4, wherein: The state line path is connected in series with the state line of the first driver chip and the state line of the second driver chip, and the series connection position of the first driver chip is before the second driver chip.

6. The display driving system according to claim 4, wherein: When the second driver chip enters the unlocking state, the second driver chip transmits the unlocking information to the first driver chip through the state line; and after the first driver chip receives the unlocking information, the first driver chip turns off the scrambling code.

7. The display driving system according to claim 4, wherein: When the second driver chip enters the unlocked state, the second driver chip transmits the unlocking information to the first driver chip through the state line; and after the first driver chip receives the unlocking information, the first driver chip enters the unlocked state.

8. A driver chip for a display driver system, characterized in that: The driver chip is configured as: The data line of the driver chip is point-to-point connected to a timing control chip; and After the driving chip receives at least one synchronization signal from the timing control chip, the driving chip reads a picture control information signal provided by the timing control chip in an unscrambled manner.

9. The driver chip for a display driver system according to claim 8, wherein: The driver chip is further configured as follows: When the driver chip enters the unlocking state, the driver chip transmits unlocking information to at least one other driver chip located in series before the driver chip on the path of the state line via a state line.

10. The driver chip for a display driver system according to claim 8, wherein: The driver chip is further configured as follows: When the driver chip receives unlocking information from the status line of the driver chip, the driver chip turns off the scrambling code.

11. The driver chip for a display driver system according to claim 8, wherein: The driver chip is further configured as follows: When the driving chip receives unlocking information from the state line of the driving chip, the driving chip enters the unlocking state.

12. A display driving system, characterized in that: Include: A timing control chip; a first driver chip; and a second driver chip; The data line of the first driver chip and the data line of the second driver chip are point-to-point connected to the timing control chip; When the second driving chip enters the unlocked state to enable the timing control chip to enter a synchronization process, the timing control chip enables the first driving chip to enter the unlocked state.

13. The display driving system according to claim 12, wherein: Before the timing control chip enters the synchronization process, the timing control chip transmits an error signal to the first driving chip to enable the first driving chip to enter an unlocking state.

14. A timing control chip for a display drive system, characterized in that: The timing control chip is configured as: The timing control chip is connected to the data lines of multiple driver chips through point-to-point connection; When at least one of the plurality of driving chips enters an unlocked state, the timing control chip enters a synchronization process; as well as Before the synchronization process, the timing control chip enables each of the plurality of driving chips to enter an unlocked state.

15. The timing control chip for a display driving system according to claim 14, wherein: The timing control chip is further configured as follows: Before the synchronization process, the timing control chip transmits an error signal to each of the plurality of driving chips to enable each of the plurality of driving chips to enter an unlocked state.

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