Load control circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a load control circuit and a display panel. The load control circuit comprises a delay control module, which is used for outputting a first control signal at power-on and continuously outputting a second control signal after outputting the first control signal for a preset time length; a first control module, which is used for sending light-load display data or a power-on clock signal to the source driving circuit and the gate driving circuit under the action of the first control signal; and a second control module, which is used for sending normal display data or a normal clock signal to the source driving circuit or the gate driving circuit under the action of the second control signal. Therefore, the application solves the problem of boot abnormality caused by boot heavy-load voltage drop by providing light-load display data at power-on and / or reducing the refresh frequency of the panel at power-on.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a load control circuit and a display panel. BACKGROUND

[0002] During the starting stage of electronic products, each load module needs to be switched from zero state to full load work in a very short time, and the instantaneous load current will show a sharp increase, which is called start-up inrush current. According to the power formula P=UI, when the load current (I) increases sharply, it will cause the supply voltage (U) to drop significantly, forming a transient voltage drop.

[0003] At present, when the display panel encounters a heavy load display screen during startup, a large transient voltage drop will occur, and the voltage drop amplitude may exceed the lower limit of the normal working voltage, causing the core chip to trigger the undervoltage protection mechanism, thereby causing abnormal phenomena such as startup failure.

[0004] Therefore, how to improve the abnormal phenomena caused by the start-up heavy load voltage drop is a problem to be solved at present. SUMMARY

[0005] The present application provides a load control circuit and a display panel, which solves the problem of start-up abnormality caused by start-up heavy load voltage drop by providing light load display data during power-up or / and reducing the refresh frequency of the panel during power-up.

[0006] In a first aspect, the embodiments of the present application provide a load control circuit applied to a display panel, the display panel comprising a timing controller, a source driving circuit and a gate driving circuit, the load control circuit comprising: a delay control module configured to output a first control signal at power-on and continuously output a second control signal after outputting the first control signal for a preset time length; a first control module, a control end of the first control module being connected to an output end of the delay control module, a first end of the first control module being connected to an output end of the timing controller, and a second end of the first control module being connected to the source driving circuit or the gate driving circuit, the first control module being configured to send light-load display data output by the timing controller to the source driving circuit or send a power-on clock signal with a first clock frequency output by the timing controller to the gate driving circuit under the action of the first control signal; and a second control module, a control end of the second control module being connected to the output end of the delay control module, a first end of the second control module being connected to the output end of the timing controller, and a second end of the second control module being connected to the source driving circuit or the gate driving circuit, the second control module being configured to send normal display data output by the timing controller to the source driving circuit or send a normal clock signal with a second clock frequency output by the timing controller to the gate driving circuit under the action of the second control signal; wherein the first clock frequency is less than the second clock frequency.

[0007] Optionally, the delay control module comprises: a first resistor, a first end of the first resistor being connected to an output end of an external power supply; a first capacitor, a first end of the first capacitor being connected to a second end of the first resistor, and a second end of the first capacitor being grounded; a first transistor, a control end of the first transistor being connected to the first end of the first capacitor; a second resistor, a first end of the second resistor being grounded, and a second end of the second resistor being connected to a first end of the first transistor; a third resistor, a first end of the third resistor being connected to the output end of the external power supply; and a second transistor, a control end of the second transistor being connected to the control end of the first transistor, a first end of the second transistor being connected to a second end of the third resistor, and a second end of the second transistor being connected to a second end of the first transistor; wherein the first transistor has a low-level opening voltage, the second transistor has a high-level opening voltage, and the second end of the first transistor or the second end of the second transistor is taken as the output end of the delay control module.

[0008] Optionally, the delay control module comprises: a differential amplifier, a first input end of the differential amplifier being connected with a reference voltage output end, a second input end of the differential amplifier being connected with a power supply end of the timing controller, for amplifying a difference between a current power supply voltage on the power supply end of the timing controller and the reference voltage; a comparator, a first input end of the comparator being connected with a reference threshold end, a second input end of the comparator being connected with an output end of the differential amplifier, for outputting the first control signal or the second control signal according to a comparison result of the voltage difference output by the differential amplifier and the reference threshold.

[0009] Optionally, the delay control module comprises: an exclusive-NOR gate, a first input end of the exclusive-NOR gate being connected with a first time voltage output end, a second input end of the exclusive-NOR gate being connected with a second time voltage output end, an output end of the exclusive-NOR gate being used as an output end of the delay control module; wherein the first time voltage output end is used for outputting a first power supply voltage of the power supply end of the timing controller at t time, and the second time voltage output end is used for outputting a second power supply voltage of the power supply end of the timing controller at t+N time.

[0010] Optionally, the first control module comprises a third transistor, a control end of the third transistor being connected with an output end of the delay control module, a first end of the third transistor being connected with a first output end of the timing controller, and a second end of the third transistor being connected with a source electrode drive circuit or a gate electrode drive circuit; the second control module comprises a fourth transistor, a control end of the fourth transistor being connected with the output end of the delay control module, a first end of the fourth transistor being connected with a second output end of the timing controller, and a second end of the fourth transistor being connected with the source electrode drive circuit or the gate electrode drive circuit; wherein the turn-on voltages of the third transistor and the fourth transistor are opposite.

[0011] Optionally, the first control module comprises: an inverter, an input end of the inverter being connected with an output end of the delay control module, for inverting the output signal of the delay control module; a first AND gate, a first input end of the first AND gate being connected with a first output end of the timing controller, a second input end of the first AND gate being connected with an output end of the inverter, and an output end of the first AND gate being connected with a source electrode drive circuit or a gate electrode drive circuit, for sending the light load display data output by the timing controller or the power-on clock signal to the source electrode drive circuit or the gate electrode drive circuit when the second input end receives a high level.

[0012] Optionally, the second control module comprises: a fifth transistor, a control end of the fifth transistor being connected with an output end of the delay control module, a first end of the fifth transistor being connected with an enable end of the timing controller; a second AND gate, a first input end of the second AND gate being connected with a second end of the fifth transistor, a second input end of the second AND gate being connected with an output end of the timing controller, an output end of the second AND gate being connected with a source electrode drive circuit or a gate electrode drive circuit; the second AND gate being used for sending normal display data or normal clock signals output by the timing controller to the source electrode drive circuit or the gate electrode drive circuit when receiving a high level at the first input end.

[0013] Optionally, the display panel further comprises M clock signal lines, two ends of the 2m-1th clock signal line being respectively connected with a 2m-1th clock signal output end of the timing controller and a 2m-1th clock signal receiving end of the gate electrode drive circuit, and the load control circuit further comprises: a plurality of control tubes, a control end of an mth control tube being connected with an output end of the delay control module, a first end of the mth control tube being connected with a 2mth clock signal output end of the timing controller, and a second end of the mth control tube being electrically connected with one end of a 2mth clock signal line; another end of the 2mth clock signal line being connected with a 2mth clock signal receiving end of the gate electrode drive circuit.

[0014] Or, the display panel further comprises M clock signal lines, two ends of the 2mth clock signal line being respectively connected with a 2mth clock signal output end of the timing controller and a 2mth clock signal receiving end of the gate electrode drive circuit, and the load control circuit further comprises: a plurality of control tubes, a control end of an mth control tube being connected with an output end of the delay control module, a first end of the mth control tube being connected with a 2m-1th clock signal output end of the timing controller, and a second end of the mth control tube being electrically connected with one end of a 2m-1th clock signal line; another end of the 2m-1th clock signal line being connected with a 2m-1th clock signal receiving end of the gate electrode drive circuit; wherein, M is an integer greater than 1.

[0015] Optionally, the load control circuit further comprises: a sixth transistor, a control end of the sixth transistor being connected with an output end of the delay control module, a first end of the sixth transistor being connected with an output end of the external power supply; a seventh transistor, a control end of the seventh transistor being connected with the control end of the sixth transistor, a first end of the seventh transistor being connected with a second end of the sixth transistor, a second end of the seventh transistor being grounded; a first inductor, a first end of the first inductor being connected with the first end of the seventh transistor, a second end of the first inductor being connected with a power supply end of the subsequent load; a second capacitor, a first end of the second capacitor being connected with the second end of the first inductor, a second end of the second capacitor being grounded; wherein the turn-on voltages of the sixth transistor and the seventh transistor are opposite.

[0016] In a second aspect, the embodiments of the present application provide a display panel, comprising a display area and a non-display area, the display area comprising a pixel array; the non-display area comprising a timing controller, a gate drive circuit, a source drive circuit and a load control circuit, the load control circuit being electrically connected with the timing controller, the gate drive circuit or / and the source drive circuit respectively.

[0017] The technical scheme provided by the present application has at least the following beneficial effects:

[0018] The first control module in the present application sends the light-load display data output by the timing controller to the source drive circuit according to the first control signal output by the delay control module when power is turned on, so that the source drive circuit drives the pixels in the display panel to perform low-load display according to the light-load display data, or / and sends the low-frequency power-on clock signal output by the timing controller to the gate drive circuit, so that the gate drive circuit drives the scanning lines in the display panel to open row by row according to the power-on clock signal, thereby reducing the refresh rate of the display panel, which can avoid the problem of sharp increase of load current, and thus realize normal booting of the display panel. In addition, after a preset time length of power-on, the second control module sends the normal display data output by the timing controller to the source drive circuit according to the second control signal output by the delay control module, so that the source drive circuit drives the pixels in the display panel to perform normal display according to the normal display data, or / and sends the normal clock signal output by the timing controller to the gate drive circuit, so that the gate drive circuit drives the pixels in the display panel to perform normal display according to the normal clock signal. Therefore, the present application solves the problem of booting abnormality caused by booting heavy load voltage drop by providing light-load display data during power-on or / and reducing the refresh frequency of the panel during power-on. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure. It is to be understood that the drawings are only schematic, and that they do not purport to be to scale with respect to one another. The embodiments will be described with reference to the drawings in conjunction with the detailed description, which illustrates and sets forth various embodiments of the present disclosure.

[0020] Figure 1 Fig. 1 shows a structure diagram of a first load control circuit according to an embodiment of the present application.

[0021] Figure 2 Fig. 2 shows a structure diagram of a second load control circuit according to an embodiment of the present application.

[0022] Figure 3 Fig. 3 shows a circuit diagram of the first load control circuit according to an embodiment of the present application.

[0023] Figure 4 Fig. 4 shows a circuit diagram of the second load control circuit according to an embodiment of the present application.

[0024] Figure 5 Fig. 5 shows a circuit diagram of a third load control circuit according to an embodiment of the present application.

[0025] Figure 6 Fig. 6 shows a circuit diagram of a fourth load control circuit according to an embodiment of the present application.

[0026] Figure 7 Fig. 7 shows a circuit diagram of a fifth load control circuit according to an embodiment of the present application.

[0027] Figure 8 Fig. 8 shows a clock signal diagram according to an embodiment of the present application.

[0028] Figure 9 Fig. 9 shows a circuit diagram of a sixth load control circuit according to an embodiment of the present application.

[0029] Legend of reference signs:

[0030] 100, load control circuit; 110, delay control module; 120, first control module; 130, second control module; 200, timing controller; 300, source driving circuit; 400, gate driving circuit; 500, clock signal line; 600, external power supply; 700, load at the back stage;

[0031] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; Tc, control tube; R1, first resistor; R2, second resistor; R3, third resistor; C1, first capacitor; C2, second capacitor; L1, first inductor; U1, differential amplifier; U2, comparator; U3, XNOR gate; U4, inverter; U5, first AND gate; U6, second AND gate. DETAILED DESCRIPTION

[0032] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example implementations to those skilled in the art.

[0033] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the

[0034] The application will be further described with reference to the drawings and specific examples. It is to be understood that the description applied to embodiments of the application described herein is equally applicable to the respective features of the application, unless the context clearly indicates otherwise. The examples described below are examples only and are not intended to limit the scope of the application.

[0035] In a first aspect, embodiments of the present application provide a load control circuit, specifically including the following embodiments:

[0036] Figure 1 Fig. 1 shows a structure schematic diagram of a first load control circuit provided by embodiments of the present application; as Figure 1 As shown, the load control circuit 100 includes a delay control module 110, configured to output a first control signal at power-on, and continuously output a second control signal after outputting the first control signal for a preset time length.

[0037] It should be noted that the load control circuit 100 of the embodiment can be applied in a display panel, the display panel at least comprising a timing controller and a source driving circuit; when the display panel is powered on, that is, the load control circuit 100 is powered on, the delay control module 110 outputs a first control signal; after the delay control module 110 outputs the first control signal for a preset time length, the second control signal is continuously outputted; wherein the phases of the first control signal and the second control signal are opposite, that is, when the first control signal is at a low level, the second control signal is at a high level; conversely, when the first control signal is at a high level, the second control signal is at a low level. In addition, the preset time length can be a fixed time length, for example, after the delay control module 110 outputs the first control signal for 1 second, the second control signal is continuously outputted; the preset time length can also be a time length obtained by dynamic detection according to the specific application scenario.

[0038] In the embodiment, the load control circuit 100 further comprises a first control module 120, a control end of the first control module 120 is connected with an output end of the delay control module 110, a first end of the first control module 120 is connected with a first output end of the timing controller 200, and a second end of the first control module 120 is connected with the source driving circuit 300, for sending the light load display data outputted by the timing controller 200 to the source driving circuit 300 under the action of the first control signal.

[0039] In the embodiment, the first control module 120 is used for receiving the first control signal outputted by the delay control module 110, and is also used for sending the light load display data outputted by the timing controller 200 to the source driving circuit 300 under the action of the first control signal, so that the source driving circuit 300 drives the pixels in the display panel to display in a low load mode according to the light load display data; specifically, if the normal display data is a heavy load picture when powered on, a large transient voltage drop will be generated, resulting in problems such as power-on failure or display abnormality; in view of this, the first control module 120 sends the light load display data outputted by the timing controller 200 to the source driving circuit 300 under the action of the first control signal outputted by the delay control module 110, so that the source driving circuit 300 drives the pixels in the display panel to display in a low load mode according to the light load display data, that is, the display panel displays the light load display data (i.e. low load display data) when powered on, so that the problem of sharp increase of load current does not occur, and the normal power-on of the display panel is realized.

[0040] In this embodiment, the load control circuit 100 further includes a second control module 130. The control terminal of the second control module 130 is connected to the output terminal of the delay control module 110. The first terminal of the second control module 130 is connected to the second output terminal of the timing controller 200. The second terminal of the second control module 130 is connected to the source drive circuit 300. It is used to send the normal display data output by the timing controller 200 to the source drive circuit 300 under the action of the second control signal.

[0041] It should be noted that after a certain period of power-on, the second control module 130, under the action of the second control signal output by the delay control module 110, sends the normal display data output by the timing controller 200 to the source drive circuit 300, so that the source drive circuit 300 drives the pixels in the display panel to display normally according to the normal display data.

[0042] It is worth noting that when the delay control module 110 outputs the first control signal, the second control module 130 does not work; similarly, when the delay control module 110 outputs the second control signal, the first control module 120 does not work.

[0043] In summary, the first control module 120 in this application sends the light-load display data output by the timing controller 200 to the source drive circuit 300 based on the first control signal output by the delay control module 110 upon power-on. This allows the source drive circuit 300 to drive the pixels in the display panel for low-load display based on the light-load display data, thus preventing a sharp increase in load current and ensuring normal power-on of the display panel. After a preset power-on time, the second control module 130 sends the normal display data output by the timing controller 200 to the source drive circuit 300 based on the second control signal output by the delay control module 110. This allows the source drive circuit 300 to drive the pixels in the display panel for normal display based on the normal display data. Therefore, this application solves the problem of abnormal power-on caused by heavy-load voltage drop by providing light-load display data upon power-on and restoring the input of normal display data after power-on stabilization.

[0044] Figure 2 The diagram shown is a structural schematic of the second type of load control circuit provided in an embodiment of this application; Figure 2 The illustrated embodiments and Figure 1 The differences lie in the type of output signal from the timing controller and the load connected to the second terminal of the first and second control modules; specifically, as follows: Figure 2 As shown, the load control circuit 100 includes a delay control module 110, which outputs a first control signal upon power-on and continuously outputs a second control signal after outputting the first control signal for a preset duration. The working principle of the load control circuit 100 provided in this embodiment is the same as that in the above embodiment (Figure 1 The embodiments shown are the same, so they will not be described again here.

[0045] In this embodiment, the load control circuit 100 further includes a first control module 120. The control terminal of the first control module 120 is connected to the output terminal of the delay control module 110. The first terminal of the first control module 120 is connected to the third output terminal of the timing controller 200. The second terminal of the first control module 120 is connected to the gate drive circuit 400. Under the action of the first control signal, the first power-on clock signal LX1 output by the timing controller 200 with a first clock frequency is sent to the gate drive circuit 400, so that the gate drive circuit 400 drives the scan lines in the display panel to open line by line according to the power-on clock signal LX1.

[0046] In this embodiment, the first clock frequency is lower than the clock frequency during normal display, thereby reducing the refresh rate of the display panel. Specifically, if the displayed data is a heavy load image when powered on, a large transient voltage drop will occur, leading to problems such as power-on failure or display abnormalities. To address this, this embodiment uses the first control signal output by the delay control module 110 when powered on, which causes the first control module 120 to send the low-frequency power-on clock signal output by the timing controller 200 to the gate drive circuit 400. This causes the gate drive circuit 400 to drive the scan lines in the display panel to open line by line according to the power-on clock signal, thereby reducing the refresh rate of the display panel and avoiding a sharp increase in load current, thus enabling the display panel to power on normally.

[0047] In this embodiment, the load control circuit 100 further includes a second control module 130. The control terminal of the second control module 130 is connected to the output terminal of the delay control module 110. The first terminal of the second control module 130 is connected to the fourth output terminal of the timing controller 200. The second terminal of the second control module 130 is connected to the gate drive circuit 400. It is used to send the normal clock signal LX2 with the second clock frequency output by the timing controller 200 to the gate drive circuit 400 under the action of the second control signal.

[0048] It should be noted that the second clock frequency can be used as the normal display clock frequency, that is, the second clock frequency is greater than the first clock frequency; after a certain period of power-on, the second control module 130, under the action of the second control signal output by the delay control module 110, sends the normal clock signal LX2 output by the timing controller 200 to the gate drive circuit 400, so that the gate drive circuit 400 drives the pixels in the display panel to display normally according to the normal clock signal.

[0049] In summary, the first control module 120 in this application sends a low-frequency power-on clock signal output by the timing controller 200 to the gate drive circuit 400 based on the first control signal output by the delay control module 110 upon power-on. This causes the gate drive circuit 400 to drive the scan lines in the display panel to open line by line according to the power-on clock signal, thereby reducing the refresh rate of the display panel and avoiding a sharp increase in load current, thus achieving normal power-on of the display panel. After a preset power-on time, the second control module 130 sends a normal clock signal output by the timing controller 200 to the gate drive circuit 400 based on the second control signal output by the delay control module 110. This causes the gate drive circuit 400 to drive the pixels in the display panel to display normally according to the normal clock signal. Therefore, this application solves the problem of abnormal power-on caused by heavy load voltage drop by reducing the refresh rate of the panel upon power-on and restoring the normal refresh rate after power-on stabilization.

[0050] Combination Figure 1 and Figure 2 It is understood that this application can place the load control circuit 100 between the timing controller 200 and the source drive circuit 300 to improve the problem of power-on heavy load voltage drop by providing light load display data when powered on; this application can also place the load control circuit 100 between the timing controller 200 and the gate drive circuit 400 to improve the problem of power-on heavy load voltage drop by reducing the panel refresh rate when powered on; this application can also place the load control circuit 100 between the timing controller 200 and the source drive circuit 300, and between the timing controller 200 and the gate drive circuit 400, so that the problem of power-on heavy load voltage drop can be improved by simultaneously providing light load display data and reducing the refresh rate when powered on.

[0051] Figure 3 The diagram shown is a schematic diagram of the first type of load control circuit provided in this application embodiment; as follows: Figure 3 As shown, the delay control module 110 of this embodiment includes a first resistor R1, a first capacitor C1, a first transistor T1, a second resistor R2, a third resistor R3, and a second transistor T2. Specifically, the first end of the first resistor R1 is connected to the output terminal of an external power supply; the first end of the first capacitor C1 is connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is grounded; the control terminal of the first transistor T1 is connected to the first end of the first capacitor C1; the first end of the second resistor R2 is grounded, and the second end of the second resistor R2 is connected to the first end of the first transistor T1; the first end of the third resistor R3 is connected to the output terminal of an external power supply; the control terminal of the second transistor T2 is connected to the control terminal of the first transistor T1, the first end of the second transistor T2 is connected to the second end of the third resistor R3, and the second end of the second transistor T2 is connected to the second end of the first transistor T1.

[0052] In addition, the turn-on voltage of the first transistor T1 is low, which can be understood as a P-type MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor). The turn-on voltage of the second transistor T2 is high, which can be understood as an N-type MOS transistor. The second terminal of the second transistor T2 or the second terminal of the first transistor T1 is used as the output terminal of the delay control module 110.

[0053] It should be noted that the specific working principle of the delay control module 110 provided in this embodiment is as follows:

[0054] (1) Initial power-on phase: The storage voltage on the first capacitor C1 is 0V, that is, the gate voltage (i.e., control terminal voltage) of the first transistor T1 and the gate voltage of the second transistor T2 are both equal to 0V. Then the first transistor T1 is turned on and the second transistor T2 is turned off, so the first control signal output by the delay control module 110 is low level.

[0055] (2) Charging process: After power-on, the output voltage of the external power supply charges the first capacitor C1 through the first resistor R1. The gate voltage of the first transistor T1 gradually increases. When the gate voltage increases to the turn-off voltage of the first transistor T1, the first transistor T1 is turned off and the second transistor T2 is turned on, so that the second control signal output by the delay control module 110 is high level.

[0056] In this embodiment, the delay time from low level to high level is mainly determined by the first resistor R1 and the first capacitor C1; therefore, the delay time (i.e., the preset duration) can be flexibly set by adjusting the parameter values ​​of the first resistor R1 and the first capacitor C1; wherein, in this embodiment, the second resistor R2 has a pull-down function, causing the second terminal of the first transistor T1 to output a low level when the first transistor T1 is turned on; in this embodiment, the third resistor R3 has a pull-up function, causing the second terminal of the second transistor T2 to output a high level when the second transistor T2 is turned on.

[0057] It should also be noted that the external power supply has multiple output terminals, and the voltage output by each terminal can be the same or different; for example... Figure 3 As shown, the first end of the first resistor R1 is connected to the output terminal VDD1 of the external power supply, and the first end of the second resistor R2 is connected to the output terminal VDD2 of the external power supply. The output voltages of the output terminals VDD1 and VDD2 can be the same or different. In addition, the first end of the first resistor R1 and the first end of the second resistor R2 can be connected to the same output terminal of the external power supply.

[0058] like Figure 3As shown, the first control module 120 in this embodiment includes a third transistor T3. The control terminal of the third transistor T3 is connected to the output terminal of the delay control module 110. The first terminal of the third transistor T3 is connected to the first output terminal of the timing controller 200. The second terminal of the third transistor T3 is connected to the source drive circuit 300.

[0059] The second control module 130 in this embodiment includes a fourth transistor T4. The control terminal of the fourth transistor T4 is connected to the output terminal of the delay control module 110. The first terminal of the fourth transistor T4 is connected to the second output terminal of the timing controller 200. The second terminal of the fourth transistor T4 is connected to the source drive circuit 300.

[0060] Here, the first output terminal of the timing controller 200 outputs light-load display data D0, and the second output terminal of the timing controller 200 outputs normal display data; in addition, the turn-on voltages of the third transistor T3 and the fourth transistor T4 in this embodiment are opposite.

[0061] It should be noted that in this embodiment, the third transistor T3 is a P-type MOSFET and the fourth transistor T4 is an N-type MOSFET. Upon power-up, the first control signal output by the delay control module 110 is low, the third transistor T3 is turned on, and the fourth transistor T4 is turned off. Thus, the light-load display data D0 output from the first output terminal of the timing controller 200 is transmitted to the source drive circuit 300 through the turned-on third transistor T3. After a preset power-up time, the second control signal output by the delay control module 110 is high, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. Thus, the second control signal output by the delay control module 200 is transmitted to the source drive circuit 300 through the turned-on fourth transistor T4. The normal display data D0 output from the output terminal is sent to the source drive circuit 300. Since the light load display data can be a black screen or a low grayscale screen, the normal display screen is output after the power-on gradually stabilizes. This is equivalent to using a step, raising the display screen to the first step first, and then from the first step to the second step, thus dividing the process into two segments and reducing the instantaneous load. Furthermore, during the period when the delay control module outputs the first control signal, the light load display data can include multiple display data. By inserting different screens or grayscale displays, the load increases sequentially from low load to high load, solving the problem of abnormal power-on caused by heavy load voltage drop and improving the stability of the power-on screen.

[0062] In another embodiment, the first terminal of the third transistor T3 can also be connected to the third output terminal of the timing controller 200, and the second terminal of the third transistor T3 is connected to the gate drive circuit 400; the first terminal of the fourth transistor T4 can also be connected to the fourth output terminal of the timing controller 200, and the second terminal of the fourth transistor T4 is connected to the gate drive circuit 400. It should be noted that in this embodiment, the third output terminal of the timing controller outputs a power-on clock signal with a first clock frequency, and the fourth output terminal of the timing controller outputs a normal clock signal with a second clock frequency; the working principle of the third transistor T3 and the fourth transistor T4 in this embodiment is the same as... Figure 3 They are the same, the only difference being the connection objects of the first and second ends of each transistor, which will not be elaborated here.

[0063] Figure 4 The diagram shown is a schematic diagram of a second type of load control circuit provided in an embodiment of this application; Figure 4 and Figure 3 The difference lies in the specific structure of the delay control module 110; for example... Figure 4 As shown, the delay control module 110 in this embodiment includes a differential amplifier U1 and a comparator U2. The first input terminal of the differential amplifier U1 is connected to the reference voltage output terminal, and the second input terminal of the differential amplifier U1 is connected to the power supply terminal of the timing controller 200, for amplifying the difference between the current power supply voltage Vin and the reference voltage Vref at the power supply terminal of the timing controller. The first input terminal of the comparator U2 is connected to the reference threshold terminal, and the second input terminal of the comparator U2 is connected to the output terminal of the differential amplifier U1, for outputting a first control signal or a second control signal based on the comparison result between the voltage difference output by the differential amplifier U1 and the reference threshold Vth.

[0064] It should be noted that the reference voltage output terminal can be an output terminal of the timing controller, an output terminal of an external power supply, or an output terminal of another processor. The reference voltage Vref output by this reference voltage output terminal can be the normal supply voltage of the external power supply. In the initial stage of power-on, due to the power-on load removal, the current power supply voltage Vin is less than the reference voltage Vref. The difference between the current power supply voltage and the reference voltage is amplified by the differential amplifier U1, and then the voltage difference is input into the comparator U2 for comparison with the reference threshold Vth. When the voltage difference is greater than the reference threshold, the comparator U2 outputs a first control signal; conversely, when the voltage difference is less than or equal to the reference threshold, the comparator U2 outputs a second control signal. In this embodiment, the reference threshold can be set according to the amplification factor of the differential amplifier U1. In addition, the reference threshold terminal can be a voltage output terminal of the timing controller 200, or it can be a triangular wave or square wave output terminal. Figure 4 The working principle of the third transistor T3 and the fourth transistor T4 in the middleFigure 2 The same applies, so I won't go into details here.

[0065] Figure 5 The diagram shown is a circuit diagram of the third type of load control circuit provided in an embodiment of this application; Figure 5 and Figure 2 The difference lies in the specific structure of the delay control module 110; for example... Figure 5 As shown, the delay control module 110 in this embodiment includes an XNOR gate U3. The first input terminal of the XNOR gate U3 is connected to the voltage output terminal at the first time moment, the second input terminal of the XNOR gate U3 is connected to the voltage output terminal at the second time moment, and the output terminal of the XNOR gate U3 serves as the output terminal of the delay control module 110.

[0066] In this embodiment, the first-time voltage output terminal is used to output the first power supply voltage Vt1 of the power supply terminal of the timing controller 200 at time t, and the second-time voltage output terminal is used to output the second power supply voltage Vt2 of the power supply terminal of the timing controller 200 at time t+N. The XOR gate U3 compares the voltages at two adjacent times to determine whether the current state is the power-on phase or the stable phase. If Vt1 and Vt2 are different, it indicates that the voltage is unstable, i.e., in the power-on phase, and the XOR gate U3 outputs a low-level control signal. Conversely, if Vt1 and Vt2 are the same, it indicates that the voltage is stable, i.e., in the stable phase, and the XOR gate U3 outputs a high-level control signal. Here, t varies with time, and N is a constant, such as 50ms, 100ms, etc.

[0067] In one embodiment, the delay control module 110 may further include a timing chip, and the delay duration can be controlled by setting the software program inside the timing chip.

[0068] In another embodiment, the delay control module 110 may further include a comparator to determine whether the current state is the power-on phase or the stable phase by comparing the voltages at two adjacent moments; that is, to... Figure 5 The XOR gates in the code can be replaced with voltage comparators, but the specific output logic remains the same, so it will not be described in detail here.

[0069] Figure 6 The diagram shown is a circuit diagram of the fourth load control circuit provided in an embodiment of this application; Figure 6 and Figure 5 The difference lies in the specific structure of the first control module 120 and the second control module 130; for example Figure 6As shown, the first control module 120 in this embodiment includes an inverter U4 and a first AND gate U5. The input terminal of the inverter U4 is connected to the output terminal of the delay control module 110. The inverter U4 is used to invert the output signal of the delay control module 110. The first input terminal of the first AND gate U5 is connected to the first output terminal of the timing controller 200, the second input terminal of the first AND gate U5 is connected to the output terminal of the inverter U4, and the output terminal of the first AND gate U5 is connected to the source drive circuit 300 or the gate drive circuit 400. When the first AND gate U5 receives a high level at its second input terminal, it sends the light-load display data or power-on clock signal output by the timing controller 200 to the source drive circuit 300 or the gate drive circuit 400, respectively.

[0070] It should be noted that the working principle of the first control module 120 in this embodiment is explained in detail as follows: When the delay control module 110 outputs a low level, it is inverted by the inverter U4 to obtain a high level; at this time, the second input terminal of the first AND gate U5 is at a high level, and the first AND gate U5 outputs the light load display data or power-on clock signal received at the first input terminal as the output signal; conversely, when the delay control module 110 outputs a high level, it is inverted by the inverter U4 to obtain a low level; at this time, the second input terminal of the first AND gate U5 is at a low level, and the first AND gate U5 does not output any signal or outputs a low-level signal to the back end.

[0071] like Figure 6 As shown, the second control module 130 includes a fifth transistor T5 and a second AND gate U6. The control terminal of the fifth transistor T5 is connected to the output terminal of the delay control module 110, and the first terminal of the fifth transistor T5 is connected to the enable terminal of the timing controller 200. The first input terminal of the second AND gate U6 is connected to the second terminal of the fifth transistor T5, the second input terminal of the second AND gate U6 is connected to the output terminal of the timing controller 200, and the output terminal of the second AND gate U6 is connected to the source drive circuit 300 or the gate drive circuit 400. When the first input terminal receives a high level, the second AND gate U6 is used to send the normal display data or normal clock signal output by the timing controller 200 to the source drive circuit 300 or the gate drive circuit 400.

[0072] In this embodiment, the fifth transistor T5 is an N-type MOS transistor. The enable terminal of the timing controller 200 outputs a high level. The working principle of the second control module 130 is explained in detail as follows: When the delay control module 110 outputs a high level, the fifth transistor T5 is turned on. At this time, the first input terminal of the second AND gate U6 receives the high level output from the enable terminal of the timing controller 200. Then, the second AND gate U6 outputs the normal display data or normal clock signal received at the second input terminal as the output signal. Conversely, when the delay control module 110 outputs a low level, the fifth transistor T5 is turned off. At this time, the first input terminal of the second AND gate U6 is in a low-level or high-impedance state. Then, the second AND gate U6 does not output any signal or outputs a low-level signal to the back end.

[0073] Figure 7 The diagram shown is a circuit diagram of the fifth type of load control circuit provided in the embodiments of this application; Figure 7 Is Figures 1 to 6 Based on this, add multiple control transistors Tc, specifically: such as Figure 7 As shown, the display panel also includes M clock signal lines 500. The two ends of the (2m-1)th clock signal line 500 are connected to the (2m-1)th clock signal output terminal of the timing controller 200 and the (2m-1)th clock signal receiving terminal of the gate drive circuit 400, respectively. The load control circuit also includes multiple control transistors Tc. The control terminal of the mth control transistor Tc is connected to the output terminal of the delay control module 110. The first end of the mth control transistor Tc is connected to the (2m)th clock signal output terminal of the timing controller 200. The second end of the mth control transistor Tc is electrically connected to one end of the 2mth clock signal line 500. The other end of the 2mth clock signal line 500 is connected to the (2m)th clock signal receiving terminal of the gate drive circuit 400.

[0074] It is worth noting that, as can be seen from the foregoing embodiments, the circuit structure of the delay control module 110 of this application includes at least three embodiments (i.e., Figure 3 , Figure 4 and Figure 5 As shown), the first control module 120 includes at least two embodiments (i.e. Figure 5 and Figure 6 As shown) and the second control module 130 also include at least two embodiments (i.e. Figure 5 and Figure 6 As shown in the diagram, different embodiments of each module can be combined with each other; however, examples and accompanying drawings of such combinations will not be provided here. Figure 7 Only the delay control module 110 and additional technical features are shown in the illustration. For simplicity, the first control module 120 and the second control module 130 are not shown, but in practical applications... Figure 7 The illustrated embodiment should include a first control module 120 and a second control module 130.

[0075] Figures 1-6 The illustrated embodiment addresses the power-on anomaly caused by heavy load voltage drop by providing light-load display data and / or reducing the panel refresh rate during power-on. Furthermore, it improves the power-on load reduction problem by using multiple control transistors Tc to lower the power-on resolution. Specifically, taking an N-type MOS transistor as an example, when the delay control module 110 outputs a low-level first control signal during power-on, each control transistor Tc is turned off. Therefore, the gate drive circuit 400 can only receive half of the clock signal at this time. Figure 8 As shown, only the odd-numbered rows of scan lines in the display panel can be turned on, thereby reducing the current drawdown of the display panel; after power-on stabilization, when the delay control module 110 outputs a high-level second control signal, each control transistor Tc is turned on, and the gate drive circuit 400 can receive all the clock signals, turning on all the scan lines in the display panel row by row.

[0076] In another embodiment, the display panel further includes M clock signal lines 500. The two ends of the 2m-th clock signal line 500 are respectively connected to the 2m-th clock signal output terminal of the timing controller 200 and the 2m-th clock signal receiving terminal of the gate drive circuit 400. The load control circuit further includes: a plurality of control transistors Tc. The control terminal of the m-th control transistor Tc is connected to the output terminal of the delay control module 110. The first end of the m-th control transistor Tc is connected to the 2m-1-th clock signal output terminal of the timing controller 200. The second end of the m-th control transistor Tc is electrically connected to one end of the 2m-1-th clock signal line 500. The other end of the 2m-1-th clock signal line 500 is connected to the 2m-1-th clock signal receiving terminal of the gate drive circuit 400. M is an integer greater than 1.

[0077] This embodiment and Figure 7 The difference shown lies in whether odd-numbered or even-numbered scan lines are enabled; the other working principles are the same and will not be repeated here. Additionally, This means dividing M by 2 and rounding down, which is equivalent to when M is an even number. When M is odd

[0078] Figure 9 The diagram shown is a circuit diagram of the sixth load control circuit provided in an embodiment of this application; Figure 9 respectively with Figures 1-6 The difference is: Figure 8 In addition to the other load control circuit 100, it also includes a sixth transistor T6, a seventh transistor T7, a first inductor L1, and a second capacitor C2.

[0079] Specifically, the control terminal of the sixth transistor T6 is connected to the output terminal of the delay control module 110, and the first terminal of the sixth transistor T6 is connected to the output terminal of the external power supply 600; the control terminal of the seventh transistor T7 is connected to the control terminal of the sixth transistor T6, the first terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6, and the second terminal of the seventh transistor T7 is grounded; the first terminal of the first inductor L1 is connected to the first terminal of the seventh transistor T7, and the second terminal of the first inductor L1 is connected to the power supply terminal of the subsequent load 700; the first terminal of the second capacitor C2 is connected to the second terminal of the first inductor L1, and the second terminal of the second capacitor C2 is grounded; the turn-on voltages of the sixth transistor T6 and the seventh transistor T7 are opposite.

[0080] Here, taking the delay control module 110, which includes a differential amplifier U1 and a comparator U2, as an example, the working principle of the load control circuit 100 in this embodiment will be described in detail:

[0081] (1) The voltage difference between the current supply voltage Vin and the reference voltage Vref is input to comparator U2 using differential amplifier U1. Comparator U2 compares the voltage difference with a triangular wave (i.e., a reference threshold) to determine the pulse width of the output signal and control the output voltage. Optionally, comparator U2 generates the voltage difference by comparing the voltage error signal from the current supply voltage and the reference voltage with a constant sawtooth ramp waveform. The ramp is initiated by a clock signal from the oscillator, achieving good noise tolerance with a fixed ramp amplitude. Voltage regulation is independent of the output current. The voltage mode requires a fixed, predictable switching frequency and is also useful when there may be large output load variations.

[0082] (2) The conduction and shutdown of the sixth transistor T6 and the seventh transistor T7 are controlled by the output signal of the comparator U2. Specifically: if the current power supply voltage is less than the reference voltage, the delay control module 110 outputs a low level to turn on the sixth transistor T6, and charges the first inductor L1 and the second capacitor C2 through the output voltage of the external power supply 600, thereby raising the voltage at the power supply terminal of the subsequent load 700, so that the voltage is not pulled down when powering on or when switching heavy load screens; if the current power supply voltage is equal to or greater than the reference voltage, the delay control module 110 outputs a high level to turn on the seventh transistor T7, does not receive the output voltage of the external power supply 600, and discharges through the first inductor L1 and the second capacitor C2, thereby lowering the voltage at the power supply terminal of the subsequent load 700, so that the normal operating voltage is restored after the power-on is stable.

[0083] Meanwhile, the load control circuit 100 in this embodiment also adjusts the current display data or refresh rate through the first control module 120 and the second control module 130. Therefore, this embodiment adjusts the magnitude of the voltage received at the load end through the sixth transistor T6, the seventh transistor T7, the first inductor L1 and the second capacitor C2, and at the same time, in conjunction with the first control module 120 and the second control module 130 to adjust the current display data or refresh rate, which can further improve the problem of voltage drop under heavy load at startup and ensure the normal startup of the display panel.

[0084] It should also be noted that Figure 9 The downstream load 700 in the middle can be a general term for the timing controller, source drive circuit, gate drive circuit and other modules.

[0085] Secondly, embodiments of this application provide a display panel, including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a timing controller, a gate driving circuit, a source driving circuit, and a load control circuit. The load control circuit is electrically connected to the timing controller, the gate driving circuit, and the source driving circuit, respectively.

[0086] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A load control circuit, characterized in that, Applied to a display panel, the display panel includes a timing controller, a source drive circuit, and a gate drive circuit, and the load control circuit includes: The delay control module is used to output a first control signal when powered on, and to continuously output a second control signal after outputting the first control signal for a preset duration; A first control module, wherein the control terminal of the first control module is connected to the output terminal of the delay control module, the first terminal of the first control module is connected to the output terminal of the timing controller, and the second terminal of the first control module is connected to the source drive circuit or the gate drive circuit. The first control module is used to send the light-load display data output by the timing controller to the source drive circuit or send the power-on clock signal with a first clock frequency output by the timing controller to the gate drive circuit under the action of the first control signal. The second control module has its control terminal connected to the output terminal of the delay control module, its first terminal connected to the output terminal of the timing controller, and its second terminal connected to the source drive circuit or the gate drive circuit. Under the action of the second control signal, the second control module sends the normal display data output by the timing controller to the source drive circuit, or sends the normal clock signal with a second clock frequency output by the timing controller to the gate drive circuit; wherein the first clock frequency is less than the second clock frequency. The sixth transistor has its control terminal connected to the output terminal of the delay control module, and its first terminal connected to the output terminal of an external power supply. A seventh transistor, the control terminal of which is connected to the control terminal of the sixth transistor, the first terminal of which is connected to the second terminal of the sixth transistor, and the second terminal of which is grounded; The first inductor has its first end connected to the first end of the seventh transistor, and its second end connected to the power supply terminal of the subsequent load. The second capacitor has its first terminal connected to the second terminal of the first inductor, and its second terminal grounded. The turn-on voltages of the sixth transistor and the seventh transistor are opposite.

2. The load control circuit according to claim 1, characterized in that, The delay control module includes: The first resistor has its first end connected to the output terminal of an external power supply. A first capacitor, the first terminal of which is connected to the second terminal of the first resistor, and the second terminal of the first capacitor is grounded; The first transistor, wherein the control terminal of the first transistor is connected to the first terminal of the first capacitor; The second resistor has a first terminal grounded and a second terminal connected to the first terminal of the first transistor. The third resistor, the first end of which is connected to the output terminal of the external power supply; The second transistor has its control terminal connected to the control terminal of the first transistor, its first terminal connected to the second terminal of the third resistor, and its second terminal connected to the second terminal of the first transistor. The first transistor has a low turn-on voltage, the second transistor has a high turn-on voltage, and the second terminal of either the first transistor or the second transistor is used as the output terminal of the delay control module.

3. The load control circuit according to claim 1, characterized in that, The delay control module includes: A differential amplifier, wherein the first input terminal of the differential amplifier is connected to the reference voltage output terminal, and the second input terminal of the differential amplifier is connected to the power supply terminal of the timing controller, for amplifying the difference between the current power supply voltage and the reference voltage at the power supply terminal of the timing controller; The comparator has a first input terminal connected to a reference threshold terminal and a second input terminal connected to the output terminal of the differential amplifier. It is used to output the first control signal or the second control signal based on the comparison result between the voltage difference output by the differential amplifier and the reference threshold.

4. The load control circuit according to claim 1, characterized in that, The delay control module includes: The XOR gate has its first input connected to the voltage output at the first time point, its second input connected to the voltage output at the second time point, and its output serving as the output of the delay control module. Wherein, the first time-of-flight voltage output terminal is used to output the first power supply voltage of the power supply terminal of the timing controller at time t, and the second time-of-flight voltage output terminal is used to output the second power supply voltage of the power supply terminal of the timing controller at time t+N.

5. The load control circuit according to any one of claims 2-4, characterized in that, The first control module includes a third transistor, the control terminal of which is connected to the output terminal of the delay control module, the first terminal of which is connected to the first output terminal of the timing controller, and the second terminal of which is connected to the source drive circuit or the gate drive circuit. The second control module includes a fourth transistor, the control terminal of which is connected to the output terminal of the delay control module, the first terminal of which is connected to the second output terminal of the timing controller, and the second terminal of which is connected to the source drive circuit or the gate drive circuit. The turn-on voltages of the third transistor and the fourth transistor are opposite.

6. The load control circuit according to any one of claims 2-4, characterized in that, The first control module includes: An inverter, the input of which is connected to the output of the delay control module, is used to invert the output signal of the delay control module. The first AND gate has its first input connected to the first output of the timing controller, its second input connected to the output of the inverter, and its output connected to the source drive circuit or the gate drive circuit. When a high level is received at the second input, the gate is used to send the light-load display data or power-on clock signal output by the timing controller to the source drive circuit or the gate drive circuit, respectively.

7. The load control circuit according to claim 6, characterized in that, The second control module includes: The fifth transistor has its control terminal connected to the output terminal of the delay control module, and its first terminal connected to the enable terminal of the timing controller. The second AND gate has its first input connected to the second terminal of the fifth transistor, its second input connected to the output of the timing controller, and its output connected to the source drive circuit or the gate drive circuit. When the first input receives a high level, the second AND gate sends the normal display data or normal clock signal output by the timing controller to the source drive circuit or the gate drive circuit.

8. The load control circuit according to claim 1, characterized in that, The display panel further includes M clock signal lines, with the two ends of the (2m-1)th clock signal line respectively connected to the (2m-1)th clock signal output terminal of the timing controller and the (2m-1)th clock signal receiving terminal of the gate drive circuit. The load control circuit further includes: Multiple control transistors are provided. The control terminal of the m-th control transistor is connected to the output terminal of the delay control module. The first terminal of the m-th control transistor is connected to the 2m-th clock signal output terminal of the timing controller. The second terminal of the m-th control transistor is electrically connected to one end of the 2m-th clock signal line. The other end of the 2m-th clock signal line is connected to the 2m-th clock signal receiving terminal of the gate drive circuit. Alternatively, the display panel may further include M clock signal lines, with the two ends of the 2mth clock signal line connected to the 2mth clock signal output terminal of the timing controller and the 2mth clock signal receiving terminal of the gate drive circuit, respectively. The load control circuit may further include: Multiple control transistors are provided. The control terminal of the m-th control transistor is connected to the output terminal of the delay control module. The first terminal of the m-th control transistor is connected to the (2m-1)-th clock signal output terminal of the timing controller. The second terminal of the m-th control transistor is electrically connected to one end of the (2m-1)-th clock signal line. The other end of the (2m-1)-th clock signal line is connected to the (2m-1)-th clock signal receiving terminal of the gate drive circuit. in, M is an integer greater than 1.

9. A display panel, comprising a display area and a non-display area, characterized in that, The display area includes a pixel array; The non-display area includes a timing controller, a gate driving circuit, a source driving circuit, and a load control circuit as described in any one of claims 1-8, wherein the load control circuit is electrically connected to the timing controller, the gate driving circuit, and the source driving circuit, respectively.

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