Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a driving circuit; the driving circuit comprises N levels of shift register units which are cascaded with each other. In the same shift register unit, an initial control module is used for at least receiving an input signal, a first clock signal and a second clock signal, and controlling signals of a first initial node and a second initial node; the stage transmission output module is used for at least receiving a signal of a first initial node, a signal of a second initial node, a first level signal and a second level signal, and controlling a stage transmission signal; the auxiliary driving module is used for at least receiving an auxiliary control signal, a third clock signal, a fourth clock signal and a second level signal, and controlling an auxiliary driving signal; and the driving output module is used for receiving a driving control signal, a signal of the first initial node, a signal of the second initial node, a stage transmission signal, an auxiliary driving signal, a first level signal, a second level signal and a control gate driving signal, so that the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, display panels have penetrated into every aspect of our daily lives. Display panels can use different image refresh rates in different application scenarios. For example, a higher refresh rate (also known as high-frequency drive) can be used to drive dynamic images to ensure smooth display, while a lower refresh rate (also known as low-frequency drive) can be used to drive static images to reduce power consumption.

[0003] In order to achieve the image refresh function, the pixel circuits of the display panel are usually scanned with a scanning cycle that matches the image refresh frequency. At this time, a driving circuit is usually provided in the display panel, and the enable level of the gate driving signal is provided to each row of pixel circuits in turn through each shift register in the driving circuit, so that the display units driven by each row of pixel circuits can display.

[0004] In order to meet the diversified display effects of partitioned display, a gating circuit is usually set in the shift register to select whether to transmit the enable level of the gate drive signal to the pixel circuit according to the refresh frequency of the area where the pixel is located.

[0005] However, in a multi-frequency driving mode that satisfies partition refresh, the shift register can only output one valid pulse of the gate driving signal in one refresh cycle, which cannot meet the pixel circuit's multi-pulse requirement for the gate driving signal. Summary of the Invention

[0006] The present invention provides a display panel and a display device, which can realize multi-pulse output of a gate drive signal on the basis of realizing partition refresh.

[0007] According to one aspect of the present invention, there is provided a display panel, comprising: a driving circuit;

[0008] The driving circuit includes N stages of shift register units cascaded with each other; the shift register unit includes an initial control module, a stage transmission output module, an auxiliary driving module and a driving output module;

[0009] In the same shift register unit, the initial control module is used to receive at least an input signal, a first clock signal and a second clock signal, and control the signals of the first initial node and the second initial node;

[0010] The level transmission output module is used to receive at least the signal of the first initial node, the signal of the second initial node, the first level signal and the second level signal, and control the level transmission signal;

[0011] The auxiliary driving module is used to receive at least the auxiliary control signal, the third clock signal, the fourth clock signal and the second level signal, and control the auxiliary driving signal;

[0012] The driving output module is used to receive the driving control signal, the signal of the first initial node, the signal of the second initial node, the stage transmission signal, the auxiliary driving signal, the first level signal and the second level signal, and control the gate driving signal;

[0013] Among them, the level transmission signal of the shift register unit of the i-th level is the input signal of the shift register unit of the j-th level; and the auxiliary driving signal of the shift register unit of the i-th level is the auxiliary control signal of the shift register unit of the j-th level; i, j and N are all positive integers, i≠j and i and j are both less than or equal to N.

[0014] According to another aspect of the present invention, a display device is provided, comprising the above-mentioned display panel.

[0015] The technical solution of the embodiment of the present invention uses the level transmission signal output by the intermediate output module of each shift register unit as the input signal of the shift register units of other levels, and controls the drive output module to output the gate drive signal through the drive control module, which is used as the drive signal of the pixel circuit in the display panel. This can make the level transmission signal and the gate drive signal output by the same shift register unit to other levels independent of each other and not affect each other, thereby ensuring that the level transmission and shifting of signals between the shift register units can be performed. At the same time, the polarity of the gate output signal provided to the pixel circuit can be flexibly controlled, so that the driving modes of the pixel circuits in different rows of the display panel can be the same or different, thereby enabling the display panel to meet diversified display requirements and broaden the application scenarios of the display panel. For example, different areas of the display panel can have different refresh frequencies. On this basis, by providing an auxiliary drive module in the shift register unit, the auxiliary drive signal output by the auxiliary drive module can control the shift register unit corresponding to the high-frequency refresh area to ensure multi-pulse output of the gate drive signal, thereby meeting the multi-pulse gate drive signal requirement of the pixel circuit in the high-frequency refresh area, which is conducive to improving the display effect of the display panel.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a structural diagram of a shift register unit in the prior art;

[0019] Figure 2 This is a schematic structural diagram of a display panel in the prior art;

[0020] Figure 3 This is a driving timing diagram of a shift register unit in the prior art;

[0021] Figure 4 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0022] Figure 5 1 is a structural diagram of a shift register unit provided by an embodiment of the present invention;

[0023] Figure 6 This is a driving timing diagram of a shift register unit provided by an embodiment of the present invention;

[0024] Figure 7 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0025] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0026] Figure 9 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0027] Figure 10 is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0028] Figure 11 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0029] Figure 12 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0030] Figure 13 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0031] Figure 14 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0032] Figure 15 This is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0033] Figure 16 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0034] Figure 17 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0035] Figure 18 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0036] Figure 19 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0037] Figure 20 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0038] Figure 21 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0039] Figure 22 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0040] Figure 23 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0041] Figure 24 This is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0042] Figure 25 This is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0043] Figure 26 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] As described in the background technology, Figure 1 This is a structural diagram of a shift register unit in the prior art. Figure 1 As shown, the shift register unit 01′ includes an initial control module 011′, a stage transmission output module 012′, and a driver output module 013′. The initial control module 011′ receives at least the input signal Vin′, the first clock signal ck1′, and the second clock signal ck2′, and controls the signals of the first initial node N1′ and the second initial node N2′. The stage transmission output module 012′ receives the signals of the first initial node N1′ and the second initial node N2′, and outputs a stage transmission signal Vnext′, which can serve as the input signal of the next stage shift register unit 01′. The driver output module 013′ receives the drive control signal Vct′, the signals of the first initial node N1′ and the second initial node N2′, and is used to control the signal of the drive control node N3′. The driver output module 014′ receives the signals of the drive control node N3′ and the second initial node N2′, and outputs the gate drive signal Gout′.

[0047] Figure 2 This is a schematic diagram of the structure of a display panel in the prior art. Figure 1 and Figure 2, the display panel 100′ may include a first display area A1′ and a second display area A2′, and the refresh frequency of the first display area A1′ is greater than the refresh frequency of the second display area A2′. In each level of shift register unit G′, the first level shift register unit receives the start signal Stv′, and the input signal Vin′ of the next level shift register unit is the level transfer signal Vnext′ of the previous level shift register unit. Then, when the display screen is displayed in a partition refresh mode, when each shift register unit G′ connected to the first display area A1′ sequentially outputs the level transfer signal Vnext′ as a valid level, the drive control signal Vct′ can be maintained at an enable level, so that the gate drive signal Gout′ of the shift register unit G′ is consistent with the frequency of the level transfer signal Vnext′ outputting the valid level, that is, when the level transfer signal Vnext′ is a valid level, the drive output module 013′ outputs the valid level of the gate drive signal Gout′, thereby performing high-frequency refresh on the pixel circuit 10′, achieving high frequency display; and when the shift register G′ connected to the second display area A2′ sequentially outputs the level transfer signal Vnext′ as a valid level, the driving control signal Vct′ jumps to the non-enable level. At this time, whether the level transfer signal Vnext′ output by the shift register unit 01′ corresponding to the second display area A2′ is a valid level or an invalid level, the gate driving signal Gout′ output by the driving output module 013′ is always maintained at an invalid level, so that the frequency of the effective level of the gate driving signal Gout′ provided to the pixel circuit 10′ is reduced, thereby achieving low-frequency display.

[0048] Figure 3 This is a driving timing diagram of a shift register unit in the prior art, combined with reference Figure 1 、 Figure 2 and Figure 3, the shift register unit 01′ adjacent to the second display area A2′ in the first display area A1′ is the first shift register unit G01′, the shift register unit 01′ adjacent to the first display area A1′ in the second display area A2′ is the second shift register unit G02′, and the level transmission signal Vnext01′ of the first shift register unit G01′ is the input signal VIN02′ of the second shift register unit G02′. The moment when the drive control signal Vct′ jumps from the enable level to the non-enable level is the first moment t1′. Since for the shift register unit G′ that realizes high-frequency refresh, the gate drive signal Gout′ and the level transmission signal Vnext′ synchronously output the valid level, if the gate drive signal Gout′ is to realize multiple pulse outputs within one refresh cycle, the level transmission signal Vnext′ needs to output multiple valid pulses within one refresh cycle. Taking the high-frequency refresh shift register unit G' outputting two valid pulses of the gate drive signal Gout' in one refresh cycle as an example, when the display panel 100' operates in the partition refresh mode, for the first shift register unit G01', after its level transmission signal Vnext01' outputs the first valid level (high level), in order to make the gate drive signal Gout02' of the second shift register unit G02' of the second display area A2' not output the valid level and remain at the invalid level (low level), before the level transmission signal Vnext02' of the second shift register unit G02' in the second display area A2' outputs the valid level (i.e., at time t1'), the control driving control signal Vct' is controlled to jump from the enable level (low level) to the disable level (high level), then at the level transmission signal Vnext02' of the first shift register unit G01', the gate drive signal Gout02' of the second shift register unit G02' is output. When the transmission signal Vnext01′ outputs the second valid pulse, its driving output module 013′ cannot synchronously output the valid pulse of the gate driving signal Gout01′ because the driving control signal Vct′ has become a non-enable level (high level), so that the gate driving signal Gout01′ of the first shift register unit G01′ can only output one valid pulse in one refresh cycle, and cannot achieve multi-pulse output of the gate driving signal Gout01′, thereby failing to meet the pixel circuit 10′’s multi-pulse requirement for the gate driving signal Gout01′, affecting the display effect of the corresponding pixel circuit 10′, for example, during the display process of the pixel circuit 10′, it is impossible to adjust its bias and an obvious ghosting phenomenon occurs, or it is impossible to write the data signal to the driving transistor T0, resulting in inaccurate display.

[0049] To solve the above technical problems, an embodiment of the present invention provides a display panel, which includes a driving circuit; the driving circuit includes N-stage shift register units cascaded with each other; the shift register unit includes an initial control module, a stage transmission output module, an auxiliary driving module and a driving output module; in the same shift register unit, the initial control module is used to receive at least an input signal, a first clock signal and a second clock signal, and control the signals of the first initial node and the second initial node; the stage transmission output module is used to receive at least a signal of the first initial node, a signal of the second initial node, a first level signal and a second level signal, and control the stage transmission signal; the auxiliary driving module The block is used to receive at least an auxiliary control signal, a third clock signal, a fourth clock signal and a second level signal to control the auxiliary drive signal; the drive output module is used to receive the drive control signal, the signal of the first initial node, the signal of the second initial node, the level transmission signal, the auxiliary drive signal, the first level signal and the second level signal to control the gate drive signal; wherein, the level transmission signal of the i-th stage shift register unit is the input signal of the j-th stage shift register unit; and, the auxiliary drive signal of the i-th stage shift register unit is the auxiliary control signal of the j-th stage shift register unit; i, j and N are all positive integers, i≠j and i and j are both less than or equal to N.

[0050] With the above technical solution, by using the level transmission signal output by the intermediate transmission output module of each shift register unit as the input signal of the shift register units of other levels, and controlling the drive output module to output the gate drive signal through the drive control module as the drive signal of the pixel circuit in the display panel, the level transmission signal and the gate drive signal output by the same shift register unit to other levels can be independent of each other and do not affect each other, thereby ensuring that the level transmission and shifting of signals between the shift register units can be performed. At the same time, the polarity of the gate output signal provided to the pixel circuit can be flexibly controlled, so that the driving modes of the pixel circuits in different rows of the display panel can be the same or different, thereby enabling the display panel to meet diversified display requirements and broaden the application scenarios of the display panel. For example, different areas of the display panel can have different refresh frequencies. On this basis, by providing an auxiliary drive module in the shift register unit, the auxiliary drive signal output by the auxiliary drive module can control the shift register unit corresponding to the high-frequency refresh area to ensure multi-pulse output of the gate drive signal, thereby meeting the multi-pulse gate drive signal requirement of the pixel circuit in the high-frequency refresh area, which is conducive to improving the display effect of the display panel.

[0051] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without inventive work are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0052] Figure 4 is a structural diagram of a display panel provided by an embodiment of the present invention, Figure 5 This is a structural diagram of a shift register unit provided by an embodiment of the present invention, combined with reference Figure 4 and Figure 5 The display panel 100 includes a driving circuit 10; the driving circuit 10 includes N stages of shift register units G (G1, G2, ..., Gi, ..., Gj, ..., Gn-1, Gn) cascaded with each other; the shift register unit G includes an initial control module 110, a stage transmission output module 120, an auxiliary driving module 130 and a driving output module 140; in the same shift register unit G, the initial control module 110 is used to receive at least an input signal Vin, a first clock signal ck1 and a second clock signal ck2, and control the signals of the first initial node N1 and the second initial node N2; the stage transmission output module 120 is used to receive at least a signal of the first initial node N1, a signal of the second initial node N2, a first level signal Vgl and a second level signal Vgh, and control the stage transmission signal Vnext; the auxiliary driving module 1 30 is used to receive at least the auxiliary control signal Vac, the third clock signal ck3, the fourth clock signal ck4 and the first level signal Vgl, and control the auxiliary drive signal Vad; the drive output module 140 is used to receive the drive control signal Vct, the signal of the first initial node N1, the signal of the second initial node N2, the level transmission signal Vnext, the auxiliary drive signal Vad, the first level signal Vgl and the second level signal Vgh, and control the gate drive signal Gout; wherein, the level transmission signal Vnext of the i-th stage shift register unit Gi is the input signal Vin of the j-th stage shift register unit; and, the auxiliary drive signal Vad of the i-th stage shift register unit Gi is the auxiliary control signal Vac of the j-th stage shift register unit; i, j and N are all positive integers, i≠j and i and j are both less than or equal to N.

[0053] Exemplarily, the display panel 100 may further include a plurality of pixel circuits 20 arranged in an array. It should be noted that the above description is merely illustrative of an example in which the driver circuit 10 is located in the non-display area A1 and the pixel circuit 20 is located in the display area A2. In other embodiments of the present invention, both the pixel circuit 20 and the driver circuit 10 may be located in the display area A2, so that the number of devices disposed in the non-display area A1 of the display panel 100 is sufficiently small, thereby reducing the size of the non-display area A1 of the display panel 100, thereby facilitating a narrow bezel of the display panel 100 and enabling the display panel 100 to have a higher screen-to-body ratio.

[0054] For ease of description, without special limitations, the embodiments of the present invention take the driving circuit 10 located in the non-display area A1 of the display panel 100 and the pixel circuit 20 located in the display area A2 of the display panel 100 as an example to exemplify the technical solutions of the embodiments of the present invention.

[0055] For example, in the multi-frequency driving mode, different areas of the display panel 100 have different refresh frequencies. Figure 4 The display area A2 may include a low-frequency display area A21 and a high-frequency display area A22. In the multi-frequency driving mode, the refresh frequency of the pixel circuits 20 in the high-frequency display area A21 is lower than the refresh frequency of the pixel circuits 20 in the low-frequency display area A22. The shift register unit G electrically connected to the pixel circuits 20 in the low-frequency display area A21 is a first-type shift register unit G01, and the shift register unit G electrically connected to the pixel circuits 20 in the high-frequency display area A22 is a second-type shift register unit G02. Figure 6 This is a driving timing diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Figures 4 to 6 The operating mode of the display panel 100 includes a first mode Mode1, and the first operating mode Mode1 can be a multi-frequency driving mode. The display frame of the first mode Mode1 includes a first display frame DF1 and at least one second display frame DF2. In the first display frame DF1, the gate driving signal Gout output by each level of shift register unit G in the driving circuit 10 includes a valid pulse to refresh the signal of each row of pixel circuits 20 in the display area A2; and in the second display frame DF2, only the gate driving signal Gout02 output by each second type of shift register unit G02 includes a valid pulse to achieve signal refresh of each row of pixel circuits 20 in the high-frequency display area A22, and the gate driving signal Gout01 output by each first type of shift register unit G01 does not include a valid pulse, so that the pixel circuits 20 in the low-frequency display area A21 do not undergo signal refresh, and display is performed according to the grayscale data written in the previous display frame. In the first display frame DF1 and the second display frame DF2, the level transmission signal Vnext01 output by the first type shift register unit G01 and the level transmission signal Vnext02 output by the second type shift register unit G02 both include valid pulses, so that the input signal Vin01 received by each level of the first type shift register unit G01 and the input signal Vin02 received by each level of the second type shift register unit G02 both include valid pulses, so as to realize the driving of the next level shift register unit G.

[0056] It is understandable that Figure 6It is exemplified in the figure that the effective pulses of the level transfer signal Vnext and the gate drive signal Gout are high-level signals for controlling the NMOS transistor in the pixel circuit 20. In other feasible embodiments of the present invention, the effective pulses of the level transfer signal Vnext and the gate drive signal Gout may also be low-level signals for controlling the PMOS transistor in the pixel circuit 20. The embodiments of the present invention do not specifically limit this.

[0057] Continue to refer Figure 4 and Figure 5 , the output end of the level transmission output module 120 of the i-th level shift register unit Gi can be electrically connected to the input end of the initial control module 110 of the j-th level shift register unit Gj, so that the level transmission signal Vnext output by the level transmission output module 120 of the i-th level shift register unit Gi can be the input signal Vin of the initial control module 110 of the j-th level shift register unit Gi. Among them, the i-th level shift register unit Gi and the j-th level shift register unit Gj can be two adjacent levels of shift register units, in which case, j can be equal to i+1. Alternatively, the i-th level shift register unit Gi and the j-th level shift register unit Gj can also be two non-adjacent levels of shift register units G, in which case ji can be a positive integer greater than or equal to 2. Under the premise of being able to achieve the core inventive point of the embodiment of the present invention, the values of i and j in the embodiment of the present invention are not specifically limited.

[0058] For ease of description, without special limitations, the embodiments of the present invention take the i-th stage shift register unit Gi and the i-th stage shift register unit Gj as two adjacent stages of shift register units G as an example to exemplify the technical solutions of the embodiments of the present invention.

[0059] Continue to refer Figure 4 and Figure 5 In the same shift register unit G, the initial control module 110 and the stage transmission output module 120 can be electrically connected to the first initial node N1 and the second initial node N2, respectively, and the initial control module 110 can also be electrically connected to the driving output module 140 at the first initial node N1 and the second initial node N2, respectively, and the driving output module 140 is also electrically connected to the output end of the stage transmission output module 120, and the driving output module 140 is also electrically connected to the output end of the auxiliary driving module 130.

[0060] For the first-stage shift register unit G1, the input signal Vin received by its initial control module 110 can be a start signal Stv provided by a start control circuit (not shown in the figure), so that the first-stage shift register unit G1 can respond to at least the start signal Stv and the first clock signal ck1 and provide corresponding signals to its first initial node N1 and second initial node N2 respectively. For the shift register units G of the other stages except the first-stage shift register unit G1, the input end of the initial control module 110 can be electrically connected to the output end of the stage transmission output module 120 of the previous-stage shift register unit G, so that the shift register units G of each stage can respond to at least the stage transmission signal Vnext and the first clock signal ck1 output by the stage transmission output module 120 of the previous-stage shift register unit G and provide corresponding signals to its first initial node N1 and second initial node N2. In the same shift register unit G, the polarities of the signals at the first initial node N1 and the second initial node N2 can be the same or opposite. In an optional embodiment, at least part of the time, the polarities of the signals of the first initial node N1 and the second initial node N2 are opposite, that is, when the signal of the first initial node N1 is at a high level, the signal of the second initial node N2 may be at a low level; or, when the signal of the first initial node N1 is at a low level, the signal of the second initial node N2 is at a high level.

[0061] Accordingly, in the same shift register unit G, the stage transmission output module 120 can output a corresponding stage transmission signal Vnext based on the received signal of the first initial node N1 and the second initial node N2. For example, when the signal of the first output node N1 is at the enable level, the stage transmission output module 120 can output the first level signal Vgl as the stage transmission signal Vnext, and when the signal of the second output node N2 is at the enable level, the stage transmission output module 120 can output the second level signal Vgh as the stage transmission signal Vnext.

[0062] The auxiliary driving module 130 can output a corresponding auxiliary driving signal Vad to the driving output module 140 based on at least the auxiliary control signal Vac, the third clock signal ck3, the fourth clock signal ck4, and the second level signal Vgh it receives. For example, under the control of the auxiliary control signal Vac and the third clock signal ck3, the auxiliary driving module 130 can output the high level, low level, or second level signal Vgh of the fourth clock signal ck4 as the auxiliary driving signal Vad to the driving output module 140. In this way, by providing the auxiliary driving module 130 in the shift register unit G, the auxiliary driving module 130 controls the auxiliary driving signal Vad based on at least the auxiliary control signal Vac, the third clock signal ck3, the fourth clock signal ck4, and the second level signal Vgh. This allows the auxiliary driving signal Vad to be controlled by the auxiliary control signal Vac, the third clock signal ck3, the fourth clock signal ck4, and the second level signal Vgh simultaneously. This allows the auxiliary driving signal Vad to be independently controlled without being affected by the first initial node N1, the second initial node N2, and the stage transfer signal Vnext. The driving signal Vad affects the number of valid levels of the gate driving signal Gout output by the driving output module 140. For example, for a shift register unit G that has already output a valid pulse within a refresh cycle (i.e., the shift register unit G corresponding to the high-frequency refresh area A21), the enable level of the auxiliary driving signal Vad can control the driving output module 140 to continue outputting a second, or even a third, or multiple valid pulses. However, for a shift register unit G that has not output the first valid pulse (i.e., the shift register unit G corresponding to the low-frequency refresh area A22), the driving output module 140 does not continue outputting the second, third, or multiple subsequent valid pulses. Furthermore, the auxiliary driving signal Vad, as another stage transmission signal that can be transmitted to the input end of the auxiliary driving module 130 in the next-stage shift register unit G, can cause the auxiliary driving signal Vad of each stage of the shift register unit G to shift sequentially, so that each stage of the shift register unit G can receive the enable level of the auxiliary driving signal Vad at the corresponding time, thereby controlling the number of valid pulses of the gate driving signal Gout output by each stage of the shift register unit G.

[0063] The driver output module 140 can output a corresponding gate drive signal Gout based on at least the drive control signal Vct, the signal at the first initial node N1, the signal at the second initial node N2, the level transmission signal Vnext, the auxiliary drive signal Vad, the first level signal Vgl, and the second level signal Vgh. For example, when the drive control signal Vct is at an enable level, the gate drive signal Gout output by the driver output module 140 is the same as the level transmission signal Vnext and can output a valid level simultaneously with the level transmission signal Vnext. When the drive control signal Vct is at a disable level, the gate drive signal Gout output by the driver output module 140 remains at a disable level. At the same time, under the control of the enable level of the auxiliary drive signal Vad, the shift register unit G corresponding to the high-frequency refresh area A21 can be unaffected by the change of the drive control signal Vct from the enable level to the disable level and can output multiple valid pulses following the level transmission signal Vnext within a refresh cycle, without affecting the multiple pulse output of the gate drive signal Gout of the shift register unit G corresponding to the high-frequency refresh area.

[0064] It is understood that the level transmission signal Vnext and the gate drive signal Gout can both be pulse signals consisting of a high level and a low level, and one of the high level and the low level is an enable level and the other is a disable level. When the level transmission signal Vnext and the gate drive signal Gout output by the same shift register unit G are different, the level transmission signal Vnext and the gate drive signal Gout output by the same shift register unit G can have different periods, different enable level durations, different numbers of enable level pulses, etc., which can be set according to actual needs and are not specifically limited in the embodiment of the present invention.

[0065] It can also be understood that the gate drive signal Gout output by the drive output module 140 of each level of the shift register unit G can be respectively provided to each row of pixel circuits 20. The pixel circuit 20 can include a preset module, so that the gate drive signal Gout output by the shift register unit G can control the preset module in the pixel circuit 20 to turn on or off. That is, when the gate drive signal Gout output by the shift register unit G is at an enable level, the preset module of the pixel circuit 20 can be controlled to turn on, and when the gate drive signal Gout output by the shift register unit G is at a non-enable level, the preset module of the pixel circuit 20 can be controlled to turn off, thereby refreshing the signal in the pixel circuit 20. The pixel circuit 20 may further include other modules, and the embodiment of the present invention does not specifically limit the specific structure of the pixel circuit 20.

[0066] For example, Figure 7 is a structural diagram of a pixel circuit provided by an embodiment of the present invention, such as Figure 7As shown, the pixel circuit 20 includes a driving transistor T0, a data writing module 210, a bias adjustment module 220, a reset module 230, a threshold compensation module 240 and a light-emitting element D0; the data writing module 210 is used to receive a data signal Vdata and a first scan control signal S1, and write the data signal Vdata to the gate of the driving transistor T0 under the control of the first scan control signal S1; the bias adjustment module 220 is used to receive a bias adjustment signal DVH and a second scan control signal S2, and control the signal transmission path of the bias adjustment signal DVH to the driving transistor T0 according to the second scan control signal S2; the reset module 230 is used to receive a reset signal Vref and a second scan control signal S2, and control the signal transmission path of the reset signal Vref to the light-emitting element D0 according to the second scan control signal S2; the threshold compensation module 240 is used to receive a third scan control signal S3, and compensate the threshold compensation voltage to the gate of the driving transistor T0 under the control of the third scan control signal S3; wherein the third scan control signal S3 is the gate drive signal Gout.

[0067] Specifically, since the light-emitting element D0 is typically a current-driven element, and the data signal Vdata provided by the data writing module 210 is typically a voltage signal, the pixel circuit 20 is configured to include a driving transistor T0, so that the data signal Vdata provided by the data writing module 210 can be written to the gate of the driving transistor T0. This allows the driving transistor T0 to generate a corresponding driving current based on the signal at its gate and provide the current to the light-emitting element D0, thereby driving the light-emitting element D0 to emit light of a corresponding brightness. In this case, one of the source and drain of the driving transistor T0 receives the positive power signal PVDD, and the other is coupled to the anode of the light-emitting element D0. The cathode of the light-emitting element D0 can receive the negative power signal PVEE. Thus, a voltage difference exists between the positive power signal PVDD and the negative power signal PVEE, forming a current path. This allows the driving transistor T0 to generate a driving current and provide the current to the light-emitting element D0, thereby driving the light-emitting element D0 to emit light.

[0068] It is understandable that if Figure 7 As shown, the active layer material of the driving transistor T0 may include low-temperature polysilicon material, so that it has a high carrier mobility, thereby meeting the requirements of high reaction speed and low power consumption. In this case, the driving transistor T0 may be a PMOS transistor. In other optional embodiments, Figure 8 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 8As shown, the active layer material of the driving transistor T0 may also include an oxide semiconductor material. In this case, the driving transistor T0 may be an NMOS transistor. The present invention does not specifically limit the material and type of the driving transistor T0 as long as the core invention of the present invention can be achieved.

[0069] Accordingly, the data writing module 210 can be connected to the first electrode of the driving transistor T0 to provide the data signal Vdata to the driving transistor T0. The bias adjustment module 220 can be connected to the first electrode or the second electrode of the driving transistor to provide the bias adjustment signal DVH to the driving transistor T0 to adjust the bias of the driving transistor T0. The reset module 230 can be connected to the anode of the light-emitting element D0 to provide a reset signal Vref to the anode of the light-emitting element D0 to reset the anode voltage of the light-emitting element D0.

[0070] Among them, the control end of the data writing module 210 can receive a first scanning control signal S1, and the first scanning control signal S1 controls the data writing module 210 to be turned on or off; the control end of the bias adjustment module 220 receives a second scanning control signal S2, and the second scanning control signal S2 controls the bias adjustment module 220 to be turned on or off; the control end of the reset module 230 receives a second scanning control signal S2, and the second scanning control signal S2 controls the reset module 230 to be turned on or off.

[0071] When the first scanning signal S1 controls the data writing module 210 to turn on, the data signal Vdata can be written to the first electrode of the driving transistor T0 through the data writing module 210 to refresh the signal of the first electrode of the driving transistor T0; if the driving transistor T0 is in the turned-on state at this time, and the third scanning signal S3 controls the threshold compensation module 240 to turn on, then the data signal Vdata can also be provided to the second electrode of the driving transistor T0 through the driving transistor T0, and provided to the gate of the driving transistor T0 through the threshold compensation module 240, and the threshold voltage Vth of the driving transistor T0 is compensated to the gate of the driving transistor T0, so that the signals of the gate and the second electrode of the driving transistor T0 can be refreshed, so that the driving current generated by the driving transistor T0 can be independent of its threshold voltage Vth.

[0072] The bias adjustment module 220 can be turned on or off under the control of the second scanning control signal S2, and when the second scanning control signal S2 controls the bias adjustment module 220 to be turned on, the bias adjustment signal DVH can be provided to the first electrode and / or the second electrode of the driving transistor T0 to bias the driving transistor T0.

[0073] The reset module 230 is connected to the anode of the light-emitting element D0 and is configured to provide a reset signal Vref to the light-emitting element D0 to reset the anode of the light-emitting element 40. The reset module 230 can be turned on or off under the control of the second scan control signal S2, and when the second scan control signal S2 controls the reset module 230 to be turned on, the reset signal Vref can be provided to the anode of the light-emitting element D0.

[0074] In an exemplary embodiment, the data writing module 210 may include a data writing transistor T1, a first electrode of the data writing transistor T1 receiving a data signal Vdata, a second electrode of the data writing transistor T1 being electrically connected to a first electrode of the driving transistor T0, and a gate of the data writing transistor T1 receiving a first scanning control signal S1, so that the first scanning control signal S1 controls the turning on or off of the data writing transistor T1; the bias adjustment module 220 may include a bias adjustment transistor T2, a first electrode of the bias adjustment transistor T2 receiving a bias adjustment signal DVH, a second electrode of the bias adjustment transistor T2 being electrically connected to a first electrode or a second electrode of the driving transistor T0, and a gate of the bias adjustment transistor T2 receiving a second scanning control signal S2, so that the second scanning control signal S2 can Controlling the bias adjustment transistor T2 to turn on or off; the reset module 230 includes a reset transistor T3, a first electrode of the reset transistor T3 receives a reset signal Vref, a second electrode of the reset transistor T3 is electrically connected to the anode of the light-emitting element D0, and a gate of the reset transistor T3 receives a second scan control signal S2, so that the second scan signal S2 controls the turning on or off of the reset transistor T3; the threshold compensation module 240 includes a threshold compensation transistor T4, a first electrode of the threshold compensation transistor T4 is electrically connected to the second electrode of the driving transistor T0, a second electrode of the threshold compensation transistor T4 is electrically connected to the gate of the driving transistor T0, and the gate of the threshold compensation transistor T4 receives a third scan control signal S3, so that the third scan control signal S3 controls the turning on or off of the threshold compensation transistor T4.

[0075] Optional, continue to refer to Figure 6 or Figure 7The pixel circuit 20 further includes: an initialization module 250, a first light-emitting control module 260, a second light-emitting control module 270 and a storage module 280; the initialization module 250 is used to receive the initialization signal Vini and the fourth scan control signal S4, and control the signal transmission path of the initialization signal Vini to the driving transistor T0 according to the fourth scan control signal S4; the first light-emitting control module 260 and the second light-emitting control module 270 are used to receive the light-emitting control signal EM, and to control the driving transistor T0 to provide a driving current to the light-emitting element D0 according to the light-emitting control signal EM; one end of the storage module 280 receives a fixed voltage signal, and the other end of the storage module 280 is electrically connected to the gate of the driving transistor T0, and the storage module 280 is used to store the gate voltage signal of the driving transistor T0.

[0076] Specifically, the initialization module 250 can be connected to the gate of the driving transistor T0 to provide the initialization signal Vini to the gate of the driving transistor T0 to initialize the gate of the driving transistor T0. The control end of the initialization module 250 receives the fourth scan control signal S4, and the fourth scan control signal S4 controls the opening and closing of the initialization module 250. When the fourth scan signal S4 controls the initialization module 250 to be turned on, the initialization signal Vini can be transmitted to the gate of the driving transistor T0 to reset the gate voltage of the driving transistor T0, thereby clearing the data signal Vdata provided to the gate of the driving transistor T0 in the previous driving cycle and preparing for the subsequent writing of the data signal Vdata.

[0077] The initialization module 250 includes an initialization transistor T5, a first electrode of the initialization transistor T5 receives the initialization signal Vini, a second electrode of the initialization transistor T5 is electrically connected to the gate of the driving transistor T0, and the gate of the initialization transistor T5 receives the fourth scan control signal S4, so that the fourth scan control signal S4 controls the opening or closing of the initialization transistor T5.

[0078] The first and second light-emitting control modules 260 and 270 can control the current path between the positive power supply signal PVDD and the negative power supply signal PVEE, thereby controlling the timing at which the driving transistor T0 provides the driving current to the light-emitting element D0. The first and second light-emitting control modules 260 and 270 can be turned on or off under the control of the light-emitting control signal EM. When the light-emitting control signal EM turns the first and second light-emitting control modules 260 and 270 on, the driving transistor T0 can generate a driving current and provide this driving current to the light-emitting element 4D0, thereby driving the light-emitting element D0 to emit light.

[0079] In an exemplary embodiment, the first light-emitting control module 260 may include a first light-emitting control transistor T6, and the second light-emitting control module 270 may include a second light-emitting control transistor T7. The first electrode of the first light-emitting control transistor T6 receives a positive power supply signal PVDD, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the driving transistor T0, the first electrode of the second light-emitting control transistor T7 is electrically connected to the second electrode of the driving transistor T0, and the second electrode of the second light-emitting control transistor T7 is electrically connected to the anode of the light-emitting element D0. The gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T7 both receive a light-emitting control signal EM, so that the light-emitting control signal EM can control the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be turned on or off at the same time.

[0080] The storage module 280 may include a storage capacitor Cst, a first plate of which receives a fixed signal (eg, a positive power signal PVDD), and a second plate of which is electrically connected to the gate of the driving transistor T0 to store a signal at the gate of the driving transistor T0.

[0081] It should be noted that Figure 7 and Figure 8 The structures of two pixel circuits are provided as examples only, but not all. On the premise that the core invention points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not limit the specific structure of the pixel circuit.

[0082] Based on the above pixel circuit, the gate drive signal Gout can be provided as the third scanning control signal S3 to the threshold compensation module 240, which can control the threshold compensation transistor T4 to be turned on before writing the data signal Vdata to the driving transistor T0 to achieve bias adjustment of the driving transistor T0, and control the threshold compensation transistor T4 to be turned on when writing the data signal Vdata to write the data signal Vdata to the driving transistor T0. Figure 6 Taking the driving transistor T0, the data writing transistor T1, the bias adjustment transistor T2, the reset transistor T3, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 as PMOS transistors, and the initialization transistor T5 and the threshold compensation transistor T4 as NMOS transistors as an example, the working process of the pixel circuit provided by the embodiment of the present invention is exemplarily described.

[0083] Figure 9 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention, combined with reference to Figure 7 and Figure 9 The working process of the pixel circuit includes an initialization phase t1, a data writing phase t2, a bias adjustment phase t3 and a light emitting phase t4.

[0084] During the first bias adjustment phase t1, the emission control signal EM, the first scan control signal S1, and the third scan control signal S3 are at a high level, while the second scan control signal S2 and the fourth scan control signal S4 are at a low level. The emission control signal EM controls the first emission control transistor T6 and the second emission control transistor T7 to be turned off, the first scan control signal S1 controls the data write transistor T1 to be turned off, the fourth scan control signal S4 controls the initialization transistor T5 to be turned off, the second scan control signal S2 controls the bias adjustment transistor T2 and the reset transistor T3 to be turned on, and the third scan control signal S3 controls the threshold compensation transistor T4 to be turned on. As a result, the bias adjustment signal DVH is transmitted to the drive transistor T0 via the bias adjustment transistor T2, adjusting the bias state of the drive transistor T0. This reverse biases the drive transistor T0, weakens the polarization of particles within the drive transistor T0, and reduces the threshold voltage of the drive transistor T0. The threshold voltage of the drive transistor T0 is adjusted via the bias adjustment transistor T2 to compensate for the threshold voltage drift caused by the hysteresis effect of the drive transistor T0 due to long-term forward bias. Exemplarily, the bias adjustment signal DVH can be a DC positive voltage signal with a larger voltage value, so that a larger instantaneous current can flow through the driving transistor T0 to adjust the bias defect problem inside the driving transistor T0, which can improve the hysteresis characteristics of the driving transistor T0, thereby weakening the bias effect of the previous frame display image, so that when the data signal Vdata of the current display image is written, the driving transistor T0 is closer to the initial state, thereby weakening the bias difference between the driving transistor T0 in the current frame display image and the previous frame display image, improving the threshold drift problem of the driving transistor T0, and thus improving the display effect.

[0085] In the initialization stage t2, the light-emitting control signal EM, the first scan control signal S1, the second scan control signal S2, and the fourth scan control signal S4 are at a high level, and the third scan control signal S3 is at a low level. The light-emitting control signal EM controls the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to turn off, the first scan control signal S1 controls the data writing transistor T1 to turn off, the second scan control signal S2 controls the bias adjustment transistor T2 and the reset transistor T3 to turn off, the third scan control signal S3 controls the threshold compensation transistor T4 to turn off, and the fourth scan control signal S4 controls the initialization transistor T5 to turn on. The turned-on initialization transistor T5 transmits the initialization signal Vini to the gate of the driving transistor T0, thereby initializing the gate of the driving transistor T0 and preparing for the writing of the data signal Vdata.

[0086] In the data writing phase t3, the light-emitting control signal EM, the second scanning control signal S2 and the third scanning control signal S3 are at a high level, the first scanning control signal S1 and the fourth scanning control signal S4 are at a low level, the light-emitting control signal EM controls the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be turned off, the second scanning control signal S2 controls the bias adjustment transistor T2 and the reset transistor T3 to be turned off, the fourth scanning control signal S4 controls the initialization transistor T5 to be turned off, and the first scanning control signal S1 controls the data writing transistor T1 to be turned on, and the third scanning control signal S3 controls the threshold compensation transistor T4 to be turned on. The turned-on data writing transistor T1 transmits the data signal Vdata to the first electrode of the driving transistor T0, and transmits it to the first electrode of the threshold compensation transistor T4 through the turned-on driving transistor T0; the turned-on threshold compensation transistor T4 transmits the voltage of the second electrode of the driving transistor T0 to the gate of the driving transistor T0 until the gate voltage of the driving transistor T0 is charged to the sum of the data signal Vdata and the threshold voltage of the driving transistor T0, and the driving transistor T0 is in a critical state of conduction.

[0087] In the second bias adjustment stage t4, the light-emitting control signal EM and the first scan control signal S1 are at a high level, the second scan control signal S2, the third scan control signal S3, and the fourth scan control signal S4 are at a low level, the light-emitting control signal EM controls the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be turned off, the first scan control signal S1 controls the data writing transistor T1 to be turned off, the third scan control signal S3 controls the threshold compensation transistor T4 to be turned off, and the fourth scan control signal S4 controls the initialization transistor T5 to be turned off, while the second scan control signal S2 controls the bias adjustment transistor T2 and the reset transistor T3 to be turned on. The turned-on reset transistor T3 transmits the reset signal Vref to the anode of the light-emitting element D0, thereby resetting the anode voltage of the light-emitting element D0 and preventing the charge retained in the previous driving cycle from affecting the luminous brightness of the current driving cycle. At the same time, the turned-on bias adjustment transistor T2 transmits the bias adjustment signal DVH to the first electrode of the driving transistor T0, so that the first electrode signal of the driving transistor T0 can be consistent with the bias adjustment signal DVH, ensuring that before entering the light-emitting stage, the first electrode signal of the driving transistor T0 remains the bias adjustment signal DVH, preventing the accuracy of the driving current provided by the driving transistor T0 from being affected by the different written data signals Vdata, thereby facilitating improving the light-emitting accuracy of the light-emitting element D0.

[0088] In the light-emitting stage t5, the light-emitting control signal EM, the third scan control signal S3 and the fourth scan control signal S4 are at a low level, the first scan control signal S1 and the second scan control signal S2 are at a high level, the first scan control signal S1 controls the data writing transistor T1 to be turned off, the second scan control signal S2 controls the bias adjustment transistor T2 and the reset transistor M8 to be turned off, the third scan control signal S3 controls the threshold compensation transistor T4 to be turned off, and the fourth scan control signal S4 controls the initialization transistor T5 to be turned off, while the light-emitting control signal EM controls the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be turned on; the turned-on first light-emitting control transistor T6 transmits the first power supply voltage provided by the first power supply PVDD to the first electrode of the driving transistor T0, and the driving transistor T0 generates a driving current according to the voltage of its first electrode and gate, and transmits the driving current to the second power supply PVEE through the turned-on second light-emitting control transistor T7 through the light-emitting element D0, so that the first power supply PVDD and the second power supply PVEE form a current path to drive the light-emitting element D0 to emit light.

[0089] Based on the operation process of the above-described pixel circuit, the third scanning control signal S3 received by the threshold compensation transistor T4 in the threshold compensation module 240 outputs a high level (enable level) in both the first bias adjustment phase t1 and the data writing phase t3, and outputs a low level (disabled level) in the initialization phase t2 between the first bias adjustment phase t1 and the data writing phase t3. This causes the threshold compensation transistor T4 to be turned on in the first bias adjustment phase t1 to adjust the bias of the drive transistor T0, and to be turned on in the data writing phase t3 to write data to the drive transistor T0. Therefore, the third scanning control signal S3 received by the threshold compensation module 240 in the pixel circuit 20 includes two valid pulses in one data refresh frame of the pixel circuit 20. As described in the background technology, in the multi-frequency driving mode of partitioned display, the shift register unit in the high-frequency display area close to the low-frequency display area may lose valid pulses. That is, after outputting a valid pulse, the second valid pulse cannot be output due to the jump of the driven control signal to the non-enabled level, making it impossible for the pixel circuit connected to the shift register unit to write data signals normally, thereby causing abnormal display of the pixel circuit in this row, affecting the display effect.

[0090] In the embodiment of the present invention, the auxiliary driving module 130 is not affected by the related signals of the initial control module 11 and the level transmission output module 120, so that the auxiliary driving signal Vad and the level transmission signal Vnext of the level transmission output module 120 are independent of each other, and the effective pulse of the auxiliary driving signal Vad can be output before the effective pulse of the level transmission signal Vnext is output by the level transmission output module 120. Figure 6In the same first-type shift register unit G01, the stage ta1 at which the auxiliary control signal Vac01 outputs a valid pulse is located before the stage tb1 at which the input signal Vin01 outputs a valid pulse, and after the shift output of the first-type shift register unit G01, the stage ta2 at which the auxiliary drive signal Vad01 outputs a valid pulse is located before the stage tb2 at which the level transfer signal Vnext01 outputs a valid pulse; and in the same second-type shift register unit G02, the stage ta3 at which the auxiliary control signal Vac02 outputs a valid pulse is located before the stage tb3 at which the input signal Vin02 outputs a valid pulse, and after the shift output of the second-type shift register unit G02, the stage ta4 at which the auxiliary drive signal Vad02 outputs a valid pulse is located before the stage tb4 at which the level transfer signal Vnext02 outputs a valid pulse. The driving output module 140 of the corresponding shift register unit G (for example, the shift register unit G connected to the pixel circuit 20 in the high-frequency refresh area A21) can be unaffected by the driving control signal Vct jumping from the enable level to the non-enable level, and can continue to output the second, third and other multiple valid pulses after outputting the first valid pulse, thereby ensuring the multi-pulse output of the gate driving signal Gout, thereby meeting the multi-pulse requirements of the pixel circuit 20 in the high-frequency refresh area A21 for the gate driving signal Gout, which is beneficial to improving the display effect of the display panel 100.

[0091] A display panel provided by an embodiment of the present invention uses the level transmission signal output by the level transmission output module of each level of shift register unit as the input signal of the shift register unit of other levels, and controls the drive output module to output a gate drive signal through a drive control module, which is used as the drive signal of the pixel circuit in the display panel. This allows the level transmission signal and the gate drive signal output by the same shift register unit to other levels to be independent of each other and not affect each other, thereby ensuring that the level transmission and shifting of signals between the shift register units can be performed. At the same time, the polarity of the gate output signal provided to the pixel circuit can be flexibly controlled, so that the driving modes of the pixel circuits in different rows of the display panel can be the same or different. This allows the display panel to meet diversified display requirements and broaden the application scenarios of the display panel. For example, different areas of the display panel can have different refresh frequencies. On this basis, by providing an auxiliary drive module in the shift register unit, the auxiliary drive signal output by the auxiliary drive module can control the shift register unit corresponding to the high-frequency refresh area to ensure multi-pulse output of the gate drive signal, thereby meeting the multi-pulse gate drive signal requirement of the pixel circuit in the high-frequency refresh area, which is conducive to improving the display effect of the display panel.

[0092] Optional, combined with reference Figures 4 to 6In the first type shift register unit G01, the frequency of the level transfer signal Vnext01 is F11, and the frequency of the gate drive signal Gout01 is F12; the operating mode of the display panel 100 includes the first mode Mode1; in the first mode Mode1, F11≠F12.

[0093] Specifically, when the display panel 100 operates in the first mode Mode1, the pulse change frequency F12 of the gate drive signal Gout01 of the first type shift register unit G01 is set to be different from the pulse change frequency F11 of the level transmission signal Vnext01, that is, the period of the gate drive signal Gout01 is different from the period of the level transmission signal Vnext01. At this time, when the display panel 100 operates in the first mode Mode1, the enable level time of the level transmission signal Vnext01 of the first type shift register unit G01 will be different from the non-enable level time of the gate drive signal Gout01. There is overlap, and / or, the time of the enable level of the gate drive signal Gout01 overlaps with the time of the non-enable level of the level transfer signal Vnext01, so that the time of the enable level of the level transfer signal Vnext01 provided to the next-level shift register unit G and the time of the enable level of the gate drive signal Gout01 provided to the pixel circuit do not overlap with each other, thereby making the gate drive signal Gout01 and the level transfer signal Vnext01 output by the same shift register unit G independent of each other and do not affect each other, which can meet the driving requirements of the driving circuit while ensuring that the display panel can display normally.

[0094] Optional, continue with reference Figures 4 to 6, in the first mode Mode1, F11>F12. Specifically, during the operation of the display panel 100 in the first mode, the pulse change frequency F11 of the level transmission signal Vnext01 of the first type shift register unit G01 is set to be greater than the pulse change frequency F12 of the gate drive signal Gout01, that is, the period T02 of the gate drive signal Gout01 is greater than the period T01 of the level transmission signal Vnext01, so that during the operation of the display panel 100 in the first mode Mode1, there is at least a portion of time when the enable level time of the level transmission signal Vnext01 of the first type shift register unit G01 overlaps with the non-enable level time of the gate drive signal Gout01, and / or there is another portion of time when the enable level time of the gate drive signal Gout01 overlaps with the enable level time of the level transmission signal Vnext01, so as to ensure that in a portion of the time period in the first mode, the first type shift register unit G01 normally shifts to the next stage. The device G provides a level transmission signal Vnext01 including an enable level, and provides a gate driving signal Gout01 of a non-enable level to the pixel circuit 20, so that the next-level shift register unit G can work normally, and the corresponding connected pixel circuit 20 will not perform signal refresh; and in another part of the time period under the first mode Mode1, the first-type shift register unit G01 provides a level transmission signal Vnext01 including an enable level to its next-level shift register unit G, and provides a gate signal Gout01 also including an enable level to the pixel circuit 20, so that the next-level shift register unit G can work normally while the pixel circuit 20 can perform signal refresh; in this way, during part of the time, the power consumption generated by the signal refresh in the pixel circuit 20 can be reduced, which is beneficial to the low power consumption of the display panel, and by refreshing the signal in the pixel circuit 20 in another part of the time, it can ensure the normal display of the display panel 100 and prevent the screen from flickering.

[0095] Optional, continue to refer to Figures 4 to 6 In the second type shift register unit G02 , the frequency of the stage transfer signal Vnext02 is F21 , and the frequency of the gate drive signal Gout02 is F22 ; in the first mode Mode1 , F21 = F22 .

[0096] Specifically, when the display panel 100 operates in the first mode Mode1, the pulse change frequency F21 of the level transmission signal Vnext02 of the second type shift register unit G02 is set to be equal to the pulse change frequency F22 of the gate drive signal Gout02, that is, the period of the gate drive signal Gout02 of the second type shift register unit G02 is equal to the period of the level transmission signal Vnext02, so that when the display panel 100 operates in the first mode, the time of the enable level of the level transmission signal Vnext02 of the second type shift register unit G02 will be equal to the time of the enable level of the gate drive signal Gout02. Overlap, and the time of the non-enable level of the gate drive signal Gout02 overlaps with the time of the non-enable level of the level transfer signal Vnext02, so as to ensure that in the first mode Mode1, the second type shift register unit G02 provides the level transfer signal Vnext02 and the gate drive signal Gout02 to its next level shift register unit G, both of which are enable level or non-enable level at the same time, so that the next level shift register unit G can work normally, and the corresponding connected pixel circuit 20 will also perform signal refresh, so that the pixel circuit connected to the second type shift register unit G02 can realize normal row-by-row scanning in the first working mode.

[0097] Optional, Figure 10 This is another driving timing diagram of the shift register unit provided by the embodiment of the present invention, and is further combined with reference to Figure 4 、 Figure 5 and Figure 10 , the operating mode of the display panel 200 also includes a second mode Mode2; in the second mode Mode2, F11 = F12.

[0098] Specifically, when the display panel 100 operates in the second mode, the pulse change frequency F11 of the level transmission signal Vnext01 of the first type shift register unit G01 is set to be equal to the pulse change frequency F12 of the gate drive signal Gout01, that is, the period T02 of the gate drive signal Gout01 of the first type shift register unit G01 is equal to the period T01 of the level transmission signal Vnext01, so that when the display panel 100 operates in the first mode Mode1, the time of the invalid pulse of the level transmission signal Vnext01 of the first type shift register unit G01 will be equal to the period T02 of the gate drive signal Gout01. The time of the invalid level overlaps, and the time of the valid pulse of the gate drive signal Gout01 overlaps with the time of the valid pulse of the level transfer signal Vnext01, so as to ensure that in the second mode, the first type of shift register unit G01 provides the level transfer signal Vnext01 and the gate drive signal Gout01 to its next level shift register unit G, both of which are at the enable level or at the non-enable level at the same time, so that the next level shift register unit G can work normally, and the corresponding connected pixel circuit will also perform signal refresh, so that the pixel circuit connected to the first type of shift register unit G01 can realize normal row-by-row scanning in the second mode.

[0099] It should be noted that in the shift register unit, because the auxiliary driver module receives at least the auxiliary control signal, the third clock signal, the fourth clock signal, and the second level signal, it is able to output valid pulses at corresponding stages under the control of each of the above signals, which is related to the specific structure of the auxiliary driver module. Furthermore, because the stage transmission output module receives at least the signal of the first initial node and the second initial node, the driver output module receives at least the drive control signal, the signal of the first initial node, the signal of the second initial node, the stage transmission signal, and the auxiliary driver signal to control the gate drive signal. The stage transmission signal and the gate drive signal can be the same or different, which is related to the specific structure of the initial control module, the stage transmission output module, the auxiliary driver module, and the driver output module. The following uses a typical example to illustrate the structure of the initial control module, the stage transmission output module, the auxiliary driver module, and the driver output module.

[0100] Optional, Figure 11 FIG. 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention. Figure 11As shown, the auxiliary driving module 130 includes: a first auxiliary node control unit 131, a second auxiliary node control unit 132 and an auxiliary driving output unit 133; the first auxiliary node control unit 132 is used to receive the auxiliary control signal Vac and the third clock signal ck3, and control the signal of the first auxiliary node N3; the second auxiliary node control unit 132 is used to receive the signal of the first auxiliary node N3, the third clock signal ck3 and the first level signal Vgl, and control the signal of the second auxiliary node N4; the auxiliary driving output unit 133 is used to receive the signal of the first auxiliary node N3, the signal of the second auxiliary node N4, the second level signal Vgh and the fourth clock signal ck4, and control the auxiliary driving signal Vad.

[0101] Specifically, the first auxiliary node control unit 131 can provide a signal to the first auxiliary node N3 under the control of the auxiliary control signal Vac and the third clock signal ck3, so that the auxiliary control signal Vac and the third clock signal ck3 can control the polarity and amplitude of the signal at the first auxiliary node N3. The second auxiliary node control unit 132 can provide a signal to the second auxiliary node N4 under the control of the signal at the first auxiliary node N3, the third clock signal ck3, and the first level signal Vgl, so that the signal at the first auxiliary node N3, the third clock signal ck3, and the first level signal Vgl can control the polarity and amplitude of the signal at the second auxiliary node N4. The auxiliary drive output unit 133 can output the auxiliary drive signal Vad under the control of the signal at the first auxiliary node N3, the signal at the second auxiliary node N4, the second level signal Vgh, and the fourth clock signal ck4, so that the signal at the first auxiliary node N3, the signal at the second auxiliary node N4, the second level signal Vgh, and the fourth clock signal ck4 can control the auxiliary drive signal Vad.

[0102] In an exemplary embodiment, when the third clock signal ck3 is at an enable level, the first auxiliary node control unit 131 may transmit the auxiliary control signal Vac to the first auxiliary node N3, so that the signal at the first auxiliary node N3 is consistent with the auxiliary control signal Vac. Simultaneously, when the third clock signal ck3 is at an enable level, the second auxiliary node control unit 132 may transmit the first-level signal Vgl to the second auxiliary node N4, and when the signal at the first auxiliary node N3 is at an enable level, transmit the third clock signal ck3 to the second auxiliary node N4. Furthermore, when the signal at the first auxiliary node N3 is at an enable level, the auxiliary driver output unit 133 may control the auxiliary driver signal Vad to be consistent with the fourth clock signal ck4, and when the signal at the second auxiliary node N4 is at an enable level, the auxiliary driver output unit 133 may control the auxiliary driver signal Vad to be consistent with the second-level signal Vgh. In the same shift register unit G, the polarities of the signals at the first auxiliary node N3 and the second auxiliary node N4 may be the same or opposite. In an optional embodiment, at least part of the time, the polarities of the signals of the first auxiliary node N3 and the second auxiliary node N4 are opposite, that is, when the signal of the first auxiliary node N3 is at a high level, the signal of the second auxiliary node N4 may be at a low level; or, when the signal of the first auxiliary node N3 is at a low level, the signal of the second auxiliary node N4 is at a high level.

[0103] Optional, Figure 12 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 12 As shown, the first auxiliary node control unit 131 includes a first auxiliary transistor M31; a first electrode of the first auxiliary transistor M31 receives the auxiliary control signal Vac, a second electrode of the first auxiliary transistor M31 is electrically connected to the first auxiliary node N3, and a gate of the first auxiliary transistor M31 receives the third clock signal ck3.

[0104] Specifically, the first auxiliary transistor M31 can be turned on or off under the control of the third clock signal ck3. When the third clock signal ck3 controls the first auxiliary transistor M31 to be turned on, the auxiliary control signal Vac can be transmitted to the first auxiliary node N3 through the first auxiliary transistor M31, so that the signal at the first auxiliary node N3 is consistent with the auxiliary control signal Vac. When the third clock signal ck3 controls the first auxiliary transistor M31 to be turned off, the auxiliary control signal Vac received by the first electrode of the first auxiliary transistor M31 cannot be transmitted to the first auxiliary node N3.

[0105] Optional, reference Figure 12The second auxiliary node control unit 132 includes a second auxiliary transistor M32 and a third auxiliary transistor M33; the first electrode of the second auxiliary transistor M32 receives the first level signal Vgl, the second electrode of the second auxiliary transistor M32 is electrically connected to the second auxiliary node N4, and the gate of the second auxiliary transistor M32 receives the third clock signal ck3; the first electrode of the third auxiliary transistor M33 receives the third clock signal ck3, the second electrode of the third auxiliary transistor M33 is electrically connected to the second auxiliary node N4, and the gate of the third auxiliary transistor N4 is electrically connected to the first auxiliary node N3.

[0106] Specifically, the second auxiliary transistor M32 can be turned on or off under the control of the third clock signal ck3. When the third clock signal ck3 controls the second auxiliary transistor M32 to be turned on, the first level signal Vgl can be transmitted to the second auxiliary node N4 through the second auxiliary transistor M32. When the third clock signal ck3 controls the second auxiliary transistor M32 to be turned off, the first level signal Vgl cannot be transmitted to the second auxiliary node N4. The third auxiliary transistor M33 can be turned on or off under the control of the first auxiliary node N3. When the signal of the first auxiliary node N3 controls the third auxiliary transistor M33 to be turned on, the third clock signal ck3 can be transmitted to the second auxiliary node N4 through the third auxiliary transistor M33. When the signal of the first auxiliary node N3 controls the third auxiliary transistor M33 to be turned off, the third clock signal ck3 cannot be transmitted to the second auxiliary node N4.

[0107] Optional, continue to refer to Figure 12 The auxiliary drive output unit 133 includes a fourth auxiliary transistor M34 and a fifth auxiliary transistor M35; the first electrode of the fourth auxiliary transistor M33 receives the fourth clock signal ck4, the gate of the fourth auxiliary transistor M34 is electrically connected to the first auxiliary node N3, and the second electrode of the fourth auxiliary transistor M34 outputs the auxiliary drive signal Vad; the first electrode of the fifth auxiliary transistor M35 receives the second level signal Vgh, the gate of the fifth auxiliary transistor M35 is electrically connected to the second auxiliary node N4, and the second electrode of the fifth auxiliary transistor M35 outputs the auxiliary drive signal Vad.

[0108] Specifically, the fourth auxiliary transistor M34 can be turned on or off under the control of the first auxiliary node N3. When the signal of the first auxiliary node N3 controls the fourth auxiliary transistor M34 to be turned on, the fourth clock signal ck4 received by the first electrode of the fourth auxiliary transistor M34 can be transmitted to its second electrode, so that the fourth clock signal ck4 serves as the auxiliary drive signal Vad output by the second electrode of the fourth auxiliary transistor M34. The fifth auxiliary transistor M35 can be turned on or off under the control of the second auxiliary node N4. When the signal of the second auxiliary node N4 controls the fifth auxiliary transistor M35 to be turned on, the second level signal Vgh received by the first electrode of the fifth auxiliary transistor M35 can be transmitted to its second electrode, so that the second level signal Vgh serves as the auxiliary drive signal Vad output by the second electrode of the fifth auxiliary transistor M35.

[0109] Optional, Figure 13 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 13 As shown, the auxiliary driving module 130 further includes a first voltage stabilizing unit 134 , and the gate of the fourth auxiliary transistor M34 is electrically connected to the first auxiliary node N3 through the first voltage stabilizing unit 134 .

[0110] Specifically, assuming that the connection node between the first voltage stabilizing unit 134 and the gate of the fourth auxiliary transistor M34 is the third auxiliary node N5, the first voltage stabilizing unit 134 can isolate the first auxiliary node N3 and the third auxiliary node N5, so that the signal of the first auxiliary node N3 and the signal of the third auxiliary node N5 are relatively stable, preventing the signal fluctuation of the first auxiliary node N3 and / or the signal fluctuation of the third auxiliary node N5 from affecting the output of the auxiliary driving signal Vad of the fourth auxiliary transistor M34, which is beneficial to improving the stability of the gate driving signal Gout output by the driving output module 140, thereby improving the working stability of the shift register unit G, and further improving the display effect of the display panel.

[0111] Optional, Figure 14 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 14 As shown, the first voltage stabilizing unit 134 includes: a sixth auxiliary transistor M36; the first electrode of the sixth auxiliary transistor M36 is electrically connected to the first auxiliary node N3, the second electrode of the sixth auxiliary transistor M36 is electrically connected to the gate of the fourth auxiliary transistor M34, and the gate of the sixth auxiliary transistor M36 receives the first level signal Vgl.

[0112] Specifically, the first-level signal Vgl can control the sixth auxiliary transistor M36 to remain in a continuously turned-on state, ensuring that the signal at the third auxiliary node N5 remains substantially consistent with the signal at the first auxiliary node N3. Furthermore, because the turned-on sixth auxiliary transistor M36 has a certain resistance, when the signal at the third auxiliary node N5 changes, the sixth auxiliary transistor M36 can reduce the amount by which the signal at the first auxiliary node N3 changes in response to the signal at the third auxiliary node N5. Similarly, when the signal at the first auxiliary node N3 changes, the sixth auxiliary transistor M36 can also reduce the amount by which the signal at the third auxiliary node N5 changes in response to the signal at the first auxiliary node N3. Thus, by providing the sixth auxiliary transistor M36 between the third auxiliary node N5 and the first auxiliary node N3, the stability of the signals at the third auxiliary node N5 and the first auxiliary node N3 can be ensured, thereby improving the stability of the auxiliary drive signal Vad output by the fourth auxiliary transistor M34.

[0113] Optional, reference Figure 12 or Figure 14 The auxiliary drive module also includes: a first capacitor C1 and a second capacitor C2; the first capacitor C1 is electrically connected between the gate and the second electrode of the fourth auxiliary transistor M34; the second capacitor C2 is electrically connected between the gate and the first electrode of the fifth auxiliary transistor M35. The first capacitor C1 is used to store the gate potential of the fourth auxiliary transistor M34, thereby improving the stability of the gate potential of the fourth auxiliary transistor M34; the second capacitor C2 is used to store the gate potential of the fifth auxiliary transistor M35, thereby improving the stability of the gate potential of the fifth auxiliary transistor M35. In this way, the stability of the gate drive signal Gout output by the fourth auxiliary transistor M34 and the fifth auxiliary transistor M35 can be improved, thereby improving the display effect of the display panel 100.

[0114] It is understandable that in the embodiment of the present invention, one of the enable level and the disable level is a high level and the other is a low level. For example, when the first auxiliary transistor M31 is an NMOS, the enable level for controlling the first auxiliary transistor M31 to turn on is a high level, and the disable level for controlling the first auxiliary transistor M31 to turn off is a low level. When the first auxiliary transistor M31 is a PMOS, the enable level for controlling the first auxiliary transistor M31 to turn on is a low level, and the disable level for controlling the first auxiliary transistor M31 to turn off is a high level. Therefore, the level of the enable level and the disable level involved in the embodiment of the present invention is related to the type of the controlled transistor, and the embodiment of the present invention does not specifically limit this.

[0115] Exemplarily, the valid pulses of the third clock signal ck3 and the valid pulses of the fourth clock signal ck4 do not overlap. The third clock signal ck3 can be a pulse signal, such that the third clock signal ck3 can include a high level and a low level. The auxiliary control signal Vac is the auxiliary drive signal Vad of the previous-stage shift register unit G, such that the auxiliary control signal Vac can also include a high level and a low level. The first-level signal Vgl and the second-level signal Vgh are both fixed signals. For example, the first-level signal Vgl can be a low-level signal, and the second-level signal Vgh can be a high-level signal. The third clock signal ck3 and the fourth clock signal ck4 can have the same pulse frequency. In this case, the third clock signal ck3 and the fourth clock signal ck4 have different phases, i.e., when the third clock signal ck3 is at an enable level, the fourth clock signal ck4 is at an inactive level; conversely, when the fourth clock signal ck4 is at an enable level, the third clock signal ck3 is at an inactive level.

[0116] When the second auxiliary node N4 requires a low-level signal, the third clock signal ck3 can be set to a low level to control the second auxiliary transistor M32 to turn on, and the low-level first-level signal Vgl can be transmitted to the second auxiliary node N4 through the turned-on second initial control transistor M02. Alternatively, when the third clock signal ck3 and the auxiliary control signal Vac are low, the signal on the first auxiliary node N3 controls the third auxiliary transistor M33 to turn on, so that the low-level third clock signal ck3 is transmitted to the second auxiliary node N4. When the second auxiliary node N4 requires a high-level signal, the third auxiliary transistor M33 can be controlled to turn on when the signal on the first auxiliary node N3 is low and the third clock signal ck3 is high, so that the high-level third clock signal ck3 is transmitted to the second auxiliary node N4. Thus, the signal on the second auxiliary node N4 can be set according to actual needs.

[0117] Similarly, when the first auxiliary node N3 requires a high-level signal, the third clock signal ck3 can control the first auxiliary transistor M31 to turn on when the auxiliary control signal Vac is at a high level. At this time, the signal at the first initial node N1 can be consistent with the high-level input signal Vin. When the first auxiliary node N3 requires a low-level signal, the third clock signal ck3 can control the first auxiliary transistor M31 to turn on when the auxiliary control signal Vac is at a low level, allowing the first auxiliary transistor M31 to transmit the low-level auxiliary control signal Vac to the first auxiliary node N3. This configuration allows the signal at the first auxiliary node N3 to be controlled as needed.

[0118] For example, if all transistors in the auxiliary driving module 130 are PMOS transistors, Figure 15This is another driving timing diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Figure 14 and Figure 15 Before stage t01, since the auxiliary control signal Vac is at a high level, the first auxiliary transistor M31, when turned on, transmits the high-level auxiliary control signal Vac to the first auxiliary node N3, causing the signal at the first auxiliary node N3 to remain at a high level, and thus keeping the third auxiliary transistor M33 in the off state. When the second auxiliary transistor M32 is turned on, it writes the first-level signal Vgl to the second auxiliary node N4, causing the second auxiliary node N4 to remain at a low level. Consequently, the fourth auxiliary transistor M34 remains off, and the fifth auxiliary transistor M35 remains on, causing the auxiliary drive signal Vad to remain consistent with the second-level signal Vgh, i.e., the auxiliary drive signal Vad is at a high level.

[0119] At stage t01, the auxiliary control signal Vac and the third clock signal ck3 are at a low level, and the fourth clock signal ck4 is at a high level. The third clock signal ck3 then turns on the first auxiliary transistor M31. The low-level auxiliary control signal Vac is transmitted to the first auxiliary node N3 via the first auxiliary transistor M31. The signal at the first auxiliary node N3 turns on the third auxiliary transistor M33, and the third clock signal ck3 turns on the second auxiliary transistor M32. The low-level third clock signal ck3 is transmitted to the second auxiliary node N4 via the third auxiliary transistor M33, and the first-level signal Vgl is transmitted to the second auxiliary node N4 via the second auxiliary transistor M32, causing the second auxiliary node N4 to also be at a low level. The fourth auxiliary transistor M34 and the fifth auxiliary transistor M35 are then both turned on. The high-level fourth clock signal ck4 is transmitted from the first electrode of the fourth auxiliary transistor M34 to its second electrode, and the second-level signal Vgh is transmitted from the first electrode of the fifth auxiliary transistor M35 to its second electrode, causing the auxiliary drive signal Vad to be a high-level signal.

[0120] At stage t02, the auxiliary control signal Vac, the third clock signal ck3, and the fourth clock signal ck4 are all at a high level. The first auxiliary transistor M31 and the second auxiliary transistor M32 are turned off, the first auxiliary node N3 remains at the low level of the previous stage, and the third auxiliary transistor M33 remains on. The high-level third clock signal ck3 is written to the second auxiliary node N4 through the third auxiliary transistor M33, and the second auxiliary node N4 is at a high level. The fourth auxiliary transistor M34 is then turned on and the fifth auxiliary transistor M35 is turned off, so that the auxiliary drive signal Vad is consistent with the fourth clock signal ck4, that is, the auxiliary drive signal Vad is at a high level.

[0121] At stage t03, the auxiliary control signal Vac and the third clock signal ck3 remain high, while the fourth clock signal ck4 is low. The first auxiliary transistor M31 and the second auxiliary transistor M32 remain off, and the first auxiliary node N3 is low, turning on the third auxiliary transistor M33 and the fourth auxiliary transistor M34. The high-level third clock signal ck3 is written to the second auxiliary node N4 via the third auxiliary transistor M33. The second auxiliary node N4 is high, turning off the fifth auxiliary transistor M35. The low-level fourth clock signal ck4 is transmitted via the first electrode to the second electrode of the fourth auxiliary transistor M34, causing the auxiliary drive signal Vad to be low. Simultaneously, the low-level signal at the second electrode of the fourth auxiliary transistor M34 is coupled to the first auxiliary node N3 via the coupling effect of the first capacitor C1, further lowering the potential of the first auxiliary node N3.

[0122] At stage t04, the auxiliary control signal Vac, the third clock signal ck3, and the fourth clock signal ck4 are all high. The first auxiliary transistor M31 and the second auxiliary transistor M32 remain off, and the first auxiliary node N3 remains low without any new signal being written. The third auxiliary transistor M33 and the fourth auxiliary transistor M34 are turned on, and the high level of the fourth clock signal ck4 is written to the second auxiliary node N4 via the turned-on third auxiliary transistor M33, causing the second auxiliary node N4 to remain high. The fourth auxiliary transistor M34 remains on, and the fifth auxiliary transistor M35 remains off. The high level of the fourth clock signal ck4 is transmitted via the first electrode of the fourth auxiliary transistor M34 to its second electrode, causing the auxiliary drive signal Vad to be high. Simultaneously, the high level signal at the second electrode of the fourth auxiliary transistor M34 is coupled to the first auxiliary node N3 via the coupling effect of the first capacitor C1, thereby raising the potential of the first auxiliary node N3.

[0123] At stage t05, the auxiliary control signal Vac and the fourth clock signal ck4 are high, and the third clock signal ck3 is low. The first auxiliary transistor M31 and the second auxiliary transistor M32 are turned on. The high-level auxiliary control signal Vac is written to the first auxiliary node N3 via the first auxiliary transistor M31, causing the first auxiliary node N3 to be high. The low-level first-level signal Vgl is written to the second auxiliary node N4 via the second auxiliary transistor M32. The high level of the first auxiliary node N3 controls the third auxiliary transistor M33 to be turned off, causing the second auxiliary node N4 to be low. The fourth auxiliary transistor M34 is then turned off, and the fifth auxiliary transistor M35 is turned on. This causes the second-level signal Vgh to be transmitted from the first electrode of the fifth auxiliary transistor M35 to its second electrode, causing the auxiliary drive signal Vad to remain consistent with the second-level signal Vgh at a high level.

[0124] After the t05 stage, since the auxiliary control signal Vac always remains a high-level signal, the first auxiliary node N1 is never written with a new signal and remains at a high level, so that the third auxiliary transistor M33 and the fourth auxiliary transistor M34 always remain in the off state, and the second auxiliary node N2 writes the first-level signal Vgl when the second auxiliary transistor M32 is turned on, and remains at the low-level signal of the previous stage when the second auxiliary transistor M32 is turned off, so that the fifth auxiliary transistor M35 always remains in the on state, so that the auxiliary drive signal Vad always remains consistent with the second-level signal Vgh as a high-level signal, until the auxiliary control signal Vac jumps to a low level again, and the above-mentioned t01 to t05 stages are repeated.

[0125] Optional, Figure 16 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 16 As shown, the drive output module 140 includes: a first drive control unit 141, a second drive control unit 142 and a drive output unit 143; the first drive control unit 141 is used to receive at least a drive control signal Vct, a level transfer signal Vnext and an auxiliary drive signal Vad, and control the signal of the first drive control node N6; the second drive control unit 142 is used to receive the signal of the first drive control node N6, the signal of the first initial node N1, the signal of the second initial node N2 and the second level signal Vgh, and control the signal of the second drive control node N7; the drive output unit 143 is used to receive the signal of the second drive control node N7, the signal of the first initial node N1, the first level signal Vgl and the second level signal Vgh, and control the gate drive signal Gout.

[0126] Specifically, the first drive control unit 141 can provide corresponding signals to the first drive control node N6 under the control of the drive control signal Vct, the stage transmission signal Vnext, and the auxiliary drive signal Vad, so that the drive control signal Vct, the stage transmission signal Vnext, and the auxiliary drive signal Vad can control the polarity and amplitude of the signal at the first drive control node N6. The second drive control unit 142 can provide corresponding signals to the second drive control node N7 based on the signal at the first drive control node N6, the signal at the first initial node N1, the signal at the second initial node N2, and the second level signal Vgh, so that the signal at the first drive control node N6, the signal at the first initial node N1, the signal at the second initial node N2, and the second level signal Vgh can control the signal at the second drive control node N7. The drive output unit 143 can output corresponding gate drive signals Gout under the control of the signal at the second drive control node N7, the signal at the first initial node N1, the first level signal Vgl, and the second level signal Vgh, so that the signal at the second drive control node N7, the signal at the first initial node N1, the first level signal Vgl, and the second level signal Vgh can control the gate drive signals Gout.

[0127] In an exemplary embodiment, when both the stage transfer signal Vnext and the auxiliary drive signal Vad are at an enable level, the first drive control unit 141 can transmit the drive control signal Vct to the first drive control node N6, such that the signal at the first drive control node N6 is consistent with the drive control signal Vct. When the signal at the first drive control node N6 is at an enable level, the second drive control unit 142 can transmit the signal at the second initial node N2 to the second drive control node N7, such that the signal at the second drive control node N7 is consistent with the signal at the second initial node N2. When the signal at the first initial node N1 is at an enable level, the second drive control unit 142 can transmit the second-level signal Vgh to the second drive control node N7, such that the second drive control node N7 is consistent with the second-level signal Vgh. When the signal at the second drive control node N7 is at an enable level, the drive output unit 143 can control the gate drive signal Gout to be consistent with the second-level signal Vgh. When the signal at the first initial node N1 is at an enable level, the drive output unit 143 can control the gate drive signal Gout to be consistent with the first-level signal Vgl.

[0128] In this way, before the driving control signal Vct jumps from the enable level to the disable level, the first driving control unit 141 can be controlled by the level transmission signal Vnext and the auxiliary driving signal vad to transmit the enable level of the driving control signal Vct to the first driving control node N6. Then, after any one of the level transmission signal Vnext and the auxiliary driving signal vad is at the disable level, the first driving control node N6 remains at the enable level unchanged, so that the second driving control unit 142 can make the signal of the second driving control node N7 consistent with the signal of the second initial node N2 under the control of the first driving control node N6, so that the driving output unit 143 can control the gate driving signal Gout to be consistent with the level transmission signal Vnext, and when the level transmission signal Vnext outputs multiple high-level pulses, the gate driving signal Gout can synchronously output multiple valid pulses, which can solve the problem that some shift register units G in the high-frequency refresh area A21 cannot achieve multi-pulse output, thereby facilitating improving the display effect of the display panel 100. For each shift register unit G in the low-frequency refresh area A22, the drive control signal Vct jumps to the non-enable level before the first drive control unit 141 is turned on, so that when the first drive control unit 141 is turned on, the first drive control node N6 is written with the non-enable level of the auxiliary drive signal Vad, and when the first initial node N1 is at the enable level, the second level signal Vgh is written into the second drive control node N7 through the second drive control unit 142, so that the drive output module 143 cannot control the gate drive signal Gout to be consistent with the second level signal Vgh, and always remains consistent with the first level signal Vgl, and no longer outputs a high-level valid pulse, so that the corresponding pixel circuit 20 can be refreshed at a low frequency.

[0129] Optional, Figure 17 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 17 As shown, the first drive control unit 141 includes a first drive control transistor M41, a second drive control transistor M42 and a third capacitor C3; the first electrode of the first drive control transistor M41 receives the drive control signal Vct, the gate of the first drive control transistor M41 receives the auxiliary drive signal Vad, and the second electrode of the first drive control transistor M41 is electrically connected to the first electrode of the second drive control transistor M42; the gate of the second drive control transistor M42 receives the level transfer signal Vnext, and the second electrode of the second drive control transistor M42 is electrically connected to the first drive control node N6; one end of the third capacitor C3 receives a fixed voltage signal, and one end of the third capacitor C3 is electrically connected to the first drive control node N6.

[0130] Specifically, the first drive control transistor M41 can be turned on or off under the control of the auxiliary drive signal Vad. When the auxiliary drive signal Vad controls the first drive transistor M41 to be turned on, the auxiliary drive signal Vad is transmitted to the first electrode of the second drive control transistor M42 through the first drive transistor M41. The second drive control transistor M42 can be turned on or off under the control of the level transmission signal Vnext. When the level transmission signal Vnext controls the second drive control transistor M42 to be turned on, the second drive control transistor M42 can transmit the signal at its first electrode to the first drive control node N6. The first end of the third capacitor C3 can receive a fixed voltage signal, which can be a high-level signal or a low-level signal. In the embodiment of the present invention, the fixed voltage signal received by the first end of the third capacitor C3 is exemplarily shown as the second-level signal Vgh. Since the second end of the third capacitor C3 is electrically connected to the first drive control node N6, the third capacitor C3 can store the signal at the first drive control node N6 and stabilize the potential of the first drive control node N6.

[0131] Taking the first drive control transistor M41 and the second drive control transistor M42 as PMOS transistors as an example, before the drive control signal Vct jumps from the enable level to the non-enable level, before the stage transmission signal Vnext outputs the first high level pulse, that is, during the process of the stage transmission signal Vnext outputting a low level, the auxiliary drive signal Vad can be first controlled to output a low level pulse, so that the drive control signal Vct is sequentially transmitted to the first drive control node N6 through the first drive control transistor M41 and the second drive control transistor M42. Then, after the auxiliary drive signal Vad jumps to a high level, the signal of the first drive control node N6 is no longer affected by the drive control signal V ct, and can stabilize the potential of the first drive control node N6 through the third capacitor C3, so that the first drive control node N6 can remain at the enable level after the drive control signal Vct jumps to the non-enable level, so that the second drive control unit 142 can remain in the on state without being affected by the drive control signal Vct, thereby ensuring that the signal of the second drive control node N7 remains consistent with the signal of the second initial node N2, and can control the gate drive signal Gout output by the drive output unit 143 to be consistent with the stage transfer signal Vnext, so that the current shift register unit can realize multi-pulse output of the gate drive signal Gout. For each shift register G in the low-frequency refresh area A22, the drive control signal Vct jumps to the non-enable level before the auxiliary drive signal Vad outputs a low-level pulse, so that the first drive control node N6 is written with the non-enable level of the auxiliary drive signal Vad. Then, when the first initial node N1 is at the enable level, the second level signal Vgh is written into the second drive control node N7 through the second drive control unit 142, so that the drive output module 143 cannot control the gate drive signal Gout to be consistent with the second level signal Vgh, and always remains consistent with the first level signal Vgl, and no longer outputs a high-level valid pulse, so that the corresponding pixel circuit 20 can be refreshed at a low frequency.

[0132] Optional, reference Figure 17The second drive control unit 142 includes: a third drive control transistor M43, a fourth drive control transistor M44 and a fourth capacitor C4; a first electrode of the third drive control transistor M43 receives a signal from the second initial node N2, a gate of the third drive control transistor M43 receives a signal from the first drive control node N6, and a second electrode of the third drive control transistor M43 is electrically connected to the second drive control node N7; a first electrode of the fourth drive control transistor M44 receives a second level signal Vgh, a gate of the fourth drive control transistor M44 receives a signal from the first initial node N1, and a second electrode of the fourth drive control transistor M44 is electrically connected to the second drive control node N7; a first end of the fourth capacitor C4 receives a fixed voltage signal, and a second end of the fourth capacitor C4 is electrically connected to the second drive control node N7.

[0133] Specifically, the third drive control transistor M43 can be turned on or off under the control of the first drive control node N6, and when the signal of the first drive control node N6 controls the third drive control transistor M43 to be turned on, the signal of the second initial node N2 can be transmitted to the second drive control node N7 through the third drive control transistor M43, so that the signal of the second drive control node N7 is consistent with the signal of the second initial node N2. The fourth drive control transistor M44 can be turned on or off under the control of the first initial node N1, and when the first initial node N1 controls the fourth drive control transistor M44 to be turned on, the second level signal Vgh can be transmitted to the second drive control node N7 through the fourth drive control transistor M44, so that the second drive control node N7 is consistent with the second level signal Vgh. The first end of the fourth capacitor C4 can receive a fixed voltage signal, which can be a high-level signal or a low-level signal. The embodiment of the present invention exemplarily shows that the fixed voltage signal received by the first end of the fourth capacitor C4 is a second-level signal Vgh. Since the second end of the fourth capacitor C4 is electrically connected to the second drive control node N7, the fourth capacitor C4 can store the signal of the second drive control node N7 and stabilize the potential of the second drive control node N7.

[0134] Optional, continue to refer to Figure 17 The driving output unit 143 includes a first driving output transistor M45 and a second driving output transistor M46; the first electrode of the first driving output transistor M45 receives the first level signal Vgl, the gate of the first driving output transistor M45 receives the signal of the first initial node N1, and the second electrode of the first driving output transistor M45 outputs the gate driving signal Gout; the first electrode of the second driving output transistor M46 receives the second level signal Vgh, the gate of the second driving output transistor M46 receives the signal of the second driving control node N7, and the second electrode of the second driving output transistor M46 outputs the gate driving signal Gout.

[0135] Specifically, the first driver output transistor M45 can be turned on or off under the control of the first initial node N1, and when the first initial node N1 controls the first driver output transistor M45 to be turned on, the first level signal Vgl can be transmitted through the first electrode of the first driver output transistor M45 to the second electrode thereof, so that the gate drive signal Gout is the first level signal Vgl. The second driver output transistor M46 can be turned on or off under the control of the second driver control node N7, and when the second driver control node N7 controls the second driver output transistor M46 to be turned on, the second level signal Vgh can be transmitted through the first electrode of the second driver output transistor M46 to the second electrode thereof, so that the gate drive signal Gout is the second level signal Vgh.

[0136] Optional, Figure 18 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 18 As shown, the stage transmission output module 120 includes a first-stage transmission output unit 121 and a second-stage transmission output unit 122; the first-stage transmission output unit 121 is used to receive the signal of the first initial node N1 and the first level signal Vgl, and control the stage transmission signal Vnext; the second-stage transmission output unit 122 is used to receive the signal of the second initial node N2 and the second level signal Vgh, and control the stage transmission signal Vnext.

[0137] Specifically, the first-stage output unit 121 can output a corresponding level-transmitting signal Vnext under the control of the first initial node N1 and the first level signal Vgl, such that the signal of the first initial node N1 and the first level signal Vgl can control the level-transmitting signal Vnext. The second-stage output unit 122 can output a corresponding level-transmitting signal Vnext under the control of the second initial node N2 and the second level signal Vgh, such that the signal of the second initial node N2 and the second level signal Vgh can control the level-transmitting signal Vnext. In an exemplary embodiment, when the signal of the first initial node N1 is at an enable level, the first-stage output unit 121 controls the level-transmitting signal Vnext to be consistent with the first level signal Vgl; when the signal of the second initial node N2 is at an enable level, the second-stage output unit 122 controls the level-transmitting signal Vnext to be consistent with the second level signal Vgh.

[0138] For example, Figure 19 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 19As shown, the first-stage output unit 121 includes a first-stage output transistor M21. The first electrode of the first-stage output transistor M21 receives the first-level signal Vgl. The gate of the first-stage output transistor M21 is electrically connected to the first initial node N1. The second electrode of the first-stage output transistor M21 outputs the first-stage output signal Vnext. The first-stage output transistor M21 is turned on or off under the control of the first initial node N1. When the signal at the first initial node N1 controls the first-stage output transistor M21 to turn on, the first-level signal Vgl can be transmitted to the second electrode of the first-stage output transistor M21 through the first electrode, so that the first-level signal Vnext is the first-level signal Vgl.

[0139] The second-stage output unit 122 includes a second-stage output transistor M22. A first electrode of the second-stage output transistor M22 receives the second-level signal Vgh. A gate of the second-stage output transistor M22 is electrically connected to the second initial node N2. A second electrode of the second-stage output transistor M22 outputs the next-stage signal Vnext. The second-stage output transistor M22 can be turned on or off under the control of the second initial node N2. When the signal at the second initial node N2 controls the second-stage output transistor M22 to be turned on, the second-level signal Vgh can be transmitted to the second electrode of the second-stage output transistor M22 via the first electrode, so that the next-stage signal Vnext is the second-level signal Vgh.

[0140] Optional, Figure 20 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 20 As shown, the initial control module 110 includes a first initial control unit 111 and a second initial control unit 112; the first initial control unit 111 is used to receive at least the input signal Vin and the first clock signal ck1, and control the signal of the first initial node N1; the second initial control unit 112 is used to receive at least the signal of the first initial node N1, the first clock signal ck1, the second clock signal ck2 and the first level signal Vgl, and control the signal of the second initial node N2.

[0141] Specifically, the first initial control unit 111 can provide a corresponding signal to the first initial node N1 under the control of the first clock signal ck1 and the input signal Vin, so that the first clock signal ck1 and the input signal Vin can control the polarity and amplitude of the first initial node N1; the second initial control unit 112 can provide a signal to the second initial node N2 under the control of the signal of the first initial node N1, the first clock signal ck1, the second clock signal ck2 and the first level signal Vgl, so that the signal of the first initial node N1, the first clock signal ck1, the second clock signal ck2 and the first level signal Vgl can control the polarity and amplitude of the second initial node N2.

[0142] In an exemplary embodiment, when the first clock signal ck1 is at an enable level, the first initial control unit 111 may transmit the input signal Vin to the first initial node N1, such that the signal at the first initial node N1 is consistent with the input signal Vin. Regarding the second initial control unit 112, when the signal at the first initial node N1 is at an enable level, the second initial control unit 112 may transmit the first clock signal ck1 to the second initial node N2, such that the signal at the second initial node N2 is consistent with the first clock signal ck1. When the first clock signal ck1 is at an enable level, the second initial control unit 112 may transmit the first level signal Vgl to the second initial node N2, such that the signal at the second initial node N2 is consistent with the first level signal Vgl.

[0143] Optional, Figure 21 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 21 As shown, the first initial control unit 111 includes a first initial control transistor M01. A first electrode of the first initial control transistor M01 receives an input signal Vin, a second electrode of the first control transistor M01 is electrically connected to a first initial node N1, and a gate electrode of the first initial control transistor M01 receives a first clock signal ck1. When the first initial control transistor M01 is turned on under the control of the first clock signal ck1, the input signal Vin can be transmitted to the first initial node N1 through the first initial control transistor M01.

[0144] refer to Figure 21The second initial control unit 112 includes a second initial control transistor M02, a third initial control transistor M03, a fourth initial control transistor M04, a fifth initial control transistor M05, a sixth initial control transistor M06, a seventh initial control transistor M07, a twelfth initial control transistor M12, and a fifth capacitor C5. A first electrode of the second initial control transistor M02 receives a first level signal Vgl, a second electrode of the second initial control transistor M02 is electrically connected to the first control node N21, and a gate of the second initial control transistor M02 receives a first clock signal ck1. When the second initial control transistor M02 is turned on under the control of the first clock signal ck1, the first level signal Vgl can be transmitted to the first control node N21 via the second control transistor M12. The gates of the third initial control transistor M03 and the fourth initial control transistor M04 are both electrically connected to the first initial node N1. A first electrode of the third initial control transistor M03 receives the first clock signal ck1. A second electrode of the third initial control transistor M03 is electrically connected to the first electrode of the fourth initial control transistor M04. A second electrode of the fourth initial control transistor M04 is electrically connected to the first control node N21. The third initial control transistor M03 and the fourth initial control transistor M04 have the same channel type. Therefore, when the third initial control transistor M13 and the fourth initial control transistor M04 are turned on under the control of the signal at the first initial node N1, the first clock signal ck1 can be transmitted to the first control node N21 through the third initial control transistor M03 and the fourth initial control transistor M04 in sequence.

[0145] The fifth initial control transistor M05 is a voltage stabilizing transistor. A gate of the fifth initial control transistor M05 receives a first level signal Vgl. A first electrode of the fifth initial control transistor M05 is electrically connected to the first control node N21. A second electrode of the fifth initial control transistor M05 and a gate of the sixth initial control transistor M06 are electrically connected to the second control node N22. The first stage of the sixth initial control transistor M06 and the first stage of the seventh initial control transistor M07 both receive the second clock signal ck2. A second electrode of the sixth initial control transistor M06 and a first electrode of the seventh initial control transistor M07 are electrically connected to the third control node N23. A second electrode of the seventh initial control transistor M07 is electrically connected to the second initial node N2. A fifth capacitor C5 is electrically connected between the second control node N9 and the third control node N10.

[0146] The fifth initial control transistor M05 is preferably a PMOS transistor and is always in the on state under the control of the first level signal Vgl. When the potential of one of the first control node N21 and the second control node N22 is abnormal, it can stabilize the voltage of the other node, thereby protecting the devices electrically connected to the node. The sixth initial control transistor M06 is turned on or off under the control of the second control node N22 and transmits the second clock signal ck2 to the third control node N23 when turned on. The fifth capacitor C5 serves as a storage capacitor. Due to the function of the fifth capacitor C5, the potential of the second control node N23 is kept stable, thereby ensuring that the sixth initial control transistor M06 is stably in the on state. The seventh initial control transistor M07 can be turned on or off under the control of the second clock signal ck2 and transmits the signal of the third control node N23 to the second initial node N2 when turned on.

[0147] The gate of the twelfth initial control transistor M12 is electrically connected to the first initial node N1, the first electrode of the twelfth initial control transistor M12 receives the second level signal Vgh, and the second electrode of the twelfth initial control transistor M12 is electrically connected to the second initial node N2. When the first initial node N1 is at a low level, the twelfth initial control transistor M12 is turned on, so that the second level signal Vgh can be transmitted to the second initial node N2 through the twelfth initial control transistor M12, thereby ensuring that the second stage transmission output transistor M22 in the stage transmission output module 120 is in a disconnected state, thereby ensuring the accuracy of the stage transmission signal Vnext output by the stage transmission output module 120.

[0148] Exemplarily, the initial control module 110 may further include an eighth initial control transistor M08, wherein the gate of the eighth initial control transistor M08 may receive the reset signal Rst, the first electrode of the eighth initial control transistor M08 may receive the first level signal Vgh, and the second electrode of the eighth initial control transistor M08 may be electrically connected to the first initial node N1. The eighth initial control transistor M08 may be turned on or off under the control of the reset signal Rst, and when turned on, transmits the second level signal Vgh to the first initial node N1, thereby preventing the stage transmission output module 120 from outputting the first level signal Vgl as the stage transmission signal Vnext. Therefore, when the stage transmission output module 120 needs to output a high-level stage transmission signal Vnext, the reset signal Rst may be controlled to an enable level to turn on the eighth initial control transistor M08.

[0149] Taking the example of each transistor in the second initial control unit 112 being a PMOS transistor, when the first clock signal ck1 is at a low level, the second initial control transistor M02 is turned on, and the first level signal Vgl is written to the first control node N21. The signal of the first control node N21 is then transmitted to the second control node N22 via the fifth initial control transistor M05, causing the signal of the second control node N22 to be the first level signal Vgl. Consequently, the sixth initial control transistor M06 is turned on, causing the second clock signal ck2 to be written to the third control node N23. When the second clock signal ck2 is the first level signal Vgl, the seventh initial control transistor M07 is turned on, thereby transmitting the first level signal Vgl to the second initial node N2. This allows the stage transmission output module 120 to output the second level signal Vgh as the stage transmission signal Vnext. When the first clock signal ck1 is at a high level, the input signal Vin is written to the first initial node N1. If the input signal Vin is the second level signal Vgh at this time, the stage transmission output module 120 cannot output the first level signal Vgl as the stage transmission signal Vnext. If the input signal Vin is the second level signal Vgl at this time, the stage transmission output module 120 outputs the first level signal Vgl.

[0150] Exemplarily, the valid pulses of the first clock signal ck1 and the valid pulses of the second clock signal ck2 do not overlap. It is understood that the first clock signal ck1 can be a pulse signal, such that the first clock signal ck1 can include a high level and a low level; the input signal Vin is the stage transfer signal Vnext of the previous-stage shift register unit G, such that the input signal Vin can also include a high level and a low level. The pulse frequencies of the first clock signal ck1 and the second clock signal ck2 can be the same; in this case, the phases of the first clock signal ck1 and the second clock signal ck2 are different, i.e., when the first clock signal ck1 is at an enable level, the second clock signal ck2 is at an inactive level; conversely, when the second clock signal ck2 is at an enable level, the first clock signal ck1 is at an inactive level.

[0151] When the second initial node N2 requires a low-level signal, the first clock signal ck1 can be set to a low level to control the second initial control transistor M02 to turn on. The low-level first-level signal Vgl can be transmitted to the first control node N21 through the turned-on second initial control transistor M02, and then transmitted to the second control node N22 through the fifth initial control transistor M05, so that the fifth capacitor C5 stores the current first-level signal Vgl of the second control node N22. When the second clock signal ck2 jumps to a low level, the seventh initial control transistor M07 is controlled to be turned on so that the low-level first-level signal Vgl can be transmitted to the second initial node N2; and / or, When the first clock signal ck1 and the input signal are low, the signal at the first initial node N1 controls the third initial control transistor M03 and the fourth initial control transistor M04 to turn on, causing the low-level first clock signal ck1 to be transmitted to the first control node N21. Similar to the above process, the low-level signal at the first control node N21 is transmitted to the second control node N22 via the fifth initial control transistor M05, causing the fifth capacitor C5 to store the current low-level signal at the second control node N22. When the second clock signal ck2 transitions to a low level, the seventh initial control transistor M07 is controlled to turn on, allowing the low-level signal to be transmitted to the second initial node N2. When the second initial node N2 requires a high-level signal, the twelfth initial control transistor M12 can be controlled to turn on when the signal at the first initial node N1 is low, causing the high-level second-level signal Vgh to be transmitted to the second initial node N2. This allows the signal at the second initial node N2 to be set as needed.

[0152] Similarly, when the first initial node N1 requires a high-level signal, the first clock signal ck1 can control the first initial control transistor M01 to turn on when the input signal Vin is at a high level. In this case, the signal at the first initial node N1 can be consistent with the high-level input signal Vin. Alternatively, the reset signal Rst can be used to control the eighth initial control transistor M08 to turn on, so that the high-level second-level signal Vgh is transmitted to the first initial node N1. When the first initial node N1 requires a low-level signal, the first clock signal ck1 can control the first initial control transistor M11 to turn on when the input signal Vin is at a low level, so that the first initial control transistor M01 can transmit the low-level input signal Vin to the first initial node N1. This configuration allows the signal at the first initial node N1 to be controlled as needed.

[0153] Figure 22 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 22As shown, the initial control module 110 further includes a charge pump unit 113, which includes an eighth initial control transistor M08, a ninth initial control transistor M09, a tenth initial control transistor M10, and a sixth capacitor C6. The first initial node N1 includes a first initial sub-node N1a and a second initial sub-node N1b. The gate and first electrode of the eighth initial control transistor M08 are both electrically connected to the first initial sub-node N1a, and the second electrode of the eighth initial control transistor M08 is electrically connected to the second initial sub-node N1b. The gate of the ninth initial control transistor M09 is electrically connected to the first initial sub-node N1a, and the first electrode of the ninth initial control transistor M09 receives the second clock signal ck2. The second electrode of the ninth initial control transistor M09 is electrically connected to the first plate of the sixth capacitor C6, and the second plate of the sixth capacitor C6 is electrically connected to the first initial sub-node N1a. A gate of the tenth initial control transistor M10 is electrically connected to the second control node N21 , a first electrode of the tenth initial control transistor M10 receives the second level signal Vgh, and a second electrode of the tenth initial control transistor M10 is electrically connected to the first plate of the sixth capacitor C6 .

[0154] For example, taking the eighth initial control transistor M08, the ninth initial control transistor M09, and the tenth initial control transistor M10 as P-type MOS transistors, when the input signal Vin is at a low level, if the first clock signal ck1 is at a low level, the first initial control transistor M01 is turned on, so that the first initial sub-node N1a is at a low level, thereby making the eighth initial control transistor M88 and the ninth initial control transistor M09 both turned on, and the second initial sub-node N1b is also at a low level. The polarity of the first clock signal ck1 is opposite to that of the second clock signal ck2, and at this time, the second clock signal ck2 is at a high level; at this time, if the first clock signal When the clock signal ck1 jumps from a low level to a high level, the second clock signal ck2 jumps from a high level to a low level, the first initial control transistor M01 is disconnected, and the first initial sub-node N11 remains at a low level, so that the eighth initial control transistor M08 and the ninth initial control transistor M09 are continuously turned on. Under the coupling action of the sixth capacitor C6, the low level of the second clock signal ck2 causes the potential of the second initial sub-node N12 to be further pulled down, so that the first-level transmission output transistor M21 in the level transmission output module 120 is fully turned on, so that the level transmission signal Vnext output by the level transmission output module 120 quickly jumps to the first level signal Vgl. When the input signal Vin is at a high level, if the first clock signal ck1 is at a low level, the first initial control transistor M01 is turned on, causing the first initial sub-node N11 to be at a high level, turning off the eighth initial control transistor M08 and the ninth initial control transistor M09. The low level of the first clock signal ck1 also turns on the second initial control transistor M02, writing the first level signal Vgl to the first control node N21, turning on the tenth initial control transistor M10, and writing the second level signal Vgh to the sixth capacitor C6 via the tenth initial control transistor M10. At this point, under the coupling effect of the sixth capacitor C6, the potential of the first initial sub-node N11 is pulled up, completely turning off the eighth initial control transistor M08, thereby reducing leakage current at the second initial sub-node N12 and maintaining a stable signal at the second initial sub-node N12, thereby ensuring that the second-stage output transistor M21 in the stage output module 120 is stably in the off state.

[0155] For example, continue to refer to Figure 22The initial control module 110 further includes an eleventh initial control transistor M11. A first electrode of the eleventh initial control transistor M11 is electrically connected to the second electrode of the first initial control transistor M01. A second electrode of the eleventh initial control transistor M11 and a first electrode of the eighth initial control transistor M08 are electrically connected to the first initial sub-node N11. A gate of the eleventh initial control transistor M11 receives a first level signal Vgl. The eleventh initial control transistor M11 may be a PMOS transistor, serving as a voltage stabilizing transistor for stabilizing the voltage between the first initial sub-node N11 and its first electrode.

[0156] Figure 23 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 23 As shown, the first initial control unit 111 may further include a thirteenth initial control transistor M13. The gate of the thirteenth initial control transistor M13 receives the first clock signal ck1, the first electrode of the thirteenth initial control transistor M13 receives the input signal Vin, and the second electrode of the thirteenth initial control transistor M13 is electrically connected to the third initial subnode N13. Thus, the thirteenth initial control transistor M13 can be turned on or off under the control of the first clock signal ck1, and when turned on, writes the input signal Vin to the third initial subnode N13. The channel type of the thirteenth initial control transistor M13 can be the same as the channel type of the first initial control transistor M01, for example, both can be P-type MOS transistors, so that the signal at the third initial subnode N13 can be the same as the signal at the first initial subnode N11. In this case, the gate of the third initial control transistor M03, the gate of the fourth initial control transistor M04, and the first electrode of the eighth initial control transistor M08 in the second initial control unit 112 can all be electrically connected to the third initial subnode N13.

[0157] Exemplary, reference Figure 23 The initial control module 110 further includes a fourteenth initial control transistor M14, whose gate can receive the first level signal Vgl, a first electrode electrically connected to the third initial sub-node N13, and a second electrode electrically connected to the fourth initial sub-node N14. The fourteenth initial control transistor M14 can be a PMOS transistor, serving as a voltage regulator transistor for stabilizing the voltages of the third initial sub-node N13 and the fourth initial sub-node N14. At this time, the gate of the twelfth initial control transistor M12 can be electrically connected to the fourth initial sub-node N14.

[0158] In an exemplary embodiment, taking the case where all transistors in the shift register unit are P-type transistors, Figure 24 This is another driving timing diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Figure 22 and Figure 24The first display frame of the first mode Mode1 includes stages t11 to t17. During stage t11, the drive control signal Vct remains at a low level, the auxiliary control signal Vac is at a low level, the input signal Vin is at a low level, and the first clock signal ck1 and the fourth clock signal ck4 are at a high level, while the second clock signal and the third clock signal ck3 are at a low level. At this time, the first clock signal ck1 controls the first initial control transistor M01 and the second initial control transistor M02 to be disconnected, and the signal V_N1 of the first initial node N1 remains at the low level of the previous stage. The third initial control transistor M03, the fourth initial control transistor M04, the twelfth initial control transistor M12, the first-stage transmission output transistor M21, the fourth drive control transistor M44, and the first drive output transistor M45 are all turned on. The second level signal Vgh is transmitted to the second initial node N2 through the twelfth initial control transistor M12, so that the signal V_N2 of the second initial node N2 is high, and the fifth capacitor C5 keeps the high level of the second initial node N2 stable. Then, the high level signal of the second initial node N2 controls the second-stage transmission output transistor M22 to be disconnected, and the second level signal Vgh cannot be transmitted to the second electrode of the second-stage transmission output transistor M22. The first level signal Vgl is transmitted from the first electrode of the first-stage transmission output transistor M21 to its second electrode, so that the stage transmission signal Vnext is the first level signal Vgl of low level. Combined with reference Figure 15 In the stage t01 of the embodiment, when the auxiliary control signal Vac and the third clock signal ck3 are at a low level and the fourth clock signal ck4 is at a high level, the auxiliary drive signal Vad is at a low level, the first drive control transistor M41 is turned off, and the drive control signal Vct cannot be written to the first drive control node N6, so that the signal V_N6 of the first drive control node N6 remains at a high level in the previous stage. Then, the third drive control transistor M43 is turned off, and the signal of the second initial node N2 cannot be written to the second drive control node N7. The first-level signal Vgh is written to the second drive control node N7 through the conductive fourth drive control transistor M44, so that the signal V_N7 of the second drive control node N7 is at a high level, controlling the second drive output transistor M46 to be turned off, so that the second-level signal Vgh cannot be transmitted to the second electrode of the second drive output transistor M46. The first-level signal Vgl is transmitted from the first electrode to the second electrode of the first drive output transistor M45, so that the gate drive signal Gout is the low-level first-level signal Vgl, which is the same as the stage transfer signal Vnext.

[0159] In the t12 stage, the drive control signal Vct remains at a low level, the auxiliary control signal Vac is at a high level, the input signal Vin becomes a high level, and at the same time the first clock signal ck1 and the fourth clock signal ck4 are at a low level, and the second clock signal ck2 and the third clock signal ck3 are at a high level. At this time, the first clock signal ck1 controls the first initial control transistor M01 and the second initial control transistor M02 to be turned on, and the high level of the input signal Vin is written to the first initial node N1 through the first initial control transistor M01, so that the signal V_N1 of the first initial node N1 becomes a high level. The high level signal can control the third initial control transistor M03, the fourth initial control transistor M04, the twelfth initial control transistor M12, the first-stage transmission output transistor M21, the fourth drive control transistor M44 and the first The driving output transistors M45 are all disconnected; the first level signal Vgl is written to the first control node N21 through the second initial control transistor M02, so that the second control node N22 follows the first control node N21 to become the low level first level signal Vgl, then the sixth initial control transistor M06 is turned on, the high level second clock signal ck2 is transmitted to the third control node N23 through the sixth initial control transistor M06, and the high level second clock signal ck2 controls the seventh initial control transistor M07 to turn off, the signal V_N2 of the second initial node N2 remains at the high level written in the previous stage, and controls the second stage transmission transistor M22 to turn off, so that the high level first level signal Vgh cannot be transmitted to the second electrode of the second stage transmission transistor M22, so that the stage transmission signal Vnext maintains the low level of the previous stage. Then the stage transmission signal Vnext second driving control transistor M42 is turned on, combined with reference Figure 15 In the t03 stage, when the auxiliary control signal Vac and the third clock signal ck3 are at a high level and the fourth clock signal ck4 is at a low level, the auxiliary drive signal Vad is at a low level, and the first drive control transistor M41 is controlled to be turned on, so that the low level of the drive control signal Vct is sequentially written to the first drive control node N6 through the first drive control transistor M41 and the second drive control transistor M42, that is, the signal V_N6 of the first drive control node N6 is at a low level, so that the high level signal of the second initial node N2 is transmitted to the second drive control node N7 through the third drive control transistor M33, and the signal V_N7 of the second drive control node N7 is at a high level. This high level signal can control the second drive output transistor M46 to be turned off, so that the second level signal Vgh cannot be transmitted to the second electrode of the second drive output transistor M46, so that the stage transfer signal Vnext and the gate drive signal Gout both remain at the low level of the previous stage.

[0160] In the t13 stage, the drive control signal Vct remains at a low level, the auxiliary control signal Vac remains at a high level, the input signal Vin remains at a high level, and at the same time, the first clock signal ck1 and the fourth clock signal ck4 are at a high level, and the second clock signal ck2 and the third clock signal ck3 are at a low level. At this time, the first clock signal ck1 controls the first initial control transistor M01 and the second initial control transistor M02 to be disconnected, the signal V_N1 of the first initial node N1 remains at a high level of the previous stage, the third initial control transistor M03, the fourth initial control transistor M04, the twelfth initial control transistor M12, the first-stage transfer output transistor M21, the fourth drive control transistor M44 and the first drive output transistor M45 are all disconnected; and the first control node N21 and the second control node N2 2 remains at the low level of the previous stage; the sixth initial control transistor M06 remains turned on, and the low-level second clock signal ck2 controls the seventh initial control transistor M07 to turn on, so that the low-level second clock signal ck2 is written to the third control node N23 through the sixth initial control transistor M06, and then written to the second initial node N2 through the turned-on seventh initial control transistor M07, so that the signal V_N2 of the second initial node N2 is low, and the fifth capacitor C5 makes the low level of the second initial node N2 remain stable, then the second initial node N2 controls the second-stage transmission output transistor M22 to turn on, and the second-level signal Vgh is transmitted to its second electrode through the first electrode of the second-stage transmission output transistor M22, so that the stage transmission signal Vnext is the high-level second-level signal Vgh. Combined with reference Figure 15 In the t05 stage, when the auxiliary control signal Vac and the fourth clock signal ck4 are at a high level and the third clock signal ck3 is at a low level, the auxiliary drive signal Vad is at a high level, controlling the first drive control transistor M41 to be disconnected, and the drive control signal Vct cannot be transmitted to the first drive control node N6, so that the signal V_N6 of the first drive control node N6 is maintained at a low level in the previous stage under the action of the third capacitor C3, and the third drive control transistor M43 remains turned on, and the low-level signal of the second initial node N2 is written to the second drive control node N7. The signal V_N7 of the second drive control node N7 is at a low level, controlling the second drive output transistor M46 to be turned on, so that the second-level signal Vgh is transmitted to the second electrode of the second drive output transistor M46 through the first electrode thereof, so that the gate drive signal is the second-level signal Vgh of a high level, which is the same as the stage transfer signal Vnext.

[0161] In the t14 stage, the drive control signal Vct remains at a low level, the auxiliary control signal Vac is at a high level, the input signal Vin remains at a high level, and at the same time, the first clock signal ck1 and the fourth clock signal ck4 are at a low level, and the second clock signal ck2 and the third clock signal ck3 are at a high level. At this time, the first clock signal ck1 controls the first initial control transistor M01 and the second initial control transistor M02 to be turned on, and the high level of the input signal Vin is written to the first initial node N1 through the first initial control transistor M01, so that the signal V_N1 of the first initial node N1 remains at a high level, the third initial control transistor M03, the fourth initial control transistor M04, the twelfth initial control transistor M12, the first-stage transmission output transistor M21, the fourth drive control transistor M44 and the first drive output transistor M4 5 are all kept in the off state; the first level signal Vgl is written to the first control node N21 through the second initial control transistor M02, so that the second control node N22 follows the first control node N21 to become the low level first level signal Vgl, then the sixth initial control transistor M06 is turned on, the high level second clock signal ck2 is transmitted to the third control node N23 through the sixth initial control transistor M06, and the high level second clock signal ck2 controls the seventh initial control transistor M07 to be turned off, the signal V_N2 of the second initial node N2 is kept at the low level written in the previous stage, and the second-stage transmission output transistor M22 is controlled to be turned on, so that the high level first level signal Vgh is transmitted from the first electrode of the second-stage transmission output transistor M22 to its second electrode, and the stage transfer signal Vnext maintains the high level of the previous stage. The high-level stage transfer signal Vnext controls the second drive control transistor M42 to turn off, and the high-level auxiliary drive signal Vad controls the first drive control transistor M41 to turn off, then the stage transfer signal Vnext controls the second drive control transistor M42 to turn off, and at the same time, the auxiliary drive signal Vad remains at a high level to control the first drive control transistor M41 to turn off, so that the signal V_N6 of the first drive control node N6 remains at the low level written in the previous stage, so that the third drive control transistor M43 is turned on, so that the low-level signal of the second initial node N2 is transmitted to the second drive control node N7 through the third drive control transistor M33, and the signal V_N7 of the second drive control node N7 is low, then the second drive output transistor M46 remains turned on, and the gate drive signal Gout output by the second drive output transistor M46 is the second level signal Vgh, so that the stage transfer signal Vnext and the gate drive signal Gout both remain at the high level of the previous stage.

[0162] In the t15 stage, the drive control signal Vct remains at a low level, the auxiliary control signal Vac remains at a high level, the input signal Vin becomes a low level, and at the same time the first clock signal ck1 and the fourth clock signal ck4 are at a high level, the second clock signal ck2 and the third clock signal ck3 are at a low level. At this time, the first clock signal ck1 controls the first initial control transistor M01 and the second initial control transistor M02 to be disconnected, the signal V_N1 of the first initial node N1 remains at a high level of the previous stage, the third initial control transistor M03, the fourth initial control transistor M04, the twelfth initial control transistor M12, the first-stage transfer output transistor M21, the fourth drive control transistor M44 and the first drive output transistor M45 are all disconnected; and the first control node N21 and the second control node N22 remain It is the low level of the previous stage; the sixth initial control transistor M06 remains turned on, and the low-level second clock signal ck2 controls the seventh initial control transistor M07 to be turned on, so that the low-level second clock signal ck2 is written to the third control node N23 through the sixth initial control transistor M06, and then written to the second initial node N2 through the turned-on seventh initial control transistor M07, so that the signal V_N2 of the second initial node N2 is low, and the fifth capacitor C5 keeps the low level of the second initial node N2 stable, then the low-level signal of the second initial node N2 controls the second-stage transmission output transistor M22 to be turned on, then the second-level signal Vgh is transmitted to its second pole through the first pole of the second-stage transmission output transistor M22, so that the stage transmission signal Vnext is the high-level second-level signal Vgh. The high-level stage transfer signal Vnext controls the second drive control transistor M42 to turn off, and the auxiliary drive signal Vad remains at a high level to control the first drive control transistor M41 to turn off. The signal V_N6 of the first drive control node N6 remains at a low level in the previous stage, then the third drive control transistor M43 remains turned on, the low-level signal of the second initial node N2 is written to the second drive control node N7, and the signal V_N7 of the second drive control node N7 is at a level, which controls the second drive output transistor M46 to turn on, so that the second-level signal Vgh is transmitted through the first electrode of the second drive output transistor M46 to its second electrode, so that the gate drive signal is a high-level second-level signal Vgh, which is the same as the stage transfer signal Vnext.

[0163] In the t16 phase, the drive control signal Vct remains at a high level, the auxiliary control signal Vac remains at a high level, the input signal Vin remains at a low level, and the first clock signal ck1 and the fourth clock signal ck4 are at a low level, while the second clock signal ck2 and the third clock signal ck3 are at a high level. At this time, the first clock signal ck1 controls the first initial control transistor M01 and the second initial control transistor M02 to be turned on. The low level of the input signal Vin is written to the first initial node N1 through the first initial control transistor M01, causing the signal V_N1 of the first initial node N1 to be at a low level. The third initial control transistor M03, the fourth initial control transistor M04, the twelfth initial control transistor M12, the first-stage transmission output transistor M21, the fourth drive control transistor M44, and the first drive output transistor M45 are all turned on. The first level signal Vgl is written to the first control node N21 through the second initial control transistor M02, causing the second control node N22 to follow the first level signal Vgl at a low level at the first control node N21. Then, the sixth initial control transistor The initial control transistor M06 is turned on, and the high-level second clock signal ck2 is transmitted to the third control node N23 through the sixth initial control transistor M06. The high-level second clock signal ck2 controls the seventh initial control transistor M07 to be turned off. The high-level second-level signal Vgh is written to the second initial node N2 through the twelfth initial control transistor M12. The signal V_N2 of the second initial node N2 is high, which controls the second-stage transmission output transistor M22 to be turned off, so that the high-level first-level signal Vgh cannot be transmitted to the second electrode of the second-stage transmission output transistor M22, and the first-level signal Vgh is transmitted to the second electrode of the first-stage transmission output transistor M21 through the first electrode, so that the stage transfer signal Vnext is the low-level first-level signal Vgl. The low-level stage transfer signal Vnext controls the second drive control transistor M42 to turn on, and the auxiliary drive signal Vad remains at a high level to control the first drive control transistor M41 to turn off, so that the signal V_N6 of the first drive control node N6 remains at the low level written in the previous stage, so that the third drive control transistor M43 is turned on, so that the high-level signal of the second initial node N2 is transmitted to the second drive control node N7 through the third drive control transistor M33, and the signal V_N7 of the second drive control node N7 is high. Then, the second drive output transistor M46 is turned off, and the second-level signal Vgh cannot be transmitted to the second electrode of the second drive output transistor M46. The first-level signal Vgl is transmitted to the second electrode of the first drive output transistor M45 through the first electrode, so that the gate drive signal Gout and the stage transfer signal Vnext both become low levels.

[0164] In the t17 stage, the input signal Vin remains at a low level, the drive control signal Vct remains at a low level, the auxiliary drive signal Vad remains at a high level, and the jumps of the first clock signal ck1 and the third clock signal ck3 do not affect the potentials of the first initial node N1, the second initial node N2, the sixth drive control node N6 and the second drive control node N7, so that the stage transfer signal Vnext and the gate drive signal Gout remain at a low level.

[0165] Until entering the second display frame DF2, the second display frame DF2 includes stages t21 to t27. In stage t21, the first clock signal ck1 and the fourth clock signal ck4 are high, the second clock signal and the third clock signal ck3 are low, the auxiliary control signal Vac jumps to a low level, the auxiliary driving module 130 repeats the working process of stage t11, and outputs a low-level auxiliary driving signal Vad; at the same time, the input signal Vin is low, the initial control module 110 and the stage transmission output module 120 repeat the working process of stage t11, output a low-level stage transmission signal Vnext, and the driving output module 140 repeats the working process of stage t11, and outputs a low-level gate driving signal Gout.

[0166] In the stage t22, the first clock signal ck1 and the fourth clock signal ck4 are at a low level, the second clock signal ck2 and the third clock signal ck3 are at a high level, the auxiliary control signal Vac jumps to a high level, the auxiliary driving module 130 repeats the working process of the stage t12, and outputs the low-level auxiliary driving signal Vad; the input signal Vin is at a high level, the initial control module 110 and the stage transmission output module 120 repeat the working process of the stage t12, and output the low-level stage transmission signal Vnext. At this time, the drive control signal Vct is at a high level, and the high-level drive control signal Vct is transmitted to the first drive control node N6 through the turned-on first drive control transistor M41, so that the signal V_N6 of the first drive control node N6 is high, and the high-level signal of the first drive control node N6 is stored by the third capacitor C3 to stabilize the potential of the first drive control node N6, then the third drive control transistor M43 is turned off, and the signal V_N2 of the second initial node N2 cannot be transmitted to the second drive control node N7, and the signal V_N7 of the second drive control node N7 remains at the high level of the previous stage, then the second drive output transistor M46 is turned off, and the high-level signal of the first initial node N1 controls the first drive output transistor M45 to turn off, so that the gate drive signal Gout remains at the low level of the previous stage.

[0167] At stage t23, the first clock signal ck1 and the fourth clock signal ck4 are high, the second clock signal ck2 and the third clock signal ck3 are low, the auxiliary control signal Vac remains high, the auxiliary drive module 130 repeats the operation process of stage t13 and outputs a high-level auxiliary drive signal Vad; the input signal Vin remains high, the initial control module 110 and the stage transmission output module 120 repeat the operation process of stage t13 and output a high-level stage transmission signal Vnext. At this time, the high-level auxiliary drive signal Vad controls the first drive control transistor M41 to turn off, the signal V_N6 at the first drive control node N6 remains high from the previous stage, the third drive control transistor M43 remains off, and the signal V_N7 at the second drive control node N7 remains high from the previous stage, causing the second drive output transistor M46 to remain off. The high-level signal at the first initial node N1 controls the first drive output transistor M45 to turn off, causing the gate drive signal Gout to remain low from the previous stage.

[0168] At stage t24, the first clock signal ck1 and the fourth clock signal ck4 are at a low level, the second clock signal ck2 and the third clock signal ck3 are at a high level, the auxiliary control signal Vac remains at a high level, and the auxiliary driver module 130 repeats the operation process of stage t14, outputting a high-level auxiliary driver signal Vad. The input signal Vin remains at a high level, and the initial control module 110 and the stage transmission output module 120 repeat the operation process of stage t14, outputting a high-level stage transmission signal Vnext. Since the auxiliary driver signal Vad remains at the high level of the previous stage, and the signal V_N1 at the first initial node N1 remains at the high level of the previous stage, the operating state of the driver output module 140 remains unchanged, and the low-level gate drive signal Gout continues to be output.

[0169] At stage t25, the first clock signal ck1 and the fourth clock signal ck4 are high, the second clock signal ck2 and the third clock signal ck3 are low, and the auxiliary control signal Vac remains high. The auxiliary driver module 130 repeats the operation process of stage t15 and outputs a high-level auxiliary driver signal Vad. The input signal Vin becomes low, and the initial control module 110 and the stage transmission output module 120 repeat the operation process of stage t15 and output a high-level stage transmission signal Vnext. At this time, since the auxiliary driver signal Vad remains high at the previous stage, and the signal V_N1 at the first initial node N1 remains high at the previous stage, the operating state of the driver output module 140 remains unchanged, and it continues to output the low-level gate drive signal Gout.

[0170] In the stage t26, the first clock signal ck1 and the fourth clock signal ck4 are at a low level, the second clock signal ck2 and the third clock signal ck3 are at a high level, the auxiliary control signal Vac remains at a high level, the auxiliary driving module 130 repeats the working process of the stage t15, and outputs the high-level auxiliary driving signal Vad; the input signal Vin remains at a low level, the initial control module 110 and the stage transmission output module 120 repeat the working process of the stage t15, and output the low-level stage transmission signal Vnext. At this time, since the auxiliary drive signal Vad remains at the high level of the previous stage, the first drive control transistor M41 remains in the off state, the signal V_N6 of the first drive control node N6 remains at the high level of the previous stage, the third drive control transistor M43 remains off, and the signal V_N7 of the second drive control node N7 remains at the high level of the previous stage, so that the second drive output transistor M46 remains off; the low level signal of the first initial node N1 controls the first drive output transistor M45 to turn on, so that the first level signal Vgl is transmitted from the first pole of the first drive output transistor M45 to its second pole, so that the gate drive signal Gout remains at a low level.

[0171] In the t27 stage, the input signal Vin remains at a low level, the drive control signal Vct remains at a high level, the auxiliary drive signal Vad remains at a high level, and the jumps of the first clock signal ck1 and the third clock signal ck3 do not affect the potentials of the first initial node N1, the second initial node N2, the sixth drive control node N6 and the second drive control node N7, so that the stage transfer signal Vnext and the gate drive signal Gout remain at a low level.

[0172] Optional, combined with reference Figure 22 and 24 In the same display frame, the valid pulse of the auxiliary driving signal Vad of the same shift register unit G is located before the first valid pulse of the level transfer signal Vnext.

[0173] Specifically, when the level transfer signal Vnext outputs a low level, the auxiliary drive signal Vad can output a valid pulse, so that the current drive control signal Vct can be transmitted to the first drive control node N6, so that the drive control signal Vct can control the signal of the second drive control node N7, thereby realizing the setting of the gate drive signal Gout.

[0174] In this way, when the level transmission signal Vnext of the i-th stage shift register unit Gi is used as the input signal Vin of the j-th stage shift register unit Gj, in the stage where the driving control signal Vct is at a low level, the auxiliary driving signal Vad can be controlled to output a low-level pulse before the level transmission signal Vnext outputs the first valid pulse, so that the driving control signal Vct can control the signal V_N7 of the second driving control node N7 to be consistent with the signal V_N2 of the second initial node N2. Then, under the control of the enable level of the driving control signal Vct, the level transmission signal Vnext of the i-th stage shift register unit Gi and the j-th stage shift register unit Gj can be made consistent. The low-level signal of the level transmission signal Vnext of the register unit Gj can be shifted in sequence. At the same time, the low-level signals of the gate drive signal Gout of the i-th level shift register unit Gi and the gate drive signal Gout of the y-th level shift register unit Gj can also be shifted in sequence, so that the low-level signals of the level transmission signal Vnext and the gate drive signal Gout output by the shift register units G at each level of the driving circuit can be shifted in sequence. At this time, if the gate drive signal Gout output by the shift register units G at each level is used to control the signal refresh time of each row of pixel circuits, it is possible to achieve row-by-row scanning of each row of pixel circuits in the display panel. During the high-level phase of the drive control signal Vct, the auxiliary drive signal Vad can be controlled to output a low-level pulse before the first valid pulse of the level transmission signal Vnext is output. This allows the drive control signal Vct to control the signal V_N7 of the second drive control node N7 without being affected by the signal V_N2 of the second initial node N2. The low-level signals of the level transmission signal Vnext of the x-th shift register unit Gx and the level transmission signal Vnext of the y-th shift register unit Gy can be shifted sequentially, allowing each level of the shift register unit G to operate normally. The gate drive signal Gout of the x-th shift register unit Gx remains high, and the pixel circuit electrically connected to the x-th shift register unit Gx stops refreshing. In this way, by setting the drive control signal VCT received by the shift register unit G corresponding to different display areas, different display areas can have different refresh frequencies.

[0175] Optional, combined with reference Figure 4 、 Figure 22 and Figure 24 , the first clock signal ck1 is multiplexed into the fourth clock signal ck4; the second clock signal ck2 is multiplexed into the third clock signal ck3.

[0176] Specifically, in each of the above-mentioned stages, the first clock signal ck1 and the fourth clock signal ck4 have the same transition conditions, and the second clock signal ck2 and the third clock signal ck3 have the same transition conditions. Therefore, the first clock signal ck1 can be set to be multiplexed as the fourth clock signal ck4, and the second clock signal ck2 can be multiplexed as the third clock signal ck3, which can reduce the signal setting and reduce the setting of the clock signal line in the display panel 100. In this way, it can be ensured that each shift register unit G can reduce the setting of the clock signal line and simplify the circuit structure on the basis of normally outputting the gate drive signal Gout and the stage transfer signal Vnext.

[0177] Exemplary, reference Figure 4 A row of pixel circuits 20 in the high-frequency display area A22 that is adjacent to the low-frequency display area A21 constitutes a first pixel row 21. The shift register unit G electrically connected to each pixel circuit 20 in the first pixel row 21 is a first shift register unit GA. A row of pixel circuits 20 in the low-frequency display area A21 that is adjacent to the high-frequency display area A22 constitutes a second pixel row 22. The shift register unit G electrically connected to each pixel circuit 20 in the second pixel row 22 is a second shift register unit GB. The first shift register unit GA is cascaded with the second shift register unit GB. That is, the stage transfer signal VnextA of the first shift register unit GA serves as the input signal VinB of the second shift register unit GB, and the auxiliary drive signal VadA of the first shift register unit GA serves as the auxiliary control signal VacB of the second shift register unit GB. Figure 25 This is another driving timing diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Figure 3 、 Figure 22 and Figure 25 In the second display frame DF of the first mode Mode, after the gate drive signal GoutA of the first shift register unit GA outputs a valid pulse, in order to prevent the gate drive signal Gout of the second shift register unit GB from outputting a valid pulse, the drive control signal Vct is controlled to jump to a high level when the auxiliary drive signal VadB of the second shift register unit GB outputs a low level pulse, or before the auxiliary drive signal VadB of the second shift register unit GB outputs a low level pulse, that is, the drive control signal Vct is controlled to jump to a high level during the t32 stage or before the t32 stage, so that when the auxiliary drive signal VadB outputs a low level pulse, the high level of the drive control signal Vct is written to its first drive control node V_N6_B, so that the first drive control node V_N6_B remains at a high level, thereby ensuring that the gate drive signal GoutB of the second shift register unit GB continues to remain at a low level, and the signal of the second pixel row 22 is not refreshed.

[0178] Optional, combined with reference Figure 3 、 Figure 22and Figure 25 , in the same display frame, the gate driving signals of at least some of the shift register units G output m valid pulses; m is a positive integer, and m≥2.

[0179] Specifically, in the second display frame DF2 of the first mode Mode1, the gate drive signal Gout02 output by each of the second-type shift register units G02 can be set to include two or more valid pulses, so that the gate drive signal Gout02 output by each of the second-type shift register units G02 can meet the multi-pulse requirements of the pixel circuits 20 in the high-frequency display area A22, thereby enabling data writing and bias adjustment of the drive transistors T0 in the pixel circuits 20, thereby improving the display effect of the display panel 100. In the second mode Mode2, the gate drive signal output by each of the second-type shift register units G can be set to include two or more valid pulses, so that the gate drive signal Gout output by each of the second-type shift register units G can meet the multi-pulse requirements of the pixel circuits 20 in each row in the display area A2, thereby improving the display effect of the display panel 100.

[0180] For the case where the gate drive signal Gout includes multiple valid pulses, the figure exemplarily shows that the gate drive signal Gout includes two valid pulses. Then, at the t31 stage, the auxiliary drive signal VadA outputs a low-level pulse. At the same time, the level transfer signal VnextA and the drive control signal Vct of the first shift register unit GA are low-level. The drive control signal Vct is written to its first drive control node V_N6_A, so that the first drive control node V_N6_A remains at a low level. After the t31 stage, the auxiliary drive signal VadA jumps to a high level and remains at a low level. If the driving control signal Vct is maintained at a high level and no longer jumps, then when the driving control signal Vct jumps to a high level in the t32 stage, the high-level signal of the driving control signal Vct will not be written to its first driving control node V_N6_A, so that the signal of the first driving control node V_N6_A of the first shift register unit GA remains at a low level in the current display frame, thereby making the gate driving signal GoutA of the first shift register unit GA consistent with the level transmission signal Vnext, and the gate driving signal GoutA can synchronously output a valid pulse when the level transmission signal Vnext outputs a valid pulse.

[0181] In this way, by setting the auxiliary driving module 130 to provide the auxiliary driving signal Vad to the driving output module 140, and controlling the auxiliary driving signal Vad to output a valid pulse before the level transfer signal Vnext outputs the first valid pulse, the multi-pulse output of the first shift register unit GA can be guaranteed, so that the display grayscale of the current display frame will not be inaccurate due to pulse loss, and the output of the non-enable level of the gate driving signal Gout of each first-class register unit G01 will not be affected, and the low-frequency refresh of the low-frequency display area A21 will not be affected, thereby improving the display effect of the display panel.

[0182] Optional, combined with reference Figure 3 、 Figure 22 and Figure 24 , during at least a portion of the time in the first mode Mode1, the driving control signal Vct is at a non-enable level; and during a portion of the time in the first mode Mode1, the driving control signal Vct is at an enable level.

[0183] Specifically, during part of the time in the first mode Mode1, the driving control signal Vct is at the enable level, such as Figure 24 In the stage of the first display frame DF1, in the shift register units G at each level where the enable level time of the stage transfer signal Vnext overlaps with the enable level time of the drive control signal Vct, the signal of the second drive control node N7 can be synchronized with the signal of the second initial node N2 during the time period when the drive control signal Vct is at the enable level, so that the gate drive signal Gout outputted therefrom is synchronized with the initial output signal Vnext, so that the shift register unit G can work normally while the corresponding connected pixel circuit 20 also performs signal refresh.

[0184] Optional, combined with reference Figure 4 、 Figure 22 and Figure 10 In the second mode Mode2, the drive control signal Vct is at the enable level. In the second mode Mode2, the drive control signal Vct is continuously maintained at the enable level, which allows the drive control module of the first-type shift register unit G01 to control the signal of the second drive control node N7 to be synchronized with the signal of the second initial node N2. In this process, the gate drive signal Gout output by each level of the shift register unit G is synchronized with the initial output signal Vnext, so that each level of the shift register unit G can operate normally and the corresponding pixel circuit can also perform signal refresh.

[0185] Optional, combined with reference Figure 4 、 Figure 22 、 Figure 24 and Figure 25In the first mode Mode1, when the auxiliary driving signal Vad of the second type shift register unit G02 outputs a valid pulse, the driving control signal Vct is at an enable level.

[0186] Specifically, when the auxiliary drive signal Vad of the second-type shift register unit G02 outputs a valid pulse, the drive control signal Vct is at an enable level, so that the enable level signal of the drive control signal Vct can be written to its first drive control node V_N6, so that the first drive control node V_N6_A remains at an enable level, thereby ensuring that the non-enable level signal of the drive control signal Vct will not be written to its first drive control node V_N6, so that the signal of the first drive control node V_N6 of the second-type shift register unit G02 at each level remains at a low level in the current display frame, thereby making the gate drive signal Gout of the second-type shift register unit G02 at each level consistent with the level transmission signal Vnext, and being able to synchronously output a valid pulse when the level transmission signal Vnext outputs a valid pulse.

[0187] Optional, continue with reference Figure 4 、 Figure 22 、 Figure 24 and Figure 25 In the first mode Mode1, when the auxiliary driving signal Vad of the first type shift register unit G01 outputs a valid pulse, the driving control signal Vct is at a non-enable level.

[0188] Specifically, when the auxiliary driving signal Vad of the first type shift register unit G01 outputs a valid pulse, the driving control signal Vct is at a non-enable level, so that the non-enable level signal of the driving control signal Vct can be written to its first driving control node V_N6, so that the first driving control node V_N6 remains at a non-enable level, thereby ensuring that the enable level signal of the driving control signal Vct will not be written to its first driving control node V_N6, so that the signal of the first driving control node V_N6 of the second type shift register unit G02 at each level remains at a non-enable level in the current display frame, thereby making the gate driving signal Gout of the second type shift register unit G02 at each level remain at a non-enable level, and no valid pulse is output, thereby realizing low-frequency refresh of the low-frequency display area A21.

[0189] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel provided in embodiments of the present invention. Therefore, the display device possesses the technical features of the display panel and driving method provided in embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in embodiments of the present invention. Similarities can be found in the above description of the display panel provided in embodiments of the present invention, and will not be repeated here.

[0190] For example, Figure 26 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 26 As shown, the display device 200 includes the display panel 100 provided in an embodiment of the present invention. The display device 200 provided in an embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0191] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: Drive circuit; The driving circuit includes N stages of shift register units cascaded with each other; the shift register unit includes an initial control module, a stage transmission output module, an auxiliary driving module and a driving output module; In the same shift register unit, the initial control module is used to receive at least an input signal, a first clock signal and a second clock signal, and control the signals of the first initial node and the second initial node; The level transmission output module is used to receive at least the signal of the first initial node, the signal of the second initial node, the first level signal and the second level signal, and control the level transmission signal; The auxiliary driving module is used to receive at least the auxiliary control signal, the third clock signal, the fourth clock signal and the second level signal, and control the auxiliary driving signal; The driving output module is used to receive the driving control signal, the signal of the first initial node, the signal of the second initial node, the stage transmission signal, the auxiliary driving signal, the first level signal and the second level signal, and control the gate driving signal; Among them, the level transmission signal of the shift register unit of the i-th level is the input signal of the shift register unit of the j-th level; and the auxiliary driving signal of the shift register unit of the i-th level is the auxiliary control signal of the shift register unit of the j-th level; i, j and N are all positive integers, i≠j and i and j are both less than or equal to N.

2. The display panel according to claim 1, wherein: In a same display frame, the valid pulse of the auxiliary driving signal of the same shift register unit is located before the first valid pulse of the stage transfer signal.

3. The display panel according to claim 1, wherein: In a same display frame, the gate driving signals of at least part of the shift register units output m valid pulses; m is a positive integer, and m≥2.

4. The display panel according to claim 1, wherein: The auxiliary driving module includes: a first auxiliary node control unit, a second auxiliary node control unit and an auxiliary driving output unit; The first auxiliary node control unit is used to receive the auxiliary control signal and the third clock signal, and control the signal of the first auxiliary node; The second auxiliary node control unit is used to receive the signal of the first auxiliary node, the third clock signal and the first level signal, and control the signal of the second auxiliary node; The auxiliary driving output unit is configured to receive the signal of the first auxiliary node, the signal of the second auxiliary node, the second level signal, and the fourth clock signal, and control the auxiliary driving signal.

5. The display panel according to claim 4, wherein: The first auxiliary node control unit includes a first auxiliary transistor; A first electrode of the first auxiliary transistor receives the auxiliary control signal, a second electrode of the first auxiliary transistor is electrically connected to the first auxiliary node, and a gate of the first auxiliary transistor receives the third clock signal.

6. The display panel according to claim 4, wherein: The second auxiliary node control unit includes a second auxiliary transistor and a third auxiliary transistor; A first electrode of the second auxiliary transistor receives the first level signal, a second electrode of the second auxiliary transistor is electrically connected to the second auxiliary node, and a gate of the second auxiliary transistor receives the third clock signal; A first electrode of the third auxiliary transistor receives the third clock signal, a second electrode of the third auxiliary transistor is electrically connected to the second auxiliary node, and a gate of the third auxiliary transistor is electrically connected to the first auxiliary node.

7. The display panel according to claim 4, wherein: The auxiliary drive output unit includes a fourth auxiliary transistor and a fifth auxiliary transistor; A first electrode of the fourth auxiliary transistor receives the fourth clock signal, a gate of the fourth auxiliary transistor is electrically connected to the first auxiliary node, or the gate of the fourth auxiliary transistor is electrically connected to the first auxiliary node via a first voltage stabilizing unit, and a second electrode of the fourth auxiliary transistor outputs the auxiliary driving signal; A first electrode of the fifth auxiliary transistor receives the second level signal, a gate of the fifth auxiliary transistor is electrically connected to the second auxiliary node, and a second electrode of the fifth auxiliary transistor outputs the auxiliary driving signal.

8. The display panel according to claim 7, wherein: The first voltage stabilizing unit includes: a sixth auxiliary transistor; A first electrode of the sixth auxiliary transistor is electrically connected to the first auxiliary node, a second electrode of the sixth auxiliary transistor is electrically connected to the gate of the fourth auxiliary transistor, and the gate of the sixth auxiliary transistor receives the first level signal.

9. The display panel according to claim 7, wherein: The auxiliary driving module further includes: a first capacitor and a second capacitor; The first capacitor is electrically connected between the gate and the second electrode of the fourth auxiliary transistor; the second capacitor is electrically connected between the gate and the first electrode of the fifth auxiliary transistor.

10. The display panel according to claim 1, wherein The display panel includes a first type shift register unit; in the first type shift register unit, the frequency of the level transmission signal is F11, and the frequency of the gate driving signal is F12; The operating mode of the display panel includes a first mode; in the first mode, F11≠F12.

11. The display panel according to claim 10, wherein: In the first mode, F11>F12.

12. The display panel according to claim 10, wherein: The display panel includes a second type of shift register unit; in the second type of shift register unit, the frequency of the level transmission signal is F21, and the frequency of the gate driving signal is F22; In the first mode, F21 = F22.

13. The display panel according to claim 10, wherein: The operating mode of the display panel further includes a second mode; in the second mode, F11 = F12.

14. The display panel according to claim 10, wherein: During at least part of the time in the first mode, the drive control signal is at a non-enable level; Furthermore, during a portion of the time in the first mode, the driving control signal is at an enable level.

15. The display panel according to claim 13, wherein: In the second mode, the driving control signal is at an enable level.

16. The display panel according to claim 12, wherein: In the first mode, when the auxiliary driving signal of the second-type shift register unit outputs a valid pulse, the driving control signal is at an enable level.

17. The display panel according to claim 16, wherein: In the first mode, when the auxiliary driving signal of the first type shift register unit outputs a valid pulse, the driving control signal is at a non-enable level.

18. The display panel according to claim 1, wherein The valid pulses of the first clock signal and the valid pulses of the second clock signal do not overlap with each other; The valid pulse of the third clock signal and the valid pulse of the fourth clock signal do not overlap with each other.

19. The display panel according to claim 18, wherein: The first clock signal is multiplexed into the fourth clock signal; The second clock signal is multiplexed into the third clock signal.

20. The display panel according to claim 1, wherein The drive output module includes: a first drive control unit, a second drive control unit and a drive output unit; The first driving control unit is used to receive at least the driving control signal, the stage transmission signal and the auxiliary driving signal, and control the signal of the first driving control node; The second driving control unit is configured to receive the signal of the first driving control node, the signal of the first initial node, the signal of the second initial node, and the second level signal, and control the signal of the second driving control node; The driving output unit is configured to receive a signal from the second driving control node, a signal from the first initial node, the first level signal, and the second level signal, and control a gate driving signal.

21. The display panel according to claim 20, wherein: The first drive control unit includes a first drive control transistor, a second drive control transistor and a third capacitor; A first electrode of the first drive control transistor receives the drive control signal, a gate of the first drive control transistor receives the auxiliary drive signal, and a second electrode of the first drive control transistor is electrically connected to a first electrode of the second drive control transistor; The gate of the second drive control transistor receives the level transmission signal, and the second electrode of the second drive control transistor is electrically connected to the first drive control node; A first end of the third capacitor receives a fixed voltage signal, and a second end of the third capacitor is electrically connected to the first driving control node.

22. The display panel according to claim 20, wherein: The second driving control unit includes: a third driving control transistor, a fourth driving control transistor and a fourth capacitor; A first electrode of the third drive control transistor receives a signal from the second initial node, a gate of the third drive control transistor receives a signal from the first drive control node, and a second electrode of the third drive control transistor is electrically connected to the second drive control node; A first electrode of the fourth drive control transistor receives the second level signal, a gate of the fourth drive control transistor receives the signal of the first initial node, and a second electrode of the fourth drive control transistor is electrically connected to the second drive control node; A first end of the fourth capacitor receives a fixed voltage signal, and a second end of the fourth capacitor is electrically connected to the second driving control node.

23. The display panel according to claim 20, wherein: The driving output unit includes a first driving output transistor and a second driving output transistor; A first electrode of the first driving output transistor receives the first level signal, a gate of the first driving output transistor receives the signal of the first initial node, and a second electrode of the first driving output transistor outputs the gate driving signal; A first electrode of the second driving output transistor receives the second level signal, a gate of the second driving output transistor receives a signal of the second driving control node, and a second electrode of the second driving output transistor outputs the gate driving signal.

24. The display panel according to claim 1, wherein The initial control module includes a first initial control unit and a second initial control unit; The first initial control unit is configured to receive at least the input signal and the first clock signal, and control the signal of the first initial node; The second initial control unit is configured to receive at least the signal of the first initial node, the first clock signal, the second clock signal, and the first level signal, and control the signal of the second initial node.

25. The display panel according to claim 1, wherein The level transmission output module includes a first level transmission output unit and a second level transmission output unit; The first-level transmission output unit is used to receive the signal of the first initial node and the first level signal, and control the level transmission signal; The second-stage transmission output unit is used to receive the signal of the second initial node and the first level signal, and control the stage transmission signal.

26. The display panel according to claim 1, wherein Also includes: A plurality of pixel circuits arranged in an array; The pixel circuit includes a driving transistor, a data writing module, a bias adjustment module, a reset module, a threshold compensation module and a light-emitting element; The data writing module is used to receive a data signal and a first scanning control signal, and write the data signal into the gate of the driving transistor under the control of the first scanning control signal; The bias adjustment module is used to receive a bias adjustment signal and a second scanning control signal, and control a signal transmission path of the bias adjustment signal to the driving transistor according to the second scanning control signal; The reset module is used to receive a reset signal and the second scanning control signal, and control a signal transmission path of the reset signal to the light-emitting element according to the second scanning control signal; The threshold compensation module is used to receive a third scanning control signal and compensate the threshold compensation voltage to the gate of the driving transistor under the control of the third scanning control signal; Wherein, the third scanning control signal is the gate driving signal.

27. The display panel according to claim 25, wherein: The pixel circuit further includes: an initialization module, a first light emitting control module, a second light emitting control module and a storage module; The initialization module is used to receive an initialization signal and a fourth scanning control signal, and control a signal transmission path of the initialization signal to the driving transistor according to the fourth scanning control signal; The first light emitting control module and the second light emitting control module are used to receive a light emitting control signal, and to control the driving transistor to provide a driving current to the light emitting element according to the light emitting control signal; One end of the storage module receives a fixed voltage signal, and the other end of the storage module is electrically connected to the gate of the driving transistor. The storage module is used to store the gate voltage signal of the driving transistor.

28. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 27.

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