Display device

Abstract

The invention provides a display device, which is characterized in that a data line is electrically connected to two columns of pixels arranged at intervals, a plurality of pixels in the same row comprise first pixels and corresponding second pixels which are electrically connected to the same data line, one row of pixels corresponds to a first gate line and a second gate line, and the first gate line and the second gate line correspond to each other. The first gate lines and the second gate lines are electrically connected to the corresponding multiple first pixels and the corresponding second pixels respectively, the multiple first pixels and the multiple second pixels in the same row of pixels are conducted in a time-sharing mode, and the gate line set comprises at least two first gate lines or at least two second gate lines; at least two first gate lines or at least two second gate lines in the same gate line group are electrically connected to a plurality of pixels of the same data line in the same color, the gate driver is used for transmitting a plurality of corresponding gate pulses to the plurality of gate line groups in sequence, and the phenomenon of image abnormity such as color crossing can be avoided by adopting the DLG technology under the DLS architecture.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device. Background Art

[0002] The DLS (Data Line Sharing) architecture in display devices reduces the number of source driver chips by reducing the number of data lines, thereby doubling the number of gate lines required. This means that two pixels connected to the same data line in the same row are time-shared. To increase the refresh rate of display devices, DLG (Dual Gate Line) technology is often used. This technology cuts the number of required scans in half by scanning two rows of pixels at a time, and then duplicates the displayed content to fill the remaining pixels, achieving a frequency doubling effect.

[0003] In the DLS architecture, since data lines need to be shared, if driven according to the timing of conventional DLG technology, two pixels of different colors connected to the same data line and controlled by adjacent gate lines will be turned on at the same time, resulting in abnormal screen effects such as cross-color when displaying pure color images. Summary of the Invention

[0004] The object of the present invention is to provide a display device to solve the technical problem of abnormal image phenomena such as cross-color caused by the conventional DLG technology used in the DLS architecture of the existing display device.

[0005] An embodiment of the present invention provides a display device, including:

[0006] A plurality of pixels are arranged in row and column directions;

[0007] a plurality of data lines, the data lines being electrically connected to two columns of pixels, each pixel P in each column of pixels P corresponding to the data lines being electrically connected to the data lines, and the plurality of pixels in the same row including a first pixel and a corresponding second pixel electrically connected to the same data line;

[0008] a plurality of first gate lines and a plurality of second gate lines, wherein a row of pixels corresponds to one first gate line and one second gate line, the first gate line is electrically connected to the corresponding plurality of first pixels, and the second gate line is electrically connected to the corresponding second pixels, and two gate pulses respectively transmitted by the first gate line and the second gate line electrically connected to the pixels in a row are used to control the plurality of first pixels and the plurality of second pixels in the row to be turned on in a time-sharing manner;

[0009] a gate driver electrically connected to the plurality of first gate lines and the plurality of second gate lines;

[0010] The plurality of first gate lines and the plurality of second gate lines comprise a plurality of gate line groups, the gate line groups comprising at least two of the first gate lines or at least two of the second gate lines, and at least two of the first gate lines or at least two of the second gate lines in the same gate line group are electrically connected to a plurality of pixels on the same data line having the same color;

[0011] The gate driver is used to sequentially transmit the corresponding plurality of gate pulses to the plurality of gate line groups.

[0012] In some embodiments, the same data line is used to transmit data voltages of the same polarity to two corresponding columns of pixels, and the polarities of the data voltages corresponding to the multiple columns of pixels arranged in sequence are reversed every i columns, where i is a positive integer.

[0013] In some embodiments, the polarities of the data voltages corresponding to the plurality of columns of pixels arranged sequentially are alternately arranged, and an odd number of columns of pixels are provided between two columns of pixels electrically connected to the same data line.

[0014] In some embodiments, the jth data line is electrically connected to the pixels in the jth column and the pixels in the j+kth column, j and k are both positive integers, and the pixels in the jth column arranged continuously are electrically connected to the corresponding j data lines.

[0015] In some embodiments, the i is an even number, and two adjacent columns of pixels are electrically connected to the same data line.

[0016] In some embodiments, the polarities of the two data voltages transmitted by two adjacent data lines are opposite.

[0017] In some embodiments, the same gate line group includes two first gate lines or two second gate lines, and the gate driver includes:

[0018] A plurality of cascaded gate driving units, each of the gate driving units being electrically connected to a corresponding gate line group;

[0019] Among the two gate line groups corresponding to at least two adjacent stages of the gate driving units, one includes two first gate lines, and the other includes two second gate lines.

[0020] In some embodiments, two first gate lines in the same gate line group are arranged adjacent to each other, or at least one second gate line is arranged between two first gate lines in the same gate line group.

[0021] In some embodiments, one second gate line is arranged between two first gate lines in each gate line group.

[0022] In some embodiments, the pixels in the same column have the same color.

[0023] The present invention provides a display device, wherein a data line is electrically connected to two columns of pixels arranged at intervals, at least one column of pixels is provided between the two columns of pixels electrically connected to the same data line, a plurality of pixels in the same row include first pixels and corresponding second pixels electrically connected to the same data line; a row of pixels corresponds to a first gate line and a second gate line, the first gate line is electrically connected to the corresponding plurality of first pixels, and the second gate line is electrically connected to the corresponding second pixels, and two gate pulses respectively transmitted by the first gate line and the second gate line corresponding to the pixels in the same row are used to control the time-sharing conduction of the plurality of first pixels and the plurality of second pixels in the corresponding row of pixels; the plurality of first gate lines and the plurality of second gate lines include a plurality of gate line groups, the gate line groups include at least two of the first gate lines or at least two of the second gate lines, and the plurality of pixels electrically connected to the same data line by at least two of the first gate lines or at least two of the second gate lines in the same gate line group have the same color, and the gate driver is used to sequentially transmit the corresponding plurality of gate pulses to the plurality of gate line groups, thereby achieving the goal of avoiding screen abnormalities such as cross-color by using DLG technology under the DLS architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a diagram illustrating the architecture of a display device provided by an embodiment of the present invention.

[0025] Figure 2 and Figure 3 A schematic diagram of connections among multiple gate lines, multiple data lines, and multiple pixels is provided in an embodiment of the present invention.

[0026] Figure 4 for Figure 2 Timing diagram of multiple gate signals corresponding to multiple rows of pixels.

[0027] Figure 5 A schematic diagram of the connection between a multi-stage gate driving circuit and multiple gate lines provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0029] In the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the said features. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is the same as the attached structure. Figure 1 The same is not a limitation of the actual device.

[0030] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] The present invention provides a display device, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0032] In some embodiments, combined Figures 1 to 4 As shown, the display device 100 includes: a plurality of pixels P arranged along a row direction O1 and a column direction O2; a plurality of data lines (D1 to Dm), wherein the data line (one of D1 to Dm) is electrically connected to two columns of the pixels P, and each pixel P in each column of the pixels P corresponding to the data line is electrically connected to the data line (so the number of data lines is less than the number of columns of pixels P), at least one column of pixels P is provided between two columns of the pixels P electrically connected to the same data line, and the plurality of pixels P in the same row include a first pixel P1 and a corresponding second pixel P2 electrically connected to the same data line (one of D1 to Dm); and a plurality of gate lines (G1 to Gn). , comprising a plurality of first gate lines g1 and a plurality of second gate lines g2, wherein a row of pixels P corresponds to one first gate line g1 and one second gate line g2, the first gate line g1 being electrically connected to the corresponding plurality of first pixels P1, and the second gate line g2 being electrically connected to the corresponding second pixels P2, and the two gate pulses p respectively transmitted by the first gate line g1 and the second gate line g2 corresponding to the pixels P in the same row are used to control the time-sharing conduction of the plurality of first pixels P1 and the plurality of second pixels P2 in the corresponding row of pixels P; a gate driver 101 being electrically connected to the plurality of first gate lines g1 and the plurality of second gate lines g2. Wherein, n and m are both positive integers.

[0033] The display device 100 may be a liquid crystal display device. The display device 100 may include a panel body 10 for displaying an image and a driver 20. The panel body 10 includes the aforementioned multiple gate lines (G1 to Gn), multiple data lines (D1 to Dm) and multiple pixels P. The driver 20 may include a source driver 201 and a timing controller 202. The aforementioned gate driver 101 may be integrated into the aforementioned panel body 10 or the driver 20. Figure 1 Only the former is taken as an example.

[0034] like Figure 1 As shown, an array arrangement of multiple pixels P is used as an example for illustration, and may be arranged in n' rows and m' columns (n' is a positive integer less than n, and m' is a positive integer greater than m). Each gate line (one of G1 to Gn) is electrically connected to a portion of the pixels P in a corresponding row to output a corresponding gate signal gate (including a gate pulse p for controlling the corresponding pixel P to turn on) thereto, and each data line (one of D1 to Dm) is connected to a plurality of pixels P in at least two corresponding columns to output a corresponding data signal data thereto. The plurality of data signals data corresponding to the plurality of columns of pixels P are matched so that when a portion of the pixels P in the corresponding row is turned on, the corresponding m data voltages are respectively transmitted to the corresponding portion of the pixels P via the m data lines.

[0035] It should be noted that, in this embodiment, since the data line (one of D1 to Dm) is electrically connected to two columns of pixels P, in order to avoid the two pixels P in the same row that are electrically connected to the same data line being turned on at the same time, causing the data signal data currently transmitted by the data line to be mistakenly charged to one of the two pixels P, the two pixels P are electrically connected to the corresponding first gate line g1 and the corresponding second gate line g2 respectively to avoid the two being turned on at the same time. Similarly, in order to avoid the two pixels electrically connected to each data line in the row of pixels P being turned on at the same time, the two pixels P connected to each data line in the multiple pixels P in the row can be divided into a first pixel P1 and a second pixel P2, and the relative positions of the multiple first pixels P1 and the multiple second pixels P2 in the same row of pixels P are not restricted. All the first pixels P1 in the row are electrically connected to the corresponding first gate line g1, and all the second pixels P2 in the row are electrically connected to the corresponding second gate line g2.

[0036] Among them, Figure 2As shown, the multiple first gate lines g1 and the multiple second gate lines g2 of this embodiment are divided into multiple gate line groups Gg, and the gate line group Gg includes at least two of the first gate lines g1 or at least two of the second gate lines g2, and at least two of the first gate lines g1 or at least two of the second gate lines g2 in the same gate line group Gg are electrically connected to the same data line (one of D1 to Dm) and the colors of the multiple pixels P are the same; wherein the gate driver 101 is used to transmit the corresponding multiple gate pulses p to the multiple gate line groups Gg in sequence.

[0037] Therefore, this embodiment provides two gate lines between two adjacent rows of pixels P, wherein one gate line can be electrically connected to a plurality of pixels P in an adjacent row of pixels P that are connected to different data lines, and the other gate line can be electrically connected to a plurality of pixels P in an adjacent row of pixels P that are connected to different data lines. At the same time, two pixels P in the same row that are electrically connected to the same data line are electrically connected to two gate lines (two adjacent ones from G1 to Gn) located on different sides of the two pixels, so that the two pixels P in the same row that are electrically connected to the same data line can be controlled by two gate signals gate to be turned on in time-sharing, thereby receiving corresponding data voltages in time-sharing. At the same time, the gate signal gate transmitted by each gate line can control the transistors in the plurality of pixels P in the same row of pixels P that are connected to different data lines to be turned on simultaneously, so that the corresponding plurality of pixels P are respectively affected by the plurality of data voltages transmitted by the plurality of data lines (D1 to Dm).

[0038] It can be understood that in this embodiment, on the basis that multiple first pixels P1 and multiple second pixels P2 in the same row are respectively electrically connected to the corresponding first gate line g1 and the corresponding second gate line g2, the data line (one of D1 to Dm) is set to be electrically connected to all pixels P in two columns of pixels P instead of being electrically connected to part of the pixels P in the two columns of pixels P on both sides thereof. This is conducive to setting the at least two first gate lines g1 or at least two second gate lines g2 divided into the same gate line group Gg to have the same color as the corresponding at least two pixels P (corresponding to a similar DLS architecture) electrically connected to the same data line. When the corresponding part of the pixels P in at least two rows of pixels P corresponding to the gate line group Gg (at least two first gate lines g1 or at least two second gate lines g2) is turned on (corresponding to the DLG technology), the data signal data transmitted by each data line (one of D1 to Dm) can enable at least two pixels P of the same color to emit light, thereby achieving the goal of avoiding screen abnormalities such as cross-color when using the DLG technology under the DLS architecture.

[0039] Further, combined Figures 1 to 5As shown, the same gate line group Gg includes two first gate lines g1 or two second gate lines g2, that is, each gate line group Gg only includes two corresponding gate lines. The gate driver 101 can simultaneously drive all the first pixels P1 in the two rows of pixels P corresponding to the corresponding two first gate lines g1 to turn on, or can simultaneously drive all the second pixels P2 in the two rows of pixels P corresponding to the corresponding two second gate lines g2 to turn on, thereby achieving a frequency doubling effect.

[0040] Further, such as Figure 2 and Figure 3 As shown, the colors of the multiple pixels P in the same column are the same. It can be understood that this embodiment is based on the data line (one of D1 to Dm) being electrically connected to two columns of pixels P, and the colors of the multiple pixels P in the same column are set to be the same, so that each data line is electrically connected to one column of pixels P with the same color and another column of pixels P with the same color. Specifically, there is no restriction on whether the colors of the two columns of pixels P connected to the same data line are the same or different. Here, the colors of the multiple columns of pixels P are arranged in a cyclic manner according to the first color R, the second color G, and the third color B as the minimum repeating unit. For example, Figure 2 The colors of the two columns of pixels P connected to the same data line are the same. For example Figure 3 The colors of two columns of pixels P connected to the same data line are different.

[0041] It can be understood that since the multiple pixels P in the same column have the same color, and the multiple first gate lines g1 in the same gate line group Gg are electrically connected to the multiple first pixels P1 in the multiple rows of pixels P, and the multiple first pixels P1 in the multiple first pixels P1 that are connected to the same data line are located in the same column (i.e., have the same color), it can be achieved that the multiple pixels P corresponding to the same data line in the multiple first pixels P1 in the multiple rows of pixels P that are electrically connected to the same gate line group Gg have the same color. The same explanation can be given for the multiple second gate lines g2 included in the same gate line group Gg.

[0042] In some embodiments, as Figure 2 As shown, two first gate lines g1 in the same gate line group Gg are arranged adjacent to each other, or at least one second gate line g2 is arranged between two first gate lines g1 in the same gate line group Gg. Similarly, two second gate lines g2 in the same gate line group Gg are arranged adjacent to each other, or at least one first gate line g1 is arranged between two second gate lines g2 in the same gate line group Gg.

[0043] Specifically, for two adjacent rows of pixels P (for example, the 3rd and 4th rows), the first gate line g1 corresponding to the previous row of pixels P (for example, the 3rd row) can be set close to the first gate line g1 corresponding to the previous and next row of pixels P (for example, the 4th row), so that the two first gate lines g1 corresponding to the two are located between the two second gate lines g2 corresponding to the two; and / or, for two adjacent rows of pixels P (for example, the 1st and 2nd rows), the second gate line g2 corresponding to the previous row of pixels P (for example, the 1st row) can be set close to the second gate line g2 corresponding to the previous and next row of pixels P (for example, the 2nd row), so that the two second gate lines g2 corresponding to the two are located between the two first gate lines g1 corresponding to the two.

[0044] If the plurality of first gate lines g1 and the plurality of second gate lines g2 are based on Figure 2 The arrangement shown is as follows: for example, for the 3rd and 4th rows of pixels P, the two first gate lines g1 (i.e., the sixth gate line G6 and the seventh gate line G7) in one gate line group Gg are arranged adjacent to each other; for example, for the 1st and 2nd rows of pixels P, at least one (e.g., two) second gate lines g2 (i.e., the second gate line G2 and the third gate line G3) are arranged between the two first gate lines g1 (i.e., the first gate line G1 and the fourth gate line G4) in another gate line group Gg. Similarly, the arrangement order of the first gate lines g1 and the second gate lines g2 in the other gate line group Gg corresponding to the 3rd and 4th rows of pixels P and the other gate line group Gg corresponding to the 1st and 2nd rows of pixels P can be analyzed in the same way.

[0045] In some embodiments, as Figure 3 As shown, one second gate line g2 is arranged between two first gate lines g1 in each gate line group Gg. Similarly, one first gate line g1 is arranged between two second gate lines g2 in each gate line group Gg.

[0046] Specifically, for each row of pixels P (for example, the 3rd and 4th rows), the corresponding first gate line g1 can be arranged closer to the front than the corresponding second gate line g2, that is, the relative position relationship between the first gate line g1 and the corresponding second gate line g2 of each row of pixels P is the same. At this point, the first gate line g1 and the second gate line g2 can be arranged alternately in the column direction O2, with a second gate line g2 arranged between two adjacent first gate lines g1, and a first gate line g1 arranged between two adjacent second gate lines g2.

[0047] If the plurality of first gate lines g1 and the plurality of second gate lines g2 are based on Figure 3The arrangement shown is as follows: no matter for the gate line group Gg including two first gate lines g1 or two second gate lines g2, another type of second gate line g2 or first gate line g1 is arranged between the corresponding two first gate lines g1 or two second gate lines g2.

[0048] In some embodiments, combined Figures 1 to 5 As shown, the gate driver 101 includes: a plurality of cascaded gate driving circuits 1011, each of the gate driving circuits 1011 is electrically connected to the corresponding gate line group Gg; wherein, among the two gate line groups Gg corresponding to at least two adjacent levels of the gate driving circuits 1011, one includes two of the first gate lines g1, and the other includes two of the second gate lines g2.

[0049] Combined with the above discussion, it can be seen that each row of pixels P has a corresponding first gate line g1 and a corresponding second gate line g2. Here, the gate line group Gg includes two first gate lines g1 or two second gate lines g2. And through the definition of the gate line group Gg, it can be seen that the two first gate lines g1 or the two second gate lines g2 correspond to the same data line. The two pixels P have the same color.

[0050] Furthermore, in order to reduce line loss caused by distance, two first gate lines g1 or two second gate lines g2 that are closer to each other may be selected to form a gate line group Gg to be electrically connected to the corresponding gate driving circuit 1011, for example Figure 2 and Figure 3 In the figure, the two first gate lines g1 corresponding to two adjacent rows of pixels P constitute one gate line group Gg, and the corresponding two second gate lines g2 constitute another gate line group Gg. Correspondingly, the cascaded multiple gate driving circuits 1011 are also electrically connected to the multiple gate line groups Gg in the display area according to the principle of proximity. Therefore, at least for two adjacent levels of gate driving circuits 1011, one of the corresponding two gate line groups Gg includes two first gate lines g1, and the other includes two second gate lines g2.

[0051] For example Figure 2 As shown, there is a possibility that the gate line group Gg including two first gate lines g1 is located above the gate line group Gg including two second gate lines g2, or for example Figure 3As shown, since there is a possibility that the gate line group Gg including two first gate lines g1 and the gate line group Gg including two second gate lines g2 overlap, in order to make the corresponding two rows of pixels P be turned on almost synchronously and each two adjacent rows of pixels P be turned on in turn, the two gate line groups Gg corresponding to the two adjacent rows of pixels P can be electrically connected to the adjacent two-stage gate driving circuits 1011. Since the cascaded multiple gate driving circuits 1011 output the corresponding multiple gate pulses in turn to control the pixels P corresponding to the multiple gate line groups Gg to be turned on in turn, it appears as a top-to-bottom scan.

[0052] Here Figure 2 As shown in FIG. 1 , the arrangement order of the plurality of first gate lines g1 and the plurality of second gate lines g2 and the division method of the gate line group Gg are taken as an example. Figure 4 and Figure 5 As shown, the two first gate lines g1 electrically connected to the odd-level gate driving circuit 1011 (the 2N-1th level gate driving circuit 1011, N is a positive integer) may include the 1+4(N-1)th gate line G[1+4(N-1)] and the 4+4(N-1)th gate line [4+4(N-1)], and the two second gate lines g2 electrically connected to the adjacent next even-level gate driving circuit 1011 (the 2Nth level gate driving circuit 1011) may include the 2+4(N-1)th gate line G[2+4(N-1)]] and the 3+4(N-1)th gate line G[3+4(N-1)].

[0053] Among them, combined Figure 2 、 Figure 4 and Figure 5 As shown, the following analysis is given:

[0054] When N is 1, the first-stage gate driving circuit 1011 is electrically connected to the first gate line G1 and the fourth gate line G4, and the second-stage gate driving circuit 1011 is electrically connected to the second gate line G2 and the third gate line G3. Therefore, the gate pulses p of the gate signal gate1 corresponding to the first gate line G1 and the gate signal gate4 corresponding to the fourth gate line G4 are in the same time period, and the gate pulses p of the gate signal gate2 corresponding to the second gate line G2 and the gate signal gate3 corresponding to the third gate line G3 are in the same time period and lag behind the first two.

[0055] When N is 2, the third-level gate driving circuit 1011 is electrically connected to the fifth gate line G5 and the eighth gate line G8, and the fourth-level gate driving circuit 1011 is electrically connected to the sixth gate line G6 and the seventh gate line G7. Therefore, the gate pulse p of the gate signal gate5 corresponding to the fifth gate line G5 and the gate signal gate8 corresponding to the eighth gate line G8 are both in a time period that lags behind the gate pulse p of the gate signal gate3 corresponding to the third gate line G3. The gate pulse p of the gate signal gate6 corresponding to the sixth gate line G6 and the gate signal gate7 corresponding to the seventh gate line G7 are in the same time period and lag behind the former two.

[0056] The same analysis is performed subsequently until the last stage of the gate driving circuit 1011 .

[0057] In some embodiments, as Figure 2 and Figure 3 As shown, the same data line (one of D1 to Dm) is used to transmit data voltages of the same polarity (positive "+" or negative "-") to two corresponding columns of pixels P. The polarity of the data voltages corresponding to the multiple columns of pixels P arranged in sequence is reversed every i columns, where i is a positive integer. In other words, the two columns of pixels P connected to the same data line are both acted upon by data voltages of the same polarity, thus avoiding time-sharing polarity switching of the same data line.

[0058] It can be understood that in this embodiment, the polarity of the data voltage corresponding to the multiple columns of pixels P arranged in sequence is reversed once every i columns. The larger i is, the lower the frequency of the polarity switching of the data voltage corresponding to the multiple columns of pixels P arranged in sequence is. The smaller i is, the higher the frequency of the polarity switching of the data voltage corresponding to the multiple columns of pixels P arranged in sequence is. This embodiment does not limit the specific value of i. The above setting can achieve the polarity switching of the data voltage corresponding to the multiple columns of pixels P arranged in sequence at the corresponding frequency, which can avoid the problem that the liquid crystal molecules are deflected in the same direction in the row direction and cannot be recovered.

[0059] In some embodiments, as Figure 2 and Figure 3As shown, the polarities of the data voltages corresponding to the plurality of sequentially arranged columns of pixels P are alternately arranged (i.e., i is 1, for example, the polarities of the pixels P in the odd columns are positive and the polarities of the pixels P in the even columns are negative, or vice versa). An odd column of pixels P is provided between two columns of pixels P electrically connected to the same data line. Since the same data line (one of D1 to Dm) is used to transmit data voltages of the same polarity (e.g., positive "+") to the corresponding two columns of pixels P, based on the data line (one of D1 to Dm) being electrically connected to the two alternately arranged columns of pixels P, since the two columns of pixels P with the same polarity necessarily include at least one column of pixels P with another polarity (e.g., negative "-"), or further include two columns of pixels P with the same polarity (i.e., positive "+"), by analogy, the two columns of pixels P electrically connected to the same data line (one of D1 to Dm) necessarily include an odd column of pixels P.

[0060] It can be understood that in this embodiment, the polarities of the data voltages corresponding to the multiple columns of pixels P arranged in sequence are alternately set, so that the frequency of polarity switching of the multiple data voltages corresponding to the multiple columns of pixels P reaches its highest frequency, so that the brightness change of the display screen in the first direction O1 is approximately the average value of the brightness change of two adjacent pixels P in their respective directions, thereby improving the uniformity of the display screen.

[0061] Specifically, such as Figure 2 and Figure 3 As shown, the jth data line is electrically connected to the jth column pixel P and the j+kth column pixel P, j and k are both positive integers, and the jth column pixels P are electrically connected to the corresponding j data lines.

[0062] For example Figure 2 As shown, k is 6, and the following analysis is made:

[0063] When j is 1, the first data line is electrically connected to the pixels P in the 1st and 7th columns; when j is 2, the second data line is electrically connected to the pixels P in the 2nd and 8th columns; when j is 3, the third data line is electrically connected to the pixels P in the 3rd and 9th columns; when j is 4, the fourth data line is electrically connected to the pixels P in the 4th and 10th columns; when j is 5, the fifth data line is electrically connected to the pixels P in the 5th and 11th columns; when j is 6, the sixth data line is electrically connected to the pixels P in the 6th and 12th columns; and so on to the last data line.

[0064] For example Figure 3 As shown, k is 2, and the following analysis is made:

[0065] When j is 1, the first data line is electrically connected to the pixels P in the 1st and 3rd columns; when j is 2, the second data line is electrically connected to the pixels P in the 2nd and 4th columns; when j is 3, the third data line is electrically connected to the pixels P in the 1st column and the pixels P in the 9th column; when j is 4, the fourth data line is electrically connected to the pixels P in the 4th and 10th columns; when j is 5, the fifth data line is electrically connected to the pixels P in the 5th and 11th columns; when j is 6, the sixth data line is electrically connected to the pixels P in the 6th and 12th columns; and so on to the last data line.

[0066] It can be understood that in this embodiment, since one column of pixels P electrically connected to each of the multiple data lines (D1 to Dm) is arranged continuously, and another column of pixels P electrically connected to each of the multiple data lines is also arranged continuously, the frequency of polarity switching of the multiple data voltages corresponding to the multiple columns of pixels P can be controlled by changing the frequency of polarity of the multiple data signals data transmitted by the multiple data lines.

[0067] Furthermore, if the polarities of the two data voltages transmitted by two adjacent data lines (two adjacent ones among D1 to Dm) are opposite, Figure 2 and Figure 3 In the embodiment shown, since the same data line is electrically connected to two alternate columns of pixels P, even if the same data line only transmits data signals of the same polarity, the polarities of the multiple data voltages transmitted by the multiple data lines (two adjacent ones among D1 to Dm) are alternately set, thereby achieving the alternating polarities of the data signals data of the multiple columns of pixels P arranged continuously.

[0068] In some embodiments, different from Figure 2 and Figure 3 As shown, i is an even number, and two adjacent columns of pixels P are electrically connected to the same data line. That is, in this embodiment, every two adjacent columns of pixels P are electrically connected to the same data line to obtain data signals data with the same polarity. Since the same data line only transmits data signals with the same polarity, the polarity of the data signals data of at least two consecutive columns of pixels P is the same.

[0069] Furthermore, if the polarities of the two data voltages transmitted by two adjacent data lines (two adjacent data lines among D1 to Dm) are opposite. Figure 2 and Figure 3 The embodiment shown can achieve the above-mentioned i=2, that is, the polarity of the multiple data signals data corresponding to the multiple columns of pixels P is switched once every two columns. At this time, the frequency of the polarity switching of the multiple data voltages corresponding to the multiple pixels P arranged in the first direction O1 can still reach its higher frequency, so that the display image has higher uniformity.

[0070] The display device provided by the embodiments of the present invention is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: include: A plurality of pixels are arranged in row and column directions; a plurality of data lines, the data lines being electrically connected to two columns of pixels, each pixel P in each column of pixels P corresponding to the data lines being electrically connected to the data lines, and the plurality of pixels in the same row including a first pixel and a corresponding second pixel electrically connected to the same data line; a plurality of first gate lines and a plurality of second gate lines, wherein a row of pixels corresponds to one first gate line and one second gate line, the first gate line is electrically connected to the corresponding plurality of first pixels, and the second gate line is electrically connected to the corresponding second pixels, and two gate pulses respectively transmitted by the first gate line and the second gate line electrically connected to the pixels in a row are used to control the plurality of first pixels and the plurality of second pixels in the row to be turned on in a time-sharing manner; a gate driver electrically connected to the plurality of first gate lines and the plurality of second gate lines; The plurality of first gate lines and the plurality of second gate lines comprise a plurality of gate line groups, the gate line groups comprising at least two of the first gate lines or at least two of the second gate lines, and at least two of the first gate lines or at least two of the second gate lines in the same gate line group are electrically connected to a plurality of pixels on the same data line having the same color; The gate driver is used to sequentially transmit the corresponding plurality of gate pulses to the plurality of gate line groups.

2. The display device according to claim 1, wherein The same data line is used to transmit data voltages of the same polarity to the corresponding two columns of pixels. The polarities of the data voltages corresponding to the multiple columns of pixels arranged in sequence are reversed every i columns, where i is a positive integer.

3. The display device according to claim 2, wherein The polarities of the data voltages corresponding to the plurality of columns of pixels arranged sequentially are alternately arranged, and an odd number of columns of pixels are provided between two columns of pixels electrically connected to the same data line.

4. The display device according to claim 2, wherein The jth data line is electrically connected to the pixels in the jth column and the pixels in the j+kth column, j and k are both positive integers, and the pixels in the jth column arranged continuously are electrically connected to the corresponding j data lines.

5. The display device according to claim 2, wherein The i is an even number, and two adjacent columns of pixels are electrically connected to the same data line.

6. The display device according to claim 2, wherein: The polarities of the two data voltages respectively transmitted by the two adjacent data lines are opposite.

7. The display device according to any one of claims 1 to 6, wherein: The same gate line group includes two first gate lines or two second gate lines, and the gate driver includes: A plurality of cascaded gate driving units, each of the gate driving units being electrically connected to a corresponding gate line group; Among the two gate line groups corresponding to at least two adjacent stages of the gate driving units, one includes two first gate lines, and the other includes two second gate lines.

8. The display device according to claim 7, wherein: Two first gate lines in the same gate line group are arranged adjacent to each other, or at least one second gate line is arranged between two first gate lines in the same gate line group.

9. The display device according to claim 7, wherein: One second gate line is arranged between two first gate lines in each gate line group.

10. The display device according to any one of claims 1 to 6, wherein: The pixels in the same column have the same color.

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