Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving circuit; a first control module in a shift register in the driving circuit is electrically connected with a signal input end, a first clock end and a first node respectively; the isolation control module is electrically connected with the isolation control end, the first node and the second node. The second control module is electrically connected with the first clock end, the first level end and the third node; the output module is connected with a second node, a third node, a second clock end, a second level end and a signal output end. And in the same first type of shift registers, the isolation of the control end is isolated within at least part of time when the input signal of the signal input end is the effective level. The control signal controls the isolation control module to conduct a signal transmission path between the first node and the second node; at least after the input signal jumps from the effective level to the ineffective level, the isolation control signal controls the isolation control module to disconnect a signal transmission path between the first node and the second node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, electronic products with display functions have been widely used in various fields. For example, televisions, mobile phones, computers, personal digital assistants, etc. are all electronic products with display functions, becoming an indispensable part of people's lives and work. Among them, the display panel is the core structure that realizes the display function of electronic products.

[0003] A display panel typically includes a pixel array and a driver circuit for driving the pixel array. The driver circuit scans the pixel array row by row to display an image. However, due to process fluctuations or equipment errors in the driver circuit manufacturing process, leakage current can occur within the driver circuit, leading to display anomalies and other issues. Summary of the Invention

[0004] The present invention provides a display panel and a display device, so as to improve the accuracy of a gate signal output by a shift register in the display panel, thereby improving the display effect of the display panel.

[0005] In a first aspect, the present invention provides a display panel, comprising: a driving circuit; the driving circuit comprising a multi-stage shift register;

[0006] The shift register includes a first control module, a second control module, an isolation control module, an output module, a signal input terminal, a first clock terminal, a second clock terminal, a first level terminal, a second level terminal, an isolation control terminal and a signal output terminal; the first control module is electrically connected to the signal input terminal, the first clock terminal and the first node respectively; the isolation control module is electrically connected to the isolation control terminal, the first node and the second node respectively; the second control module is electrically connected to the first clock terminal, the first level terminal and the third node respectively; the output module is electrically connected to the second node, the third node, the second clock terminal, the second level terminal and the signal output terminal respectively;

[0007] The signal input terminal of the x-th stage shift register is electrically connected to the signal output terminal of the y-th stage shift register; x and y are both positive integers, and x≠y;

[0008] In the multi-stage shift register, at least some of the shift registers are first-class shift registers;

[0009] In the same first-class shift register, during at least part of the time when the input signal at the signal input end is at a valid level, the isolation control signal at the isolation control end controls the isolation control module to turn on the signal transmission path between the first node and the second node; at least after the input signal jumps from a valid level to an invalid level, the isolation control signal controls the isolation control module to disconnect the signal transmission path between the first node and the second node.

[0010] In a second aspect, the present invention provides a display device comprising the display panel described in the first aspect.

[0011] The technical solution of the present invention is to set an isolation control module between the first control module and the output module in the shift register, so that during at least part of the time when the input signal at the signal input terminal of the first control module is at an effective level, the isolation control signal at the isolation control terminal can control the isolation control module to be in a conductive state, so that the effective level of the input signal received by the first node is transmitted to the second node through the isolation control module, so as to ensure that the output module can output the corresponding gate drive signal to its signal output terminal under the control of the signal at the second node, thereby ensuring the normal operation of the shift register and controlling the display panel to display normally. At the same time, at least after the input signal jumps from the effective level to the invalid level, the isolation control signal at the isolation control terminal is set to control the isolation control module to be turned off, so that the path between the second node and the first node is in a disconnected state, so that when there is leakage current between the first node and the signal input terminal, the leakage current will not affect the signal of the second node, thereby ensuring the accuracy of the signal of the second node, so that the signal of the second node can accurately control the gate drive signal provided by the output module to the signal output terminal, thereby facilitating the improvement of the accuracy of the gate drive signal output by the shift register. In addition, when the gate drive signal output by the shift register is used to scan the pixel circuits in the display panel row by row, each pixel circuit can receive an accurate gate drive signal, which is beneficial to improving the display luminescence accuracy of the pixel and further improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic structural diagram of a display panel in related technology;

[0013] Figure 2 A schematic diagram of the structure of a shift register in related technology;

[0014] Figure 3 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0016] Figure 5 A schematic structural diagram of a driving circuit provided by an embodiment of the present invention;

[0017] Figure 6 A schematic structural diagram of another driving circuit provided by an embodiment of the present invention;

[0018] Figure 7 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0019] Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 9 A schematic diagram of the circuit structure of a second type of shift register provided by an embodiment of the present invention;

[0021] Figure 10 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0022] Figure 11 A timing diagram of a gate drive signal provided by a drive circuit provided in an embodiment of the present invention;

[0023] Figure 12 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0024] Figure 13 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0025] Figure 14 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0026] Figure 15 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0027] Figure 16 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0028] Figure 17 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0029] Figure 18 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0030] Figure 19 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0031] Figure 20A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0032] Figure 21 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0033] Figure 22 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0034] Figure 23 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0035] Figure 24 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0036] Figure 25 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0037] Figure 26 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0038] Figure 27 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0039] Figure 28 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0040] Figure 29 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0041] Figure 30 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0042] Figure 31 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0043] Figure 32 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0044] Figure 33 for Figure 32 Driving timing diagram of the shift register;

[0045] Figure 34 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0046] Figure 35A schematic structural diagram of a driving circuit provided by an embodiment of the present invention;

[0047] Figure 36 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0048] Figure 37 for Figure 36 Driving timing diagram of the shift register;

[0049] Figure 38 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0050] Figure 39 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0051] Figure 40 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0052] Figure 41 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0053] Figure 42 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0054] Figure 43 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0055] Figure 44 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0056] Figure 45 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0058] Figure 1 Schematic diagram of the structure of a display panel in related technology. Figure 2 A schematic diagram of a shift register structure of the related art is shown in FIG. Figure 1 and Figure 2The display panel 001 is provided with a driving circuit 01 and an array-arranged pixel circuit 05. The driving circuit 01 includes a plurality of cascaded shift registers 010. The driving signal output end of each shift register 010 is also electrically connected to the pixel circuit 05 located in the same row to provide a gate driving signal to the pixel circuit 05 in the same row to drive the pixel circuit 05 in the same row to display light.

[0059] The existing shift register 010 includes a drive control module 011 and an output module 012. The drive control module 011 may include a transistor to control the transistor to be turned on or off, thereby transmitting the start signal from the start signal terminal STV to the second node Q02 or the third node Q03, so that the output module 012 can output a corresponding gate drive signal to the output terminal G01 based on the signal at the second node Q02 and / or the third node Q03. However, when the transistor in the drive control module 011 is in the off state, due to fluctuations in the manufacturing process or equipment errors, the transistor has a certain leakage current in the off state. As a result, the effective level at the second node Q02 or the effective level at the third node Q03 can leak through the transistor in the drive control module 011 to the signal input terminal IN0, causing the electrical signal at the second node Q02 or the third node Q03 to change, affecting the accuracy of the signal at the second node Q02 or the third node Q03, and further affecting the accuracy of the gate drive signal output by the output module 012 to the signal output terminal G01, thereby affecting the display effect of the display panel 001.

[0060] In order to solve the above technical problems, an embodiment of the present invention provides a display panel, which includes: a driving circuit; the driving circuit includes a multi-stage shift register; the shift register includes a first control module, a second control module, an isolation control module, an output module, a signal input terminal, a first clock terminal, a second clock terminal, a first level terminal, a second level terminal, an isolation control terminal and a signal output terminal; the first control module is electrically connected to the signal input terminal, the first clock terminal and the first node respectively; the isolation control module is electrically connected to the isolation control terminal, the first node and the second node respectively; the second control module is electrically connected to the first clock terminal, the first level terminal and the third node respectively; the output module is electrically connected to the second node, the third node, a second clock terminal, a second level terminal and a signal output terminal; wherein the signal input terminal of the x-th stage shift register is electrically connected to the signal output terminal of the y-th stage shift register; x and y are both positive integers, and x≠y; in the multi-stage shift register, at least some of the shift registers are first-class shift registers; in the same first-class shift register, during at least part of the time when the input signal of the signal input terminal is at a valid level, the isolation control signal of the isolation control terminal controls the isolation control module to turn on the signal transmission path between the first node and the second node; at least after the input signal jumps from a valid level to an invalid level, the isolation control signal controls the isolation control module to disconnect the signal transmission path between the first node and the second node.

[0061] The above technical solution is adopted, by setting an isolation control module between the first control module and the output module in the shift register, so that during at least part of the time when the input signal at the signal input terminal of the first control module is at an effective level, the isolation control signal at the isolation control terminal can control the isolation control module to be in a conductive state, so that the effective level of the input signal received by the first node is transmitted to the second node through the isolation control module, so as to ensure that the output module can output the corresponding gate drive signal to its signal output terminal under the control of the signal at the second node, thereby ensuring the normal operation of the shift register and controlling the display panel to display normally. At the same time, at least after the input signal jumps from the effective level to the ineffective level, the isolation control signal at the isolation control terminal is set to control the isolation control module to be turned off, so that the path between the second node and the first node is in a disconnected state, so that when there is leakage current between the first node and the signal input terminal, the leakage current will not affect the signal of the second node, thereby ensuring the accuracy of the signal of the second node, so that the signal of the second node can accurately control the gate drive signal provided by the output module to the signal output terminal, thereby facilitating the improvement of the accuracy of the gate drive signal output by the shift register. In addition, when the gate drive signal output by the shift register is used to scan the pixel circuits in the display panel row by row, each pixel circuit can receive an accurate gate drive signal, which is beneficial to improving the display luminescence accuracy of the pixel and further improving the display effect of the display panel.

[0062] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without inventive work are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0063] Figure 3 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 A schematic diagram of a shift register structure provided by an embodiment of the present invention, with reference to Figure 3 and Figure 4 The display panel 100 includes a driving circuit 10, which includes a multi-stage shift register G. The shift register G includes a first control module 11, a second control module 12, an isolation control module 13, an output module 14, a signal input terminal Vin, a first clock terminal CK1, a second clock terminal CK2, a first level terminal VGH, a second level terminal VGL, an isolation control terminal Ct, and a signal output terminal Gout. The first control module 11 is electrically connected to the signal input terminal Vin, the first clock terminal CK1, and the first node Q1, respectively; the isolation control module 13 is electrically connected to the isolation control terminal Ct, the first node Q1, and the second node Q2, respectively; the second control module 12 is electrically connected to the first clock terminal CK1, the first level terminal VGH, and the third node Q3, respectively; and the output module 14 is electrically connected to the second node Q2, the third node Q3, the second clock terminal CK2, the second level terminal VGL, and the signal output terminal Gout, respectively.

[0064] The first level terminal VGH can receive a first level signal vgh, and the second level terminal VGL can receive a second level signal vgl. Both the first level signal vgh and the second level signal vgl can be fixed levels, and the polarity of the first level signal vgh and the second level signal vgl can be opposite, that is, when the first level signal vgh is low, the second level signal vgl is high; alternatively, when the first level signal vgh is high, the second level signal vgl can be low. The signal input terminal Vin can receive an input signal vin, the first clock terminal CK1 can receive a first clock signal ck1, the second clock terminal CK2 can receive a second clock signal ck2, and the isolation control terminal Ct can receive an isolation control signal ct. The input signal vin, the first clock signal ck1, the second clock signal ck2 and the isolation control signal ct may all include a high level and a low level, and the first clock signal ck1 and the second clock signal ck2 may vary within a certain clock cycle. The effective levels of the input signal vin, the first clock signal ck1, the second clock signal ck2 and the isolation control signal ct may be a high level or a low level, and the effective levels of the input signal vin, the first clock signal ck1, the second clock signal ck2 and the isolation control signal ct may be the same or different, and may be specifically designed according to actual needs. The embodiments of the present invention all take the effective levels of the input signal vin, the first clock signal ck1, the second clock signal ck2 and the isolation control signal ct as high levels as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0065] Specifically, in the same first-type shift register unit 1G, the first control module 11 is electrically connected to the signal input terminal Vin, the first clock terminal CK1, and the first node Q1, respectively, so that the first control module 11 can control the signal output from the first node Q1 based on the signals at the first clock terminal CK1 and the signal input terminal Vin. For example, when the first clock signal ck1 is at an active level, the first control module 11 can control the input signal vin from the signal input terminal Vin to be transmitted to the first node Q1, so that the signal at the first node Q1 can be consistent with the input signal vin.

[0066] The second control module 12 is electrically connected to the first level terminal VGH, the first clock terminal CK1, and the third node Q3, respectively, so that the second control module 12 can control the signal output by the third node Q3 based on the signals of the first clock terminal CK1 and the first level terminal VGH. For example, when the first clock signal ck1 is at an active level, the second control module 12 can control the first level signal vgh of the first level terminal VGH to be transmitted to the third node Q3, so that the signal of the third node Q3 is consistent with the first level signal vgh.

[0067] The isolation control module 13 is electrically connected to the first node Q1, the second node Q2, and the isolation control terminal Ct, respectively, so that the isolation control module 13 can control the signal of the second node Q2 based on the signal of the isolation control terminal Ct and the signal of the first node Q1, or control the signal of the first node Q1 based on the signal of the isolation control terminal Ct and the signal of the second node Q2. For example, when the signal of the isolation control terminal CT is at an active level, the isolation control module 13 can transmit the signal of the first node Q1 to the second node Q2, or transmit the signal of the second node Q2 to the first node Q1, so that the signal of the first node Q1 and the signal of the second node Q2 are consistent.

[0068] The output module 14 is electrically connected to the second clock terminal CK2, the second node Q2, the third node Q3, the second clock terminal VGL, and the signal output terminal Gout, respectively, so that the output module 14 can control the gate drive signal output by the signal output terminal Gout according to the second clock signal ck2 of the second clock terminal CK2, the signal at the third node Q3, and the second level signal vgl of the second level terminal VGL. For example, when the signal at the second node Q2 is at a valid level and the signal at the third node Q3 is at an invalid level, the output module 14 can transmit the second clock signal ck2 of the second clock terminal CK2 to the signal output terminal Gout as the gate drive signal, so that the gate drive signal can be consistent with the second clock signal ck2. Conversely, when the signal at the second node Q2 is at an invalid level and the signal at the third node Q3 is at a valid level, the output module 14 can transmit the second level signal vgl of the second level terminal VGL to the signal output terminal Gout as the gate drive signal, so that the gate drive signal can be consistent with the second level signal vgl.

[0069] Continue to refer Figure 3 and Figure 4 , the signal input terminal Vin of the x-th stage shift register Gx is electrically connected to the signal output terminal Gout of the y-th stage shift register Gy; x and y are both positive integers, and x≠y.

[0070] It can be understood that the driving circuit 10 may include an N-stage shift register G, where N can be a positive integer greater than or equal to 2, that is, two or more shift register units G can be provided in the driving circuit 10, or other numbers. N can be set according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0071] The signal output terminal Gout of the y-stage shift register Gy is electrically connected to the signal input terminal Vin of the first control module 11 of the x-stage shift register Gx, so that the gate drive signal output by the signal output terminal Gout of the y-stage shift register Gy can serve as the input signal vin of the signal input terminal Vin of the x-stage shift register Gx. When the signal output terminal Gout of the shift register Gy cascaded with the current-stage shift register Gx outputs a valid level of the gate drive signal, the signal at the signal input terminal Vin of the current-stage shift register Gx is at a valid level. When the first clock signal ck1 received by the current-stage shift register Gx controls the first control module 11 to be in an on state, the input signal vin of the signal input terminal Vin is transmitted to the first node Q1 to charge the first node Q1, so that the signal at the first node Q1 of the current-stage shift register Gx can be consistent with the gate drive signal output by the signal output terminal Gout of the y-stage shift register Gy. In this way, the gate drive signal output by the signal output terminal Gout of the y-th stage shift register Gy can control the signal of the first node Q1 in the x-th stage shift register Gx, so that the x-th stage shift register Gx can output the corresponding gate drive signal according to the gate drive signal output by the signal output terminal Gout of the y-th stage shift register Gy, thereby realizing the effective pulses of the gate drive signals output by the shift registers G at each level to shift in sequence.

[0072] It is understood that x≠y, that is, x can be greater than y or x can be less than y. In an exemplary embodiment, Figure 5 As shown, when the x-th stage shift register Gx and the y-th stage shift register Gy are two adjacent stages of shift registers, if x is equal to i, then y can be equal to i-1; or, as Figure 6 As shown, the x-th stage shift register Gx and the y-th stage shift register Gy may also be two non-adjacent stage shift registers, in which case xy may be positive integers greater than or equal to 2. The values of x and y in the embodiment of the present invention are not specifically limited as long as the core inventive point of the embodiment of the present invention can be achieved.

[0073] Continue to refer Figure 3 and Figure 4 In the multi-stage shift register G, at least some of the shift registers G are first-type shift registers 1G. In the same first-type shift register 1G, during at least a portion of the time when the input signal at the signal input terminal Vin is at an active level, the isolation control signal at the isolation control terminal Ct controls the isolation control module 13 to connect the signal transmission path between the first node Q1 and the second node Q2; and at least after the input signal jumps from an active level to an inactive level, the isolation control signal controls the isolation control module 13 to disconnect the signal transmission path between the first node Q1 and the second node Q2.

[0074] Specifically, when the isolation control signal ct of the isolation control terminal Ct is at an active level, the isolation control signal ct can control the isolation control module 13 to be in an on state, and the signal at the first node Q1 can be transmitted to the second node Q2, so that the signals at the first node Q1 and the second node Q2 remain consistent. When the isolation control signal ct of the isolation control terminal Ct is at an inactive level, the isolation control signal ct can control the isolation control module 13 to be in an off state, so that the signal at the first node Q1 cannot be transmitted to the second node Q2, and the signal at the second node Q2 cannot be transmitted to the first node Q1. Therefore, in the absence of other signals being written, the signals at the first node Q1 and the second node Q2 can remain unchanged.

[0075] It is understandable that when the input signal vin at the signal input terminal Vin, the first clock signal ck1, and the isolation control signal ct are all at valid levels, and the first control module 11 and the isolation control module 13 are both in the on state, the valid level of the input signal vin can be transmitted to the first node Q1 through the first control module 11, and then transmitted from the first node Q1 to the second node Q2 through the isolation control module 13. When the input signal vin at the signal input terminal Vin is at an invalid level, if the isolation control signal ct still controls the isolation control module 13 to be in the on state, then if leakage current exists between the first node Q1 and the signal input terminal Vin, the signal at the second node Q2 will be transmitted to the signal input terminal Vin through the isolation control module 13 and the first node Q1, thereby causing an inaccurate electrical signal at the second node Q2.

[0076] In this embodiment, the isolation control signal ct of the isolation control terminal Ct is set to control the isolation control module 13 to be turned on during at least part of the time when the input signal vin of the signal input terminal Vin is at a valid level, so that the valid level of the input signal vin can be transmitted to the first node Q1 through the first control module 11, and then can be further transmitted to the second node Q2 through the isolation control module 13, so as to control the output module 14 to output a corresponding signal to the signal output terminal Gout, so that the pixel circuit electrically connected to the signal output terminal Gout can display light, so that the display panel can display normally. Accordingly, at least after the input signal jumps from the valid level to the invalid level, the isolation control signal ct set at the isolation control terminal Ct can control the isolation control module 13 to be turned off to disconnect the connection path between the first node Q1 and the second node Q2, so that when there is a leakage current between the first node Q1 and the signal input terminal Vin, the leakage current will not affect the signal of the second node Q2, and the signal of the second node Q2 will not be transmitted to the first node Q1, thereby ensuring the accuracy of the signal at the second node Q2, so that the signal of the second node Q2 can accurately control the gate drive signal provided by the output module 14 to the signal output terminal Gout, thereby facilitating the improvement of the accuracy of the gate drive signal output by the shift register G, so that the pixel circuits electrically connected to each shift register G can receive an accurate gate drive signal, which is beneficial to the display accuracy of the display panel 100, thereby improving the display effect of the display panel 100.

[0077] It can be understood that at least part of the time when the input signal vin of the signal input terminal Vin is at a valid level can specifically be part of the time when the input signal vin of the signal input terminal Vin is at a valid level, or the entire time when the input signal vin of the signal input terminal Vin is at a valid level. On the basis that the isolation control module 13 can transmit the valid level of the signal input terminal Vin to the second node Q2, at least part of the time when the input signal vin of the signal input terminal Vin is at a valid level can be set according to actual needs and is not specifically limited here.

[0078] The technical solution of the present invention is to set an isolation control module between the first control module and the output module in the shift register, so that during at least part of the time when the input signal at the signal input terminal of the first control module is at an effective level, the isolation control signal at the isolation control terminal can control the isolation control module to be in a conductive state, so that the effective level of the input signal received by the first node is transmitted to the second node through the isolation control module, so as to ensure that the output module can output the corresponding gate drive signal to its signal output terminal under the control of the signal at the second node, thereby ensuring the normal operation of the shift register and controlling the display panel to display normally. At the same time, at least after the input signal jumps from the effective level to the invalid level, the isolation control signal at the isolation control terminal is set to control the isolation control module to be turned off, so that the path between the second node and the first node is in a disconnected state, so that when there is leakage current between the first node and the signal input terminal, the leakage current will not affect the signal of the second node, thereby ensuring the accuracy of the signal of the second node, so that the signal of the second node can accurately control the gate drive signal provided by the output module to the signal output terminal, thereby facilitating the improvement of the accuracy of the gate drive signal output by the shift register. In addition, when the gate drive signal output by the shift register is used to scan the pixel circuits in the display panel row by row, each pixel circuit can receive an accurate gate drive signal, which is beneficial to improving the display luminescence accuracy of the pixel and further improving the display effect of the display panel.

[0079] It is understandable that at least some of the shift registers are first-type shift registers 1G, that is, some or all of the shift registers G are first-type shift registers 1G. The specific design can be based on actual needs, and the embodiment of the present invention does not make any specific limitation on this.

[0080] In an alternative embodiment, reference Figure 3The display panel 100 may include a display area AA, in which a plurality of pixel circuits 50 and a plurality of gate signal lines 51 may be arranged in an array. At least some of the pixel circuits 50 in the same row are electrically connected to the same gate signal line 51. In this case, the signal output terminal Gout of each first-type shift register 1G may be electrically connected to different gate signal lines 51, that is, each shift register electrically connected to each gate signal line 51 is a first-type shift register 1G. Each first-type shift register 1G may output a gate drive signal to each gate signal line 51, so that each gate signal line 51 receives an accurate gate drive signal. When each gate signal line 51 transmits the gate drive signal to each row of pixel circuits 50, each row of pixel circuits 50 may be accurately scanned row by row, so that each row of pixel circuits 50 can accurately write a corresponding display signal (e.g., a data signal) to each row of pixel circuits 50, thereby controlling each row of pixel circuits 50 to accurately display and emit light, so that the display panel 100 can accurately present a corresponding display image, thereby improving the display effect of the display panel 100.

[0081] In another alternative embodiment, Figure 7 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the first type shift register 1G may also be electrically connected to only part of the gate signal lines 51. For example, the display panel 100 may include a pixel circuit 501 for displaying dynamic images and a pixel circuit 502 for displaying static images. Exemplarily, the display panel 100 may include a first display area AA1 and a second display area AA2. The pixel circuit 501 in the first display area AA1 is a pixel circuit for displaying dynamic images, and the pixel circuit 502 in the second display area AA2 may be a pixel circuit for displaying static images.

[0082] For the pixel circuit 501 in the first display area AA1, its data signal is constantly changing, and the changing data signal needs to be accurately written into the pixel. At this time, a first-type shift register 1G can be set to be electrically connected to the pixel circuit 501 located in the first display area AA1, so as to ensure that the pixel circuit located in the first display area AA1 can accurately receive the gate drive signal, so that the data signal of the pixel circuit in the first display area AA1 can be accurately written, and the pixel circuit in the first display area AA1 is controlled to accurately display light, thereby improving the display effect of the display panel.

[0083] Accordingly, since the second display area AA2 is used to display a static image, the data signal it receives remains unchanged for a period of time. That is, during each frame of the display image within the period of time, the pixel circuits 502 of the second display area AA2 all receive the same data signal, so there is no need to consider the writing time of the data signal of the pixel circuits 502 of the second display area AA2. In this case, the driving circuit 10 may also include a third type of shift register 3G, which can be electrically connected to the pixel circuits 502 located in the second display area AA2. The structure of the third type of shift register 3G can be different from that of the first type of shift register 1G. For example, during the operation of the display panel 100, the isolation control terminal Ct of the third type of shift register 3G can continuously receive the effective level of the isolation control signal ct. When the signals at the first node Q1 and the second node Q2 are both within the normal signal value range, the isolation control module 13 can, under the control of the effective level of the isolation control signal ct and the signal at the first node Q1 or the second node Q2, conduct the signal transmission path between the first node Q1 and the second node Q2, so that the signal at the first node Q1 and the signal at the second node Q2 are both within the normal signal value range. The signals remain consistent, and when either the signal at the first node Q1 or the signal at the second node Q2 exceeds the normal signal value range, the effective level of the isolation control signal ct is combined with the signal at the first node Q1 or the second node Q2 that exceeds the normal signal value range, and the isolation control module 13 is controlled to be in a closed state, disconnecting the signal transmission path between the first node Q1 and the second node Q2, thereby preventing the signal at the first node Q1 from affecting the stability of the signal at the second node Q2, or the signal at the second node Q2 from affecting the stability of the signal at the first node Q1, thereby improving the operation safety and stability of the third type shift register 3G.

[0084] In other optional embodiments, Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 9 A schematic diagram of the circuit structure of a second type of shift register provided by an embodiment of the present invention is provided. Figure 8 and Figure 9 The multi-stage shift register G further includes a second type shift register 2G; in the second type shift register 2G, the isolation control terminal Ct is electrically connected to the first level terminal VGH.

[0085] Specifically, during operation of the display panel 100, the isolation control terminal Ct of the second-type shift register 2G can continuously receive the first-level signal vgh provided by the first-level terminal VGH. When the signals at the first node Q1 and the second node Q2 are both within a normal signal value range, the isolation control module 13 can, under the control of the first-level signal vgh and the signal at the first node Q1 or the second node Q2, conduct the signal transmission path between the first node Q1 and the second node Q2, so that the signal at the first node Q1 and the signal at the second node Q2 remain consistent. When either the signal at the first node Q1 or the second node Q2 exceeds the normal signal value range, the first-level signal vgh is combined with the signal at the first node Q1 or the second node Q2 that exceeds the normal signal value range to control the isolation control module 13 to be in a closed state, disconnecting the signal transmission path between the first node Q1 and the second node Q2, thereby preventing the signal at the first node Q1 from affecting the stability of the signal at the second node Q2, or the signal at the second node Q2 from affecting the stability of the signal at the first node Q1, thereby improving the operational safety and stability of the second-type shift register 2G. At the same time, the isolation control terminal Ct is electrically connected to the first level terminal VGH, so that the isolation control terminal Ct is electrically connected to the signal line providing the first level signal vgh. This eliminates the need for a separate signal line for the isolation control terminal Ct, thereby simplifying the structure of the driver circuit 10 and reducing the overall size of the driver circuit 10. When the display panel 100 further includes a non-display area NA that at least partially surrounds the display area AA, if the driver circuit 10 is disposed in the non-display area NA, the smaller driver circuit 10 occupies less space in the non-display area NA, thereby reducing the size of the non-display area NA and facilitating a narrow bezel for the display panel 100.

[0086] It should be noted that when the driving circuit 10 includes both the first-type shift register 1G and the second-type shift register 2G, since the isolation control terminal Ct in the second-type shift register 2G is directly electrically connected to the first level terminal VGH, the signal at the isolation control terminal Ct in the second-type shift register 2G is a fixed signal, while the signal at the isolation control terminal Ct in the first-type shift register 1G is a variable signal. As a result, the gate drive signals output by the second-type shift register 2G and the first-type shift register 1G may differ. Therefore, when the display panel 100 further includes a plurality of pixel circuits 50 and a plurality of gate signal lines 51 arranged in an array, and at least some of the pixel circuits 50 in the same row are electrically connected to the same gate signal line 51, each level of the first-type shift register 1G can be electrically connected to the pixel circuits 50 in each row through each gate signal line 51, while each level of the second-type shift register 2G can be electrically disconnected from each gate signal line 51. This improves the consistency of the gate drive signals transmitted by each gate signal line 51, thereby improving the display uniformity of the display panel 100. At this time, the second type shift register 2G may exist in the driving circuit 10 as a virtual shift register unit.

[0087] It is understandable that the number of the second type shift register 2G can be 1 or 2, or other numbers, which is not specifically limited in the embodiment of the present invention. In an optional embodiment, the first m stages of shift registers G are the second type shift register 2G; wherein m≥n.

[0088] Among them, x can be y+n, that is, when n=2, the signal output terminal Gout of the i-th stage shift register Gi is electrically connected to the signal input terminal Vin of the i+2-th stage shift register Gi+2, for example, the signal output terminal Gout of the first-stage shift register G1 is electrically connected to the signal input terminal Vin of the third-stage shift register G3; when n=3, the signal output terminal Gout of the i-th stage shift register Gi is electrically connected to the signal input terminal Vin of the i+3-th stage shift register Gi+3, for example, the signal output terminal Gout of the first-stage shift register G1 is electrically connected to the signal input terminal Vin of the fourth-stage shift register G4. By making the setting number m of the second-type shift register 2G greater than or equal to n, after the signal input terminal Vin of the first m-level second-type shift register 2G receives the input signal vin, the input signal vin can be stage-transmitted and then transmitted to the signal input terminal Vin of each first-type shift register 1G, so that the first-type shift register 1G can all receive the stage-transmitted input signal vin, ensuring that the signal input terminal Vin of the shift register G connected to the gate signal line 51 can all receive the gate drive signal output by other shift registers electrically connected to it, thereby improving the consistency of the input signals received by the first-type shift register 1G at each level.

[0089] It is understandable that the type of the shift register G in the driving circuit 10 can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. In an exemplary embodiment, Figure 3 As shown, the driving circuit 10 may only include the first type shift register 1G. In this case, the signal input terminal Vin of the first n-stage first type shift register 1G is electrically connected to the start signal line STV to receive the start control signal stv transmitted by the start signal line STV, and outputs the corresponding gate drive signal to the pixel circuit 50 of the corresponding row under the combined action of the start control signal stv and other signals received, and uses the gate drive signal as the input signal vin of other shift registers G cascaded therewith, so as to control the other shift registers to accurately output the gate drive signal. In another exemplary embodiment, as Figure 7 As shown, the driving circuit 10 may include both the first type shift register 1G and the third type shift register 3G. In this case, if the first n stages of shift registers are the third type shift register 3G, the signal input terminal Vin of the first n stages of the third type shift register 3G is electrically connected to the start signal line to receive the start control signal transmitted by the start signal line, and outputs a corresponding gate drive signal to the pixel circuit 50 of the corresponding row under the combined action of the start control signal and other signals received, and uses the gate drive signal as the input signal vin of the other shift registers G cascaded therewith, so as to control the other shift registers G to accurately output the gate drive signal. In another exemplary embodiment, as Figure 8 As shown, the driving circuit 10 may include both a first-type shift register 1G and a second-type shift register 2G. In this case, the first m-stage shift register may be the second-type shift register 2G, so that the signal input terminal Vin of the first m-stage second-type shift register 2G is electrically connected to the start signal line to receive the start control signal transmitted by the start signal line, and outputs a corresponding gate drive signal to the signal input terminal Vin of the corresponding first-type shift register 1G under the combined action of the start control signal and other signals received. Therefore, the first-type shift register 1G outputs a corresponding gate drive signal to the pixel circuit 50 of the corresponding row under the combined action of the input signal Vin and other signals received, and uses the gate drive signal as the input signal of other shift registers cascaded with it, so as to control the other shift registers to accurately output gate drive signals. Alternatively, in other exemplary embodiments, the driving circuit 10 may also include the first-type shift register 1G, the second-type shift register 2G, and the third-type shift register 3G.

[0090] For the convenience of description, under the premise that there is no special limitation, the embodiments of the present invention all take the driving circuit 10 including only the first type shift register 1G as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0091] It should be noted that, in an embodiment of the present invention, the shift registers G of each level of the drive circuit 10 are used to scan the pixel circuit 50 row by row. The pixel circuit 50 may include a preset module for receiving the gate drive signal output by the shift registers G of each level in the drive circuit 10, so that the preset module can be turned on or off under the control of the gate drive signal output by the shift register G. When the gate drive signal is at a valid level, the preset module can be controlled to be turned on, and signal transmission can be carried out between the nodes connected to the preset module. When the gate drive signal is at an invalid level, the preset module can be controlled to be turned off, and signal transmission cannot be carried out between the nodes connected to the preset module. In this way, the gate drive signal output by the shift register G can control the driving process of the pixel circuit 50.

[0092] It is understandable that the preset module may include active and / or passive devices, and the active devices may include, for example, transistors, and the passive devices may include, for example, capacitors, resistors, inductors, etc. When the preset module includes a PMOS transistor, the low level of the gate drive signal is the valid level of the gate drive signal, and the high level of the gate drive signal is the invalid level of the gate drive signal. Conversely, when the preset module includes an NMOS transistor, the high level of the gate drive signal is the valid level of the gate drive signal, and the low level of the gate drive signal is the invalid level of the gate drive signal. For ease of description, without special limitations, the embodiments of the present invention all take the transistors in the preset module as NMOS transistors as an example to exemplify the technical solutions of the embodiments of the present invention.

[0093] It is also understandable that the preset module of the pixel circuit 50 can be any module in the pixel circuit 50 and can be selected according to actual needs. The pixel circuit 50 and its preset module mentioned in the embodiment of the present invention are exemplarily described below with typical examples.

[0094] Optional, Figure 10 A schematic diagram of a pixel circuit according to an embodiment of the present invention is shown in FIG. Figure 10 As shown, the pixel circuit 50 includes at least a driving module 52, a writing module 53, a reset module 54 and a light-emitting module 55; the driving module 52 includes a driving transistor DT; the writing module 53 and the gate of the driving transistor DT are electrically connected to the gate node N2; the reset module 54 is electrically connected to the gate node N2, and the reset module 54 is also electrically connected to the light-emitting module 55 at the light-emitting reset node N3.

[0095] Specifically, the driving cycle of the pixel circuit 50 may include a reset phase, a write phase and a light-emitting phase performed in sequence; in the reset phase, the reset module 54 may provide a reset signal Vref to the gate node N2 and the light-emitting reset node N3 to reset the gate of the driving transistor DT and the light-emitting reset node N3; in the write phase, the write module 53 may provide a data signal Vdata to the driving transistor DT; in the light-emitting phase, the driving module 52 provides a driving current to the light-emitting module 55 according to the gate signal of its driving transistor DT to drive the light-emitting module 55 to emit light.

[0096] In an optional embodiment, the driving transistor DT can be a dual-gate structure, that is, the driving transistor can include a main gate and an auxiliary gate, the main gate can be connected to the gate node N2, and the auxiliary gate can be connected to the light-emitting reset node N3, which can reduce the internal resistance of the driving transistor DT and improve the transmission efficiency of the driving current.

[0097] Based on the above embodiment, the reset module 54 may include a first reset transistor M2 and a second reset transistor M5. The first electrode of the first reset transistor M2 may receive a first reset signal Vref, the second electrode of the first reset transistor M2 may be electrically connected to the gate of the drive transistor DT at a gate node N2, and the gate of the first reset transistor M2 may receive a second scan signal S2. The first reset transistor M2 may be turned on or off under the control of the second scan signal S2. When the second scan signal S2 turns the first reset transistor M2 on, the first reset signal Vref may be transmitted to the gate of the drive transistor DT to reset the gate of the drive transistor DT and prepare for the subsequent writing of the data signal Vdata. The first electrode of the second reset transistor M5 may receive a second reset signal Vini, the second electrode of the second reset transistor M5 may be electrically connected to the light-emitting reset node N3 of the light-emitting module 55, and the gate of the second reset transistor M5 may receive a third scan signal S3. The second reset transistor M5 can be turned on or off under the control of the third scan signal S3 , so that when the third scan signal S3 controls the second reset transistor M5 to be turned on, the second reset signal Vini can be transmitted to the light emitting module 55 to reset the light emitting module 55 .

[0098] Based on the above embodiment, the write module 53 may optionally include a write transistor M1, wherein a first electrode of the write transistor M1 may receive the data signal Vdata, a second electrode of the write transistor M1 may be electrically connected to a gate node N2 of the drive module 52, and a gate of the write transistor M1 may receive a first scan signal S1. The first scan signal S1 may control the write transistor M1 to be turned on or off, so that when the write transistor M1 is in the on state, the data signal Vdata may be written to the drive module 52, thereby implementing the writing of the data signal Vdata.

[0099] Optionally, the light-emitting module 55 may include a current-type driving element, that is, the light-emitting module 55 can only be driven to display light when the display driving signal provided to the light-emitting module 55 is a driving current. The data signal Vdata provided by the writing module 53 is usually a voltage signal. In this case, it is necessary to set a driving module 52 in the pixel circuit 50 so that the driving transistor DT of the driving module 52 can convert the data signal Vdata into a driving current. When the driving current is provided to the light-emitting module 55, the light-emitting module 55 can display light according to the driving current, and generally, the greater the driving current, the higher the brightness of the light-emitting module 55. In this way, by providing the data signal Vdata to each pixel circuit 50 respectively, the brightness of the light-emitting module 55 can be controlled respectively, so that the display panel 100 can display a colorful picture. Among them, the light-emitting module 55 may include a current-type light-emitting element such as OLED, Mini LED, or Micro LED.

[0100] In other optional embodiments, continue to refer to Figure 10 The pixel circuit 50 may further include a light-emission control module 56, which includes a light-emission control transistor M3. A first electrode of the light-emission control transistor M3 is electrically connected to the first power supply signal ELVDD, a second electrode of the light-emission control transistor M3 is electrically connected to one end of the driver module 52, and a gate of the light-emission control transistor M3 is electrically connected to the light-emission control signal EM. The light-emission control transistor M3 can be turned on or off under the control of the light-emission control signal EM. When the light-emission control signal EM turns on the light-emission control transistor M3, the first power supply signal ELVDD is transmitted to the driver transistor DT. The light-emission control module 56 can control the timing of the driver module 52 providing the driving current to the light-emission module 55, thereby controlling the light-emission duration of the light-emission module 55.

[0101] In addition, the pixel circuit 50 also includes a storage capacitor C1 and a stabilizing capacitor Coled. The storage capacitor C is electrically connected between the gate node N2 and the light-emitting reset node N3 and is used to store the gate potential of the drive transistor DT and the threshold voltage of the drive transistor DT, thereby ensuring that the drive transistor DT can continuously provide a drive current to the light-emitting module 55 that is independent of the threshold voltage of the drive transistor DT during the light-emitting phase. The stabilizing capacitor Coled is connected in parallel with the light-emitting module 55 to stabilize the drive current of the light-emitting module 55, suppress fluctuations in the display brightness of the light-emitting module 55, and improve the light-emitting stability of the light-emitting module 55.

[0102] It should be noted that the above description is only an example of the structure of the pixel circuit 50. In the embodiment of the present invention, the structure of the pixel circuit 50 is not limited thereto. For example, the pixel circuit 50 can also be a typical 7T1C pixel circuit, that is, the pixel circuit includes seven transistors and a storage capacitor. Under the premise that the core invention of the embodiment of the present invention can be achieved, the embodiment of the present invention does not make specific limitations on this. For the convenience of description, under the premise that there are no special limitations, the embodiment of the present invention is based on Figure 10 Taking the pixel circuit structure shown as an example, the technical solution of the embodiment of the present invention is exemplarily described.

[0103] In an optional embodiment, in conjunction with reference Figure 3 and Figure 10 The preset module in the pixel circuit 50 may include a reset module 54, a write module 53 and a light-emitting control module 56. At this time, the gate drive signal output by the shift register G in the drive circuit 10 can be used as one of the first scan signal S1, the second scan signal S2, the third scan signal S3 and the light-emitting control signal EM.

[0104] Taking the example of a preset module in the pixel circuit 50 including a write module 53, in this case, the write modules 53 of at least some of the pixel circuits 50 in the same row are electrically connected to the same gate signal line 51, and the gate drive signal output by the shift register G is the first scanning signal S1 received by the write module 53. Because each level of the first-type shift register 1G is electrically connected to each gate signal line 51, the gate drive signal output by the first-type shift register 1G can be transmitted to the write module 53 of the pixel circuit 50 via the gate signal line 51 to control whether the write module 53 is turned on or off. When the gate drive signal controls the write module to be turned on, the data signal Vdata can be written to the gate of the drive transistor DT, so that during the light-emitting phase, the drive transistor DT can generate a drive current according to its gate signal, thereby driving the light-emitting module 55 to display light.

[0105] Exemplary, with reference to Figure 3 、 Figure 10 and Figure 11, gout(i) represents the gate drive signal outputted by the signal output terminal Gout of the i-th shift register Gi. When the gate drive signal gout(1) outputted by the signal output terminal Gout(1) of the first-stage shift register G1 is at an effective level, the pixel circuit 50 in the first row electrically connected to the first-stage shift register G1 can be written with data; when the gate drive signal gout(2) outputted by the signal output terminal Gout(2) of the second-stage shift register G2 is at an effective level, the pixel circuit 50 in the second row electrically connected to the second-stage shift register G2 can be written with data; when the gate drive signal gout(3) outputted by the signal output terminal Gout(3) of the third-stage shift register G3 is at an effective level, the pixel circuit 50 in the second row electrically connected to the second-stage shift register G3 can be written with data. The pixel circuit 50 in the third row electrically connected to the first-stage shift register G3 can perform data writing; by analogy, when the gate drive signal gout(N-1) outputted by the signal output terminal Gout(N-1) of the N-1th-stage shift register GN-1 is at a valid level, the pixel circuit 50 in the N-1th row electrically connected to the N-1th-stage shift register GN-1 can perform data writing; when the gate drive signal gout(N) outputted by the signal output terminal Gout(N) of the Nth-stage shift register GN is at a valid level, the pixel circuit 50 in the Nth row electrically connected to the Nth-stage shift register GN can perform data writing.

[0106] It should be understood that the above description is merely an exemplary description of the shift register G and the manner in which the shift register G provides gate drive signals to the pixel circuit 50. The present invention does not impose any specific limitations on this description, provided that the core features of the present invention can be achieved. To more clearly explain the present invention, a typical example of the shift register G is described below.

[0107] Optional, Figure 12 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 12 As shown, the isolation control module 13 includes an isolation transistor T4; in the same shift register G, the gate of the isolation transistor T4 is electrically connected to the isolation control terminal Ct, the first electrode of the isolation transistor T4 is electrically connected to the first node Q1, and the second electrode of the isolation transistor T4 is electrically connected to the second node Q2.

[0108] Specifically, the isolation control signal provided by the isolation control terminal Ct can control the conduction or shutdown of the isolation transistor T4. When the isolation control signal is at an active level, the isolation transistor T4 can be turned on, and the isolation transistor T4 can transmit the electrical signal at the first node Q1 to the second node Q2, so that the second node Q2 can be consistent with the signal at the first node Q1. When the isolation control signal is at an inactive level, the isolation transistor T4 can be turned off, which can prevent the electrical signal at the second node Q2 from being transmitted to the first node Q1 and the signal input terminal Vin, thereby generating leakage current and improving the accuracy of the potential at the second node Q2.

[0109] It is understandable that the isolation transistor T4 can be an NMOS transistor or a PMOS transistor, and can be specifically designed according to actual needs. The embodiment of the present invention does not specifically limit this. When the isolation transistor T4 is an NMOS transistor, the effective level of the isolation control signal ct is a high level; conversely, when the isolation transistor T4 is a PMOS transistor, the effective level of the isolation control signal ct is a low level. For ease of description, without special limitations, the embodiments of the present invention take the transistors in the shift register G as NMOS transistors as an example to illustrate the technical solutions of the embodiments of the present invention. Accordingly, the effective levels of the signals received by the shift register G and the signals at each node are all high levels, and the invalid levels are all low levels.

[0110] In an optional embodiment, Figure 13 A circuit diagram of another shift register provided by an embodiment of the present invention is shown. Figure 14 A schematic diagram of a circuit structure of another shift register provided in an embodiment of the present invention is provided. Figure 15 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figures 13 to 15 The shift register G also includes a reset module 15; in the same shift register G, the reset module 15 is electrically connected to the third node Q3, the second level terminal VGL, the first clock terminal CK1 and the second clock terminal CK2 respectively; the reset module 15 is also electrically connected to the first node Q1 and / or the second node Q2.

[0111] Specifically, by providing a reset module 15 electrically connected to the third node Q3, the second level terminal VGL, the first clock terminal CK1, and the second clock terminal CK2, the reset module 15 can control the signal at the third node Q3 based on the signal at the third node Q3, the second level signal vgl, the first clock signal ck1, and the second clock signal ck2, thereby resetting the potential of the third node Q3. For example, the reset module 15 can control the path along which the second level signal vgl is transmitted to the third node Q3 based on the signal at the third node Q3, the first clock signal ck1, and the second clock signal ck2. Furthermore, the reset module 15 can also be electrically connected to the first node Q1 and / or the second node Q2 to reset the first node Q1 and / or the second node Q2. Thus, by providing the reset module 15 to reset the third node Q2, the first node Q1, and / or the second node Q2, the signals at each node can accurately control the operation of the shift register G, while preparing for the next input of a valid level at each node. This improves the accuracy of the gate drive signal output by the shift register G, thereby enhancing the display quality of the display panel 100.

[0112] It can be understood that the reset module 15 is electrically connected to the first node Q1 and / or the second node Q2, that is, the reset module 15 can also be electrically connected to at least one of the first node Q1 and the second node Q2. Figure 13 As shown, the reset module 15 is electrically connected to the first node Q1 and the third node Q3, so that the reset module 15 can reset the first node Q1 and the third node Q3. Figure 14 As shown, the reset module 15 is electrically connected to the second node Q2 and the third node Q3, so that the reset module 15 can reset the second node Q2 and the third node Q3. Figure 15 As shown, the reset module 15 is electrically connected to the first node Q1, the second node Q2, and the third node Q3, respectively, so that the reset module 15 can simultaneously reset the first node Q1, the second node Q2, and the third node Q3. The embodiment of the present invention does not limit the specific connection method between the reset module and the first node Q1, the second node Q2, and the third node Q3.

[0113] In an optional embodiment, Figure 16 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 17 A circuit diagram of another shift register provided by an embodiment of the present invention is shown. Figure 18 A schematic diagram of a circuit structure of another shift register provided in an embodiment of the present invention is provided. Figure 19 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 20A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 21 A circuit diagram of another shift register provided by an embodiment of the present invention is provided. Figures 16 to 21 The reset module 15 includes a first reset submodule 151 and a second reset submodule 152; in the same shift register G: the first reset submodule 151 is electrically connected to the third node Q3, the second level terminal VGL and the second clock terminal CK2 respectively; the first reset submodule 151 is also electrically connected to the first node Q1 and / or the second node Q2; the second reset submodule 152 is electrically connected to the first clock terminal CK1 and the third node Q3 respectively; the second reset submodule 152 is also electrically connected to the first node Q1 or the second node Q2.

[0114] Specifically, the first reset submodule 151 can control the signal of the first node Q1 and / or the second node Q2 based on the signal of the third node Q3, the second clock signal ck2 of the second clock terminal CK2, and the second level signal vgl of the second level terminal VGL, so as to reset the first node Q1 and / or the second node Q2. Exemplarily, when the first reset submodule 151 is electrically connected to the third node Q3, the second clock terminal CK2, the second level terminal VGL, and the first node Q1, respectively, and when the second clock signal ck2 received by the second clock terminal CK2 and the signal of the third node Q3 are both at a valid level, the first reset submodule 151 can transmit the second level signal vgl to the first node Q1 to reset the first node Q1.

[0115] The second reset submodule 152 can control the signal at the third node Q3 based on the signal at the first node Q1 and / or the second node Q2, and the first clock signal ck1 at the first clock terminal CK1, to reset the third node Q3. For example, when the second reset submodule 152 is electrically connected to the third node Q3, the first clock terminal CK1, and the second node Q2, respectively, and the signal at the second node Q2 is at an active level and the first clock signal ck1 at the first clock terminal CK1 is at an inactive level, the second reset submodule 152 can transmit the inactive level of the first clock signal ck1 to the third node Q3, to reset the third node Q3.

[0116] It should be noted that the first reset submodule 151 can be electrically connected to the first node Q1 and / or the second node Q2 to reset the first node Q1 and / or the second node Q2; the second reset submodule 152 can be electrically connected to the first node Q1 or the second node Q2 to control the reset of the third node Q3 via the first node Q1 or the second node Q2. The electrical connection relationship between the first reset submodule 151 and the first node Q1 and the second node Q2, and the electrical connection relationship between the second reset submodule 152 and the first node Q1 or the second node Q2 can be set according to actual needs and are not specifically limited here. For ease of description, the embodiments of the present invention are described as follows: the first reset submodule 151 is electrically connected to the first node Q1, the second node Q2, and the third node Q3, and the second reset submodule 152 is electrically connected to the second node Q2 and the third node Q3.

[0117] In an optional embodiment, Figure 22 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 23 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 22 and Figure 23 The first reset submodule 151 includes a first reset unit 1511 and a second reset unit 1512; in the same shift register G: the first reset unit 1511 is electrically connected to the second clock terminal CK2, the second level terminal VGL, the third node Q3 and the first node Q1 respectively; the second reset unit 1512 is electrically connected to the second clock terminal CK2, the first level terminal VGH and the second node Q2 respectively; the second reset unit 1512 is also electrically connected to the first reset unit 1511 at the fourth node Q4, or the second reset unit 1512 is also electrically connected to the first node Q1.

[0118] Specifically, the first reset unit 1511 can control the signal at the first node Q1 based on the signal at the third node Q3, the second clock signal ck2 at the second clock terminal CK2, and the second level signal vgl at the second level terminal VGL, thereby resetting the first node Q1. For example, when the second clock signal ck2 received at the second clock terminal CK2 and the signal at the third node Q3 are both at a valid level, the first reset unit 1511 can transmit the second level signal vgl to the first node Q1 to reset the first node Q1. The second reset unit 1512 can control the signal at the second node Q2 based on the second clock signal ck2 at the second clock signal terminal CK2, the first level signal vgh at the first level terminal VGH, and the signal at the fourth node Q4 to reset the second node Q2. For example, when the second clock signal ck2 received at the second clock terminal CK2 is at a valid level and the signal at the fourth node Q4 is at a valid level, the second reset unit 1512 can transmit the invalid level of the fourth node Q4 to the second node Q2 to reset the second node Q2. In this way, by providing the first reset unit 1511 and the second reset unit 1512 , the first node Q1 and the second node Q2 are reset respectively, thereby improving reset accuracy and reliability.

[0119] It should be noted that, under the premise that the first reset unit 1511 can reset the first node Q1 and the second reset unit 1512 can reset the second node Q2, the embodiment of the present invention does not limit the specific structures of the first reset unit 1511 and the second reset unit 1512. The following uses a typical example to illustrate the specific structure of each unit in the embodiment of the present invention.

[0120] Optional, Figure 24 A circuit structure diagram of another shift register provided in an embodiment of the present invention is shown as follows: Figure 24 As shown, the first reset unit 1511 includes a first reset transistor T7 and a second reset transistor T8; in the same shift register G: the gate of the first reset transistor T7 is electrically connected to the third node Q3, the first electrode of the first reset transistor T7 is electrically connected to the second level terminal VGL, the second electrode of the first reset transistor T7 and the first electrode of the second reset transistor T8 are electrically connected to the fourth node Q4; the gate of the second reset transistor T8 is electrically connected to the second clock terminal CK2, and the second electrode of the second reset transistor T8 is electrically connected to the first node Q1.

[0121] Specifically, the first reset transistor T7 can be turned on or off according to the signal of the third node Q3. When the third node Q3 controls the first reset transistor T7 to be turned on, the second level terminal VGL and the fourth node Q4 can be controlled to form a conductive path, so that the second level signal vgl of the second level terminal VGL is transmitted to the fourth node Q4. Exemplarily, when the signal of the third node Q3 is at an active level, the first reset transistor T7 is turned on, and the second level signal vgl is transmitted to the fourth node Q4.

[0122] The second reset transistor T8 can be turned on or off based on the second clock signal ck2 provided by the second clock terminal CK2. When the second clock signal ck2 controls the first reset transistor T7 to be turned on, the second reset transistor T8 can control the fourth node Q4 to form a conductive path with the first node Q1, so that the signal of the fourth node Q4 can be transmitted to the first node Q1. For example, when the second clock signal ck2 received by the second clock terminal CK2 is at an active level, the second reset transistor T8 is turned on, and the signal of the fourth node Q4 is transmitted to the first node Q1, thereby resetting the first node Q1.

[0123] Optional, Figure 25 A schematic diagram of a circuit structure of another shift register provided in an embodiment of the present invention is provided. Figure 26 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 25 and Figure 26 The second reset unit 1512 includes a signal transmission subunit 1513 and a transmission control subunit 1514; in the same shift register G: the transmission control subunit 1514 is electrically connected to the second node Q2 and the first level terminal VGH respectively; the transmission control subunit 1514 is also electrically connected to the signal transmission subunit 1513 at the fifth node Q5; the signal transmission subunit 1513 is electrically connected to the second clock terminal CK2 and the second node Q2 respectively; the signal transmission subunit 1513 is also electrically connected to the fourth node Q4 or the first node Q1.

[0124] Specifically, the transmission control subunit 1514 can control the signal of the fifth node Q5 based on the signal of the second node Q2 and the first level signal vgh of the first level signal VGH. For example, when the signal of the second node Q2 is at a valid level, the transmission control subunit 1514 can transmit the first level signal vgh to the fifth node Q5.

[0125] The signal transmission subunit 1513 can control the signal of the second node Q2 based on the second clock signal ck2 of the second clock terminal CK2, the signal of the fifth node Q5, and the signal of the fourth node Q4 or the first node Q1, so as to reset the second node Q2. Exemplarily, the signal transmission subunit 1513 is electrically connected to the fourth node Q4, the second clock terminal CK2, the fifth node Q5, and the second node Q2, respectively. When the second clock signal ck2 received by the second clock terminal CK2 is at a valid level and the signal of the fifth node Q5 is at an invalid level, the signal transmission subunit 1513 can transmit the signal of the fourth node Q4 to the second node Q2, so as to reset the second node Q2.

[0126] In this way, by setting the signal transmission subunit 1513 to prepare for transmitting the signal of the first node Q1 or the fourth node Q4 to the second node Q2, the signal control subunit 1514 controls the moment when the signal transmission subunit 1513 transmits the reset signal to the second node Q2, and then the reset moment of the second node Q2 can be adjusted according to actual needs, thereby improving the practicality and flexibility of the second reset unit 1512.

[0127] It should be noted that, provided that the signal transmission subunit 1513 and the transmission control subunit 1514 can reset the second node Q2, the embodiment of the present invention does not limit the specific structures of the signal transmission subunit 1513 and the transmission control subunit 1514. The following uses a typical example to illustrate the specific structures of the signal transmission subunit 1513 and the transmission control subunit 1514.

[0128] Optional, Figure 27 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 28 A circuit diagram of another shift register provided by an embodiment of the present invention is provided. Figure 27 and Figure 28 The signal transmission subunit 1513 includes a third reset transistor T9 and a fourth reset transistor T10; in the same shift register G, the gate of the third reset transistor T9 and the gate of the fourth reset transistor T10 are both electrically connected to the second clock terminal CK2; the first electrode of the third reset transistor T9 is electrically connected to the first node Q1 or the fourth node Q4; the second electrode of the third reset transistor T9 and the first electrode of the fourth reset transistor T10 are electrically connected to the fifth node Q5; and the second electrode of the fourth reset transistor T10 is electrically connected to the second node Q2.

[0129] Specifically, when the first electrode of the third reset transistor T9 is electrically connected to the fourth node Q4, the second clock signal provided at the second clock terminal CK2 is at an active level, so that the second clock signal can control the third reset transistor T9 and the fourth reset transistor T10 to be in a conductive state, thereby transmitting the reset signal at the fourth node Q4 to the second node Q2, thereby resetting the second node Q2. When the first electrode of the third reset transistor T9 is electrically connected to the first node Q1, the second clock signal provided at the second clock terminal CK2 is at an active level, so that the second clock signal can control the third reset transistor T9 and the fourth reset transistor T10 to be in a conductive state, thereby transmitting the reset signal at the first node Q1 to the second node Q2, thereby resetting the second node Q2.

[0130] Optionally, the voltage difference between the effective level of the second clock signal ck2 at the second clock terminal CK2 and the first level signal ck1 at the first level terminal VGH is ΔV; the threshold voltage of the fourth reset transistor T10 is Vth. Wherein, |ΔV| <Vth。

[0131] Specifically, when the signal at the second node Q2 is at an active level, the active level of the second node Q2 can control the transmission control subunit 1514 to transmit the first-level signal at the first-level terminal VGH to the fifth node Q5. By setting the absolute value of the voltage difference |ΔV| between the second clock signal ck2 and the first-level signal ck1 to be less than the threshold voltage Vth of the fourth reset transistor T10, during the period when the second node Q2 is at an active level, even if the second clock signal ck2 is at an active level, the turn-on condition of the fourth reset transistor T10 is not met, causing the fourth reset transistor T10 to be in an off state. The fourth reset transistor T10 does not transmit the corresponding signal to the second node Q2, thereby preventing the second node Q2 from being reset when the signal at the second node Q2 is at an active level, thereby preventing the gate drive signal output by the shift register G from being affected. This improves the accuracy of the gate drive signal output by the shift register G and enhances the display effect of the display panel 100.

[0132] Optional, Figure 29 A circuit diagram of another shift register provided in an embodiment of the present invention is shown in FIG. Figure 29 As shown, the transmission control subunit 1514 includes a fifth reset transistor T11; in the same shift register G, the gate of the fifth reset transistor T11 is electrically connected to the second node Q2, the first electrode of the fifth reset transistor T11 is electrically connected to the first level end VGH, and the second electrode of the fifth reset transistor T11 is electrically connected to the fifth node Q5.

[0133] When the signal at the second node Q2 is at an active level, the signal at the second node Q2 can control the fifth reset transistor T11 to turn on, thereby transmitting the first-level signal vgh of the first level terminal VGH to the fifth node Q5, controlling the fourth reset transistor T10 to turn off, and preventing the second node Q2 from being reset. When the signal at the second node Q2 is at an inactive level, the inactive level at the second node Q2 can control the fifth reset transistor T11 to turn off, preventing the fifth reset transistor T11 from transmitting the first-level signal vgh of the first level terminal VGH to the fifth node Q5. The third reset transistor T9 and the fourth reset transistor T10 can be turned on or off in response to the second clock signal ck2 provided by the second clock terminal CK2, so that when the second clock signal ck2 is at an active level, the third reset transistor T9 and the fourth reset transistor T10 can be turned on, causing the reset signal at the fourth node Q4 or the first node Q1 to be transmitted to the second node Q2, thereby resetting the signal at the second node Q2.

[0134] Optional, Figure 30 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 31 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 30 and Figure 31 The second reset submodule 152 includes a sixth reset transistor T3. Within the same shift register G, the gate of the sixth reset transistor T3 is electrically connected to the first node Q1 or the second node Q2, the first electrode of the sixth reset transistor T3 is electrically connected to the first clock terminal CK1, and the second electrode of the sixth reset transistor T3 is electrically connected to the third node Q3. Thus, when the signal at the second node Q2 is at an active level, the signal at the second node Q2 can control the sixth reset transistor T3 to conduct, thereby transmitting the first clock signal ck1 from the first clock terminal CK1 to the third node Q3, thereby resetting the signal at the third node Q3.

[0135] The above description is merely an example of the structures of the isolation control module 13 and the reset module 15 in the shift register G. Based on this, the structures of the first control module 11, the second control module 12, and the output module 14 can be configured according to actual needs and are not specifically limited in the embodiment of the present invention. The following description uses a typical example to illustrate the specific structures of the first control module 11, the second control module 12, and the output module 14 in the embodiment of the present invention.

[0136] In an optional embodiment, Figure 32 A circuit structure diagram of another shift register provided in an embodiment of the present invention is shown as follows: Figure 32As shown, the first control module 11 includes a first control transistor T1. In the same shift register G, the gate of the first control transistor T1 is electrically connected to the first clock terminal CK1, the first electrode of the first control transistor T1 is electrically connected to the signal input terminal Vin, and the second electrode of the first control transistor T1 is electrically connected to the first node Q1. Thus, the first control transistor T1 can be turned on or off under the control of a first clock signal from the first clock terminal CK1. When the first clock signal controls the first control transistor T1 to be turned on, the signal input terminal Vin and the first node Q1 can be controlled to form a conductive path, so that the signal from the signal input terminal Vin is transmitted to the first node Q1, and the signal at the first node Q1 remains consistent with the signal from the signal input terminal Vin.

[0137] Optional, continue to refer to Figure 32 The second control module 12 includes a second control transistor T2. In the same shift register G, the gate of the second control transistor T2 is electrically connected to the first clock terminal CK1, the first electrode of the second control transistor T2 is electrically connected to the first level terminal VGH, and the second electrode of the second control transistor T2 is electrically connected to the third node Q3. Thus, the second control transistor T2 can be turned on or off under the control of the first clock signal of the first clock terminal CK1. When the first clock signal controls the second control transistor T2 to be turned on, the first level terminal VGH and the third node Q3 can be controlled to form a conductive path, so that the signal of the first level terminal VGH is transmitted to the third node Q3, and the signal of the third node Q3 remains consistent with the signal of the first level terminal VGH.

[0138] Optional, continue to refer to Figure 32 The output module 14 includes a first output transistor T5 and a second output transistor T6; in the same shift register G: the gate of the first output transistor T5 is electrically connected to the second node Q2, the first electrode of the first output transistor T5 is electrically connected to the second clock terminal CK2, and the second electrode of the first output transistor T5 is electrically connected to the signal output terminal Gout; the gate of the second output transistor T6 is electrically connected to the third node Q3, the first electrode of the second output transistor T6 is electrically connected to the second level terminal VGL, and the second electrode of the second output transistor T6 is electrically connected to the signal output terminal Gout.

[0139] Specifically, the signal at the second node Q2 can control the on / off state of the first output transistor T5. When the signal at the second node Q2 is at an active level, the first output transistor T5 can be controlled to be turned on, so that the second clock signal at the third clock terminal CK2 can be transmitted to the signal output terminal Gout, and the gate drive signal outputted by the signal output terminal Gout is consistent with the second clock signal. The signal at the third node Q3 can control the on / off state of the second output transistor T6. When the signal at the third node Q3 is at an active level, the second output transistor T6 can be controlled to be turned on, so that the second level signal vgl at the second level terminal VGL is transmitted to the signal output terminal Gout, and the gate drive signal outputted by the signal output terminal Gout is consistent with the second level signal. In this way, by controlling the signals at the second node Q2 and the third node Q3, the on-time of the first output transistor T5 and the second output transistor T6 can be controlled, thereby controlling the effective pulse time of the gate drive signal outputted by the signal output terminal Gout.

[0140] Optional, continue to refer to Figure 32 The output module 14 may further include a holding capacitor C4, which may be electrically connected between the third node Q3 and the second level end VGL to maintain the potential of the third node Q3, so that the signal of the third node Q3 can accurately control the output module 14 to output a gate drive signal.

[0141] Optional, continue to refer to Figure 32 , the shift register G further includes a bootstrap module 17; in the same shift register G, the bootstrap module 17 is electrically connected between the signal output terminal Gout and the second node Q2.

[0142] The bootstrap module 17 includes components such as a bootstrap capacitor C3 and can be configured according to actual needs.

[0143] Specifically, the bootstrap module 17 can couple the change in the signal output terminal Gout to the gate of the first output transistor T5 when the gate drive signal of the signal output terminal Gout changes, pull down or raise the voltage of the gate signal of the first output transistor T5, so that the gate signal of the first output transistor T5 can have a higher driving capability, thereby being able to accurately transmit the second clock signal ck2 to the signal output terminal Gout, so that the signal output terminal Gout can accurately output the gate drive signal.

[0144] Below Figure 32 The structure of the shift register shown in FIG. 1 is used to illustrate the working process of the first type shift register 1G. Figure 32 and Figure 33 , the driving cycle of the shift register G includes the t11 phase, the t12 phase and the t13 phase.

[0145] Before stage t11, when the first clock signal ck1 at the first clock terminal CK1 is at an active level, the second control transistor T2 is turned on, causing the first-level signal vgh at the first level terminal VGH to be transmitted to the third node Q3. The signal q3 at the third node Q3 is at an active level, which controls the second output transistor T6 in the output module 14 to be turned on. The second output transistor T6 transmits the second-level signal vgl at the second level terminal VGL to the signal output terminal Gout, and the gate drive signal gout output by the signal output terminal Gout is at an inactive level. At the same time, the signal input terminal Vin of the shift register G4 receives an input signal vin at an inactive level. Therefore, even if the first clock signal ck1 at the first clock terminal CK1 is at an active level, the first control transistor T1 is in the on state, and the signal q1 transmitted to the first node Q1 remains at an inactive level. In addition, since the third node Q3 is at an effective level, the first reset transistor T7 is in a conductive state, and the second level signal vgl of the second level terminal VGL is transmitted to the fourth node Q4, so that the signal of the fourth node Q4 is an invalid level. Therefore, when the second clock signal ck2 is at an effective level, the second reset transistor T8, the third reset transistor T9 and the fourth reset transistor T10 can all be in a conductive state, so that the signal of the fourth node Q4 can be transmitted to the first node Q1 and the second node Q2 respectively, so that the signals of the first node Q1 and the second node Q2 are both invalid levels; in addition, since in this stage, the isolation control signal ct of the isolation control terminal CT is at an invalid level, the isolation control transistor T4 is in a turned-off state, and the second node Q2 continues to maintain the signal after being reset by the third reset transistor T9 and the fourth reset transistor T10, that is, the signal of the second node Q2 is an invalid level, and the first output transistor T5 is turned off.

[0146] At stage t11, the input signal vin received by the signal input terminal Vin of the shift register G jumps to the active level, and the first clock signal ck1 of the first clock terminal CK1 and the isolation control signal ct of the isolation control terminal Ct are both at the active level, the second clock signal ck2 of the second clock terminal CK2 is at the inactive level, the first control transistor T1, the second control transistor T2 and the isolation transistor T4 are turned on, the active level of the input signal vin can be transmitted to the first node Q1 through the first control transistor T1, and the active level of the first node Q1 can be transmitted to the second node Q2 through the isolation transistor T4, and the second node Q2 controls the first output transistor T5 to be turned on; the first level signal vgh of the first level terminal VGH can be transmitted to the third node Q3 through the second control transistor T2, and the signal q3 of the third node Q3 controls the second output transistor T6 to be turned on; at this time, because the second clock signal ck2 of the second clock terminal CK2 is at the inactive level, the second clock signal ck2 transmitted by the first output transistor T5 to the signal input terminal Gout and the signal transmitted by the second output transistor T6 to the signal output terminal Gout are both at inactive levels, and the gate drive signal gout output by the signal output terminal Gout is at an inactive level.

[0147] During stage t12, the input signal vin received by the signal input terminal Vin of the shift register G becomes inactive, and the first clock signal ck1 of the first clock terminal CK1 and the isolation control signal ct of the isolation control terminal Ct are both inactive. The second clock signal ck2 of the second clock terminal CK2 is active, and the first control transistor T1, the second control transistor T2, and the isolation transistor T4 are turned off. At this time, if leakage current exists in the first control transistor T1, the signal q1 of the first node Q1 will be transmitted to the signal input terminal Vin. Because the isolation transistor T4 is in the off state, leakage current from the signal q1 of the first node Q1 will not affect the signal q2 of the second node Q2, allowing the signal q2 of the second node Q2 to continue to remain at an active level. This ensures that the active level of the second node Q2 accurately controls the conduction of the first output transistor T5. The first output transistor T5 accurately transmits the active level of the second clock signal ck2 to the signal output terminal Gout, ensuring that the gate drive signal gout outputted by the signal output terminal Gout is accurately at an active level. In addition, when the signal q2 of the second node Q2 is at a valid level, the valid level of the second node Q2 controls the sixth reset transistor T3 to turn on, and the sixth reset transistor T3 transmits the invalid level of the first clock signal ck1 to the third node Q3, and the invalid level of the third node Q3 controls the second output transistor T6 to turn off.

[0148] In the t13 stage, the input signal vin received by the signal input terminal Vin of the shift register G continues to maintain an invalid level, and the second clock signal ck2 of the second clock terminal CK2 and the isolation control signal ct of the isolation control terminal Ct are both invalid levels, the first clock signal ck1 of the first clock terminal CK1 is valid level, the first control transistor T1 and the second control transistor T2 are turned on, the second control transistor T2 transmits the first level signal vgh of the first level terminal VGH to the third node Q3, the valid level of the third node Q3 controls the first reset transistor T7 to turn on, the first reset transistor T7 transmits the second level signal vgl of the second level terminal VGL to the fourth node Q4, the valid level of the second clock signal ck2 controls the second reset transistor T8 to turn on, the second reset transistor T8 transmits the invalid level of the fourth node Q4 to the first node Q1, so as to achieve the reset of the first node Q1. The active level of the second clock signal ck2 controls the third reset transistor T9 and the fourth reset transistor T10 to turn on. The third reset transistor T9 and the fourth reset transistor T10 transmit the inactive level of the fourth node Q4 to the second node Q2, thereby resetting the signal q2 at the second node Q2. The inactive level of the second node Q2 controls the first output transistor T5 to turn off. The active level of the third node Q3 controls the second output transistor T6 to turn on. The second output transistor T6 transmits the second-level signal vgl of the second-level terminal VGL to the signal output terminal Gout. The gate drive signal gout output by the signal output terminal Gout is at an inactive level.

[0149] After stage t13, the input signal vin at the signal input terminal Vin will continue to remain at an inactive level. Even if the first clock signal ck1 is at an active level, the signal q1 transmitted to the first node Q1 will also continue to remain at an inactive level. Simultaneously, when the first clock signal ck1 is at an active level, the second control transistor T2 is in a conductive state, causing the first-level signal vgh to be transmitted to the third node Q3, causing the signal q3 at the third node Q3 to be at an active level. In the absence of any other signals being written, the third node Q3 will continue to remain at an active level. Furthermore, the active level at the third node Q3 controls the first reset transistor T7 to be in a conductive state, allowing the second-level signal vgl to be transmitted to the fourth node Q4, causing the fourth node Q4 to be at an inactive level. Consequently, when the second clock signal ck2 at the second clock terminal CK2 is at an active level, the second reset transistor T8, the third reset transistor T9, and the fourth reset transistor T10 are turned on again to reset the first node Q1 and the second node Q2, respectively, so that the signals q1 at the first node Q1 and q2 at the second node Q2 can remain at an inactive level. Therefore, after stage t13, the second output transistor T6 will continue to be turned on, the first output transistor T5 will continue to be turned off, the second output transistor T6 transmits the second level signal vgl of the second level terminal VGL to the signal output terminal Gout, and the gate drive signal gout output by the signal output terminal Gout remains at an invalid level.

[0150] It should be noted that the above description is only an exemplary description of the working process of the first type shift register 1G. In the embodiment of the present invention, the working process of the first type shift register 1G can be adjusted accordingly by adjusting the effective level time of each signal received by the first type shift register 1G. The specific implementation method can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0151] Understandably, the reference Figure 6 The isolation control signal ct received by the isolation control terminal Ct can be provided by a corresponding isolation signal transmission line. In this case, each level of the first-class shift register 1G can be connected to an isolation signal transmission line to accurately control the on-time of the isolation control module 13 in each level of the first-class shift register 1G; alternatively, each isolation signal transmission line can be electrically connected to multiple levels of the first-class shift register 1G. Under the premise that the on-time or off-time requirements of the isolation control module 13 in each level of the shift register G can be met, the embodiment of the present invention does not make any specific limitations on this.

[0152] In an optional embodiment, Figure 34 A circuit diagram of another shift register provided in an embodiment of the present invention is shown in FIG. Figure 34 As shown, in the same shift register G, the isolation control terminal Ct is electrically connected to the signal input terminal Vin.

[0153] Specifically, when the input signal of the signal input terminal Vin is at a valid level, the isolation control signal of the isolation control terminal Ct is also at a valid level. The isolation control terminal Ct can control the isolation control module 13 to be in an on state, so that the input signal of the signal input terminal Vin reaches the first node Q1 through the first control module 11, and can continue to pass through the isolation control module 13 to reach the second node Q2, so as to achieve signal transmission between the first node Q1 and the second node Q2 during at least part of the time when the input signal of the signal input terminal Vin is at a valid level. When the input signal at the signal input terminal Vin is at an invalid level, the isolation control signal at the isolation control terminal Ct is also at an invalid level. The isolation control terminal Ct can control the isolation control module 13 to be in a closed state, disconnecting the signal transmission path between the first node Q1 and the second node Q2, and preventing the effective level at the second node Q2 from discharging to the first node Q1 or the signal input terminal Vin to generate leakage current. This allows the connection path between the first node Q1 and the second node Q2 to be disconnected after the input signal at the signal input terminal Vin jumps from an effective level to an invalid level, thereby improving the accuracy of the signal at the second node Q2 and the signal input terminal Vin and improving the operating reliability of the shift register G. At the same time, the isolation control terminal Ct is electrically connected to the signal input terminal Vin, so that the isolation control terminal Ct is electrically connected to the signal line providing the input signal. This eliminates the need to provide a separate signal line for the isolation control terminal Ct, which helps simplify the structure of the drive circuit 10 and reduce the overall size of the drive circuit 10. When the display panel 100 also includes a non-display area NA that at least partially surrounds the display area AA, if the driving circuit 10 is set in the non-display area NA, the driving circuit 10 with a smaller size has a smaller occupied space in the non-display area NA, which can reduce the size of the non-display area NA, which is conducive to achieving a narrow bezel for the display panel 100.

[0154] In another alternative embodiment, Figure 35 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 35 As shown, the isolation control terminal Ct(x) of the x-th stage shift register Gx is electrically connected to the first node Q1(z) or the second node Q2(z) of the z-th stage shift register Gz; z is a positive integer, and x≠z. The effective level time of the signal at the first node Q1(z) or the signal at the second node Q2(z) of the z-th stage shift register G is the first time t01; the effective level time of the gate drive signal output by the signal output terminal Gout(y) of the y-th stage shift register Gy is the second time t02; the first time t01 and the second time t02 overlap.

[0155] It should be noted that Figure 35The Qz in the figure may be the first node Q1(z) or the second node Q2(z) of the z-th stage shift register Gz, and may be set according to actual needs. The driving circuit 10 also includes signal lines, such as Figure 35 As shown, the signal lines include a clock signal line k providing a clock signal ck, an isolation control signal line 70 providing an isolation control signal ct, and a fixed-level signal line v0 providing a fixed-level signal. The clock signal line k includes a first clock signal line k11, a second clock signal line k21, a third clock signal line k12, and a fourth clock signal line k22. The isolation control signal line 70 includes an x-th isolation control signal line 7x and a z-th isolation control signal line 7z. The fixed-level signal line v0 specifically includes a first-level signal line v1 providing a first-level signal vgh, and a second-level signal line v2 providing a second-level signal vgl.

[0156] Wherein, on the basis of x≠z, the values of x and z can be set according to actual needs. In an optional embodiment, x=z+3, or x=z+2, or x=z+1, and other values are also possible, which are not specifically limited here.

[0157] Specifically, since the signal input terminal Vin(x) of the x-th stage shift register Gx is electrically connected to the signal output terminal Gout(y) of the y-th stage shift register Gy, the input signal vin(x) of the signal input terminal Vin(x) of the x-th stage shift register Gx is synchronized with the gate drive signal gout(y) of the y-th stage shift register Gy. By setting the effective level time t01 of the signal at the first node Q1(z) or the signal at the second node Q2(z) of the z-th shift register Gz to overlap with the effective level time t02 of the gate drive signal output by the signal output terminal Gout(y) of the y-th shift register Gy, when the input signal at the signal input terminal Vin(x) of the x-th shift register Gx is at an effective level, the signal at the first node Q1(z) or the second node Q2(z) of the z-th shift register G is also at an effective level. The first node Q1(z) or the second node Q2(z) can control the isolation control module 13 of the x-th shift register Gx to be in a conductive state, thereby turning on the transmission path between the first node Q1(x) and the second node Q2(x), so that the input signal at the signal input terminal Vin(x) can be transmitted to the second node Q2(x) through the first node Q1(x), so that the shift register Gx can output an accurate gate drive signal, thereby improving the display effect of the display panel 100.

[0158] It should be noted that, under the premise that x≠y and x≠z, the specific values of x, y, and z can be set according to actual needs. In an optional embodiment, x=y+n, y≥n, y-n+1≤z≤y+n-1, and n is a positive integer. For example, when x=4 and y=2, n=2, 1≤z≤3, z can be 1, 2, or 3.

[0159] In which, the effective level time of the gate drive signal gout(x) of the x-stage shift register Gx is located after the effective level time of the gate drive signal gout(y) of the y-stage shift register Gy, the effective level time of the gate drive signal gout(z) of the z-stage shift register Gz is located between the effective level time of the gate drive signal gout(x) and the effective level time of the gate drive signal gout(y), and the effective level start time of the input signal vin(z) of the z-stage shift register Gz can be located before or after the start time of the gate drive signal gout(y) of the y-stage shift register Gy, that is, the effective level start time of the signal of the first node Q1(z) or the signal of the second node Q2(z) of the z-stage shift register Gz is located before or after the start time of the gate drive signal gout(y) of the y-stage shift register Gy, and before the effective level end time of the gate drive signal gout(z) of the z-stage shift register Gz, the signal of the first node Q1(z) and the signal of the second node Q2(z) of the z-stage shift register Gz will continue to maintain a valid level. It can be seen from this that the effective level time t01 of the signal of the first node Q1(z) or the signal of the second node Q2(z) of the z-th stage shift register Gz can overlap with the effective level time of the gate drive signal gout(y) of the y-th stage shift register Gy, that is, the effective level time t01 of the signal of the first node Q1(z) or the signal of the second node Q2(z) of the z-th stage shift register Gz can overlap with the effective level time of the input signal vin(x) of the x-th stage shift register Gx. In this way, by making x=y+n, y≥n, y-n+1≤z≤y+n-1, it is possible to ensure that the first node Q1(z) or the second node Q2(z) of the z-th shift register Gz can control the isolation control module 13 of the x-th shift register Gx to be in the on state during the time period when the input signal vin(x) of the x-th shift register Gx is at a valid level, thereby turning on the transmission path between the first node Q1(x) and the second node Q2(x), so that the input signal vin(x) of the signal input terminal Vin(x) can be transmitted to the second node Q2(x) through the first node Q1(x), so that the x-th shift register Gx can output an accurate gate drive signal, thereby improving the display effect of the display panel 100.

[0160] For example, when x=4, y=2, z=1, Figure 36 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown. Figure 37 for Figure 36 For the driving timing diagram of the shift register, refer to Figures 36 to 37 The driving cycle of the fourth-stage shift register G4 includes a t1 phase, a t2 phase, a t3 phase, and a t4 phase.

[0161] In the t1 phase, in the fourth-stage shift register G4, the gate drive signal gout(2) received by the signal input terminal Vin(4) from the signal output terminal Gout(2) of the second-stage shift register G2 is at an effective level, that is, the input signal vin(4) is at an effective level, the first clock signal ck1(4) of the first clock terminal CK1 is at an effective level, the first control transistor T1, the second control transistor T2 and the sixth reset transistor T3 are turned on, the effective level of the input signal vin(4) can be transmitted to the first node Q1 through the first control transistor T1, the first level signal vgh of the first level terminal VGH can be transmitted to the third node Q3(4) through the second control transistor T2, and the third node Q3(4) controls the second output transistor T6 to be turned on; the isolation control terminal Ct(4) of the fourth shift register G4 receives the signal q1(1) of the first node Q1(1) or the signal q2(1) of the second node Q1(1) of the shift register G1 2(1) is at an effective level, the isolation transistor T4 is turned on, and the effective level signal q1(4) of the first node Q1(4) can be transmitted to the second node Q2(4) of the shift register G4 through the isolation transistor T4, so that the signal q1(4) of the first node Q1(4) is consistent with the signal q2(4) of the second node Q2(4), so that the signal q2(4) of the second node Q2(4) can control the first output transistor T5 to be turned on; the second clock signal ck2(4) of the second clock terminal CK2 is at an inactive level, and the first output transistor T5 transmits the inactive level of the second clock signal ck2(4) to the signal output terminal Gout(4). At the same time, the second output transistor T6 transmits the second level signal vgl of the second level terminal VGL to the signal output terminal Gout(4), and the gate drive signal gout(4) output by the signal output terminal Gout(4) is at an inactive level.

[0162] In the phase t2, the signal output terminal Gout(2) of the second-stage shift register G2 changes from a valid level to an invalid level. In the fourth-stage shift register G4, the first clock signal ck1(4) of the first clock terminal CK1 becomes an invalid level, the first control transistor T1 is turned off, and the sixth reset transistor T3 transmits the invalid level of the first clock signal ck1(4) to the third node Q3(4); the signal q1(1) of the first node Q1(1) or the signal q1(2) of the second node Q1(2) in the first-stage shift register G1 is an invalid level, and the invalid level of the isolation control terminal Ct(4) of the fourth-stage shift register G4 controls the isolation transistor T4 of the fourth-stage shift register G4 to be turned off, thereby blocking the transmission path from the second node Q2(4) to the first node Q1(4) in the fourth-stage shift register G4, so that even if there is a leakage current from the first node Q1(1) to the signal input terminal Vin(4), the isolation transistor T4 of the fourth-stage shift register G4 is turned off, thereby reducing the leakage current from the second node Q2(4) to the signal input terminal Vin(4), thereby ensuring the signal stability of the second node Q2(4). At the same time, in the fourth-stage shift register G4, the fifth reset transistor T11 is turned on under the control of the stable effective level of the second node Q2(4), the first level signal vgh of the first level terminal VGH is transmitted to the fifth node Q5(4), and the third reset transistor T9 is turned off, so that the second node Q2(4) maintains the effective level, the second clock signal ck2(4) of the second clock terminal CK2 is still at the inactive level, so that the gate drive signal gout(4) outputted by the signal output terminal Gout(4) is at the inactive level.

[0163] In the t3 phase, in the fourth-stage shift register G4, the second clock signal ck2(4) of the second clock terminal CK2 is at an active level, the second node Q2(4) transmits the active level of the second clock signal ck2(4) to the signal output terminal Gout(4), and the gate drive signal gout(4) outputted by the signal output terminal Gout(4) is at an active level.

[0164] At stage t4, in the fourth-stage shift register G4, the second clock signal ck2(4) of the second clock terminal CK2 changes to an inactive level, and the second node Q2(4) transmits the inactive level of the second clock signal ck2(4) to the signal output terminal Gout(4). The gate drive signal gout(4) outputted by the signal output terminal Gout(4) is inactive.

[0165] At stage t5, the signal output terminal Gout(2) of the second-stage shift register G2 is at an invalid level. In the fourth-stage shift register G4, the first clock signal ck1(4) of the first clock terminal CK1 is at an invalid level, and the first control transistor T1 and the second control transistor T2 are turned off; the second clock signal ck2(4) of the second clock terminal CK2 is at an effective level, and the first reset transistor T7, the second reset transistor T8, the third reset transistor T9 and the fourth reset transistor T10 are turned on. The second level signal vgl of the second level terminal VGL can be transmitted to the first node Q1(4) through the first reset transistor T7 and the second reset transistor T8, and the second level signal vgl of the second level terminal VGL can be transmitted to the second node Q2(4) through the third reset transistor T9 and the fourth reset transistor T10 to reset the first node Q1(4) and the second node Q2(4). At this time, the gate drive signal gout(4) outputted by the signal output terminal Gout(4) of the fourth-stage shift register G4 is at an invalid level.

[0166] In this way, by setting x=y+n, y≥n, y-n+1≤z≤y+n-1; n is a positive integer, when the signal input terminal Gout(x) of the shift register Gx receives the signal output terminal Gout(y) of the y-th stage shift register Gy as a valid level, the isolation control terminal Ct(x) of the x-th stage shift register Gx can provide a valid level at the first node Q1(z) and the second node Q2(z) of the z-th stage shift register Gz, thereby controlling the isolation control module 14 to be turned on, and then the valid level of the signal input terminal Gout(x) can be transmitted to the second node Q2(x), so that the shift register Gx can output an accurate gate drive signal, thereby improving the display effect of the display panel 100. When the signal input terminal Gout(x) of the shift register Gx receives the signal output terminal Gout(y) of the y-stage shift register Gy as an invalid level, the isolation control terminal Ct(x) of the x-stage shift register Gx can provide an effective level at the first node Q1(z) and the second node Q2(z) of the z-stage shift register Gz, controlling the isolation control module 14 to be turned off, thereby preventing the effective level of the second node Q2(x) from being transmitted to the signal input terminal Vin(4) through the isolation control module 14 and the first control module 11, thereby preventing leakage current from being generated, improving the signal accuracy of the second node Q2(x), and improving the display effect of the display panel 100. At the same time, the isolation control terminal Ct is electrically connected to the first node Q1(z) or the second node Q2(z) of the z-stage shift register Gz, eliminating the need to set a separate signal line for the isolation control terminal Ct, thereby simplifying the structure of the drive circuit 10 and reducing the overall size of the drive circuit 10. When the display panel 100 also includes a non-display area NA that at least partially surrounds the display area AA, if the driving circuit 10 is set in the non-display area NA, the driving circuit 10 with a smaller size has a smaller occupied space in the non-display area NA, which can reduce the size of the non-display area NA, which is conducive to achieving a narrow bezel for the display panel 100.

[0167] Furthermore, in this embodiment, the first n+1 shift registers G may be second-type shift registers 2G. The isolation control terminal Ct of the second-type shift register 2G receives a signal transmitted by a signal line. For example, the isolation control terminal Ct of the second-type shift register 2G may receive a first-level signal vgh to ensure that the isolation transistors in the first n+1 shift registers G remain in a continuously conductive state.

[0168] It should be noted that the above description is only an example of the isolation control signal ct received by each level of shift register G. On the premise that the core invention of the embodiment of the present invention can be achieved, the embodiment of the present invention does not specifically limit the isolation control signal ct received by the isolation control terminal Ct.

[0169] Based on the above embodiment, optionally, Figure 38 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 39 A circuit diagram of another shift register provided by an embodiment of the present invention is shown. Figure 40 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is provided. Figures 38 to 40 , the shift register G further includes a voltage stabilizing module 16; in the same shift register G, the voltage stabilizing module 16 is electrically connected to the first node Q1 and / or the second node Q2.

[0170] The voltage stabilizing module 16 includes devices such as transistors and can be configured according to actual needs, which are not specifically limited here.

[0171] Specifically, a voltage stabilizing module 16 electrically connected to the first node Q1 and / or the second node Q2 is provided to stabilize the electrical signal at the first node Q1 and / or the second node Q2, reduce the fluctuation of the electrical signal at the first node Q1 and / or the second node Q2, and improve the stability of the electrical signal at the first node Q1 and / or the second node Q2.

[0172] In an optional embodiment, Figure 41 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 42 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 43 A circuit diagram of another shift register provided by an embodiment of the present invention is provided. Figures 41 to 43 The voltage stabilizing module 16 includes a first voltage stabilizing capacitor C1 and / or a second voltage stabilizing capacitor C2; in the same shift register G: the first plate of the first voltage stabilizing capacitor C1 is electrically connected to the first node Q1, and the second plate of the first voltage stabilizing capacitor C1 is electrically connected to the first level end VGH or the second level end VGL; the first plate of the second voltage stabilizing capacitor C2 is electrically connected to the second node Q2, and the second plate of the second voltage stabilizing capacitor C2 is electrically connected to the first level end VGH or the second level end VGL.

[0173] Specifically, the second plate of the first stabilizing capacitor C1 receives a first-level signal from the first level terminal VGH or a second-level signal from the second level terminal VGL. The first plate of the first stabilizing capacitor C1 is electrically connected to the first node Q1, so that the first stabilizing capacitor C1 can store the signal from the first node Q1 to ensure signal stability at the first node Q1. The second plate of the second stabilizing capacitor C2 receives a first-level signal from the first level terminal VGH or a second-level signal from the second level terminal VGL. The first plate of the second stabilizing capacitor C2 is electrically connected to the second node Q2, so that the second stabilizing capacitor C2 can store the signal from the second node Q2 to ensure signal stability at the second node Q2.

[0174] Based on the above embodiment, optionally, refer to Figure 5 The display panel 100 further includes a plurality of clock signal lines k. The first clock terminal CK1 of the x-th stage shift register G and the second clock terminal CK2 of the y-th stage shift register G are electrically connected to the same clock signal line k12. And / or, the second clock terminal CK2 of the x-th stage shift register G and the first clock terminal CK1 of the y-th stage shift register G are electrically connected to the same clock signal line k22. The clock signal line k is used to provide a clock signal.

[0175] Specifically, by electrically connecting the first clock terminal CK1 of the x-stage shift register G and the second clock terminal CK2 of the y-stage shift register G to the same clock signal line k12, the clock signals received by the cascaded x-stage shift register G and the y-stage shift register G are opposite, thereby causing the effective pulses of the gate drive signal provided by the x-stage shift register G and the gate drive signal provided by the y-stage shift register G to shift sequentially. Simultaneously, by electrically connecting the first clock terminal CK1 of the x-stage shift register G and the second clock terminal CK2 of the y-stage shift register G to the same clock signal line k12, and electrically connecting the second clock terminal CK2 of the x-stage shift register G and the first clock terminal CK1 of the y-stage shift register G to the same clock signal line k22, some of the shift registers G share the same clock signal line k, thereby reducing the number of clock signal lines k and improving the utilization of the wiring harness within the display panel 100.

[0176] It should be noted that the number of clock signal lines k can be set according to actual needs. Figure 5The clock signal line k is shown to include a first sub-clock signal line k1 and a second sub-clock signal line k1. The number of clock signal lines k can also be other. In addition to the clock signal line k, the display panel 100 also includes other signal lines. Optionally, the signal lines also include a start signal line STV that provides a start control signal stv. The start signal line STV is electrically connected to the signal input terminal Vin of the first-stage shift register G1. The signal lines also include isolation control signal lines 70 that provide an isolation control signal ct. Specifically, they include a first isolation control signal line 71, a second isolation control signal line 72, a y-th stage isolation control signal line 7y, an x-th stage isolation control signal line 7x, ..., an N-1-th stage isolation control signal line 7N-1, and an N-th stage isolation control signal line 7N. Each isolation control signal line 70 can be electrically connected to the isolation control terminal Ct of each stage of the shift register G. For example, the y-th stage isolation control signal line 7y is electrically connected to the isolation control terminal Ct of the y-stage shift register Gy. The display panel 100 also includes a level signal line v0 that provides a fixed level signal, specifically including a first level signal line v1 that provides a first level signal vgh, and a second level signal line v2 that provides a second level signal vgl. The first level signal line v1 can be electrically connected to the first level terminal VGH of each stage of the shift register G, and the second level signal line v2 can be electrically connected to the second level terminal VGL of each stage of the shift register G, respectively.

[0177] Figure 5 , the clock signal line k includes a first sub-clock signal line k1 and a second sub-clock signal line k2. The number of clock signal lines k can also be other, such as Figure 6 As shown, the clock signal line k includes a first clock signal line k11, a second clock signal line k21, a third clock signal line k12, and a fourth clock signal line k22; the start signal line STV includes a first start signal line STV1 and a second start signal line STV2, the first start signal line STV1 is electrically connected to the signal input terminal Vin of the first-stage shift register G1, and the second start signal line STV2 is electrically connected to the signal input terminal Vin of the second-stage shift register G2.

[0178] Optional, Figure 44 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 44 As shown, the display panel 100 also includes multiple clock signal lines; when x=y+n, the first clock terminal CK1 of the i-th stage shift register G and the first clock terminal CK1 of the i+2n-th stage shift register G are electrically connected to the same clock signal line k; and / or, the second clock terminal CK2 of the i-th stage shift register G and the second clock terminal CK2 of the i+2n-th stage shift register G are electrically connected to the same clock signal line k; i and n are both positive integers.

[0179] Specifically, by electrically connecting the first clock terminal CK1 of the i-th stage shift register G and the first clock terminal CK1 of the i+2n-th stage shift register G to the same clock signal line k, some of the shift registers G share the same clock signal line k, thereby reducing the number of clock signal lines k providing the first clock signal and improving the utilization rate of the wiring harness within the display panel 100. Accordingly, by electrically connecting the second clock terminal CK2 of the i-th stage shift register G and the second clock terminal CK2 of the i+2n-th stage shift register G to the same clock signal line k, some of the shift registers G share the same clock signal line k, thereby reducing the number of clock signal lines k providing the second clock signal and improving the utilization rate of the wiring harness within the display panel 100.

[0180] Based on the same inventive concept, embodiments of the present invention further provide a display device, comprising a display panel provided by any embodiment of the present invention. Therefore, the display device possesses the technical features of the display panel provided by any embodiment of the present invention and can achieve the beneficial effects of the display panel provided by any embodiment of the present invention. For similarities, reference can be made to the above description of the display panel provided by any embodiment of the present invention and will not be repeated here.

[0181] For example, Figure 45 A schematic structural diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 45 As shown, the display device 200 includes the display panel 100 provided in an embodiment of the present invention. The display device 200 provided in an embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0182] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit; the driving circuit includes a multi-stage shift register; The shift register includes a first control module, a second control module, an isolation control module, an output module, a signal input terminal, a first clock terminal, a second clock terminal, a first level terminal, a second level terminal, an isolation control terminal and a signal output terminal; the first control module is electrically connected to the signal input terminal, the first clock terminal and the first node respectively; the isolation control module is electrically connected to the isolation control terminal, the first node and the second node respectively; the second control module is electrically connected to the first clock terminal, the first level terminal and the third node respectively; the output module is electrically connected to the second node, the third node, the second clock terminal, the second level terminal and the signal output terminal respectively; The signal input terminal of the x-th stage shift register is electrically connected to the signal output terminal of the y-th stage shift register; x and y are both positive integers, and x≠y; Among the multiple stages of shift registers, at least some of the shift registers are first-type shift registers; In the same first-type shift register, during at least part of the time when the input signal at the signal input end is at a valid level, the isolation control signal at the isolation control end controls the isolation control module to turn on the signal transmission path between the first node and the second node; at least after the input signal jumps from a valid level to an invalid level, the isolation control signal controls the isolation control module to disconnect the signal transmission path between the first node and the second node.

2. The display panel according to claim 1, wherein: In the same shift register, the isolation control terminal is electrically connected to the signal input terminal.

3. The display panel according to claim 1, wherein: The isolation control terminal of the x-th stage shift register is electrically connected to the first node or the second node of the z-th stage shift register; z is a positive integer, and x≠z; Among them, the effective level time of the signal of the first node or the signal of the second node of the shift register at the zth level is the first time; the effective level time of the gate drive signal output from the signal output end of the shift register at the yth level is the second time; the first time overlaps with the second time.

4. The display panel according to claim 3, wherein: x=y+n, y≥n, y-n+1≤z≤y+n-1; n is a positive integer.

5. The display panel according to claim 3, wherein: The multi-stage shift register also includes a second type of shift register; In the second type shift register, the isolation control terminal is electrically connected to the first level terminal.

6. The display panel according to claim 5, wherein: The first m stages of the shift registers are the second type of shift registers; wherein m≥n.

7. The display panel according to claim 5, wherein: Also includes: A plurality of pixel circuits and a plurality of gate signal lines arranged in an array; At least part of the pixel circuits located in the same row are electrically connected to the same gate signal; Each level of the first-type shift register is electrically connected to each row of the pixel circuit via each gate signal line; The second type shift register is not electrically connected to the pixel circuit.

8. The display panel according to claim 1, wherein: The shift register further includes a reset module; In the same shift register, the reset module is electrically connected to the third node, the second level terminal, the first clock terminal and the second clock terminal respectively; The reset module is also electrically connected to the first node and / or the second node.

9. The display panel according to claim 8, wherein: The reset module includes a first reset submodule and a second reset submodule; In the same shift register: The first reset submodule is electrically connected to the third node, the second level terminal and the second clock terminal respectively; the first reset submodule is also electrically connected to the first node and / or the second node; The second reset submodule is electrically connected to the first clock terminal and the third node respectively; the second reset submodule is also electrically connected to the first node or the second node.

10. The display panel according to claim 9, wherein: The first reset submodule includes a first reset unit and a second reset unit; In the same shift register: The first reset unit is electrically connected to the second clock terminal, the second level terminal, the third node and the first node respectively; The second reset unit is electrically connected to the second clock terminal, the first level terminal and the second node respectively; The second reset unit is further electrically connected to the first reset unit at a fourth node, or the second reset unit is further electrically connected to the first node.

11. The display panel according to claim 10, wherein: The first reset unit includes a first reset transistor and a second reset transistor; In the same shift register: The gate of the first reset transistor is electrically connected to the third node, the first electrode of the first reset transistor is electrically connected to the second level end, and the second electrode of the first reset transistor and the first electrode of the second reset transistor are electrically connected to the fourth node; A gate of the second reset transistor is electrically connected to the second clock terminal, and a second electrode of the second reset transistor is electrically connected to the first node.

12. The display panel according to claim 10, wherein: The second reset unit includes a signal transmission subunit and a transmission control subunit; In the same shift register: The transmission control subunit is electrically connected to the second node and the first level end respectively; the transmission control subunit is also electrically connected to the signal transmission subunit at a fifth node; The signal transmission subunit is electrically connected to the second clock terminal and the second node respectively; the signal transmission subunit is also electrically connected to the fourth node or the first node.

13. The display panel according to claim 12, wherein: The signal transmission subunit includes a third reset transistor and a fourth reset transistor; In the same shift register, the gate of the third reset transistor and the gate of the fourth reset transistor are both electrically connected to the second clock end; the first electrode of the third reset transistor is electrically connected to the first node or the fourth node; the second electrode of the third reset transistor and the first electrode of the fourth reset transistor are electrically connected to the fifth node; and the second electrode of the fourth reset transistor is electrically connected to the second node.

14. The display panel according to claim 13, wherein: The voltage difference between the effective level of the second clock signal at the second clock terminal and the first level signal at the first level terminal is ΔV; the threshold voltage of the fourth reset transistor is Vth; Where |ΔV| <Vth。 15. The display panel according to claim 12, wherein: The transmission control subunit includes a fifth reset transistor; In the same shift register, the gate of the fifth reset transistor is electrically connected to the second node, the first electrode of the fifth reset transistor is electrically connected to the first level end, and the second electrode of the fifth reset transistor is electrically connected to the fifth node.

16. The display panel according to claim 9, wherein: The second reset submodule includes a sixth reset transistor; In the same shift register, the gate of the sixth reset transistor is electrically connected to the first node or the second node, the first electrode of the sixth reset transistor is electrically connected to the first clock terminal, and the second electrode of the sixth reset transistor is electrically connected to the third node.

17. The display panel according to claim 1, wherein: The shift register further includes a voltage stabilizing module; In the same shift register, the voltage stabilizing module is electrically connected to the first node and / or the second node.

18. The display panel according to claim 17, wherein: The voltage stabilizing module includes a first voltage stabilizing capacitor and / or a second voltage stabilizing capacitor; In the same shift register: The first plate of the first voltage-stabilizing capacitor is electrically connected to the first node, and the second plate of the first voltage-stabilizing capacitor is electrically connected to the first level end or the second level end; The first plate of the second voltage-stabilizing capacitor is electrically connected to the second node, and the second plate of the second voltage-stabilizing capacitor is electrically connected to the first level end or the second level end.

19. The display panel according to claim 1, wherein The isolation control module includes an isolation transistor; In the same shift register, the gate of the isolation transistor is electrically connected to the isolation control terminal, the first electrode of the isolation transistor is electrically connected to the first node, and the second electrode of the isolation transistor is electrically connected to the second node.

20. The display panel according to claim 1, wherein The first control module includes a first control transistor; In the same shift register, the gate of the first control transistor is electrically connected to the first clock terminal, the first electrode of the first control transistor is electrically connected to the signal input terminal, and the second electrode of the first control transistor is electrically connected to the first node.

21. The display panel according to claim 1, wherein The second control module includes a second control transistor; In the same shift register, the gate of the second control transistor is electrically connected to the first clock end, the first electrode of the second control transistor is electrically connected to the first level end, and the second electrode of the second control transistor is electrically connected to the third node.

22. The display panel according to claim 1, wherein The output module includes a first output transistor and a second output transistor; In the same shift register: The gate of the first output transistor is electrically connected to the second node, the first electrode of the first output transistor is electrically connected to the second clock terminal, and the second electrode of the first output transistor is electrically connected to the signal output terminal; A gate of the second output transistor is electrically connected to the third node, a first electrode of the second output transistor is electrically connected to the second level end, and a second electrode of the second output transistor is electrically connected to the signal output end.

23. The display panel according to claim 14, wherein: The shift register further includes a bootstrap module; In the same shift register, the bootstrap module is electrically connected between the signal output terminal and the second node.

24. The display panel according to claim 1, wherein Also includes: Multiple clock signal lines; The first clock end of the shift register at the xth level and the second clock end of the shift register at the yth level are electrically connected to the same clock signal line; and / or, the second clock end of the shift register at the xth level and the first clock end of the shift register at the yth level are electrically connected to the same clock signal line.

25. The display panel according to claim 1, wherein Also includes: Multiple clock signal lines; When x=y+n, the first clock terminal of the i-th stage shift register and the first clock terminal of the i+2n-th stage shift register are electrically connected to the same clock signal line; and / or, the second clock terminal of the i-th stage shift register and the second clock terminal of the i+2n-th stage shift register are electrically connected to the same clock signal line; Both i and n are positive integers.

26. The display panel according to claim 1, wherein Also includes: A plurality of pixel circuits and a plurality of gate signal lines arranged in an array; The pixel circuit includes at least a driving module, a writing module, a reset module and a light-emitting module; the driving module includes a driving transistor; the writing module is electrically connected to the gate of the driving transistor at a gate node; the reset module is electrically connected to the gate node, and the reset module is also electrically connected to the light-emitting module at a light-emitting reset node; The writing modules of at least some of the pixel circuits in the same row are electrically connected to the same gate signal line; Each level of the first-type shift register is electrically connected to each of the gate signal lines.

27. A display device, characterized in that: include: The display panel according to any one of claims 1 to 26.

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