Display panel and display device

Abstract

The invention discloses a display panel and a display device. A pixel circuit in the display panel comprises a driving control module and a brightness maintaining module. The driving control module comprises a driving transistor, and the driving transistor and the light-emitting element are connected in series between the first power signal end and the second power signal end. The driving transistor includes a first gate and a second gate. The brightness maintaining module comprises at least one transistor group, the transistor group comprises two transistors which are connected in series, and the output end of the transistor group and the first grid electrode are connected to a first node. The driving transistor is used for being turned on and turned off according to potential information provided by the first node to the first grid electrode. The second grid electrode is electrically connected with the series connection node of the two transistors in the transistor set, and the conduction conditions of the transistors in the brightness maintaining module are the same and are different from the conduction conditions of the driving transistors. According to the embodiment of the invention, the brightness change caused by transistor leakage current is counteracted, and the low-frequency flicker phenomenon of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As display panels become increasingly commonplace in everyday life, demand for both display quality and power consumption is increasing. Display panels include pixel circuits, which in turn include driver transistors for driving light-emitting devices. Currently, leakage current from some transistors can affect the driver transistors, thereby impacting the drive current and resulting in poor display quality. Summary of the Invention

[0003] The present invention provides a display panel and a display device to balance brightness changes caused by transistor leakage, improve low-frequency flickering of the display panel, and enhance the display effect of the display panel.

[0004] In a first aspect, the present invention provides a display panel, comprising:

[0005] Pixel circuits and light-emitting elements;

[0006] The pixel circuit includes a drive control module and a brightness maintenance module;

[0007] The drive control module includes a drive transistor, and the drive transistor and the light emitting element are connected in series between a first power signal terminal and a second power signal terminal;

[0008] The driving transistor includes a first gate and a second gate;

[0009] The brightness maintenance module includes at least one transistor group, the transistor group includes two transistors connected in series, the output end of the transistor group and the first gate are connected to a first node; the driving transistor is used to turn on and off according to the potential information provided by the first node to the first gate;

[0010] The second gate is electrically connected to a series connection node of two transistors in the transistor group;

[0011] The conduction conditions of the transistors in the brightness maintaining module are the same as those of the driving transistors.

[0012] In a second aspect, an embodiment of the present invention further provides a display device, which includes the display panel described in the first aspect.

[0013] In the technical solution of the present invention, the brightness maintenance module includes at least one transistor group, and the transistor group includes two transistors arranged in series. The output end of the transistor group is connected to the first gate of the driving transistor at a first node, and the potential information of the first node is used to control the conduction and shutdown of the driving transistor. The series node of the two transistors in the transistor group is electrically connected to the second gate of the driving transistor. When the leakage current of the transistor affects the potential information of the first node, causing the driving current of the driving transistor to increase, the potential information of the second gate is adjusted by the potential information of the series node of the two transistors in the transistor group. The potential information of the second gate affects the threshold voltage of the driving transistor. In this way, the brightness change caused by the leakage current of the transistor can be offset by adjusting the threshold voltage of the driving transistor, thereby ensuring the display uniformity of the light-emitting element and improving the low-frequency flicker phenomenon of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 2 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0016] Figure 3 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0017] Figure 4 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0018] Figure 5 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0019] Figure 6 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0020] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0021] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0022] Figure 9 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0023] Figure 10 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0024] Figure 11 is a cross-sectional schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0025] Figure 12 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described below in conjunction with the drawings in the embodiments of the present invention through specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention, which is obvious to those skilled in the art. Therefore, the present invention is intended to cover modifications and changes of the present invention that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents.

[0027] Furthermore, the words “first”, “second” and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “one”, “an” or “the” do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as “include” or “comprise” mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as “connect” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “down”, “left”, “right” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, descriptions such as “same” and “equal” involved in the embodiments of the present disclosure do not mean that the two objects are exactly the same in size or shape. Approximately the same or approximately equal within a certain error range is allowed.

[0028] Figure 1 Schematic diagram of a pixel circuit according to an embodiment of the present invention. Figure 1The display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a driving control module 110 and a brightness maintenance module 120. The driving control module 110 includes a driving transistor M1, and the driving transistor M1 and the light-emitting element 20 are connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE. The driving transistor M1 includes a first gate Q1 and a second gate Q2. The brightness maintenance module 120 includes at least one transistor group 121, and the transistor group 121 includes two transistors arranged in series. The output end of the transistor group 121 and the first gate Q1 are connected to the first node N1. The driving transistor M1 is used to turn on and off according to the potential information provided to the first gate Q1 by the first node N1. The second gate Q2 is electrically connected to the series node N2 of the two transistors in the transistor group 121. The conduction conditions of the transistors in the brightness maintenance module 120 are the same and different from the conduction conditions of the driving transistor M1.

[0029] It can be understood that the first power signal terminal PVDD is used to provide a positive power signal, and the voltage of the positive power signal can be greater than 0V. For example, the voltage range of the positive power signal can be between 5V and 15V; the second power signal terminal PVEE is used to provide a negative power signal, and the voltage of the negative power signal can be less than or equal to 0V. For example, the voltage range of the negative power signal can be between -3V and 0V.

[0030] The pixel circuit 10 includes a drive control module 110, which is electrically connected to the light-emitting element 20 to provide a drive signal to the light-emitting element 20 through the drive control module 110, thereby driving the light-emitting element 20 to emit light. The light-emitting element 20 may include a current-type light-emitting element, which may include an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), or a sub-millimeter light-emitting diode (Mini LED). The specific design can be based on actual needs and is not specifically limited in the embodiment of the present invention. In addition, the drive control module 20 may include a drive transistor M1, which can generate a drive current based on the data voltage signal it receives. At the same time, because the drive transistor M1 and the light-emitting element 20 are electrically connected between the first power signal terminal PVDD and the second power signal terminal PVEE, when the drive transistor M1 is in the on state, a current path can be formed between the first power signal terminal PVDD and the second power signal terminal PVEE, so that the drive current can flow through the light-emitting element 20, driving the light-emitting element 20 to emit light.

[0031] The driving transistor M1 includes a first gate Q1, which serves as a control terminal for the driving transistor M1. That is, the driving transistor M1 is turned on or off based on the potential information of the first gate Q1. For example, when the driving transistor M1 is an N-type transistor, the first gate Q1 of the driving transistor M1 is turned on when a high level is applied, and is turned off when a low level is applied. When the driving transistor M1 is a P-type transistor, the first gate Q1 of the driving transistor M1 is turned on when a low level is applied, and is turned off when a high level is applied. In addition, the degree of conduction of the driving transistor M1 is related to the voltage difference between the first gate Q1 and the source of the driving transistor M1, wherein the greater the degree of conduction of the driving transistor M1, the greater the driving current generated. When leakage current occurs in the transistor coupled to the first gate Q1 of the driving transistor M1, it will affect the potential of the first gate Q1, that is, the voltage difference between the first gate Q1 and the source of the driving transistor M1 changes. At this time, the driving current of the driving transistor M1 is likely to increase, causing the brightness of the light-emitting element 20 to gradually increase. At a low refresh rate, the accumulated difference in brightness increase is large, which will cause the display panel to exhibit low-frequency flickering, affecting the display effect of the display panel.

[0032] To this end, the pixel circuit 10 of the embodiment of the present invention further includes a brightness maintenance module 120. The brightness maintenance module 120 includes at least one transistor group 121. The output end of the transistor group 121 is connected to the first gate Q1 of the driving transistor M1 at a first node N1. The transistor group 121 includes two transistors arranged in series. The driving transistor M1 also includes a second gate Q2, which is electrically connected to the series connection node N2 of the two transistors in the transistor group 121. The potential information of the series connection node N2 can adjust the potential information of the second gate Q2. The threshold voltage of the driving transistor M1 is affected by the voltage difference between the second gate Q2 and the source. The greater the voltage difference between the second gate Q2 and the source, the more negative the threshold voltage of the driving transistor M1. The smaller the voltage difference between the second gate Q2 and the source, the more positive the threshold voltage of the driving transistor M1. When the voltage difference between the second gate Q2 and the source remains unchanged, the threshold voltage of the driving transistor M1 remains unchanged. In addition, since the conduction condition of the transistor in the brightness maintenance module 120 is different from the conduction condition of the driving transistor M1, the potential change of the second gate Q2 can positively regulate the potential change of the first gate Q1 caused by the leakage current, that is, by adjusting the threshold voltage of the driving transistor M1, the potential change of the first gate Q1 of the driving transistor M1 can be balanced, thereby offsetting the brightness increase of the driving transistor M1 caused by the leakage current, thereby improving the display effect of the display panel.

[0033] It should be noted that the embodiment of the present invention does not limit the specific types of transistors in the brightness maintenance module 120 and the driving transistor M1. It only needs to ensure that the conduction conditions of the transistors in the brightness maintenance module 120 are different from the conduction conditions of the driving transistor M1. Those skilled in the art can set them as needed.

[0034] In summary, in an embodiment of the present invention, the pixel circuit includes a brightness maintenance module, which includes at least one transistor group, the output end of the transistor group is connected to the first gate of the driving transistor and the first node, wherein the potential information of the first node is used to control the driving transistor to be turned on and off, the transistor group includes two transistors arranged in series, the driving transistor also includes a second gate, the second gate is electrically connected to the series node of the two transistors in the transistor group, and the series node is used to adjust the potential information of the second gate, wherein the voltage difference between the second gate and the source in the driving transistor affects the threshold voltage of the driving transistor. In this way, when the potential of the first gate changes due to leakage current, the conduction condition of the transistor in the brightness maintenance module is set to be different from the conduction condition of the driving transistor, and the series node is electrically connected to the second gate, and then the threshold voltage of the driving transistor is adjusted to balance the potential change of the first gate of the driving transistor, thereby offsetting the brightness increase caused by the leakage current of the driving transistor, thereby improving the display effect of the display panel.

[0035] Optionally, based on the above embodiment, continue to refer to Figure 1 , the transistors in the brightness maintaining module 120 are all N-type transistors, and the driving transistor M1 is a P-type transistor.

[0036] Specifically, such as Figure 1As shown, all transistors in the transistor group 121 are N-type transistors. N-type transistors are turned off at a low level and turned on at a high level. When the transistor group 121 is turned off, the potential information of the control terminal of the transistor group 121 is low, which will pull down the potential information of the first node N1. The driving transistor M1 is a P-type transistor, and the conduction condition of the P-type transistor is Vgs≤Vth. Among them, Vgs is the voltage difference between the first gate Q1 and the source of the driving transistor M1, Vth is the threshold voltage of the driving transistor M1, and the Vth of the P-type transistor is a negative value. Therefore, the more negative Vgs is, the greater the degree of conduction of the driving transistor M1 is, and the greater the drive current is. Furthermore, when the potential information of the first node N1 is pulled low, the Vgs of the driving transistor M1 becomes more negative, and the driving current generated by the driving transistor M1 is larger. Therefore, the series node N2 is electrically connected to the second gate Q2. After the transistor group 121 is turned off, the leakage current of the input end of the transistor group 121 and the first node N1 will flow to the series node N2, so that the potential of the series node N2 is pulled high, that is, the voltage of the second gate Q2 increases. At this time, the voltage difference between the second gate Q2 and the source of the driving transistor M1 becomes larger, and the threshold voltage Vth of the driving transistor M1 becomes negative. In other words, the absolute value of the threshold voltage Vth becomes larger, so that the conduction degree of the driving transistor M1 becomes smaller, thereby balancing the decrease in the potential of the first gate Q1 of the driving transistor M1, thereby offsetting the brightness increase of the driving transistor M1 caused by the leakage current, thereby improving the display effect of the display panel.

[0037] Optionally, based on the above embodiment, Figure 2 This is a schematic diagram of another pixel circuit provided by the present invention. Figure 2 The brightness maintenance module 121 includes a first transistor group 121a, which includes a first initialization transistor M2 and a second initialization transistor M3. A first electrode of the first initialization transistor M2 is electrically connected to the first reference signal terminal Vref1, a second electrode of the first initialization transistor M2 and a first electrode of the second initialization transistor M3 are electrically connected to a first series node N21, a second electrode of the second initialization transistor M3 is electrically connected to the first node N1, and the first series node N21 is electrically connected to the second gate Q2.

[0038] Specifically, such as Figure 2As shown, the brightness maintenance module 120 includes a first transistor group 121a. The first transistor group 121a includes a first initialization transistor M2 and a second initialization transistor M3. The first terminal of the first initialization transistor M2 is electrically connected to the first reference signal terminal Vref1, the second terminal of the second initialization transistor M3 is electrically connected to the first node N1, and the control terminals of the first initialization transistor M2 and the second initialization transistor M3 are electrically connected to the first scan signal terminal S1N. During the initialization phase, the first scan signal terminal S1N provides a first scan signal, and the first scan signal is at an active level (high level). The first initialization transistor M2 and the second initialization transistor M3 are turned on, and the reference signal provided by the first reference signal terminal Vref1 is written to the first node N1 to initialize the first gate Q1 of the driving transistor M1. After the initialization phase is completed, the first scan signal is at an invalid level (low level), and the first initialization transistor M2 and the second initialization transistor M3 are turned off. When turned off, affected by the coupling of the first scan signal terminal S1N, the low-level first scan signal will pull down the first node N1, and then by setting the first series node N21 to be electrically connected to the second gate Q2, the voltage of the second gate Q2 is pulled up through the first series node N21, so that the threshold voltage Vth of the driving transistor M1 is biased to negative, to balance the potential reduction of the first gate Q1 of the driving transistor M1, thereby offsetting the brightness increase of the driving transistor M1 caused by the leakage current of the first transistor group 121a, improving the low-frequency flicker phenomenon of the display panel, and enhancing the display effect of the display panel.

[0039] Optionally, based on the above embodiment, Figure 3 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 3 The pixel circuit 10 further includes a threshold compensation module 130. The threshold compensation module 130 includes a first transistor M4, a first electrode of the first transistor M4 is electrically connected to the second electrode of the driving transistor M1, and a second electrode of the first transistor M4 is electrically connected to the first node N1.

[0040] For example, Figure 3In the illustrated embodiment, the pixel circuit further includes a threshold compensation module 130, which includes a first transistor M4. A first electrode of the first transistor M4 is electrically connected to the second electrode of the driving transistor M1, a second electrode of the first transistor M4 is electrically connected to the first gate Q1 of the driving transistor M1, and a gate of the first transistor M4 is electrically connected to the second scan signal terminal S2N. The first transistor M4 is configured to compensate for the voltage of the first gate Q1 of the driving transistor M1 under the control of a second scan signal provided by the second scan signal terminal S2N. Furthermore, the pixel circuit further includes a first emission control transistor M5, a second emission control transistor M6, a data write transistor M7, and a reset transistor M8. The first emission control transistor M5 is electrically connected between the first power signal terminal PVDD and the driving transistor M1, and the second emission control transistor M6 is electrically connected between the driving transistor M1 and the second power signal terminal PVEE. The gates of the first emission control transistor M5 and the second emission control transistor M6 are both electrically connected to the emission control terminal EM. The emission control signal provided by the emission control terminal EM controls the conduction or discontinuity of the first emission control transistor M5 and the second emission control transistor M6. The second emission control transistor M6, the driving transistor M1, the first emission control transistor M5, and the light-emitting element 20 are sequentially connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE, so that the driving current provided by the driving transistor M1 can be supplied to the light-emitting element 20 only when both the second emission control transistor M3 and the first emission control transistor M3 are turned on, causing the light-emitting element 20 to emit light. A first electrode of the data write transistor M7 is electrically connected to the data signal terminal Vdata, a second electrode of the data write transistor M7 is electrically connected to the first electrode of the driving transistor M1, and a gate of the data write transistor M7 is electrically connected to the third scan signal terminal S3N. The data write transistor M7 is used to write a data signal during the data write phase. A gate of the reset transistor M8 is electrically connected to the fourth scan signal terminal S4N, a first electrode of the reset transistor M8 is electrically connected to the second reference signal terminal Vref2, and a second electrode of the reset transistor M8 is electrically connected to the light-emitting element 20, for resetting the light-emitting element 20 to prevent the previous frame's light emission from affecting the current frame's light emission.

[0041] It should be noted that Figure 3 The first initialization transistor M2, the second initialization transistor M3 and the first transistor M4 are N-type transistors, and the first light-emitting control transistor M5, the second light-emitting control transistor M6, the driving transistor M1, the data writing transistor M7 and the reset transistor M8 are P-type transistors. However, this is not limiting and those skilled in the art can set it as needed.

[0042] Optional, Figure 4is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 4 The brightness maintenance module 120 includes a second transistor group 121b, which includes a first threshold compensation transistor M9 and a second threshold compensation transistor M10. The first electrode of the first threshold compensation transistor M9 is electrically connected to the second electrode of the driving transistor M1. The second electrode of the first threshold compensation transistor M9 and the first electrode of the second threshold compensation transistor M10 are connected to a second series node N22. The second electrode of the second threshold compensation transistor M10 is electrically connected to the first node N1. The second series node N22 is electrically connected to the second gate Q2.

[0043] Specifically, such as Figure 4 In the illustrated embodiment, a first electrode of the first threshold compensation transistor M9 is electrically connected to the second electrode of the driving transistor M1, a second electrode of the first threshold compensation transistor M9 is electrically connected to the first electrode of the second threshold compensation transistor M10, a second electrode of the second threshold compensation transistor M10 is electrically connected to the first node N1, and gate electrodes of the first threshold compensation transistor M9 and the second threshold compensation transistor M10 are both electrically connected to the second scan signal terminal S2N. The first and second threshold compensation transistors M9 and M10 are configured to compensate for the voltage of the first gate electrode Q1 of the driving transistor M1 under the control of the second scan signal provided by the second scan signal terminal S2N. Exemplarily, in the threshold compensation stage, the second scanning signal provided by the second scanning signal terminal S2N is at a valid level (high level), the first threshold compensation transistor M9 and the second threshold compensation transistor M10 are turned on, and the threshold compensation is completed. After the threshold compensation stage, the second scanning signal is at an invalid level (low level), and the first threshold compensation transistor M9 and the second threshold compensation transistor M10 are turned off. When turned off, affected by the coupling of the second scanning signal terminal S2N, the low-level second scanning signal will pull down the first node N1, and then by setting the second series node N22 to be electrically connected to the second gate Q2, the voltage of the second gate Q2 is pulled up through the second series node N22, so that the threshold voltage Vth of the driving transistor M1 is biased to negative, to balance the potential reduction of the first gate Q1 of the driving transistor M1, thereby offsetting the brightness increase of the driving transistor M1 caused by the leakage current of the second transistor group 121b, improving the low-frequency flicker phenomenon of the display panel, and enhancing the display effect of the display panel.

[0044] It should be noted that if Figure 4 As shown, when the brightness maintenance module 120 only includes the second transistor group 121b, the pixel circuit also includes a second transistor M11, a first end of the second transistor M11 is electrically connected to the first reference signal terminal Vref1, a second end of the second transistor M11 is electrically connected to the first node N1, and a gate of the second transistor M11 is electrically connected to the first scan signal terminal S1N.

[0045] Optionally, in yet another embodiment, Figure 5 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 5 The brightness maintenance module 120 includes a first transistor group 121a and a second transistor group 121b. The first transistor group 121a includes a first initialization transistor M2 and a second initialization transistor M3. The first electrode of the first initialization transistor M2 is electrically connected to the first reference signal terminal Vref1, the second electrode of the first initialization transistor M2 and the first electrode of the second initialization transistor M3 are electrically connected to the first series node N21, and the second electrode of the second initialization transistor M3 is electrically connected to the first node N1. The second transistor group 121b includes a first threshold compensation transistor M9 and a second threshold compensation transistor M10. The first electrode of the first threshold compensation transistor M9 is electrically connected to the second electrode of the driving transistor M1, the second electrode of the first threshold compensation transistor M9 and the first electrode of the second threshold compensation transistor M10 are electrically connected to the second series node N22, and the second electrode of the second threshold compensation transistor M10 is electrically connected to the first node N1. The first series node N21 and the second series node N22 are both electrically connected to the second gate Q2.

[0046] Specifically, during the initialization phase, the first scan signal terminal S1N provides a first scan signal, and the first scan signal is at an active level (high), turning on the first initialization transistor M2 and the second initialization transistor M3. The reference signal provided by the first reference signal terminal Vref1 is written to the first node N1 to initialize the first gate Q1 of the drive transistor M1. After the initialization phase is completed, the first scan signal is at an inactive level (low), turning off the first initialization transistor M2 and the second initialization transistor M3. During the off-state phase, the low-level first scan signal pulls down the first node N1 due to coupling with the first scan signal terminal S1N. Similarly, during the threshold compensation phase, the second scan signal terminal S2N provides a second scan signal at an active level (high), turning on the first threshold compensation transistor M9 and the second threshold compensation transistor M10, completing threshold compensation. After the threshold compensation phase, the second scan signal is at an inactive level (low), turning off the first threshold compensation transistor M9 and the second threshold compensation transistor M10. During the off-state phase, the low-level second scan signal also pulls down the first node N1 due to coupling with the second scan signal terminal S2N. To this end, the first series node N21 and the second series node N22 are both electrically connected to the second gate Q2, so that the voltage of the second gate Q2 is pulled up through the first series node N21 and the second series node N22, so that the threshold voltage Vth of the driving transistor M1 is biased to negative, so as to balance the potential reduction of the first gate Q1 of the driving transistor M1, thereby offsetting the brightness increase of the driving transistor M1 caused by the leakage current of the first transistor group 121a and the second transistor group 121b, improving the low-frequency flicker phenomenon of the display panel, and enhancing the display effect of the display panel.

[0047] Optionally, based on the above embodiment, Figure 6 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Figure 3 and Figure 6 The scanning phase of the display panel includes a first scanning phase S1 and a second scanning phase S2. The first scanning phase S1 includes an initialization phase S11 and a threshold compensation phase S12. In the initialization phase S11, the first initialization transistor M2 and the second initialization transistor M3 are turned on to initialize the first node N1. In the threshold compensation phase S12, the first transistor M4 is turned on to perform threshold compensation on the first node N1. In the second scanning phase S2, the first initialization transistor M2, the second initialization transistor M3, and the first transistor M4 remain turned off.

[0048] Specifically, the display panel includes a low-frequency phase and a high-frequency phase, wherein the refresh frequency of the light-emitting element 20 in the low-frequency phase is lower than the refresh frequency of the light-emitting element 20 in the high-frequency phase. Figure 6 For example, the display panel is in the low frequency stage. Figure 6The scanning phase of the display panel includes a first scanning phase S1 and a second scanning phase S2. The first scanning phase S1 includes an initialization phase S11, a threshold compensation phase S12, and a light-emitting phase S13. The first initialization transistor M2, the second initialization transistor M3, and the first transistor M4 are N-type transistors, while the first light-emitting control transistor M5, the second light-emitting control transistor M6, the drive transistor M1, the data writing transistor M7, and the reset transistor M8 are P-type transistors. In the initialization phase S11, the first scanning signal terminal S1N provides a first scanning signal, and the first scanning signal is high. The first initialization transistor M2 and the second initialization transistor M3 are turned on, and the reference signal provided by the first reference signal terminal Vref1 is written to the first node N1 to initialize the first gate Q1 of the drive transistor M1. In the threshold compensation phase S12, the first scanning signal is low, turning off the first initialization transistor M2 and the second initialization transistor M3. When turned off, due to the coupling effect of the first scanning signal terminal S1N, the low-level first scanning signal pulls down the first node N1. Furthermore, the second scan signal terminal S2N provides a high-level second scan signal, turning on the first transistor M4 to complete threshold compensation of the first node N1. The third scan signal terminal S3N provides a low-level signal to turn on the data write transistor M7, completing data writing. Furthermore, during the initialization phase S11 and the threshold compensation phase S12, the emission control terminal EM provides a high-level signal, turning off the first and second emission control transistors M5 and M6, and preventing the light-emitting element 20 from emitting light. During the light-emitting phase S13, the emission control terminal EM provides a low-level signal, causing the light-emitting element 20 to emit light. The second scan phase S2 can be a sustain phase. During the second scan phase, the first scan signal terminal S1N, the second scan signal terminal S2N, and the third scan signal terminal S3N all provide inactive levels. During the sustain phase, the leakage current of the first node N1 and the leakage current of the first reference signal terminal Vref1 pull up the first series node N21, thereby raising the potential of the second gate Q2.

[0049] Optionally, based on the above embodiment, continue to refer to Figure 3 and Figure 6The gates of the first initialization transistor M2 and the second initialization transistor M3 are both electrically connected to the first scan signal terminal S1N. The gate of the first transistor M4 is electrically connected to the second scan signal terminal S2N. Specifically, the gates of the first initialization transistor M2 and the second initialization transistor M3 are controlled by the same scan signal terminal S1N. In this way, during the entire phase, the first initialization transistor M2 and the second initialization transistor M3 are simultaneously turned on or turned off. Based on the potential information of the second gate Q2 being adjusted via the first series node N21, the first initialization transistor M2 and the second initialization transistor M3 are ensured to initialize the first gate Q1 during the initialization phase S21, thereby ensuring the normal operation of the pixel circuit.

[0050] Optionally, based on the above embodiment, Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 7 , the gate of the first initialization transistor M2 is electrically connected to the first scan signal terminal S1N, and the gate of the second initialization transistor M3 and the gate of the first transistor M4 are both electrically connected to the second scan signal terminal S2N. That is, the first scan signal provided by the first scan signal terminal S1N controls the conduction and shutdown of the first initialization transistor M2, and the second scan signal provided by the second scan signal terminal S2N controls the conduction and shutdown of the second transistor M3 and the first transistor M4, so that the first initialization transistor M2 and the second initialization transistor M3 initialize the first node N1 in the initialization phase S11, and the first transistor M4 completes the threshold compensation of the first node N1 in the threshold compensation phase S12, ensuring the normal operation of the pixel circuit. In addition, Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 8 The gate of the second initialization transistor M3 is electrically connected to the first scan signal terminal S1N, and the gates of the first initialization transistor M2 and the first transistor M4 are both electrically connected to the second scan signal terminal S2N. That is, the first scan signal provided by the first scan signal terminal S1N controls the conduction and shutdown of the second initialization transistor M3, and the second scan signal provided by the second scan signal terminal S2N controls the conduction and shutdown of the first initialization transistor M2 and the first transistor M4. As a result, the first initialization transistor M2 and the second initialization transistor M3 initialize the first node N1 in the initialization phase S11, and the first transistor M4 completes the threshold compensation for the first node N1 in the threshold compensation phase S12, thereby ensuring normal operation of the pixel circuit.

[0051] It is understandable that Figure 9 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention. Figure 9In the first scanning phase S1, the effective level time of the scanning signal provided by the first scanning signal terminal S1N overlaps with the effective level time of the scanning signal provided by the second scanning signal terminal S2N. Figure 9 In the illustrated embodiment, an example is given in which the gate of the first initialization transistor M2 is electrically connected to the first scan signal terminal S1N, and the gate of the second initialization transistor M3 and the gate of the first transistor M4 are both electrically connected to the second scan signal terminal S2N. The first initialization transistor M2 and the second initialization transistor M3 can be turned on simultaneously only when the effective level time of the scan signal provided by the first scan signal terminal S1N overlaps with the effective level time of the scan signal provided by the second scan signal terminal S2N, so that the reference signal provided by the first reference signal terminal Vref can be written to the first node N1, thereby completing the initialization.

[0052] Optionally, based on the above embodiment, Figure 10 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 10 The pixel circuit 10 further includes a first reset module 140. The first reset module 140 includes a first reset transistor M12. A first electrode of the first reset transistor M12 is electrically connected to the first reset signal terminal DVH, a second electrode of the first reset transistor M12 is electrically connected to the first electrode of the drive transistor M1, and a control terminal of the first reset transistor M12 is electrically connected to the fourth scan signal terminal S4N. Specifically, when the scan signal provided by the fourth scan signal terminal S4N is at an active level, the reset signal provided by the first reset signal terminal DVH is written into the drive transistor M1 to reset the drive transistor M1.

[0053] Optional, see Figure 10 The pixel circuit 10 further includes a first capacitor C1, a first plate of which is electrically connected to the first power signal terminal PVDD. A second plate of the first capacitor C1 is electrically connected to the first series node N21. The first capacitor C1 stabilizes the potential of the first series node N21, preventing the first series node N21 from being coupled too low and causing the first initialization transistor M2 and the second initialization transistor M3 to fail in the off state.

[0054] Optional, Figure 11 is a cross-sectional schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 and Figure 11The display panel further includes a substrate 100, with the second gate Q2 located on a side of the first gate Q1 closer to the substrate 100. Specifically, the first gate Q1 serves as the top gate of the drive transistor M1, and the second gate Q2 serves as the bottom gate of the drive transistor M1. Furthermore, a source D and a drain S are provided on the same layer between the first gate Q1 and the second gate Q2. Consequently, when the potential of the first node N1 changes, the voltage difference Vgs between the first gate Q1 and the source S of the drive transistor M1 changes. This, in turn, adjusts the potential of the second gate Q2 via the first series node N21, thereby adjusting the threshold voltage Vth of the drive transistor M1 and offsetting brightness changes caused by transistor leakage.

[0055] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 12 Schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 12 As shown, the display device includes the display panel 01 in the above embodiment. The display device includes the display panel 01 of any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel 01 provided by the embodiment of the present invention, which will not be described in detail here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and an in-vehicle display device, which is not limited in the embodiment of the present invention.

[0056] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: Pixel circuits and light-emitting elements; The pixel circuit includes a drive control module and a brightness maintenance module; The drive control module includes a drive transistor, and the drive transistor and the light emitting element are connected in series between a first power signal terminal and a second power signal terminal; The driving transistor includes a first gate and a second gate; The brightness maintenance module includes at least one transistor group, the transistor group includes two transistors connected in series, the output end of the transistor group and the first gate are connected to a first node; the driving transistor is used to be turned on and off according to the potential information provided by the first node to the first gate; The second gate is electrically connected to a series connection node of two transistors in the transistor group; The conduction conditions of the transistors in the brightness maintaining module are the same as those of the driving transistors.

2. The display panel according to claim 1, wherein: The transistors in the brightness maintaining module are all N-type transistors, and the driving transistor is a P-type transistor.

3. The display panel according to claim 2, wherein: The brightness maintenance module includes a first transistor group, and the first transistor group includes a first initialization transistor and a second initialization transistor; A first electrode of the first initialization transistor is electrically connected to a first reference signal terminal, a second electrode of the first initialization transistor and a first electrode of the second initialization transistor are electrically connected to a first series node, and a second electrode of the second initialization transistor is electrically connected to the first node; The first series node is electrically connected to the second gate.

4. The display panel according to claim 3, wherein: The pixel circuit further includes a threshold compensation module; The threshold compensation module includes a first transistor, a first electrode of the first transistor is electrically connected to a second electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the first node.

5. The display panel according to claim 2, wherein: The brightness maintenance module includes a second transistor group, and the second transistor group includes a first threshold compensation transistor and a second threshold compensation transistor; The first electrode of the first threshold compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the first threshold compensation transistor and the first electrode of the second threshold compensation transistor are connected to a second series node, and the second electrode of the second threshold compensation transistor is electrically connected to the first node; The second series node is electrically connected to the second gate.

6. The display panel according to claim 2, wherein: The brightness maintenance module includes a first transistor group and a second transistor group; The first transistor group includes a first initialization transistor and a second initialization transistor; A first electrode of the first initialization transistor is electrically connected to a first reference signal terminal, a second electrode of the first initialization transistor and a first electrode of the second initialization transistor are electrically connected to a first series node, and a second electrode of the second initialization transistor is electrically connected to the first node; The second transistor group includes a first threshold compensation transistor and a second threshold compensation transistor; The first electrode of the first threshold compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the first threshold compensation transistor and the first electrode of the second threshold compensation transistor are connected to a second series node, and the second electrode of the second threshold compensation transistor is electrically connected to the first node; The first series node and the second series node are both electrically connected to the second gate.

7. The display panel according to claim 4, wherein: Also includes: The scanning phase of the display panel includes a first scanning phase and a second scanning phase; The first scanning phase includes an initialization phase and a threshold compensation phase; In the initialization phase, the first initialization transistor and the second initialization transistor are turned on to initialize the first node; In the threshold compensation stage, the first transistor is turned on to perform threshold compensation on the first node; During the second scanning phase, the first initialization transistor, the second initialization transistor, and the first transistor remain turned off.

8. The display panel according to claim 7, wherein: The gates of the first initialization transistor and the second initialization transistor are both electrically connected to the first scan signal terminal; The gate of the first transistor is electrically connected to the second scan signal terminal.

9. The display panel according to claim 7, wherein: The gate of the first initialization transistor is electrically connected to the first scan signal terminal, and the gate of the second initialization transistor and the gate of the first transistor are both electrically connected to the second scan signal terminal; Alternatively, the gate of the second initialization transistor is electrically connected to the first scan signal terminal, and the gates of the first initialization transistor and the first transistor are both electrically connected to the second scan signal terminal.

10. The display panel according to claim 9, wherein: In the first scanning phase, the effective level time of the scanning signal provided by the first scanning signal terminal overlaps with the effective level time of the scanning signal provided by the second scanning signal terminal.

11. The display panel according to claim 3, wherein The pixel circuit further includes a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first power signal terminal; The second plate of the first capacitor is electrically connected to the first series node.

12. The display panel according to claim 1, wherein The pixel circuit further includes a first reset module; The first reset module includes a first reset transistor; The first electrode of the first reset transistor is electrically connected to the first reset signal terminal, the second electrode of the first reset transistor is electrically connected to the first electrode of the driving transistor, and the control terminal of the first reset transistor is electrically connected to the fourth scan signal terminal.

13. The display panel according to claim 1, wherein The display panel further includes a substrate; The second gate is located on a side of the first gate close to the substrate.

14. A display device, characterized in that: include: The display panel according to claims 1-13.

Images