Electronic paper driving device and method

Abstract

The invention relates to the technical field of display, and discloses an electronic paper driving device and method, and the device comprises a panel module which comprises a thin film transistor substrate and a color film substrate, a cholesteric liquid crystal layer is clamped between the thin film transistor substrate and the color film substrate, the color film substrate is provided with an alternating-current common stage, and the alternating-current common stage is provided with a liquid crystal layer; the alternating current common stage is divided into 2N independent blocks, the polarities of the adjacent independent blocks are opposite, and N is a positive integer; the N parallel thin film transistor sets are arranged between the adjacent independent blocks, each parallel thin film transistor set is formed by connecting m thin film transistor units in parallel, and m is larger than or equal to 1000; and the driving control module comprises a time schedule controller and a gate driving circuit. According to the device and the method, through block driving design, parallel thin film transistor group charge hedging and dynamic voltage adjustment, the problem of non-uniform current distribution in the electronic paper driving process is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an electronic paper driving device and method. Background Art

[0002] Cholesteric liquid crystal (ChLC) is widely used in electronic paper display technology due to its bistability. Common states include: the H state (homeotropic alignment), in which the liquid crystal molecules align perpendicular to the substrate, resulting in transparency; the P state (planar), in which the liquid crystal molecules align parallel to the substrate, forming a helical structure with selective reflection; and the FC state (focal conic), a transitional state between the H and P states.

[0003] like Figure 1 As shown in the figure, the schematic diagram of the cholesteric electronic paper module structure, the overall panel includes a thin film transistor substrate and a color filter substrate, wherein the driving requires the use of an AC common voltage on the color filter substrate. During the image refresh process, the AC common voltage will alternately charge and discharge the panel with three voltages: positive common voltage -0V and negative common voltage -0V. The AC common voltage is routed through the binding pins of the X-PCB board to the COF / FPC and then to the binding pins on the thin film transistor substrate. When it enters the color filter substrate side, the voltage charged by the pixel electrode of the thin film transistor substrate forms an electric field to control the state of the cholesteric liquid crystal layer sandwiched between them (H state / P state / FC state). Figure 2 As shown in the figure, the AC common lines are routed on both sides, avoiding the source and gate lines that intersperse in the middle; but as the panel becomes larger, the secondary charge and discharge current will reach a higher level, causing device damage. Figure 3 and Figure 4 As shown in the figure, this is a conventional AC common-level design. The AC common levels of all the traces on both sides are directly short-circuited together in the X PCB board. This results in differences in the charge and discharge currents of each trace, such as Figure 5 The AC common-level trace shown has the smallest resistance on both sides and the largest resistance in the middle. This difference will cause the current on both sides to be the largest, as shown in Figure 6 As shown, the current of P1 / P6 is about 5A, that of P2 / 5 is about 2.5A, and that of P3 / 4 is less than 1A. This difference will cause the binding area of P1 / P6 to burn out due to the high current. After burning out, these two paths will be disconnected, and the high current will continue to flow through P2 / 5, burning out P2 / 5, and then burning out P3 / 4 in turn, causing the screen to not display normally.

[0004] In existing drive solutions, AC common-voltage switching utilizes a full-surface, same-polarity switching design, transmitting charge and discharge currents to the panel via the PCB. However, as panel size increases, the uneven distribution of AC common-voltage trace resistance leads to significant differences in charge and discharge currents, with the highest currents (e.g., 5A) flowing along the sides and the lowest currents (e.g., 1A) flowing along the center. This current differential can cause binding pins (e.g., P1 / P6) to overheat and burn out, triggering cascade failures and ultimately rendering the screen inoperable. Furthermore, current overload issues are exacerbated in high-temperature environments, further reducing product reliability. Summary of the Invention

[0005] In order to solve the technical problems existing in the background technology, the present invention provides an electronic paper driving device and method.

[0006] The present invention provides an electronic paper driving device, comprising:

[0007] A panel module includes a thin film transistor substrate and a color filter substrate, wherein a cholesteric liquid crystal layer is sandwiched between the thin film transistor substrate and the color filter substrate, and an AC common voltage is provided on the color filter substrate. The AC common voltage is divided into 2N independent blocks, and adjacent independent blocks have opposite polarities, where N is a positive integer;

[0008] N parallel thin film transistor groups are arranged between adjacent independent blocks, each parallel thin film transistor group is composed of m thin film transistor units connected in parallel, where m ≥ 1000;

[0009] A drive control module includes a timing controller and a gate drive circuit; the timing controller is configured to output a high-impedance signal during a polarity switching phase, the high-impedance signal being used to disconnect an external power input during the polarity switching phase and synchronously turn on the gate voltages of N parallel thin-film transistor groups; the gate drive circuit is connected to the gates of the parallel thin-film transistor groups and is used to dynamically adjust the gate voltages of the parallel thin-film transistor groups based on real-time current distribution data.

[0010] Preferably, it also includes:

[0011] The current monitoring module is embedded in the wiring of each independent block of the AC common level and includes a current sensor and a data feedback unit; the current sensor monitors the charging and discharging current of each independent block in real time and transmits the current distribution data to the drive control module through the data feedback unit.

[0012] Preferably, the source and drain of the thin film transistor unit are connected in series with an impedance through a winding layout, and the m thin film transistor units correspond one to one to the m impedances.

[0013] Preferably, the layout density of the parallel thin film transistor groups is dynamically adjusted according to the block area to ensure that no less than 50 groups of thin film transistor units are covered per square centimeter.

[0014] Preferably, the drive control module further includes:

[0015] The temperature compensation unit is used to automatically reduce the gate voltage to 10V when the panel temperature is detected to be ≥85°C, so as to suppress the hot carrier effect of the thin film transistor unit.

[0016] Preferably, the source and drain of the thin film transistor unit are arranged in a serpentine pattern, with a total length of ≥500 μm.

[0017] The present invention provides an electronic paper driving method, which is applied to any of the electronic paper driving devices described above, and includes:

[0018] During the polarity switching phase, the drive control module outputs a high-impedance signal to disconnect the external power input and synchronously turns on N parallel thin-film transistor groups;

[0019] Acquire current distribution data and dynamically adjust the gate voltages of the N parallel thin-film transistor groups based on the current distribution data, wherein the current distribution data includes real-time charge and discharge current values of each independent block;

[0020] When the real-time charge and discharge current value of any independent block exceeds a first threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is increased to a first voltage value; when the real-time charge and discharge current value of any independent block is less than a second threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is reduced to a second voltage value, wherein the first threshold is greater than the second threshold, and the first voltage value is greater than the second voltage value;

[0021] By turning on the thin film transistor group, the positive and negative charges of adjacent independent blocks are offset to achieve charge neutralization.

[0022] Preferably, it also includes:

[0023] When the hedging operation between 2N independent blocks is completed, the drive control module resumes external power input and enters the next image refresh cycle.

[0024] Preferably, the completion of the hedging operation is determined by the external current falling below a third threshold, the voltage difference between the independent blocks approaching zero, and the timing control reaching a preset time.

[0025] Preferably, the preset duration is 10 .

[0026] The electronic paper drive device and method proposed in the present invention employs a drive control module that outputs a high-impedance signal during the polarity switching phase to disconnect the external power input and synchronously turns on N parallel thin-film transistor groups. Current distribution data is obtained, and the gate voltages of the N parallel thin-film transistor groups are dynamically adjusted based on the current distribution data. The current distribution data includes the real-time charge and discharge current values of each independent block. When the real-time charge and discharge current value of any independent block exceeds a first threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is increased to a first voltage value. When the real-time charge and discharge current value of any independent block is less than a second threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is decreased to a second voltage value, wherein the first threshold is greater than the second threshold, and the first voltage value is greater than the second voltage value. By turning on the thin-film transistor groups, the positive and negative charges of adjacent independent blocks are offset, achieving charge neutralization. Through the block-based drive design, parallel thin-film transistor group charge offset, and dynamic voltage adjustment, the binding pin current and temperature rise are reduced, improving the reliability of large-size panels in high-temperature environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of a cholesteric electronic paper module;

[0028] Figure 2 Schematic diagram of AC common-stage charging and discharging of cholesteric electronic paper module;

[0029] Figure 3 Schematic diagram of substrate distribution of cholesteric electronic paper module;

[0030] Figure 4 Schematic diagram of the co-level distribution of the cholesteric electronic paper module;

[0031] Figure 5 It is a schematic diagram of the driving structure of the prior art;

[0032] Figure 6 for Figure 5 Schematic diagram of current overcharge of driving structure;

[0033] Figure 7 This is a schematic diagram of the structure of an electronic paper driving device proposed by the present invention cut into six independent blocks;

[0034] Figure 8 This is a schematic diagram of the parallel structure of 1000 thin-film transistor units in an electronic paper driving device proposed by the present invention;

[0035] Figure 9 This is a schematic diagram of the circuit connection structure of a single thin film transistor unit of an electronic paper driving device proposed by the present invention;

[0036] Figure 10This is a schematic diagram of the equivalent circuit structure of each parallel-connected thin-film transistor group in an electronic paper driving device proposed by the present invention;

[0037] Figure 11 This is a driving timing diagram of Example 1 of an electronic paper driving device proposed by the present invention;

[0038] Figure 12 This is a schematic diagram of the workflow of an electronic paper driving method proposed in the present invention. DETAILED DESCRIPTION

[0039] Reference Figure 7-11 The present invention provides an electronic paper driving device, comprising:

[0040] The panel module includes a thin film transistor substrate and a color filter substrate. A cholesteric liquid crystal layer is sandwiched between the thin film transistor substrate and the color filter substrate. An AC common voltage is provided on the color filter substrate. The AC common voltage is divided into 2N independent blocks. Adjacent independent blocks have opposite polarities, where N is a positive integer.

[0041] N parallel thin film transistor groups are arranged between adjacent independent blocks, and each parallel thin film transistor group is composed of m thin film transistor units connected in parallel, where m≥1000.

[0042] A drive control module includes a timing controller and a gate drive circuit; the timing controller is configured to output a high-impedance signal during the polarity switching phase, and the high-impedance signal is used to disconnect the external power input during the polarity switching phase and synchronously turn on the gate voltage of N parallel thin-film transistor groups; the gate drive circuit is connected to the gate of the parallel thin-film transistor group and is used to dynamically adjust the gate voltage of the parallel thin-film transistor group according to real-time current distribution data.

[0043] In this embodiment, it also includes:

[0044] The current monitoring module is embedded in the wiring of each independent block of the AC common level and includes a current sensor and a data feedback unit. The current sensor monitors the charging and discharging current of each independent block in real time and transmits the current distribution data to the drive control module through the data feedback unit.

[0045] Specifically, the current sensor of the current monitoring module is a Hall effect sensor with a sensitivity of ±0.1mA;

[0046] The data feedback unit communicates with the drive control module via the I2C bus, with a response time of ≤1ms.

[0047] In this embodiment, the source and drain of the thin film transistor unit are connected in series with an impedance through a wiring layout, and the m thin film transistor units correspond to the m impedances one by one.

[0048] Specifically, the resistance of the series impedance of the thin film transistor unit is related to the voltage difference between adjacent independent blocks and the limiting current. When the voltage difference between adjacent independent blocks is 2x, the limiting current I limit =2x / R, where R is the parallel sum of the equivalent resistances of all TFT units between independent blocks when they are turned on. The resistance of the TFT unit series impedance can be calculated based on the number of TFT units and the parallel sum of the equivalent resistances of the TFT units.

[0049] In this embodiment, the layout density of the parallel thin film transistor groups is dynamically adjusted according to the block area to ensure that no less than 50 thin film transistor units are covered per square centimeter.

[0050] In this embodiment, the drive control module further includes:

[0051] The temperature compensation unit is used to automatically reduce the gate voltage to 10V when the panel temperature is detected to be ≥85°C, so as to suppress the hot carrier effect of the thin film transistor unit.

[0052] In this embodiment, the source and drain wiring of the thin film transistor unit adopts a serpentine wiring layout, and the total length is ≥500 μm.

[0053] Specifically, the impedance of the single thin film transistor units connected in series is formed by serpentine routing.

[0054] Example 1:

[0055] like Figure 7 As shown, the AC common is divided into 6 independent blocks P1~P6, that is, N=3, and the polarity of adjacent independent blocks is opposite. Adjacent independent blocks are provided with 3 parallel thin film transistor groups, namely T1, T2, and T3. Each parallel thin film transistor group is composed of 1000 thin film transistor units in parallel. The channel width of a single thin film transistor unit is W=1000μm, the length is L=4μm, and the threshold voltage is =5V, on-current ≤1mA.

[0056] On-state current The calculation process is as follows:

[0057] ;

[0058] in, is the carrier mobility (depending on the material, such as amorphous silicon, oxide semiconductor, etc.); is the gate oxide capacitance per unit area; is the ratio of channel width to length; is the gate voltage; is the threshold voltage; is the drain-source voltage.

[0059] according to Figure 9 In the thin film transistor architecture shown, in order to limit the current to a maximum of 1mA and prevent the thin film transistor from burning out due to excessive backlash current, the thin film transistor routing design adopts a winding layout to increase the impedance to 6kΩ before and after the tube, as shown in the figure. Figure 8-10 As shown, 1000 sets of parallel thin-film transistor units are equivalent to a 60Ω on-resistance when turned on, and can limit the current to 1A at a ±30V cross-voltage charging voltage.

[0060] In this embodiment, the first threshold is specifically 1.2A, and the first voltage is specifically a gate voltage of 14V; the second threshold is specifically 0.8A, and the second voltage is specifically a gate voltage of 10V.

[0061] If the current of any independent block exceeds the first threshold value of 1.2A, the gate voltage of the corresponding parallel thin film transistor group is increased to 14V; if the current is lower than 0.8A, the gate voltage is reduced to 10V.

[0062] When switching between positive and negative polarity in AC common voltage, unlike the traditional same polarity switching of the entire surface, the polarity of the adjacent independent blocks P1~P6 is opposite and the voltage is complementary. When switching between positive and negative polarity, T1, T2 and T3 are turned on at the same time. The working sequence is as follows: Figure 11 As shown, with this structure and timing, multiple sets of parallel thin-film transistors can directly offset positive and negative charges on the panel side, accelerating the power-down to 0V. In addition, large currents are only generated on the panel, and the current transmitted to the X PCB through the binding gold fingers can be reduced to below 0.1A (a tiny current), solving the reliability heating problem.

[0063] Specifically, the effect of hedging the positive and negative charges of adjacent blocks inside the panel is to reduce the charge and discharge current flowing through the external circuit (such as the binding pin) by neutralizing the charges between blocks with opposite polarity, thereby reducing local temperature rise and preventing pin burning, while accelerating the voltage switching process to improve driving efficiency.

[0064] Reference Figure 7-12 The present invention proposes an electronic paper driving method, which is applied to any of the electronic paper driving devices described above, and includes:

[0065] During the polarity switching phase, the drive control module outputs a high-impedance signal to disconnect the external power input and synchronously turns on N parallel thin-film transistor groups;

[0066] Acquire current distribution data and dynamically adjust the gate voltages of the N parallel thin-film transistor groups based on the current distribution data, wherein the current distribution data includes real-time charge and discharge current values of each independent block;

[0067] When the real-time charge and discharge current value of any independent block exceeds a first threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is increased to a first voltage value; when the real-time charge and discharge current value of any independent block is less than a second threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is reduced to a second voltage value, wherein the first threshold is greater than the second threshold, and the first voltage value is greater than the second voltage value.

[0068] By turning on the thin film transistor group, the positive and negative charges of adjacent independent blocks are offset to achieve charge neutralization.

[0069] During polarity switching (e.g., from positive common voltage to negative common voltage), adjacent independent blocks (e.g., P1 positive polarity and P2 negative polarity) conduct through parallel thin-film transistor groups. Positive and negative charges are neutralized directly within the panel, eliminating the need for an external power supply to provide the full current. This reduces the 5A current that would otherwise be discharged through the bonding pins to below 0.1A, significantly reducing energy loss and heat accumulation, and addressing issues of device failure and high-temperature aging caused by high current.

[0070] In this embodiment, it also includes:

[0071] When the hedging operation between 2N independent blocks is completed, the drive control module resumes external power input and enters the next image refresh cycle.

[0072] In this embodiment, the completion of the hedging operation is determined by the external current falling below a third threshold, the voltage difference between independent blocks approaching zero, and the timing control reaching a preset time.

[0073] Specifically, the preset duration is 10 , the output current of the external drive circuit is reduced to below 0.1A, and the temperature rise of the binding pin is reduced to ΔT≤10℃.

[0074] In this embodiment, the logic for dynamically adjusting the gate voltage includes: when the panel temperature is detected to be ≥85°C, the drive control module starts the temperature compensation unit to reduce the upper limit of the gate voltage from 14V to 12V to suppress the hot carrier effect of the thin film transistor.

[0075] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. An electronic paper driving device, characterized in that: include: A panel module includes a thin film transistor substrate and a color filter substrate, wherein a cholesteric liquid crystal layer is sandwiched between the thin film transistor substrate and the color filter substrate, and an AC common voltage is provided on the color filter substrate. The AC common voltage is divided into 2N independent blocks, and adjacent independent blocks have opposite polarities, where N is a positive integer; N parallel thin film transistor groups are arranged between adjacent independent blocks, each parallel thin film transistor group is composed of m thin film transistor units connected in parallel, where m ≥ 1000; A drive control module includes a timing controller and a gate drive circuit; the timing controller is configured to output a high-impedance signal during a polarity switching phase, the high-impedance signal being used to disconnect an external power input during the polarity switching phase and synchronously turn on the gate voltages of N parallel thin-film transistor groups; the gate drive circuit is connected to the gates of the parallel thin-film transistor groups and is used to dynamically adjust the gate voltages of the parallel thin-film transistor groups based on real-time current distribution data.

2. The electronic paper driving device according to claim 1, wherein: Also includes: The current monitoring module is embedded in the wiring of each independent block of the AC common level and includes a current sensor and a data feedback unit; the current sensor monitors the charging and discharging current of each independent block in real time and transmits the current distribution data to the drive control module through the data feedback unit.

3. The electronic paper driving device according to claim 1, wherein: The source and drain of the thin film transistor unit are connected in series with an impedance through a winding layout, and the m thin film transistor units correspond to the m impedances one by one.

4. The electronic paper driving device according to claim 1, wherein: The layout density of the parallel thin film transistor groups is dynamically adjusted according to the block area to ensure that no less than 50 groups of thin film transistor units are covered per square centimeter.

5. The electronic paper driving device according to claim 1, wherein: The drive control module further includes: The temperature compensation unit is used to automatically reduce the gate voltage to 10V when the panel temperature is detected to be ≥85°C, so as to suppress the hot carrier effect of the thin film transistor unit.

6. The electronic paper driving device according to claim 3, wherein: The source and drain of the thin film transistor unit are arranged in a serpentine pattern, with a total length of ≥500 μm.

7. An electronic paper driving method, characterized in that: Applied to the electronic paper driving device according to any one of claims 1 to 6, the method comprises: During the polarity switching phase, the drive control module outputs a high-impedance signal to disconnect the external power input and synchronously turns on N parallel thin-film transistor groups; Acquire current distribution data and dynamically adjust the gate voltages of the N parallel thin-film transistor groups based on the current distribution data, wherein the current distribution data includes real-time charge and discharge current values of each independent block; When the real-time charge and discharge current value of any independent block exceeds a first threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is increased to a first voltage value; when the real-time charge and discharge current value of any independent block is less than a second threshold, the gate voltage of the parallel thin-film transistor group corresponding to the independent block is reduced to a second voltage value, wherein the first threshold is greater than the second threshold, and the first voltage value is greater than the second voltage value; By turning on the thin film transistor group, the positive and negative charges of adjacent independent blocks are offset to achieve charge neutralization.

8. The electronic paper driving method according to claim 7, wherein: Also includes: When the hedging operation between 2N independent blocks is completed, the drive control module resumes external power input and enters the next image refresh cycle.

9. The electronic paper driving method according to claim 8, characterized in that: The completion of the hedging operation is determined by the external current falling below a third threshold, the voltage difference between the independent blocks approaching zero, and the timing control reaching a preset time length.

10. The electronic paper driving method according to claim 9, wherein: The preset duration is 10 .

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