Static memory cell and memory architecture

Abstract

The invention provides a static memory cell and a memory architecture which can improve the storage stability and reduce the area overhead at the same time. The static memory cell includes: a first inverter circuit having an output electrically connected to a first storage node and an input electrically connected to a second storage node; the output end of the second inverter circuit is electrically connected to the second storage node, and the input end of the second inverter circuit is electrically connected to the first storage node; a read operation transistor having a gate electrically connected to the first storage node, a drain electrically connected to a read bit line, and a source electrically connected to a read word line; and a write pass transistor having a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a high-density two-port static memory unit for a system-on-chip (SoC) chip, and a memory architecture including the static memory unit. Background Art

[0002] Thanks to advances in computer technology, cloud services, metacomputing, the Internet of Things, and 5G interconnection have flourished, bringing unprecedented convenience and novel experiences to people's lives and work. Currently, with the all-encompassing development of productivity driven by computer technology, emerging technologies such as virtual reality (VR) and augmented reality (AR) are expected to drive a new round of computer technology innovation.

[0003] Among the numerous VR / AR hardware devices, the graphics processing unit (GPU) and central processing unit (CPU), responsible for image processing, rendering, and computing, account for approximately 16% of the cost. Meanwhile, within the microprocessor, the area overhead of static random access memory (SRAM) accounts for over 50% of the total chip cost and consumes the majority of the processor's static power consumption. In short, the overhead of SRAM, used as the CPU's internal L1 cache and built-in L2 cache, is a non-negligible component of VR / AR terminal hardware.

[0004] Furthermore, with the advancement of Moore's Law and the continuous scaling of process nodes, the cost of memory devices is increasing. As a relatively mature memory technology, static random access memory (SRAM) has become a storage medium that is fully compatible with advanced CMOS processes and can be mass-produced. Furthermore, compared to various new memory technologies, SRAM offers faster operation speeds and greater endurance. However, SRAM currently faces challenges such as low storage density and relatively high design complexity.

[0005] In the past, the following two specific solutions have been proposed as commonly used SRAM cell structures.

[0006] Figure 7 Schematic diagram showing the overall structure of a single-port 6T-SRAM unit circuit in the prior art. Figure 7As shown in FIG, a single-port 6T-SRAM cell includes six MOS transistors. Among them, the first pull-up transistor P1 and the second pull-up transistor P2 composed of PMOS transistors and the first pull-down transistor N1 and the second pull-down transistor N2 composed of NMOS transistors form a pair of end-to-end inverters inside the 6T-SRAM cell. The first transfer transistor N5 and the second transfer transistor N6 composed of NMOS transistors serve as transfer transistors to support read and write operations.

[0007] Figure 8 Schematic diagram showing the main structure of a two-port 8T-SRAM unit circuit in the prior art. Figure 8 As shown, the two-port 8T-SRAM cell includes eight MOS transistors, which, in addition to the six MOS transistors in the aforementioned 6T-SRAM cell, also include two additional NMOS transistors dedicated to read operations, namely, a read select transistor N7 and a read pull-down transistor N8.

[0008] Prior art literature

[0009] Non-patent literature

[0010] "VR / AR is the middle game, Metaverse is the end game", Industry in-depth analysis - Securities Research Report, Essence Securities, September 2021 Summary of the Invention

[0011] Technical problem to be solved by the invention

[0012] In such Figure 7 In the 6T-SRAM cell shown, during a read operation, the first and second transfer transistors N5 and N6 are enabled by setting the word line WL to a high level. The data stored in the first and second storage nodes Q and QB are then read through the precharged bit line BL and inverted bit line BLB. However, because the read and write operation paths of this 6T-SRAM cell overlap, and during a read operation, the bit line BL and the first storage node Q are directly connected via the source and drain of the first transfer transistor N5, if, for example, the first storage node Q stores a zero, the precharge voltage on the bit line BL may interfere with the storage state of the first storage node Q for some reason during the initial read, leading to errors during subsequent reads of the same storage cell. This means that the 6T-SRAM structure faces the problem of read interference-induced read damage, which can affect the stability of the 6T-SRAM.

[0013] In contrast, in Figure 8In the 8T-SRAM cell shown, a bilateral operation is still used during write operations, but during read operations, a read select transistor N7 and a read pull-down transistor N8 are used as the read circuit, giving the 8T-SRAM cell a read-write separation feature. This solves the read interference problem faced by the aforementioned 6T-SRAM and improves the stability of the SRAM structure. However, the need to add two additional NMOS transistors degrades the memory density and increases the area overhead.

[0014] The present invention is completed to solve the above-mentioned problems, and its purpose is to provide a static memory unit and memory architecture that can improve the storage stability and anti-read interference capability of the memory while also taking into account the improvement of storage density and the reduction of area overhead.

[0015] Technical solutions to technical problems

[0016] In order to solve the above technical problems, the static memory cell involved in the first aspect of the present invention includes: a first inverter circuit, the output end of the first inverter circuit is electrically connected to the first storage node, and the input end is electrically connected to the second storage node; a second inverter circuit, the output end of the second inverter circuit is electrically connected to the second storage node, and the input end is electrically connected to the first storage node; a read operation transistor, the gate of the read operation transistor is electrically connected to the first storage node, the drain is electrically connected to the read bit line, and the source is electrically connected to the read word line; and a write transfer transistor, the drain of the write transfer transistor is electrically connected to the second storage node, the gate is electrically connected to the write word line, and the source is electrically connected to the write bit line.

[0017] Optionally, during a read operation, the read bit line is precharged to a first voltage, the read word line is clamped to a second voltage lower than the first voltage, and the data stored in the first storage node is read by detecting the voltage difference of the read bit line.

[0018] Optionally, during a read operation, the write word line and the write bit line are maintained at a low level.

[0019] Optionally, during a write operation, the write word line is set to a high level, and data is written to the second storage node by inputting a third voltage or a fourth voltage lower than the third voltage to the write bit line, thereby writing data to the first storage node.

[0020] Optionally, during a write operation, the read word line and the read bit line are maintained at a low level.

[0021] Optionally, in the hold state, the write word line, the write bit line, the read word line and the read bit line are all set to a low level.

[0022] Optionally, the first inverter includes a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor and the drain of the first pull-down transistor are electrically connected to the first storage node, the gate of the first pull-up transistor and the gate of the first pull-down transistor are electrically connected to the second storage node, the source of the first pull-up transistor is electrically connected to a power supply, and the source of the first pull-down transistor is grounded; the second inverter includes a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor and the drain of the second pull-down transistor are electrically connected to the second storage node, the gate of the second pull-up transistor and the gate of the second pull-down transistor are electrically connected to the first storage node, the source of the second pull-up transistor is electrically connected to the power supply, and the source of the second pull-down transistor is grounded.

[0023] In addition, in order to solve the above technical problems, the memory architecture involved in the second aspect of the present invention includes: a memory array, which is composed of a plurality of static memory cells as involved in the first aspect of the present invention, the sources of the read operation transistors of the static memory cells in the same row are electrically connected to the same read word line, the gates of the write transfer transistors of the static memory cells in the same row are electrically connected to the same write word line, the drains of the read operation transistors of the static memory cells in the same column are electrically connected to the same read bit line, and the sources of the write transfer transistors of the static memory cells in the same column are electrically connected to the same write bit line; a row driver circuit, which is electrically connected to the read word lines and write word lines of each row of the memory array, according to the row The address code signal selects the row to be read through the read word line, or selects the row to be written through the write word line according to the row address code signal; a column pre-charge drive circuit, which is electrically connected to the read bit line and the write bit line of each column of the memory array, pre-charges the read bit line of the column to be read according to the column address code signal, or pre-charges the write bit lines of all columns and writes data to the static memory cell of the column to be written through the write bit line according to the column address code signal; and a read circuit, which is electrically connected to the read bit line of each column of the memory array, selects the column to be read, and generates and outputs the read data based on the voltage of the read bit line of the column to be read.

[0024] Optionally, the row driving circuit includes a row decoder, which converts the acquired row address code signal into a row selection signal.

[0025] Optionally, the row driving circuit also includes a read word line driver. During a read operation, the read word line driver clamps the read word line of the row to be read to a second voltage according to the row selection signal, and the second voltage is lower than the first voltage pre-charged on the read bit line of the column to be read.

[0026] Optionally, the row driving circuit further includes a write word line driver. During a write operation, the write word line driver sets the write word line of the row to be written to a high level according to the row selection signal.

[0027] Optionally, the column pre-charge driving circuit includes a column decoder, which converts the acquired column address code signal into a column selection signal.

[0028] Optionally, the column pre-charge drive circuit also includes a read bit line pre-charger. During a read operation, the read bit line pre-charger pre-charges the read bit line of the column to be read to a first voltage according to the column selection signal, and the first voltage is higher than the second voltage clamped on the read word line of the row to be read.

[0029] Optionally, the read bit line precharger precharges the read bit line of the column to be read to the first voltage in units of bit width.

[0030] Optionally, the column pre-charge drive circuit also includes a write bit line pre-charge driver. Before the write operation, the write bit line pre-charge driver pre-charges the write bit lines of all columns to a high level. During the write operation, the write bit line pre-charge driver inputs a third voltage or a fourth voltage lower than the third voltage to the write bit line of the column to be written based on the column selection signal and the data signal from the outside, thereby writing data to the static memory cell to be written.

[0031] Optionally, the write bit line precharge driver writes data to the static memory cell to be written in units of bit width.

[0032] Optionally, the reading circuit includes a sense amplifier, and during a read operation, the sense amplifier amplifies the voltage variable of the read bit line of the column to be read as the read data.

[0033] Optionally, the reading circuit further includes a multiplexer, which selects the column to be read.

[0034] Optionally, the multiplexer performs the gating in units of bit width.

[0035] Effects of the Invention

[0036] The static memory cell and memory architecture according to the present invention can improve the storage stability and anti-read disturbance capability of the memory, while also taking into account the improvement of storage density and the reduction of area overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic diagram showing the structure of a static memory cell according to the first embodiment of the present invention.

[0038] Figure 2 is a circuit diagram showing a specific embodiment of a static memory cell.

[0039] Figure 3 This is a timing diagram showing an example of the operation of the static memory cell.

[0040] Figure 4 It is a bar graph showing the comparison results of the cell area of the static memory cell involved in the present invention and the single-port 6T-SRAM cell and the two-port 8T-SRAM cell of the conventional technology.

[0041] Figure 5 This is a block diagram showing the structure of a memory architecture according to the second embodiment of the present invention.

[0042] Figure 6 is a schematic diagram showing a specific embodiment of a memory architecture.

[0043] Figure 7 FIG. 1 is a schematic diagram showing the overall structure of a single-port 6T-SRAM cell circuit in the prior art.

[0044] Figure 8 FIG. 1 is a schematic diagram showing the overall structure of a two-port 8T-SRAM unit circuit in the prior art. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the specific implementation methods described herein are only used to illustrate and explain the embodiments of the present application and are not used to limit the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0046] It should be noted that the technical solutions between the various embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0047] Implementation Method 1

[0048] Refer to the following Figures 1 to 4 , the static memory cell involved in this embodiment is described.

[0049] Figure 1 Schematic diagram showing the structure of a static memory cell according to this embodiment. The static memory cell of the present invention is a two-port memory cell that can be used for a high-density two-port cache in a system-on-chip (SoC). The static memory cell includes a first inverter circuit NOT1, a second inverter circuit NOT2, a read transistor N3, and a write pass transistor N4.

[0050] like Figure 1 As shown, the output terminal of the first inverter circuit NOT1 is electrically connected to the first storage node Q, and the input terminal is electrically connected to the second storage node QB. The output terminal of the second inverter circuit NOT2 is electrically connected to the second storage node QB, and the input terminal is electrically connected to the first storage node Q. Thus, the first inverter circuit NOT1 and the second inverter circuit NOT2 form a positive feedback cross latch circuit connected end to end, and the first storage node Q and the second storage node QB store a pair of inverted data.

[0051] Read transistor N3 is an NMOS transistor with a gate electrically connected to the first storage node Q, a drain electrically connected to the read bit line RBL, and a source electrically connected to the read word line RWL. In the present invention, a read operation is performed by controlling the gate of read transistor N3 via the first storage node Q using a voltage differential current flow. This will be described in detail later.

[0052] Write pass transistor N4 is an NMOS transistor with a drain electrically connected to the second storage node QB, a gate electrically connected to the write word line WWL, and a source electrically connected to the write bit line WBL. In the present invention, a write operation is implemented by writing data to the second storage node QB via write pass transistor N4. This is a unilateral operation, which will be described in detail later.

[0053] Figure 2 Yes Figure 1 A circuit diagram of a specific embodiment of a static memory cell. Figure 2 In FIG. 1 , two pairs of PMOS transistors and NMOS transistors are used to form a Figure 1 The embodiment of the first inverter circuit NOT1 and the second inverter circuit NOT2 connected end to end is shown. However, the structure of the static memory unit of the present invention is not limited to this. As long as the structure can realize the function of the cross latch circuit, it can be used to constitute the static memory unit of the present invention. In addition, Figure 2 In, with Figure 1 The same parts are denoted by the same reference numerals.

[0054] like Figure 2 As shown, the static memory cell includes four NMOS transistors and two PMOS transistors, forming a two-port 5T1T-SRAM unit circuit.

[0055] The first pull-up transistor P1 is a PMOS transistor, and the first pull-down transistor N1 is an NMOS transistor. The drain of the first pull-up transistor P1 and the drain of the first pull-down transistor N1 are electrically connected to the first storage node Q, the gate of the first pull-up transistor P1 and the gate of the first pull-down transistor N1 are electrically connected to the second storage node QB, the source of the first pull-up transistor P1 is electrically connected to the power supply VDD, and the source of the first pull-down transistor N1 is electrically connected to the ground VSS. Thus, the first pull-up transistor P1 and the first pull-down transistor N1 constitute the following Figure 1 The first inverter NOT1 is shown.

[0056] In addition, the second pull-up transistor P2 is a PMOS transistor, and the second pull-down transistor N2 is an NMOS transistor. The drain of the second pull-up transistor P2 and the drain of the second pull-down transistor N2 are electrically connected to the second storage node QB, the gate of the second pull-up transistor P2 and the gate of the second pull-down transistor N2 are electrically connected to the first storage node Q, the source of the second pull-up transistor P2 is electrically connected to the power supply VDD, and the source of the second pull-down transistor N2 is electrically connected to the ground VSS. Thus, the second pull-up transistor P2 and the second pull-down transistor N2 constitute the following Figure 1 The second inverter NOT2 is shown.

[0057] According to the above structure, by controlling the voltage levels (hereinafter also referred to as voltages, with "high level" referred to as "high voltage" and "low level" referred to as "low voltage") on the read word line RWL, read bit line RBL, write word line WWL, and write bit line WBL, it is possible to perform read and write operations on the data stored in the first storage node Q and the second storage node QB. This is described below with reference to the accompanying drawings.

[0058] Figure 3 This is a timing diagram showing an example of the operation of the static memory cell.

[0059] like Figure 2 、 Figure 3 As shown, during the read operation, first, the read bit line RBL is precharged to a first voltage V HIGH and clamp the read word line RWL to a second voltage V LOW , wherein the second voltage V LOW Lower than the first voltage V HIGHNext, the voltage difference of the read bit line RBL is detected to read the data stored in the first storage node Q. That is, the static memory cell of this embodiment uses the so-called "voltage difference current" method to complete the read operation.

[0060] Specifically, if Figure 2 、 Figure 3 As shown in FIG, when the data stored in the first storage node Q is 0, a low voltage is applied to the gate of the read operation transistor N3. At this time, the channel between the drain and source of the read operation transistor N3 is closed, so that no voltage difference current flows from the read bit line RBL to the read word line RWL. The read bit line RBL maintains the precharged first voltage V HIGH As a result, a sense amplifier (SA) (not shown) connected to the read bit line RBL reads out that the value stored in the first storage node Q is 1 (correspondingly, the value stored in the second storage node QB is 0).

[0061] On the other hand, when the data stored in the first storage node Q is 1, a high voltage is applied to the gate of the read transistor N3. At this time, the channel between the drain and source of the read transistor N3 is opened, so that the read bit line RBL is discharged to the read word line RWL through the read transistor N3 until the voltage of the read bit line RBL increases from the first voltage V HIGH drops to the second voltage V on the read word line RWL LOW During the discharge process, a certain voltage difference (V HIGH -V LOW ). As a result, the sense amplifier (not shown) connected to the read bit line RBL reads out that the value stored in the first storage node Q is 0 (correspondingly, the value stored in the second storage node QB is 1).

[0062] In the present invention, the first voltage V HIGH and the second voltage V LOW The specific voltage value of is not particularly limited and can be set arbitrarily between the voltage of the power supply VDD and the ground VSS.

[0063] During a write operation, the write word line WWL is first set to a high voltage to turn on the channel of the write pass transistor N4. Next, data is written to the second storage node QB by inputting the third voltage WrQB1 or the fourth voltage WrQB0 to the write bit line WBL. With the help of positive feedback from the cross latch, data is then written to the first storage node Q. The third voltage WrQB1 and the fourth voltage WrQB0 are pre-set voltages, serving as pull-up and pull-down voltages, respectively, for writing a 1 or 0 to the second storage node QB. Furthermore, the fourth voltage WrQB0 is lower than the third voltage WrQB1. That is, the static memory cell of this embodiment uses a so-called "unilateral operation" approach to complete the write operation.

[0064] Specifically, when data 0 is to be written to the first storage node Q, a high voltage is applied to the gate of the write-transmit transistor N4, and the write bit line WBL is set to the third voltage WrQB1. At this time, the channel between the drain and source of the write-transmit transistor N4 is opened, and the voltage on the drain is pulled up to the same level as the third voltage WrQB1 on the source, thereby writing data 1 to the second storage node QB. Furthermore, data 0 is written to the first storage node Q through the cross-latch circuit.

[0065] On the other hand, when data 1 is to be written to the first storage node Q, a high voltage is applied to the gate of the write pass transistor N4, and the write bit line WBL is set to the fourth voltage WrQB0. At this time, the channel between the drain and source of the write pass transistor N4 is opened, and the voltage on the drain is pulled down to the same level as the fourth voltage WrQB0 on the source, thereby writing data 0 to the second storage node QB. In turn, data 1 is written to the first storage node Q through the cross latch circuit.

[0066] In the present invention, there are no specific limitations on the specific voltage values of the third voltage WrQB1 and the fourth voltage WrQB0. However, to further improve the drive capability during a write operation, it is preferred that the write bit line WBL be driven rail-to-rail. Specifically, the third voltage WrQB1 be set to the power supply voltage VDD, and the fourth voltage WrQB0 be set to the ground voltage VSS. Furthermore, it is further preferred that the write word line WWL be driven rail-to-rail. Specifically, the voltage of the write word line WWL be set to the power supply voltage VDD during a write operation and to the ground voltage VSS when a write operation is not in progress.

[0067] Furthermore, in the hold state, the write word line WWL, write bit line WBL, read word line RWL, and read bit line RBL are all set to a low voltage. Consequently, there is no voltage difference between the source and drain of read transistor N3. Consequently, regardless of whether the first storage node Q is stored with a 1 or a 0, no voltage drop current is generated on read bit line RBL. Furthermore, the gate and source of write pass transistor N4 are maintained at a low voltage, preventing any write to the second storage node QB.

[0068] Furthermore, during a read operation, the write word line WWL and write bit line WBL can be kept at a low voltage. During a write operation, the read word line RWL and read bit line RBL can be kept at a low voltage. This allows the state of either a read or write operation to remain unchanged, thus preventing interference between the two operations.

[0069] The technical effects of the static memory cell of the present invention will be described below by comparing it with a single-port 6T-SRAM cell and a two-port 8T-SRAM cell in the prior art.

[0070] Figure 4 This is a bar chart showing the comparison of the cell area of the static memory cell involved in the present invention with the single-port 6T-SRAM cell and the two-port 8T-SRAM cell of the prior art. The data in this chart is derived from the 28nm process node. The height of each bar represents the area of the SRAM cell, in μm. 2 .exist Figure 4 In Figure 2 The two-port 5T1T-SRAM cell is shown as a representative of the static memory cell of the present invention.

[0071] like Figure 4 As shown, compared to the prior art two-port 8T-SRAM cell, the two-port 5T1T-SRAM cell of the present invention reduces the SRAM cell area by approximately 56% due to the reduction of two NMOS transistors. This is comparable to the 51% area reduction of the single-port 6T-SRAM cell. Furthermore, the two-port 5T1T-SRAM cell of the present invention also offers high stability and read disturb resistance comparable to the two-port 8T-SRAM cell.

[0072] As described above, according to the static memory cell involved in this embodiment, since the gate, source, and drain of the read operation transistor N3 that completes the read operation are separated, there is no direct charging and discharging path between the read bit line RBL and the read word line RWL and the latch circuit portion of the SRAM memory cell. Therefore, the read interference problem faced by the 6T-SRAM in the prior art can be solved.

[0073] In addition, according to the static memory cell involved in this embodiment, since the write operation adopts a unilateral operation method, the use of one NMOS write transmission tube (i.e., the first transmission transistor N5 in the 8T-SRAM cell) is reduced compared to the 8T-SRAM of the prior art. At the same time, since the read operation directly adopts the voltage difference current method, the use of one NMOS read transmission tube (i.e., the read selection transistor N7 in the 8T-SRAM cell) is reduced compared to the 8T-SRAM of the prior art. In addition, to ensure logical correctness, the read pull-down transistor N8 is moved to the Q point side and becomes the read operation transistor N3. Therefore, the static memory cell of this embodiment can solve the problem of excessive cell area caused by the 8T-SRAM of the prior art by reducing the number of MOS transistors.

[0074] Implementation Method 2

[0075] Below, refer to Figure 5 and Figure 6 , the memory architecture involved in this embodiment is described.

[0076] Figure 5 is a block diagram showing the structure of the memory architecture involved in this embodiment. The memory architecture of this embodiment can be used for a high-density two-port buffer on a system-on-chip. Figure 5 As shown, the memory architecture includes a memory array 1 , a row driver circuit 2 , a column precharge driver circuit 3 and a read circuit 4 .

[0077] The memory array 1 is composed of a plurality of static memory cells as described in Embodiment 1. Figure 5 In FIG, the first four columns of the second row are taken as an example to briefly illustrate the structure of the memory array 1. In which, a box represents a static memory cell, combined with Figure 1 、 2 and Figure 5 The sources of the read transistors of the static memory cells in the same row are electrically connected to the same read word line RWL, the gates of the write-pass transistors of the static memory cells in the same row are electrically connected to the same write word line WWL, the drains of the read transistors of the static memory cells in the same column are electrically connected to the same read bit line RBL, and the sources of the write-pass transistors of the static memory cells in the same column are electrically connected to the same write bit line WBL. Furthermore, considering the voltage division and speed reduction caused by word line length, capacitance, and resistance, in this embodiment, the number of rows of the memory array 1 is preferably controlled within 64 rows. When greater capacity is required, a hierarchical storage structure can be used to splice multiple memory blocks.

[0078] The row driving circuit 2 is electrically connected to the read word line RWL and the write word line WWL of each row of the memory array 1. According to the row address code signal from the control circuit not shown, the row to be read is selected through the read word line RWL, or, according to the row address code signal from the control circuit not shown, the row to be written is selected through the write word line WWL.

[0079] The column pre-charge drive circuit 3 is electrically connected to the read bit line RBL and the write bit line WBL of each column of the memory array 1. It pre-charges the read bit line RBL of the column to be read according to the column address code signal from the control circuit (not shown), or pre-charges the write bit lines WBL of all columns and writes data to the static memory cell of the column to be written through the write bit line WBL according to the column address code signal.

[0080] The read circuit 4 is electrically connected to the read bit line RBL of each column of the memory array 1 , selects the column to be read, and generates and outputs read data based on the voltage of the read bit line RBL of the column to be read.

[0081] Figure 6 Yes Figure 5 A schematic diagram of a specific embodiment of a memory architecture. Figure 6 In, with Figure 5 The same parts are denoted by the same reference numerals.

[0082] Combine Figure 5 、 Figure 6 The row driver circuit 2 may include a row decoder 21, a read word line driver 22, and a write word line driver 23. The column precharge driver circuit 3 may include a column decoder 31, a read bit line precharger 32, and a write bit line precharger 33. The read circuit 4 may include a sense amplifier 41 and a multiplexer 42.

[0083] The row decoder 21 converts the acquired row address code signals A1, A2, ..., Ax into 2 x The row address code signals A1, A2, ..., Ax are, for example, binary codes containing the row addresses for read and write operations. The row decoder 21 is, for example, a row address decoder that converts the binary row address code signals A1, A2, ..., Ax into decimal row addresses and outputs them as row select signals.

[0084] The column decoder 31 converts the acquired column address code signals B1, B2, ..., Bm into 2 m= M-way column selection signal. The column address code signals B1, B2, ..., Bm are, for example, a series of binary codes, including the column address to be read or written. The column decoder 31 is, for example, a column address decoder, which converts a certain binary column address code signal B1, B2, ..., Bm into a binary code. m = one of M possible column addresses, and outputs a Mbit wide one-hot code as a column select signal to select 2 m = one of the M ways. Each way corresponds to N columns of memory cells, so the array has a total size of M×N columns.

[0085] During a read operation, the read word line driver 22 clamps the read word line RWL of the row to be read to a second voltage V according to the row selection signal. LOW The read bit line precharger 32 precharges the read bit line RBL of the column to be read to a first voltage V according to the column selection signal. HIGH , wherein the second voltage V LOW Lower than the first voltage V HIGH The multiplexer 42 selects the column to be read. In this embodiment, the multiplexer 42 selects one of the M read bit lines RBL, containing N columns of memory cells to be read, based on the column address of the read operation. The multiplexer 42 then electrically connects the selected read bit lines RBL to the sense amplifier 41. The sense amplifier 41 amplifies the voltage variation of the N read bit lines RBL, containing N columns of memory cells to be read, and outputs the amplified data.

[0086] Furthermore, during a read operation, the read word line driver 22 maintains the read word line RWL of a row not undergoing a read operation at a high voltage, and the read bit line precharger 32 maintains the read bit line RBL of a column not undergoing a read operation at a high voltage.

[0087] When a read operation reads 0 (the Q point of the read memory cell stores 0, and the read operation transistor N3 is turned off), for the selected column in the unselected row, since both the unselected row and the selected column are at high voltage, this will not affect the voltage of the selected column and will not cause misreading.

[0088] When the read operation reads 1 (the Q point of the read memory cell stores 1, and the read operation transistor N3 is turned on), the RBL of the selected column will discharge to the RWL of the selected row through the turned-on read operation transistor N3 to the low voltage V LOW At this time, if there is a memory cell storing 1 in the unselected row of the column, there will be a further unselected row high voltage V HIGH After the selected column is pulled down, the low voltage V LOW In this case, the circuit will eventually stabilize at V HIGH-ΔV static operating point. At the 28nm node, when the number of control array rows does not exceed 64 rows, ΔV>10mV. At this time, the 10mV voltage difference is sufficient for the sense amplifier 41 to correctly read 1. In other design backgrounds and process nodes, the configuration of "no more than 64 rows" can be adaptively adjusted based on the above principles. Therefore, the present invention does not only protect the literal meaning of "no more than 64 rows". All technologies that use the above-mentioned principle design are within the scope of protection of the present invention.

[0089] During a read operation, for unselected columns in a selected row, the multiplexer 42 will not further connect the connected read bit line RBL to the sense amplifier 41 , and thus will not affect the read data.

[0090] Before a write operation, the write bit line precharge driver 33 precharges the write bit lines WBL of all columns to a high voltage. During a write operation, the write word line driver 23 sets the write word line WWL of the row to be written to a high voltage based on the row select signal. The write bit line precharge driver 33 inputs the third voltage WrQB1 or a fourth voltage WrQB0, which is lower than the third voltage WrQB1, to the write bit line WBL of the column to be written based on the column select signal and an external data signal, thereby writing data to the static memory cell to be written.

[0091] Furthermore, during a write operation, the write word line driver 23 maintains the write word line WWL of the row not being written to at a low voltage, and the write bit line precharge driver 33 maintains the write bit line WBL of the column not being written to at a low voltage. This selects the row and column to be written to.

[0092] Furthermore, during a write operation, for static memory cells in unselected rows within a selected column, the gate of their write-pass transistor N4 is at a low voltage, closing the channel between its source and drain. Therefore, the voltage of the write bit line WBL is not written into the static memory cell. For static memory cells in unselected columns within a selected row, their write bit line WBL is unselected and remains in a floating high-impedance state, not driven by the third voltage WrQB0 or the fourth voltage WrQB1 used for the write operation. Consequently, it remains at the precharge voltage. Furthermore, the cross-latch circuit within the memory cell exhibits positive feedback characteristics, providing strong retention capability. Therefore, the voltage of the second storage node QB is not affected by the precharge voltage of the high-impedance write bit line WBL.

[0093] In practical applications, the number of rows in a stored data array is typically much greater than the number of columns. To avoid an imbalance in the number of rows and columns in memory array 1 and to ensure that the number of rows in memory array 1 is as close to or equal to the number of columns as possible, the concept of "bit width" is introduced. Specifically, the rows of the stored data array can be segmented according to a certain bit width (e.g., N bits), and the segmented data can be folded into a nearly square or square data array for read and write operations.

[0094] Therefore, if Figure 6 As shown, in this embodiment, taking into account the bit width of the stored data, the memory array 1 can be divided into M groups along the row direction, each group containing N columns of static memory cells. That is, the memory array 1 includes a total of M×N columns of static memory cells. M column select signals can be used to select which group to perform read or write operations on, and when a read or write operation is performed on the selected group, the static memory cells in all columns of the group are read or written simultaneously.

[0095] In the above case, during the read operation, the read bit line precharger 32 precharges the read bit line RBL of the column to be read to the first voltage V HIGH Furthermore, the multiplexer 42 selects the read bit lines RBL in units of a bit width of N bits, that is, it selects one of the M read bit lines RBL, a total of N lines, to be electrically connected to the sense amplifier 41 .

[0096] In contrast, during a write operation, the write bit line precharge driver 33 also writes data to the static memory cell to be written, using the bit width as a unit. Furthermore, if the external data signal is N bits of data, the write bit line precharge driver 33 writes the N bits of data at once to the selected N columns of static memory cells, using the bit width as a unit.

[0097] The number of bits N of the bit width can be set according to actual storage needs. In some specific cases, the bit width can even be set to 1 bit.

[0098] As described above, according to the memory architecture involved in this embodiment, since the static memory cells described above are used to form the memory array, the area overhead can be reduced and the storage density can be improved by controlling the number of transistors. In addition, independent functional paths can be provided for read operations and write operations respectively, thereby improving reliability.

[0099] The above describes the static memory unit and the memory architecture including the static memory unit involved in the present invention. It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0100] In addition, the above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art.

[0101] Industrial applicability

[0102] As described above, the static memory cell and the memory architecture including the static memory cell according to the present invention are useful for a high-density cache memory of a system-on-chip (SoC).

[0103] Description of labels

[0104] 1 Memory array

[0105] 2-row drive circuit

[0106] 3-column precharge drive circuit

[0107] 4 Reading circuit

[0108] 21-line decoder

[0109] 22 Read word line driver

[0110] 23 Write word line driver

[0111] 31 column decoder

[0112] 32 Read bit line precharger

[0113] 33 Write bit line precharge driver

[0114] 41 Sensitive Amplifier

[0115] 42 Multiplexer

[0116] P1 first pull-up transistor

[0117] P2 second pull-up transistor

[0118] N1 first pull-down transistor

[0119] N2 second pull-down transistor

[0120] N3 read transistor

[0121] N4 write pass transistor

[0122] N5 first pass transistor

[0123] N6 Second pass transistor

[0124] N7 read select transistor

[0125] N8 read pull-down transistor

[0126] NOT1 first inverter circuit

[0127] NOT2 second inverter circuit

[0128] RWL Read Word Line

[0129] RBL Read Bit Line

[0130] BL bit line

[0131] BLB Negative Phase Line

[0132] WWL Write Word Line

[0133] WBL Write Bit Line

[0134] WL word line

[0135] WBLB Inverted Write Bit Line

[0136] Q First storage node

[0137] QB Second Storage Node

[0138] VDD power supply

[0139] VSS is ground.

Claims

1. A static memory cell, characterized in that: include: a first inverter circuit, wherein an output terminal of the first inverter circuit is electrically connected to the first storage node, and an input terminal of the first inverter circuit is electrically connected to the second storage node; a second inverter circuit, wherein an output terminal of the second inverter circuit is electrically connected to the second storage node, and an input terminal of the second inverter circuit is electrically connected to the first storage node; a read operation transistor, wherein the gate of the read operation transistor is electrically connected to the first storage node, the drain is electrically connected to a read bit line, and the source is electrically connected to a read word line; as well as A write pass transistor has a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.

2. The static memory cell according to claim 1, wherein During a read operation, the read bit line is precharged to a first voltage, the read word line is clamped to a second voltage lower than the first voltage, and the data stored in the first storage node is read by detecting the voltage difference of the read bit line.

3. The static memory cell according to claim 2, wherein: During a read operation, the write word line and the write bit line are kept at a low level.

4. The static memory cell according to claim 1, wherein During a write operation, the write word line is set to a high level, and data is written to the second storage node by inputting a third voltage or a fourth voltage lower than the third voltage to the write bit line, thereby writing data to the first storage node.

5. The static memory cell according to claim 4, wherein During a write operation, the read word line and the read bit line are kept at a low level.

6. The static memory cell according to any one of claims 1 to 5, wherein: In the hold state, the write word line, the write bit line, the read word line, and the read bit line are all set to a low level.

7. The static memory cell according to any one of claims 1 to 5, wherein: The first inverter includes a first pull-up transistor and a first pull-down transistor, wherein the drain of the first pull-up transistor and the drain of the first pull-down transistor are electrically connected to the first storage node, the gate of the first pull-up transistor and the gate of the first pull-down transistor are electrically connected to the second storage node, the source of the first pull-up transistor is electrically connected to a power supply, and the source of the first pull-down transistor is grounded. The second inverter includes a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor and the drain of the second pull-down transistor are electrically connected to the second storage node, the gate of the second pull-up transistor and the gate of the second pull-down transistor are electrically connected to the first storage node, the source of the second pull-up transistor is electrically connected to the power supply, and the source of the second pull-down transistor is grounded.

8. A memory architecture, characterized in that: include: A memory array, the memory array comprising a plurality of static memory cells according to any one of claims 1 to 7, wherein the sources of the read transistors of the static memory cells in the same row are electrically connected to the same read word line, the gates of the write pass transistors of the static memory cells in the same row are electrically connected to the same write word line, the drains of the read transistors of the static memory cells in the same column are electrically connected to the same read bit line, and the sources of the write pass transistors of the static memory cells in the same column are electrically connected to the same write bit line; a row driver circuit, the row driver circuit being electrically connected to a read word line and a write word line of each row of the memory array, and selecting a row to be read through the read word line according to a row address code signal, or selecting a row to be written through the write word line according to a row address code signal; a column precharge drive circuit, the column precharge drive circuit being electrically connected to the read bit lines and write bit lines of each column of the memory array, and precharging the read bit lines of the column to be read according to the column address code signal, or precharging the write bit lines of all columns and writing data to the static memory cells of the column to be written through the write bit lines according to the column address code signal; as well as A read circuit is electrically connected to a read bit line of each column of the memory array, selects a column to be read, and generates and outputs read data based on a voltage of the read bit line of the column to be read.

9. The memory architecture of claim 8, wherein: The row driving circuit includes a row decoder, which converts the acquired row address code signal into a row selection signal.

10. The memory architecture of claim 9, wherein: The row driving circuit also includes a read word line driver. During a read operation, the read word line driver clamps the read word line of the row to be read to a second voltage based on the row selection signal, and the second voltage is lower than the first voltage precharged on the read bit line of the column to be read.

11. The memory architecture of claim 9, wherein: The row driving circuit further includes a write word line driver. During a write operation, the write word line driver sets the write word line of the row to be written to a high level according to the row selection signal.

12. The memory architecture of claim 8, wherein: The column precharge driving circuit includes a column decoder, which converts the acquired column address code signal into a column selection signal.

13. The memory architecture of claim 12, wherein: The column pre-charge drive circuit also includes a read bit line pre-charger. During a read operation, the read bit line pre-charger pre-charges the read bit line of the column to be read to a first voltage according to the column selection signal. The first voltage is higher than the second voltage clamped on the read word line of the row to be read.

14. The memory architecture of claim 13, wherein: The read bit line precharger precharges the read bit line of a column to be read to the first voltage in units of bit width.

15. The memory architecture of claim 12, wherein: The column pre-charge drive circuit also includes a write bit line pre-charge driver. Before a write operation, the write bit line pre-charge driver pre-charges the write bit lines of all columns to a high level. During a write operation, the write bit line pre-charge driver inputs a third voltage or a fourth voltage lower than the third voltage to the write bit line of the column to be written based on the column selection signal and the data signal from the outside, thereby writing data to the static memory cell to be written.

16. The memory architecture of claim 15, wherein: The write bit line precharge driver writes data to the static memory cell to be written using a bit width as a unit.

17. The memory architecture of claim 8, wherein: The reading circuit includes a sense amplifier. During a reading operation, the sense amplifier amplifies the voltage variation of the read bit line of the column to be read as read data.

18. The memory architecture of claim 17, wherein: The reading circuit further includes a multiplexer that selects a column to be read.

19. The memory architecture of claim 18, wherein: The multiplexer performs the gating in units of bit width.

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